origin projec
This commit is contained in:
17828169534
commit
146453b2fe
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@ -0,0 +1 @@
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-f ${SRC_ROOT_PATH}/00_flist/top.f
|
||||
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|
@ -0,0 +1,57 @@
|
|||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/pll/pll.v
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
|
||||
${SRC_ROOT_PATH}/hg_mp/lvds_rx/lvds_rx_enc.v
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
|
||||
|
||||
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/ubus_top.v
|
||||
//${SRC_ROOT_PATH}/hg_mp/local_bus/uart_2dsp_16mhz.v
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/uart_2dsp_36mhz.v
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/CRC4_D16.v
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/local_bus_slve_cis.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ad_sampling.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/rddpram_ctl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/rddpram_ctl_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/gen_sp.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/wrdpram_ctl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sort.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sort_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/exdev_ctl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/auto_rst.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sampling_fe.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sampling_fe_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/AD_config.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/fan_ctrl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/transfer_300_to_200.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/adc_addr_gen.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ch_addr_gen.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/channel_part_8478.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/fifo_adc.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/insert.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/link_line.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/mapping.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/mux_e.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/mux_i.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/prebuffer.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/prebuffer_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ram_switch.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ram_switch_state.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_addr.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_addr_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_data.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_data_rev.v
|
||||
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/cdc/cdc_sync.v
|
||||
${SRC_ROOT_PATH}/hg_mp/scan_start/scan_start_diff.v
|
||||
${SRC_ROOT_PATH}/hg_mp/sensor_lane/lscc_sensor.v
|
||||
${SRC_ROOT_PATH}/hg_mp/pixel_cdc/pixel_cdc.v
|
||||
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/drx_top/huagao_mipi_top.v
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/pll/pll.v
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
|
||||
${SRC_ROOT_PATH}/hg_mp/lvds_rx/lvds_rx_enc.v
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
|
||||
${SRC_ROOT_PATH}/hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
|
||||
|
||||
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/ubus_top.v
|
||||
//${SRC_ROOT_PATH}/hg_mp/local_bus/uart_2dsp_16mhz.v
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/uart_2dsp_36mhz.v
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/CRC4_D16.v
|
||||
${SRC_ROOT_PATH}/hg_mp/local_bus/local_bus_slve_cis.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ad_sampling.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/rddpram_ctl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/rddpram_ctl_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/gen_sp.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/wrdpram_ctl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sort.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sort_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/exdev_ctl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/auto_rst.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sampling_fe.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/sampling_fe_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/AD_config.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/fan_ctrl.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/transfer_300_to_200.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/adc_addr_gen.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ch_addr_gen.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/channel_part_8478.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/fifo_adc.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/insert.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/link_line.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/mapping.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/mux_e.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/mux_i.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/prebuffer.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/prebuffer_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ram_switch.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/ram_switch_state.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_rev.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_addr.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_data.v
|
||||
${SRC_ROOT_PATH}/hg_mp/fe/read_ram_data_rev.v
|
||||
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/cdc/cdc_sync.v
|
||||
${SRC_ROOT_PATH}/hg_mp/scan_start/scan_start_diff.v
|
||||
${SRC_ROOT_PATH}/hg_mp/sensor_lane/lscc_sensor.v
|
||||
${SRC_ROOT_PATH}/hg_mp/pixel_cdc/pixel_cdc.v
|
||||
|
||||
|
||||
${SRC_ROOT_PATH}/hg_mp/drx_top/huagao_mipi_top.v
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<FIFOConfig>
|
||||
<GeneralConfig>
|
||||
<Type>EG_LOGIC_FIFO</Type>
|
||||
<Device>EG4D20EG176</Device>
|
||||
<create_VHDL>false</create_VHDL>
|
||||
<inst>d512_w8_fifo</inst>
|
||||
</GeneralConfig>
|
||||
<DataPortOption>
|
||||
<write_width>8</write_width>
|
||||
<write_depth>1024</write_depth>
|
||||
<read_width>8</read_width>
|
||||
<read_depth>1024</read_depth>
|
||||
</DataPortOption>
|
||||
<FlagOption>
|
||||
<aempty_flag>false</aempty_flag>
|
||||
<afull_flag>false</afull_flag>
|
||||
<resetmode>SYNC</resetmode>
|
||||
<reset_release>SYNC</reset_release>
|
||||
</FlagOption>
|
||||
<OutputOption>
|
||||
<regmode_r>None</regmode_r>
|
||||
</OutputOption>
|
||||
<InputOption>
|
||||
<regmode_w>None</regmode_w>
|
||||
</InputOption>
|
||||
<EndianOption>
|
||||
<endian>Big</endian>
|
||||
</EndianOption>
|
||||
<SyncClockOption>
|
||||
<sync_clk>true</sync_clk>
|
||||
<SSROVERCE>false</SSROVERCE>
|
||||
</SyncClockOption>
|
||||
<ECC>
|
||||
<ecc_is_enable>false</ecc_is_enable>
|
||||
<ecc_is_de_enable>false</ecc_is_de_enable>
|
||||
</ECC>
|
||||
</FIFOConfig>
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/************************************************************\
|
||||
** Copyright (c) 2011-2021 Anlogic, Inc.
|
||||
** All Right Reserved.
|
||||
\************************************************************/
|
||||
/************************************************************\
|
||||
** Log : This file is generated by Anlogic IP Generator.
|
||||
** File : D:/project/my_project/I___Anlogic____mipi-to-800x1280-lcd-yingshi____EG4__EG4S20CG324-VIDEO_DEMO-V1.0/project/user_source/hdl_source/dphy_tx_general/d512_w8_fifo.v
|
||||
** Date : 2021 09 27
|
||||
** TD version : 5.0.25750
|
||||
\************************************************************/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module d1024_w8_fifo (
|
||||
rst,
|
||||
di, clk, we,
|
||||
do, re,
|
||||
empty_flag,
|
||||
full_flag
|
||||
);
|
||||
|
||||
input rst;
|
||||
input [7:0] di;
|
||||
input clk, we;
|
||||
input re;
|
||||
|
||||
output [7:0] do;
|
||||
output empty_flag;
|
||||
output full_flag;
|
||||
|
||||
EG_LOGIC_FIFO #(
|
||||
.DATA_WIDTH_W(8),
|
||||
.DATA_WIDTH_R(8),
|
||||
.DATA_DEPTH_W(1024),
|
||||
.DATA_DEPTH_R(1024),
|
||||
.ENDIAN("BIG"),
|
||||
.RESETMODE("SYNC"),
|
||||
.E(0),
|
||||
.F(1024),
|
||||
.ASYNC_RESET_RELEASE("SYNC"))
|
||||
fifo_inst(
|
||||
.rst(rst),
|
||||
.di(di),
|
||||
.clkw(clk),
|
||||
.we(we),
|
||||
.csw(3'b111),
|
||||
.do(do),
|
||||
.clkr(clk),
|
||||
.re(re),
|
||||
.csr(3'b111),
|
||||
.ore(1'b0),
|
||||
.empty_flag(empty_flag),
|
||||
.aempty_flag(),
|
||||
.full_flag(full_flag),
|
||||
.afull_flag()
|
||||
|
||||
);
|
||||
|
||||
endmodule
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,50 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<PLLConfig version="1.0">
|
||||
<GeneralConfig>
|
||||
<Type>PLL</Type>
|
||||
<Device>EG4X20BG256</Device>
|
||||
<create_VHDL>false</create_VHDL>
|
||||
</GeneralConfig>
|
||||
<Page1>
|
||||
<speed_grade>Any</speed_grade>
|
||||
<input_frequency>25.0000000000000000Mhz</input_frequency>
|
||||
<feedback_mode>Normal</feedback_mode>
|
||||
<clk_num>CLKC0</clk_num>
|
||||
<enable_reset>ENABLE</enable_reset>
|
||||
<pll_lock>ENABLE</pll_lock>
|
||||
</Page1>
|
||||
<Page2>
|
||||
<bandwidth_setting>Medium</bandwidth_setting>
|
||||
</Page2>
|
||||
<Page3>
|
||||
<setting>frequncy_setting</setting>
|
||||
<multiplication_factor>1</multiplication_factor>
|
||||
<division_factor>1</division_factor>
|
||||
<clocks>
|
||||
<clock>
|
||||
<id>0</id>
|
||||
<clock_division_factor>42</clock_division_factor>
|
||||
<clock_frequency>25.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>0.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
<clock>
|
||||
<id>1</id>
|
||||
<clock_division_factor>7</clock_division_factor>
|
||||
<clock_frequency>150.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>0.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
<clock>
|
||||
<id>2</id>
|
||||
<clock_division_factor>7</clock_division_factor>
|
||||
<clock_frequency>150.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>90.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
<clock>
|
||||
<id>3</id>
|
||||
<clock_division_factor>7</clock_division_factor>
|
||||
<clock_frequency>150.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>180.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
</clocks>
|
||||
</Page3>
|
||||
</PLLConfig>
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/************************************************************\
|
||||
** Copyright (c) 2011-2021 Anlogic, Inc.
|
||||
** All Right Reserved.
|
||||
\************************************************************/
|
||||
/************************************************************\
|
||||
** Log : This file is generated by Anlogic IP Generator.
|
||||
** File : F:/app/AE_APUG/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d_v2/prj/al_ip/clk_pll.v
|
||||
** Date : 2022 02 23
|
||||
** TD version : 5.0.43066
|
||||
\************************************************************/
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Input frequency: 25.000Mhz
|
||||
// Clock multiplication factor: 1
|
||||
// Clock division factor: 1
|
||||
// Clock information:
|
||||
// Clock name | Frequency | Phase shift
|
||||
// C0 | 25.000000 MHZ | 0 DEG
|
||||
// C1 | 150.000000MHZ | 0 DEG
|
||||
// C2 | 150.000000MHZ | 90 DEG
|
||||
// C3 | 150.000000MHZ | 180DEG
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1 ns / 100 fs
|
||||
|
||||
module clk_pll(refclk,
|
||||
reset,
|
||||
extlock,
|
||||
clk0_out,
|
||||
clk1_out,
|
||||
clk2_out,
|
||||
clk3_out);
|
||||
|
||||
input refclk;
|
||||
input reset;
|
||||
output extlock;
|
||||
output clk0_out;
|
||||
output clk1_out;
|
||||
output clk2_out;
|
||||
output clk3_out;
|
||||
|
||||
wire clk0_buf;
|
||||
|
||||
EG_LOGIC_BUFG bufg_feedback( .i(clk0_buf), .o(clk0_out) );
|
||||
|
||||
EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
|
||||
.DYNCFG("DISABLE"),
|
||||
.FIN("25.000"),
|
||||
.FEEDBK_MODE("NORMAL"),
|
||||
.FEEDBK_PATH("CLKC0_EXT"),
|
||||
.STDBY_ENABLE("DISABLE"),
|
||||
.PLLRST_ENA("ENABLE"),
|
||||
.SYNC_ENABLE("DISABLE"),
|
||||
.DERIVE_PLL_CLOCKS("DISABLE"),
|
||||
.GEN_BASIC_CLOCK("DISABLE"),
|
||||
.GMC_GAIN(2),
|
||||
.ICP_CURRENT(9),
|
||||
.KVCO(2),
|
||||
.LPF_CAPACITOR(1),
|
||||
.LPF_RESISTOR(8),
|
||||
.REFCLK_DIV(1),
|
||||
.FBCLK_DIV(1),
|
||||
.CLKC0_ENABLE("ENABLE"),
|
||||
.CLKC0_DIV(42),
|
||||
.CLKC0_CPHASE(41),
|
||||
.CLKC0_FPHASE(0),
|
||||
.CLKC1_ENABLE("ENABLE"),
|
||||
.CLKC1_DIV(7),
|
||||
.CLKC1_CPHASE(6),
|
||||
.CLKC1_FPHASE(0),
|
||||
.CLKC2_ENABLE("ENABLE"),
|
||||
.CLKC2_DIV(7),
|
||||
.CLKC2_CPHASE(7),
|
||||
.CLKC2_FPHASE(6),
|
||||
.CLKC3_ENABLE("ENABLE"),
|
||||
.CLKC3_DIV(7),
|
||||
.CLKC3_CPHASE(2),
|
||||
.CLKC3_FPHASE(4) )
|
||||
pll_inst (.refclk(refclk),
|
||||
.reset(reset),
|
||||
.stdby(1'b0),
|
||||
.extlock(extlock),
|
||||
.load_reg(1'b0),
|
||||
.psclk(1'b0),
|
||||
.psdown(1'b0),
|
||||
.psstep(1'b0),
|
||||
.psclksel(3'b000),
|
||||
.psdone(open),
|
||||
.dclk(1'b0),
|
||||
.dcs(1'b0),
|
||||
.dwe(1'b0),
|
||||
.di(8'b00000000),
|
||||
.daddr(6'b000000),
|
||||
.do({open, open, open, open, open, open, open, open}),
|
||||
.fbclk(clk0_out),
|
||||
.clkc({open, clk3_out, clk2_out, clk1_out, clk0_buf}));
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
// Verilog netlist created by TD v5.0.43066
|
||||
// Wed Feb 23 12:03:22 2022
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
module clk_pll // clk_pll.v(25)
|
||||
(
|
||||
refclk,
|
||||
reset,
|
||||
clk0_out,
|
||||
clk1_out,
|
||||
clk2_out,
|
||||
clk3_out,
|
||||
extlock
|
||||
);
|
||||
|
||||
input refclk; // clk_pll.v(33)
|
||||
input reset; // clk_pll.v(34)
|
||||
output clk0_out; // clk_pll.v(36)
|
||||
output clk1_out; // clk_pll.v(37)
|
||||
output clk2_out; // clk_pll.v(38)
|
||||
output clk3_out; // clk_pll.v(39)
|
||||
output extlock; // clk_pll.v(35)
|
||||
|
||||
wire clk0_buf; // clk_pll.v(41)
|
||||
|
||||
EG_PHY_GCLK bufg_feedback (
|
||||
.clki(clk0_buf),
|
||||
.clko(clk0_out)); // clk_pll.v(43)
|
||||
EG_PHY_CONFIG #(
|
||||
.DONE_PERSISTN("ENABLE"),
|
||||
.INIT_PERSISTN("ENABLE"),
|
||||
.JTAG_PERSISTN("DISABLE"),
|
||||
.PROGRAMN_PERSISTN("DISABLE"))
|
||||
config_inst ();
|
||||
EG_PHY_PLL #(
|
||||
.CLKC0_CPHASE(41),
|
||||
.CLKC0_DIV(42),
|
||||
.CLKC0_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC0_ENABLE("ENABLE"),
|
||||
.CLKC0_FPHASE(0),
|
||||
.CLKC1_CPHASE(6),
|
||||
.CLKC1_DIV(7),
|
||||
.CLKC1_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC1_ENABLE("ENABLE"),
|
||||
.CLKC1_FPHASE(0),
|
||||
.CLKC2_CPHASE(7),
|
||||
.CLKC2_DIV(7),
|
||||
.CLKC2_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC2_ENABLE("ENABLE"),
|
||||
.CLKC2_FPHASE(6),
|
||||
.CLKC3_CPHASE(2),
|
||||
.CLKC3_DIV(7),
|
||||
.CLKC3_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC3_ENABLE("ENABLE"),
|
||||
.CLKC3_FPHASE(4),
|
||||
.CLKC4_CPHASE(1),
|
||||
.CLKC4_DIV(1),
|
||||
.CLKC4_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC4_ENABLE("DISABLE"),
|
||||
.CLKC4_FPHASE(0),
|
||||
.DERIVE_PLL_CLOCKS("DISABLE"),
|
||||
.DPHASE_SOURCE("DISABLE"),
|
||||
.DYNCFG("DISABLE"),
|
||||
.FBCLK_DIV(1),
|
||||
.FEEDBK_MODE("NORMAL"),
|
||||
.FEEDBK_PATH("CLKC0_EXT"),
|
||||
.FIN("25.000"),
|
||||
.FREQ_LOCK_ACCURACY(2),
|
||||
.GEN_BASIC_CLOCK("DISABLE"),
|
||||
.GMC_GAIN(2),
|
||||
.GMC_TEST(14),
|
||||
.ICP_CURRENT(9),
|
||||
.IF_ESCLKSTSW("DISABLE"),
|
||||
.INTFB_WAKE("DISABLE"),
|
||||
.KVCO(2),
|
||||
.LPF_CAPACITOR(1),
|
||||
.LPF_RESISTOR(8),
|
||||
.NORESET("DISABLE"),
|
||||
.ODIV_MUXC0("DIV"),
|
||||
.ODIV_MUXC1("DIV"),
|
||||
.ODIV_MUXC2("DIV"),
|
||||
.ODIV_MUXC3("DIV"),
|
||||
.ODIV_MUXC4("DIV"),
|
||||
.PLLC2RST_ENA("DISABLE"),
|
||||
.PLLC34RST_ENA("DISABLE"),
|
||||
.PLLMRST_ENA("DISABLE"),
|
||||
.PLLRST_ENA("ENABLE"),
|
||||
.PLL_LOCK_MODE(0),
|
||||
.PREDIV_MUXC0("VCO"),
|
||||
.PREDIV_MUXC1("VCO"),
|
||||
.PREDIV_MUXC2("VCO"),
|
||||
.PREDIV_MUXC3("VCO"),
|
||||
.PREDIV_MUXC4("VCO"),
|
||||
.REFCLK_DIV(1),
|
||||
.REFCLK_SEL("INTERNAL"),
|
||||
.STDBY_ENABLE("DISABLE"),
|
||||
.STDBY_VCO_ENA("DISABLE"),
|
||||
.SYNC_ENABLE("DISABLE"),
|
||||
.VCO_NORESET("DISABLE"))
|
||||
pll_inst (
|
||||
.daddr(6'b000000),
|
||||
.dclk(1'b0),
|
||||
.dcs(1'b0),
|
||||
.di(8'b00000000),
|
||||
.dwe(1'b0),
|
||||
.fbclk(clk0_out),
|
||||
.load_reg(1'b0),
|
||||
.psclk(1'b0),
|
||||
.psclksel(3'b000),
|
||||
.psdown(1'b0),
|
||||
.psstep(1'b0),
|
||||
.refclk(refclk),
|
||||
.reset(reset),
|
||||
.stdby(1'b0),
|
||||
.clkc({open_n47,clk3_out,clk2_out,clk1_out,clk0_buf}),
|
||||
.extlock(extlock)); // clk_pll.v(78)
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DRAMConfig>
|
||||
<GeneralConfig>
|
||||
<Type>EG_LOGIC_DRAM</Type>
|
||||
<Device>EG4D20EG176</Device>
|
||||
<create_VHDL>false</create_VHDL>
|
||||
<inst>dram_16x1</inst>
|
||||
</GeneralConfig>
|
||||
<WriteMemorySize>
|
||||
<depth_a>16</depth_a>
|
||||
<width_a>1</width_a>
|
||||
</WriteMemorySize>
|
||||
<ReadMemorySize>
|
||||
<depth_b>16</depth_b>
|
||||
<width_b>1</width_b>
|
||||
</ReadMemorySize>
|
||||
<MemoryInitialization/>
|
||||
</DRAMConfig>
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/************************************************************\
|
||||
** Copyright (c) 2011-2021 Anlogic, Inc.
|
||||
** All Right Reserved.
|
||||
\************************************************************/
|
||||
/************************************************************\
|
||||
** Log : This file is generated by Anlogic IP Generator.
|
||||
** File : F:/app/anlogic_apug/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d_v2/prj/al_ip/dram_16x1.v
|
||||
** Date : 2021 02 18
|
||||
** TD version : 5.0.25878
|
||||
\************************************************************/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module dram_16x1 ( di, waddr, we, wclk, do, raddr );
|
||||
|
||||
parameter DATA_WIDTH_W = 1;
|
||||
parameter ADDR_WIDTH_W = 4;
|
||||
parameter DATA_DEPTH_W = 16;
|
||||
parameter DATA_WIDTH_R = 1;
|
||||
parameter ADDR_WIDTH_R = 4;
|
||||
parameter DATA_DEPTH_R = 16;
|
||||
|
||||
input [DATA_WIDTH_W-1:0] di;
|
||||
input [ADDR_WIDTH_W-1:0] waddr;
|
||||
input [ADDR_WIDTH_R-1:0] raddr;
|
||||
input wclk,we;
|
||||
|
||||
output [DATA_WIDTH_R-1:0] do;
|
||||
|
||||
|
||||
|
||||
EG_LOGIC_DRAM #(
|
||||
.INIT_FILE("NONE"),
|
||||
.DATA_WIDTH_W(DATA_WIDTH_W),
|
||||
.ADDR_WIDTH_W(ADDR_WIDTH_W),
|
||||
.DATA_DEPTH_W(DATA_DEPTH_W),
|
||||
.DATA_WIDTH_R(DATA_WIDTH_R),
|
||||
.ADDR_WIDTH_R(ADDR_WIDTH_R),
|
||||
.DATA_DEPTH_R(DATA_DEPTH_R))
|
||||
dram(
|
||||
.di(di),
|
||||
.waddr(waddr),
|
||||
.wclk(wclk),
|
||||
.we(we),
|
||||
.do(do),
|
||||
.raddr(raddr));
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
// Verilog netlist created by TD v5.0.25878
|
||||
// Thu Feb 18 11:05:27 2021
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
module dram_16x1 // dram_16x1.v(14)
|
||||
(
|
||||
di,
|
||||
raddr,
|
||||
waddr,
|
||||
wclk,
|
||||
we,
|
||||
do
|
||||
);
|
||||
|
||||
input [0:0] di; // dram_16x1.v(23)
|
||||
input [3:0] raddr; // dram_16x1.v(25)
|
||||
input [3:0] waddr; // dram_16x1.v(24)
|
||||
input wclk; // dram_16x1.v(26)
|
||||
input we; // dram_16x1.v(26)
|
||||
output [0:0] do; // dram_16x1.v(28)
|
||||
|
||||
parameter ADDR_WIDTH_R = 4;
|
||||
parameter ADDR_WIDTH_W = 4;
|
||||
parameter DATA_DEPTH_R = 16;
|
||||
parameter DATA_DEPTH_W = 16;
|
||||
parameter DATA_WIDTH_R = 1;
|
||||
parameter DATA_WIDTH_W = 1;
|
||||
|
||||
EG_PHY_CONFIG #(
|
||||
.DONE_PERSISTN("ENABLE"),
|
||||
.INIT_PERSISTN("ENABLE"),
|
||||
.JTAG_PERSISTN("DISABLE"),
|
||||
.PROGRAMN_PERSISTN("DISABLE"))
|
||||
config_inst ();
|
||||
EG_LOGIC_DRAM16X4 dram_c0 (
|
||||
.di({3'b000,di}),
|
||||
.raddr(raddr),
|
||||
.waddr(waddr),
|
||||
.wclk(wclk),
|
||||
.we(we),
|
||||
.do({open_n47,open_n48,open_n49,do}));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<PLLConfig version="1.0">
|
||||
<GeneralConfig>
|
||||
<Type>PLL</Type>
|
||||
<Device>EG4X20BG256</Device>
|
||||
<create_VHDL>false</create_VHDL>
|
||||
</GeneralConfig>
|
||||
<Page1>
|
||||
<speed_grade>Any</speed_grade>
|
||||
<input_frequency>25.0000000000000000Mhz</input_frequency>
|
||||
<feedback_mode>Normal</feedback_mode>
|
||||
<clk_num>CLKC0</clk_num>
|
||||
<enable_reset>ENABLE</enable_reset>
|
||||
<pll_lock>ENABLE</pll_lock>
|
||||
</Page1>
|
||||
<Page2>
|
||||
<bandwidth_setting>Medium</bandwidth_setting>
|
||||
</Page2>
|
||||
<Page3>
|
||||
<setting>frequncy_setting</setting>
|
||||
<multiplication_factor>1</multiplication_factor>
|
||||
<division_factor>1</division_factor>
|
||||
<clocks>
|
||||
<clock>
|
||||
<id>0</id>
|
||||
<clock_division_factor>42</clock_division_factor>
|
||||
<clock_frequency>25.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>0.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
<clock>
|
||||
<id>1</id>
|
||||
<clock_division_factor>7</clock_division_factor>
|
||||
<clock_frequency>150.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>0.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
<clock>
|
||||
<id>2</id>
|
||||
<clock_division_factor>7</clock_division_factor>
|
||||
<clock_frequency>150.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>90.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
<clock>
|
||||
<id>3</id>
|
||||
<clock_division_factor>7</clock_division_factor>
|
||||
<clock_frequency>150.0000000000000000Mhz</clock_frequency>
|
||||
<phase_shift>180.0000000000000000deg</phase_shift>
|
||||
</clock>
|
||||
</clocks>
|
||||
</Page3>
|
||||
</PLLConfig>
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/************************************************************\
|
||||
** Copyright (c) 2011-2021 Anlogic, Inc.
|
||||
** All Right Reserved.
|
||||
\************************************************************/
|
||||
/************************************************************\
|
||||
** Log : This file is generated by Anlogic IP Generator.
|
||||
** File : F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/eg4_pll.v
|
||||
** Date : 2021 01 21
|
||||
** TD version : 5.0.25878
|
||||
\************************************************************/
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Input frequency: 25.000Mhz
|
||||
// Clock multiplication factor: 1
|
||||
// Clock division factor: 1
|
||||
// Clock information:
|
||||
// Clock name | Frequency | Phase shift
|
||||
// C0 | 25.000000 MHZ | 0 DEG
|
||||
// C1 | 150.000000MHZ | 0 DEG
|
||||
// C2 | 150.000000MHZ | 90 DEG
|
||||
// C3 | 150.000000MHZ | 180DEG
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1 ns / 100 fs
|
||||
|
||||
module eg4_pll(refclk,
|
||||
reset,
|
||||
extlock,
|
||||
clk0_out,
|
||||
clk1_out,
|
||||
clk2_out,
|
||||
clk3_out);
|
||||
|
||||
input refclk;
|
||||
input reset;
|
||||
output extlock;
|
||||
output clk0_out;
|
||||
output clk1_out;
|
||||
output clk2_out;
|
||||
output clk3_out;
|
||||
|
||||
wire clk0_buf;
|
||||
|
||||
EG_LOGIC_BUFG bufg_feedback( .i(clk0_buf), .o(clk0_out) );
|
||||
|
||||
EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
|
||||
.DYNCFG("DISABLE"),
|
||||
.FIN("25.000"),
|
||||
.FEEDBK_MODE("NORMAL"),
|
||||
.FEEDBK_PATH("CLKC0_EXT"),
|
||||
.STDBY_ENABLE("DISABLE"),
|
||||
.PLLRST_ENA("ENABLE"),
|
||||
.SYNC_ENABLE("DISABLE"),
|
||||
.DERIVE_PLL_CLOCKS("DISABLE"),
|
||||
.GEN_BASIC_CLOCK("DISABLE"),
|
||||
.GMC_GAIN(2),
|
||||
.ICP_CURRENT(9),
|
||||
.KVCO(2),
|
||||
.LPF_CAPACITOR(1),
|
||||
.LPF_RESISTOR(8),
|
||||
.REFCLK_DIV(1),
|
||||
.FBCLK_DIV(1),
|
||||
.CLKC0_ENABLE("ENABLE"),
|
||||
.CLKC0_DIV(42),
|
||||
.CLKC0_CPHASE(41),
|
||||
.CLKC0_FPHASE(0),
|
||||
.CLKC1_ENABLE("ENABLE"),
|
||||
.CLKC1_DIV(7),
|
||||
.CLKC1_CPHASE(6),
|
||||
.CLKC1_FPHASE(0),
|
||||
.CLKC2_ENABLE("ENABLE"),
|
||||
.CLKC2_DIV(7),
|
||||
.CLKC2_CPHASE(7),
|
||||
.CLKC2_FPHASE(6),
|
||||
.CLKC3_ENABLE("ENABLE"),
|
||||
.CLKC3_DIV(7),
|
||||
.CLKC3_CPHASE(2),
|
||||
.CLKC3_FPHASE(4) )
|
||||
pll_inst (.refclk(refclk),
|
||||
.reset(reset),
|
||||
.stdby(1'b0),
|
||||
.extlock(extlock),
|
||||
.load_reg(1'b0),
|
||||
.psclk(1'b0),
|
||||
.psdown(1'b0),
|
||||
.psstep(1'b0),
|
||||
.psclksel(3'b000),
|
||||
.psdone(open),
|
||||
.dclk(1'b0),
|
||||
.dcs(1'b0),
|
||||
.dwe(1'b0),
|
||||
.di(8'b00000000),
|
||||
.daddr(6'b000000),
|
||||
.do({open, open, open, open, open, open, open, open}),
|
||||
.fbclk(clk0_out),
|
||||
.clkc({open, clk3_out, clk2_out, clk1_out, clk0_buf}));
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
// Verilog netlist created by TD v5.0.25878
|
||||
// Thu Jan 21 09:44:21 2021
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
module eg4_pll // eg4_pll.v(25)
|
||||
(
|
||||
refclk,
|
||||
reset,
|
||||
clk0_out,
|
||||
clk1_out,
|
||||
clk2_out,
|
||||
clk3_out,
|
||||
extlock
|
||||
);
|
||||
|
||||
input refclk; // eg4_pll.v(33)
|
||||
input reset; // eg4_pll.v(34)
|
||||
output clk0_out; // eg4_pll.v(36)
|
||||
output clk1_out; // eg4_pll.v(37)
|
||||
output clk2_out; // eg4_pll.v(38)
|
||||
output clk3_out; // eg4_pll.v(39)
|
||||
output extlock; // eg4_pll.v(35)
|
||||
|
||||
wire clk0_buf; // eg4_pll.v(41)
|
||||
|
||||
EG_PHY_GCLK bufg_feedback (
|
||||
.clki(clk0_buf),
|
||||
.clko(clk0_out)); // eg4_pll.v(43)
|
||||
EG_PHY_CONFIG #(
|
||||
.DONE_PERSISTN("ENABLE"),
|
||||
.INIT_PERSISTN("ENABLE"),
|
||||
.JTAG_PERSISTN("DISABLE"),
|
||||
.PROGRAMN_PERSISTN("DISABLE"))
|
||||
config_inst ();
|
||||
EG_PHY_PLL #(
|
||||
.CLKC0_CPHASE(41),
|
||||
.CLKC0_DIV(42),
|
||||
.CLKC0_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC0_ENABLE("ENABLE"),
|
||||
.CLKC0_FPHASE(0),
|
||||
.CLKC1_CPHASE(6),
|
||||
.CLKC1_DIV(7),
|
||||
.CLKC1_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC1_ENABLE("ENABLE"),
|
||||
.CLKC1_FPHASE(0),
|
||||
.CLKC2_CPHASE(7),
|
||||
.CLKC2_DIV(7),
|
||||
.CLKC2_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC2_ENABLE("ENABLE"),
|
||||
.CLKC2_FPHASE(6),
|
||||
.CLKC3_CPHASE(2),
|
||||
.CLKC3_DIV(7),
|
||||
.CLKC3_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC3_ENABLE("ENABLE"),
|
||||
.CLKC3_FPHASE(4),
|
||||
.CLKC4_CPHASE(1),
|
||||
.CLKC4_DIV(1),
|
||||
.CLKC4_DIV2_ENABLE("DISABLE"),
|
||||
.CLKC4_ENABLE("DISABLE"),
|
||||
.CLKC4_FPHASE(0),
|
||||
.DERIVE_PLL_CLOCKS("DISABLE"),
|
||||
.DPHASE_SOURCE("DISABLE"),
|
||||
.DYNCFG("DISABLE"),
|
||||
.FBCLK_DIV(1),
|
||||
.FEEDBK_MODE("NORMAL"),
|
||||
.FEEDBK_PATH("CLKC0_EXT"),
|
||||
.FIN("25.000"),
|
||||
.FREQ_LOCK_ACCURACY(2),
|
||||
.GEN_BASIC_CLOCK("DISABLE"),
|
||||
.GMC_GAIN(2),
|
||||
.GMC_TEST(14),
|
||||
.ICP_CURRENT(9),
|
||||
.IF_ESCLKSTSW("DISABLE"),
|
||||
.INTFB_WAKE("DISABLE"),
|
||||
.KVCO(2),
|
||||
.LPF_CAPACITOR(1),
|
||||
.LPF_RESISTOR(8),
|
||||
.NORESET("DISABLE"),
|
||||
.ODIV_MUXC0("DIV"),
|
||||
.ODIV_MUXC1("DIV"),
|
||||
.ODIV_MUXC2("DIV"),
|
||||
.ODIV_MUXC3("DIV"),
|
||||
.ODIV_MUXC4("DIV"),
|
||||
.PLLC2RST_ENA("DISABLE"),
|
||||
.PLLC34RST_ENA("DISABLE"),
|
||||
.PLLMRST_ENA("DISABLE"),
|
||||
.PLLRST_ENA("ENABLE"),
|
||||
.PLL_LOCK_MODE(0),
|
||||
.PREDIV_MUXC0("VCO"),
|
||||
.PREDIV_MUXC1("VCO"),
|
||||
.PREDIV_MUXC2("VCO"),
|
||||
.PREDIV_MUXC3("VCO"),
|
||||
.PREDIV_MUXC4("VCO"),
|
||||
.REFCLK_DIV(1),
|
||||
.REFCLK_SEL("INTERNAL"),
|
||||
.STDBY_ENABLE("DISABLE"),
|
||||
.STDBY_VCO_ENA("DISABLE"),
|
||||
.SYNC_ENABLE("DISABLE"),
|
||||
.VCO_NORESET("DISABLE"))
|
||||
pll_inst (
|
||||
.daddr(6'b000000),
|
||||
.dclk(1'b0),
|
||||
.dcs(1'b0),
|
||||
.di(8'b00000000),
|
||||
.dwe(1'b0),
|
||||
.fbclk(clk0_out),
|
||||
.load_reg(1'b0),
|
||||
.psclk(1'b0),
|
||||
.psclksel(3'b000),
|
||||
.psdown(1'b0),
|
||||
.psstep(1'b0),
|
||||
.refclk(refclk),
|
||||
.reset(reset),
|
||||
.stdby(1'b0),
|
||||
.clkc({open_n47,clk3_out,clk2_out,clk1_out,clk0_buf}),
|
||||
.extlock(extlock)); // eg4_pll.v(78)
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,132 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Project Version="1" Path="F:/app/AE_APUG/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d_v2/prj">
|
||||
<Project_Created_Time></Project_Created_Time>
|
||||
<TD_Encoding>UTF-8</TD_Encoding>
|
||||
<TD_Version>5.0.43066</TD_Version>
|
||||
<UCode>01000000</UCode>
|
||||
<Name>sdram_as_ram</Name>
|
||||
<HardWare>
|
||||
<Family>EG4</Family>
|
||||
<Device>EG4D20EG176</Device>
|
||||
</HardWare>
|
||||
<Source_Files>
|
||||
<Verilog>
|
||||
<File Path="al_ip/clk_pll.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../source_code/rtl/app_wrrd.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="2"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../source_code/rtl/top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="3"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../source_code/include/global_def.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="4"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="al_ip/dram_16x1.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="5"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../source_code/rtl/enc_file/ddr1_as_ram.enc.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="7"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../source_code/rtl/enc_file/ddr1_init_ref.enc.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="8"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../source_code/rtl/enc_file/ddr1_wrrd.enc.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="9"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</Verilog>
|
||||
<ADC_FILE>
|
||||
<File Path="../source_code/adcsdc/io.adc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="constrain_1"/>
|
||||
<Attr Name="CompileOrder" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</ADC_FILE>
|
||||
<SDC_FILE>
|
||||
<File Path="../source_code/adcsdc/io.sdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="constrain_1"/>
|
||||
<Attr Name="CompileOrder" Val="2"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</SDC_FILE>
|
||||
<CWC_FILE>
|
||||
<File Path="dbg.cwc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="6"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</CWC_FILE>
|
||||
</Source_Files>
|
||||
<FileSets>
|
||||
<FileSet Name="constrain_1" Type="ConstrainFiles">
|
||||
</FileSet>
|
||||
<FileSet Name="design_1" Type="DesignFiles">
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<TOP_MODULE>
|
||||
<LABEL></LABEL>
|
||||
<MODULE>top</MODULE>
|
||||
<CREATEINDEX>user</CREATEINDEX>
|
||||
</TOP_MODULE>
|
||||
<Property>
|
||||
</Property>
|
||||
<Device_Settings>
|
||||
</Device_Settings>
|
||||
<Configurations>
|
||||
</Configurations>
|
||||
<Project_Settings>
|
||||
<Step_Last_Change>2022-02-23 13:48:12.879</Step_Last_Change>
|
||||
<Current_Step>60</Current_Step>
|
||||
<Step_Status>true</Step_Status>
|
||||
</Project_Settings>
|
||||
</Project>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,43 @@
|
|||
standard
|
||||
***Report Model: top***
|
||||
|
||||
IO Statistics
|
||||
#IO 2
|
||||
#input 1
|
||||
#output 1
|
||||
#inout 0
|
||||
|
||||
LUT Statistics
|
||||
#Total_luts 259
|
||||
#lut4 123
|
||||
#lut5 30
|
||||
#lut6 0
|
||||
#lut5_mx41 0
|
||||
#lut4_alu1b 106
|
||||
|
||||
Utilization Statistics
|
||||
#lut 259 out of 19600 1.32%
|
||||
#reg 870 out of 19600 4.44%
|
||||
#le 0
|
||||
#dsp 0 out of 29 0.00%
|
||||
#bram 0 out of 64 0.00%
|
||||
#bram9k 0
|
||||
#fifo9k 0
|
||||
#bram32k 0 out of 16 0.00%
|
||||
#pad 2 out of 130 1.54%
|
||||
#ireg 0
|
||||
#oreg 0
|
||||
#treg 0
|
||||
#pll 1 out of 4 25.00%
|
||||
|
||||
Report Hierarchy Area:
|
||||
+-----------------------------------------------------------------------------------------------+
|
||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||
+-----------------------------------------------------------------------------------------------+
|
||||
|top |top |153 |106 |870 |0 |0 |
|
||||
| u0_clk |clk_pll |0 |0 |0 |0 |0 |
|
||||
| u1_app_wrrd |app_wrrd |37 |78 |142 |0 |0 |
|
||||
| u2_ram |ddr1_as_ram(self_refresh_open=1'b0) |114 |19 |720 |0 |0 |
|
||||
| u1_init_ref |ddr1_init_ref(self_refresh_open=1'b0) |39 |19 |69 |0 |0 |
|
||||
| u2_wrrd |ddr1_wrrd |75 |0 |651 |0 |0 |
|
||||
+-----------------------------------------------------------------------------------------------+
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,378 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<All_Bram_Infos>
|
||||
<Ucode>01000000</Ucode>
|
||||
<AL_PHY_BRAM>
|
||||
<INST_1>
|
||||
<rid>0X0004</rid>
|
||||
<wid>0X0004</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_000000_000</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>0</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_1>
|
||||
<INST_2>
|
||||
<rid>0X0005</rid>
|
||||
<wid>0X0005</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_000000_009</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>9</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_2>
|
||||
<INST_3>
|
||||
<rid>0X0006</rid>
|
||||
<wid>0X0006</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_000000_018</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>18</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_3>
|
||||
<INST_4>
|
||||
<rid>0X0007</rid>
|
||||
<wid>0X0007</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_000000_027</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>27</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_4>
|
||||
<INST_5>
|
||||
<rid>0X0008</rid>
|
||||
<wid>0X0008</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_000000_036</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>36</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_5>
|
||||
<INST_6>
|
||||
<rid>0X0009</rid>
|
||||
<wid>0X0009</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_000000_045</name>
|
||||
<width_a>4</width_a>
|
||||
<width_b>4</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>45</data_offset>
|
||||
<depth>2048</depth>
|
||||
<width>4</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>4</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>2048</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>4</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_6>
|
||||
<INST_7>
|
||||
<rid>0X000A</rid>
|
||||
<wid>0X000A</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_000000_049</name>
|
||||
<width_a>4</width_a>
|
||||
<width_b>4</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>49</data_offset>
|
||||
<depth>2048</depth>
|
||||
<width>2</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>2</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>2048</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>4</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_7>
|
||||
<INST_8>
|
||||
<rid>0X000B</rid>
|
||||
<wid>0X000B</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_001024_000</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>1024</address_offset>
|
||||
<data_offset>0</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_8>
|
||||
<INST_9>
|
||||
<rid>0X000C</rid>
|
||||
<wid>0X000C</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_001024_009</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>1024</address_offset>
|
||||
<data_offset>9</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_9>
|
||||
<INST_10>
|
||||
<rid>0X000D</rid>
|
||||
<wid>0X000D</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_001024_018</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>1024</address_offset>
|
||||
<data_offset>18</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_10>
|
||||
<INST_11>
|
||||
<rid>0X000E</rid>
|
||||
<wid>0X000E</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_001024_027</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>1024</address_offset>
|
||||
<data_offset>27</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_11>
|
||||
<INST_12>
|
||||
<rid>0X000F</rid>
|
||||
<wid>0X000F</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_2048x51_sub_001024_036</name>
|
||||
<width_a>9</width_a>
|
||||
<width_b>9</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>51</logic_width>
|
||||
<logic_depth>2048</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>1024</address_offset>
|
||||
<data_offset>36</data_offset>
|
||||
<depth>1024</depth>
|
||||
<width>9</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>51</section_size>
|
||||
<width_per_section>9</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>1024</depth>
|
||||
<mode_type>110</mode_type>
|
||||
<width>9</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_12>
|
||||
</AL_PHY_BRAM>
|
||||
</All_Bram_Infos>
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
standard
|
||||
***Report Model: top***
|
||||
|
||||
IO Statistics
|
||||
#IO 2
|
||||
#input 1
|
||||
#output 1
|
||||
#inout 0
|
||||
|
||||
Utilization Statistics
|
||||
#lut 554 out of 19600 2.83%
|
||||
#reg 1029 out of 19600 5.25%
|
||||
#le 1248
|
||||
#lut only 219 out of 1248 17.55%
|
||||
#reg only 694 out of 1248 55.61%
|
||||
#lut® 335 out of 1248 26.84%
|
||||
#dsp 0 out of 29 0.00%
|
||||
#bram 12 out of 64 18.75%
|
||||
#bram9k 12
|
||||
#fifo9k 0
|
||||
#bram32k 0 out of 16 0.00%
|
||||
#pad 2 out of 130 1.54%
|
||||
#ireg 0
|
||||
#oreg 0
|
||||
#treg 0
|
||||
#pll 1 out of 4 25.00%
|
||||
#gclk 7 out of 16 43.75%
|
||||
|
||||
|
||||
Detailed IO Report
|
||||
|
||||
Name Direction Location IOStandard DriveStrength PullType PackReg
|
||||
SYS_CLK INPUT P26 LVCMOS25 N/A NONE NONE
|
||||
LED OUTPUT P162 LVCMOS25 8 NONE NONE
|
||||
|
||||
Report Hierarchy Area:
|
||||
+----------------------------------------------------------------+
|
||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||
+----------------------------------------------------------------+
|
||||
|top |top |1248 |462 |92 |1029 |12 |0 |
|
||||
+----------------------------------------------------------------+
|
||||
|
||||
|
||||
DataNet Average Fanout:
|
||||
|
||||
Index Fanout Nets
|
||||
#1 1 1077
|
||||
#2 2 216
|
||||
#3 3 74
|
||||
#4 4 52
|
||||
#5 5-10 28
|
||||
#6 11-50 41
|
||||
#7 51-100 2
|
||||
Average 2.00
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,409 @@
|
|||
eagle_s20
|
||||
12 1218 923 2046 7358 0 0
|
||||
0.151 0.152 top eagle_s20 EQFP176 Detail 11 4
|
||||
clock: clk
|
||||
12 86 24 2
|
||||
Setup check
|
||||
22 3
|
||||
Endpoint: reg0_b0|reg0_b4
|
||||
22 37.006000 5 3
|
||||
Timing path: reg0_b1|reg0_b2.clk->reg0_b0|reg0_b4
|
||||
reg0_b1|reg0_b2.clk
|
||||
reg0_b0|reg0_b4
|
||||
24 37.006000 44.311000 7.305000 2 3
|
||||
rst_cnt[1] add0/ucin_al_u4.a[1]
|
||||
add0/c3 add0/u3_al_u5.fci
|
||||
n0[4] reg0_b0|reg0_b4.mi[0]
|
||||
|
||||
Timing path: reg0_b0|reg0_b4.clk->reg0_b0|reg0_b4
|
||||
reg0_b0|reg0_b4.clk
|
||||
reg0_b0|reg0_b4
|
||||
69 37.179000 44.311000 7.132000 2 3
|
||||
rst_cnt[0] add0/ucin_al_u4.b[0]
|
||||
add0/c3 add0/u3_al_u5.fci
|
||||
n0[4] reg0_b0|reg0_b4.mi[0]
|
||||
|
||||
Timing path: reg0_b1|reg0_b2.clk->reg0_b0|reg0_b4
|
||||
reg0_b1|reg0_b2.clk
|
||||
reg0_b0|reg0_b4
|
||||
114 37.393000 44.311000 6.918000 2 3
|
||||
rst_cnt[2] add0/ucin_al_u4.b[1]
|
||||
add0/c3 add0/u3_al_u5.fci
|
||||
n0[4] reg0_b0|reg0_b4.mi[0]
|
||||
|
||||
|
||||
Endpoint: add0/ucin_al_u4
|
||||
159 37.068000 7 3
|
||||
Timing path: reg0_b1|reg0_b2.clk->add0/ucin_al_u4
|
||||
reg0_b1|reg0_b2.clk
|
||||
add0/ucin_al_u4
|
||||
161 37.068000 44.311000 7.243000 2 3
|
||||
rst_cnt[1] add0/ucin_al_u4.a[1]
|
||||
add0/c3 add0/u3_al_u5.fci
|
||||
n0[6] add0/ucin_al_u4.mi[0]
|
||||
|
||||
Timing path: reg0_b0|reg0_b4.clk->add0/ucin_al_u4
|
||||
reg0_b0|reg0_b4.clk
|
||||
add0/ucin_al_u4
|
||||
206 37.220000 44.311000 7.091000 2 3
|
||||
rst_cnt[0] add0/ucin_al_u4.b[0]
|
||||
add0/c3 add0/u3_al_u5.fci
|
||||
n0[6] add0/ucin_al_u4.mi[0]
|
||||
|
||||
Timing path: reg0_b3|reg0_b5.clk->add0/ucin_al_u4
|
||||
reg0_b3|reg0_b5.clk
|
||||
add0/ucin_al_u4
|
||||
251 37.406000 44.311000 6.905000 1 2
|
||||
rst_cnt[3] add0/u3_al_u5.a[0]
|
||||
n0[6] add0/ucin_al_u4.mi[0]
|
||||
|
||||
|
||||
Endpoint: reg0_b1|reg0_b2
|
||||
294 37.101000 3 3
|
||||
Timing path: reg0_b0|reg0_b4.clk->reg0_b1|reg0_b2
|
||||
reg0_b0|reg0_b4.clk
|
||||
reg0_b1|reg0_b2
|
||||
296 37.101000 44.311000 7.210000 1 2
|
||||
rst_cnt[0] add0/ucin_al_u4.b[0]
|
||||
n0[2] reg0_b1|reg0_b2.mi[0]
|
||||
|
||||
Timing path: reg0_b1|reg0_b2.clk->reg0_b1|reg0_b2
|
||||
reg0_b1|reg0_b2.clk
|
||||
reg0_b1|reg0_b2
|
||||
339 37.433000 44.311000 6.878000 1 2
|
||||
rst_cnt[1] add0/ucin_al_u4.a[1]
|
||||
n0[2] reg0_b1|reg0_b2.mi[0]
|
||||
|
||||
Timing path: reg0_b1|reg0_b2.clk->reg0_b1|reg0_b2
|
||||
reg0_b1|reg0_b2.clk
|
||||
reg0_b1|reg0_b2
|
||||
382 37.837000 44.311000 6.474000 1 2
|
||||
rst_cnt[2] add0/ucin_al_u4.b[1]
|
||||
n0[2] reg0_b1|reg0_b2.mi[0]
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
425 3
|
||||
Endpoint: reg0_b3|reg0_b5
|
||||
427 0.599000 1 1
|
||||
Timing path: add0/ucin_al_u4.clk->reg0_b3|reg0_b5
|
||||
add0/ucin_al_u4.clk
|
||||
reg0_b3|reg0_b5
|
||||
429 0.599000 4.392000 4.991000 0 1
|
||||
rst_cnt[7] reg0_b3|reg0_b5.ce
|
||||
|
||||
|
||||
Endpoint: reg0_b1|reg0_b2
|
||||
470 0.599000 1 1
|
||||
Timing path: add0/ucin_al_u4.clk->reg0_b1|reg0_b2
|
||||
add0/ucin_al_u4.clk
|
||||
reg0_b1|reg0_b2
|
||||
472 0.599000 4.392000 4.991000 0 1
|
||||
rst_cnt[7] reg0_b1|reg0_b2.ce
|
||||
|
||||
|
||||
Endpoint: reg0_b0|reg0_b4
|
||||
513 0.706000 1 1
|
||||
Timing path: add0/ucin_al_u4.clk->reg0_b0|reg0_b4
|
||||
add0/ucin_al_u4.clk
|
||||
reg0_b0|reg0_b4
|
||||
515 0.706000 4.285000 4.991000 0 1
|
||||
rst_cnt[7] reg0_b0|reg0_b4.ce
|
||||
|
||||
|
||||
|
||||
|
||||
clock: u0_clk/pll_inst.clkc[1]
|
||||
556 7200 1950 2
|
||||
Setup check
|
||||
566 3
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12
|
||||
566 2.177000 41 3
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12
|
||||
568 2.177000 8.832000 6.655000 4 5
|
||||
wt_addr_6 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u3_al_u114.b[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c7 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u7_al_u115.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c11 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u11_al_u116.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n12[12] cw_top/wrapper_cwc_top/trigger_inst/_al_u67|cw_top/wrapper_cwc_top/trigger_inst/_al_u69.d[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u69_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12.a[0]
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b1|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b1|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12
|
||||
607 2.285000 8.832000 6.547000 4 6
|
||||
wt_addr_1 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/ucin_al_u113.a[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c3 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u3_al_u114.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c7 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u7_al_u115.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c11 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u11_al_u116.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n12[12] cw_top/wrapper_cwc_top/trigger_inst/_al_u67|cw_top/wrapper_cwc_top/trigger_inst/_al_u69.d[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u69_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12.a[0]
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b4.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b4.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12
|
||||
648 2.312000 8.832000 6.520000 4 5
|
||||
wt_addr_4 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u3_al_u114.b[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c7 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u7_al_u115.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c11 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u11_al_u116.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n12[12] cw_top/wrapper_cwc_top/trigger_inst/_al_u67|cw_top/wrapper_cwc_top/trigger_inst/_al_u69.d[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u69_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b12.a[0]
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg
|
||||
687 2.244000 33 3
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b10.clk->cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b11|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b10.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg
|
||||
689 2.244000 8.832000 6.588000 3 4
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/addr_tmp[11] u2_ram/u1_init_ref/reg1_b3|u2_ram/u1_init_ref/reg1_b4.b[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u19_o u2_ram/u1_init_ref/reg1_b5|u2_ram/u1_init_ref/reg1_b13.b[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u21_o u1_app_wrrd/reg7_b13|u1_app_wrrd/reg7_b11.a[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n6 cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg.ce
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b1|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg.clk->cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b1|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg
|
||||
726 2.455000 8.832000 6.377000 3 4
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/addr_tmp[1] u2_ram/u1_init_ref/reg1_b3|u2_ram/u1_init_ref/reg1_b4.a[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u19_o u2_ram/u1_init_ref/reg1_b5|u2_ram/u1_init_ref/reg1_b13.b[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u21_o u1_app_wrrd/reg7_b13|u1_app_wrrd/reg7_b11.a[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n6 cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg.ce
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.clk->cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg
|
||||
763 2.586000 8.832000 6.246000 3 4
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/addr_tmp[5] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b0|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4.a[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u26_o cw_top/wrapper_cwc_top/trigger_inst/_al_u29.a[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u29_o u1_app_wrrd/reg7_b13|u1_app_wrrd/reg7_b11.c[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n6 cw_top/wrapper_cwc_top/trigger_inst/_al_u32|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/overflow_reg.ce
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14
|
||||
800 2.147000 43 3
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b1|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b1|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14
|
||||
802 2.147000 8.939000 6.792000 4 6
|
||||
wt_addr_1 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/ucin_al_u113.a[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c3 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u3_al_u114.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c7 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u7_al_u115.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c11 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u11_al_u116.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n12[13] cw_top/wrapper_cwc_top/trigger_inst/_al_u67|cw_top/wrapper_cwc_top/trigger_inst/_al_u69.d[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u67_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.a[1]
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b4.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b4.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14
|
||||
843 2.174000 8.939000 6.765000 4 5
|
||||
wt_addr_4 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u3_al_u114.b[0]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c7 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u7_al_u115.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c11 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u11_al_u116.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n12[13] cw_top/wrapper_cwc_top/trigger_inst/_al_u67|cw_top/wrapper_cwc_top/trigger_inst/_al_u69.d[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u67_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.a[1]
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14
|
||||
882 2.253000 8.939000 6.686000 4 5
|
||||
wt_addr_6 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u3_al_u114.b[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c7 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u7_al_u115.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/c11 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/add0/u11_al_u116.fci
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n12[13] cw_top/wrapper_cwc_top/trigger_inst/_al_u67|cw_top/wrapper_cwc_top/trigger_inst/_al_u69.d[1]
|
||||
cw_top/wrapper_cwc_top/trigger_inst/_al_u67_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.a[1]
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
921 3
|
||||
Endpoint: auto_chipwatcher_0_logicbram_2048x51_sub_000000_000
|
||||
923 0.152000 9 3
|
||||
Timing path: u1_app_wrrd/reg6_b0|add5/ucin.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_000
|
||||
u1_app_wrrd/reg6_b0|add5/ucin.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_000
|
||||
925 0.152000 2.395000 2.547000 0 1
|
||||
u1_app_wrrd/init_data[0] auto_chipwatcher_0_logicbram_2048x51_sub_000000_000.dia[3]
|
||||
|
||||
Timing path: u1_app_wrrd/reg6_b10|reg6_b9.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_000
|
||||
u1_app_wrrd/reg6_b10|reg6_b9.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_000
|
||||
956 0.298000 2.395000 2.693000 0 1
|
||||
u1_app_wrrd/init_data[10] auto_chipwatcher_0_logicbram_2048x51_sub_000000_000.dia[4]
|
||||
|
||||
Timing path: u2_ram/u2_wrrd/reg48_b7|u2_ram/u2_wrrd/ctrl_rden_reg.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_000
|
||||
u2_ram/u2_wrrd/reg48_b7|u2_ram/u2_wrrd/ctrl_rden_reg.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_000
|
||||
987 0.392000 2.395000 2.787000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_en auto_chipwatcher_0_logicbram_2048x51_sub_000000_000.dia[2]
|
||||
|
||||
|
||||
Endpoint: auto_chipwatcher_0_logicbram_2048x51_sub_000000_027
|
||||
1018 0.223000 9 3
|
||||
Timing path: _al_u46|u2_ram/u2_wrrd/reg50_b24.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_027
|
||||
_al_u46|u2_ram/u2_wrrd/reg50_b24.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_027
|
||||
1020 0.223000 2.395000 2.618000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[24] auto_chipwatcher_0_logicbram_2048x51_sub_000000_027.dia[8]
|
||||
|
||||
Timing path: u2_ram/u2_wrrd/reg50_b17|u2_ram/u2_wrrd/reg50_b20.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_027
|
||||
u2_ram/u2_wrrd/reg50_b17|u2_ram/u2_wrrd/reg50_b20.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_027
|
||||
1051 0.299000 2.395000 2.694000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[17] auto_chipwatcher_0_logicbram_2048x51_sub_000000_027.dia[0]
|
||||
|
||||
Timing path: u2_ram/u2_wrrd/reg50_b17|u2_ram/u2_wrrd/reg50_b20.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_027
|
||||
u2_ram/u2_wrrd/reg50_b17|u2_ram/u2_wrrd/reg50_b20.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_027
|
||||
1082 0.299000 2.395000 2.694000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[20] auto_chipwatcher_0_logicbram_2048x51_sub_000000_027.dia[4]
|
||||
|
||||
|
||||
Endpoint: auto_chipwatcher_0_logicbram_2048x51_sub_000000_036
|
||||
1113 0.226000 9 3
|
||||
Timing path: u2_ram/u2_wrrd/reg47_b9|u2_ram/u2_wrrd/reg50_b30.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_036
|
||||
u2_ram/u2_wrrd/reg47_b9|u2_ram/u2_wrrd/reg50_b30.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_036
|
||||
1115 0.226000 2.395000 2.621000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[30] auto_chipwatcher_0_logicbram_2048x51_sub_000000_036.dia[6]
|
||||
|
||||
Timing path: u2_ram/u2_wrrd/reg21_b21|u2_ram/u2_wrrd/reg50_b25.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_036
|
||||
u2_ram/u2_wrrd/reg21_b21|u2_ram/u2_wrrd/reg50_b25.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_036
|
||||
1146 0.235000 2.395000 2.630000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[25] auto_chipwatcher_0_logicbram_2048x51_sub_000000_036.dia[0]
|
||||
|
||||
Timing path: u2_ram/u2_wrrd/reg21_b20|u2_ram/u2_wrrd/reg50_b31.clk->auto_chipwatcher_0_logicbram_2048x51_sub_000000_036
|
||||
u2_ram/u2_wrrd/reg21_b20|u2_ram/u2_wrrd/reg50_b31.clk
|
||||
auto_chipwatcher_0_logicbram_2048x51_sub_000000_036
|
||||
1177 0.235000 2.395000 2.630000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[31] auto_chipwatcher_0_logicbram_2048x51_sub_000000_036.dia[7]
|
||||
|
||||
|
||||
|
||||
|
||||
clock: u0_clk/pll_inst.clkc[2]
|
||||
1208 68 68 2
|
||||
Setup check
|
||||
1218 3
|
||||
Endpoint: u2_ram/u2_wrrd/reg39_b7
|
||||
1218 0.151000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b18|u2_ram/u2_wrrd/reg12_b23.clk->u2_ram/u2_wrrd/reg39_b7
|
||||
u2_ram/u2_wrrd/reg12_b18|u2_ram/u2_wrrd/reg12_b23.clk
|
||||
u2_ram/u2_wrrd/reg39_b7
|
||||
1220 0.151000 3.617000 3.466000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[23] u2_ram/u2_wrrd/reg39_b7.mi[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/reg38_b5|u2_ram/u2_wrrd/reg39_b0
|
||||
1251 0.169000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b0|u2_ram/u2_wrrd/reg12_b16.clk->u2_ram/u2_wrrd/reg38_b5|u2_ram/u2_wrrd/reg39_b0
|
||||
u2_ram/u2_wrrd/reg12_b0|u2_ram/u2_wrrd/reg12_b16.clk
|
||||
u2_ram/u2_wrrd/reg38_b5|u2_ram/u2_wrrd/reg39_b0
|
||||
1253 0.169000 3.617000 3.448000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[16] u2_ram/u2_wrrd/reg38_b5|u2_ram/u2_wrrd/reg39_b0.mi[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/reg38_b14|u2_ram/u2_wrrd/reg38_b15
|
||||
1284 0.169000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b14|u2_ram/u2_wrrd/reg12_b15.clk->u2_ram/u2_wrrd/reg38_b14|u2_ram/u2_wrrd/reg38_b15
|
||||
u2_ram/u2_wrrd/reg12_b14|u2_ram/u2_wrrd/reg12_b15.clk
|
||||
u2_ram/u2_wrrd/reg38_b14|u2_ram/u2_wrrd/reg38_b15
|
||||
1286 0.169000 3.617000 3.448000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[14] u2_ram/u2_wrrd/reg38_b14|u2_ram/u2_wrrd/reg38_b15.mi[1]
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
1317 3
|
||||
Endpoint: u2_ram/u2_wrrd/dq_t_reg
|
||||
1319 0.623000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dq_wvld_reg.clk->u2_ram/u2_wrrd/dq_t_reg
|
||||
u2_ram/u2_wrrd/dq_wvld_reg.clk
|
||||
u2_ram/u2_wrrd/dq_t_reg
|
||||
1321 0.623000 2.269000 2.892000 0 1
|
||||
u2_ram/u2_wrrd/dq_wvld u2_ram/u2_wrrd/dq_t_reg.mi[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/reg39_b3|u2_ram/u2_wrrd/reg39_b5
|
||||
1352 5.110000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b19|u2_ram/u2_wrrd/reg12_b21.clk->u2_ram/u2_wrrd/reg39_b3|u2_ram/u2_wrrd/reg39_b5
|
||||
u2_ram/u2_wrrd/reg12_b19|u2_ram/u2_wrrd/reg12_b21.clk
|
||||
u2_ram/u2_wrrd/reg39_b3|u2_ram/u2_wrrd/reg39_b5
|
||||
1354 5.110000 -2.516000 2.594000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[21] u2_ram/u2_wrrd/reg39_b3|u2_ram/u2_wrrd/reg39_b5.mi[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/reg39_b14|u2_ram/u2_wrrd/reg39_b15
|
||||
1385 5.110000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b30|u2_ram/u2_wrrd/reg12_b31.clk->u2_ram/u2_wrrd/reg39_b14|u2_ram/u2_wrrd/reg39_b15
|
||||
u2_ram/u2_wrrd/reg12_b30|u2_ram/u2_wrrd/reg12_b31.clk
|
||||
u2_ram/u2_wrrd/reg39_b14|u2_ram/u2_wrrd/reg39_b15
|
||||
1387 5.110000 -2.516000 2.594000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[30] u2_ram/u2_wrrd/reg39_b14|u2_ram/u2_wrrd/reg39_b15.mi[1]
|
||||
|
||||
|
||||
|
||||
|
||||
clock: u0_clk/pll_inst.clkc[3]
|
||||
1418 4 4 2
|
||||
Setup check
|
||||
1428 2
|
||||
Endpoint: u2_ram/u2_wrrd/dqs_oddr_on_reg
|
||||
1428 2.089000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg28_b10|u2_ram/u2_wrrd/reg27_b7.clk->u2_ram/u2_wrrd/dqs_oddr_on_reg
|
||||
u2_ram/u2_wrrd/reg28_b10|u2_ram/u2_wrrd/reg27_b7.clk
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg
|
||||
1430 2.089000 5.284000 3.195000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_en_sft[7] u2_ram/u2_wrrd/dqs_oddr_on_reg.mi[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/dqs_oddr_on_1d_reg
|
||||
1461 4.909000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dqs_oddr_on_reg.clk->u2_ram/u2_wrrd/dqs_oddr_on_1d_reg
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg.clk
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_1d_reg
|
||||
1463 4.909000 8.751000 3.842000 0 1
|
||||
u2_ram/u2_wrrd/dqs_oddr_on u2_ram/u2_wrrd/dqs_oddr_on_1d_reg.mi[0]
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
1494 2
|
||||
Endpoint: u2_ram/u2_wrrd/dqs_oddr_on_1d_reg
|
||||
1496 0.998000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dqs_oddr_on_reg.clk->u2_ram/u2_wrrd/dqs_oddr_on_1d_reg
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg.clk
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_1d_reg
|
||||
1498 0.998000 2.350000 3.348000 0 1
|
||||
u2_ram/u2_wrrd/dqs_oddr_on u2_ram/u2_wrrd/dqs_oddr_on_1d_reg.mi[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/dqs_oddr_on_reg
|
||||
1529 3.610000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg28_b10|u2_ram/u2_wrrd/reg27_b7.clk->u2_ram/u2_wrrd/dqs_oddr_on_reg
|
||||
u2_ram/u2_wrrd/reg28_b10|u2_ram/u2_wrrd/reg27_b7.clk
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg
|
||||
1531 3.610000 -0.849000 2.761000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_en_sft[7] u2_ram/u2_wrrd/dqs_oddr_on_reg.mi[0]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Timing group statistics:
|
||||
Clock constraints:
|
||||
Clock Name Min Period Max Freq Skew Fanout TNS
|
||||
u0_clk/pll_inst.clkc[1] (150.0MHz) 4.519ns 221MHz 0.399ns 485 0.000ns
|
||||
u0_clk/pll_inst.clkc[2] (150.0MHz) 6.515ns 153MHz 0.571ns 35 0.000ns
|
||||
clk (25.0MHz) 2.994ns 334MHz 0.128ns 4 0.000ns
|
||||
u0_clk/pll_inst.clkc[3] (150.0MHz) 4.577ns 218MHz 0.571ns 4 0.000ns
|
||||
Minimum input arrival time before clock: no constraint path
|
||||
Maximum output required time after clock: no constraint path
|
||||
Maximum combinational path delay: no constraint path
|
||||
Warning: No clock constraint on 2 clock net(s):
|
||||
jtck
|
||||
u2_ram/u2_wrrd/DQS[0]
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
standard
|
||||
***Report Model: top***
|
||||
|
||||
IO Statistics
|
||||
#IO 2
|
||||
#input 1
|
||||
#output 1
|
||||
#inout 0
|
||||
|
||||
Utilization Statistics
|
||||
#lut 551 out of 19600 2.81%
|
||||
#reg 1029 out of 19600 5.25%
|
||||
#le 1245
|
||||
#lut only 216 out of 1245 17.35%
|
||||
#reg only 694 out of 1245 55.74%
|
||||
#lut® 335 out of 1245 26.91%
|
||||
#dsp 0 out of 29 0.00%
|
||||
#bram 12 out of 64 18.75%
|
||||
#bram9k 12
|
||||
#fifo9k 0
|
||||
#bram32k 0 out of 16 0.00%
|
||||
#pad 2 out of 130 1.54%
|
||||
#ireg 0
|
||||
#oreg 0
|
||||
#treg 0
|
||||
#pll 1 out of 4 25.00%
|
||||
|
||||
|
||||
Detailed IO Report
|
||||
|
||||
Name Direction Location IOStandard DriveStrength PullType PackReg
|
||||
SYS_CLK INPUT P26 LVCMOS25 N/A NONE NONE
|
||||
LED OUTPUT P162 LVCMOS25 8 NONE NONE
|
||||
|
||||
Report Hierarchy Area:
|
||||
+----------------------------------------------------------------+
|
||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||
+----------------------------------------------------------------+
|
||||
|top |top |1245 |459 |92 |1029 |12 |0 |
|
||||
+----------------------------------------------------------------+
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,447 @@
|
|||
ph1_100
|
||||
13 1109 897 2088 8154 0 0
|
||||
4.333 0.177 top ph1_100 PH1A100GCG324 Placed 11 4
|
||||
clock: clk
|
||||
13 86 16 2
|
||||
Setup check
|
||||
23 3
|
||||
Endpoint: reg0_b2|reg0_b3
|
||||
23 38.714000 4 3
|
||||
Timing path: reg0_b7|reg0_b6.clk->reg0_b2|reg0_b3
|
||||
reg0_b7|reg0_b6.clk
|
||||
reg0_b2|reg0_b3
|
||||
25 38.714000 39.937000 1.223000 2 2
|
||||
rst_cnt[7] reg0_b0_al_u857.ia
|
||||
_al_u7_o reg0_b2|reg0_b3.ib
|
||||
|
||||
Timing path: reg0_b0_al_u857.clk->reg0_b2|reg0_b3
|
||||
reg0_b0_al_u857.clk
|
||||
reg0_b2|reg0_b3
|
||||
55 38.756000 39.937000 1.181000 2 2
|
||||
rst_cnt[0] reg0_b0_al_u857.ib
|
||||
_al_u7_o reg0_b2|reg0_b3.ib
|
||||
|
||||
Timing path: reg0_b1_al_u862.clk->reg0_b2|reg0_b3
|
||||
reg0_b1_al_u862.clk
|
||||
reg0_b2|reg0_b3
|
||||
85 38.833000 39.937000 1.104000 2 2
|
||||
rst_cnt[1] reg0_b0_al_u857.imf
|
||||
_al_u7_o reg0_b2|reg0_b3.ib
|
||||
|
||||
|
||||
Endpoint: reg0_b2|reg0_b3
|
||||
115 38.758000 5 3
|
||||
Timing path: reg0_b7|reg0_b6.clk->reg0_b2|reg0_b3
|
||||
reg0_b7|reg0_b6.clk
|
||||
reg0_b2|reg0_b3
|
||||
117 38.758000 39.937000 1.179000 2 2
|
||||
rst_cnt[7] reg0_b0_al_u857.ia
|
||||
_al_u7_o reg0_b2|reg0_b3.ib
|
||||
|
||||
Timing path: reg0_b0_al_u857.clk->reg0_b2|reg0_b3
|
||||
reg0_b0_al_u857.clk
|
||||
reg0_b2|reg0_b3
|
||||
147 38.800000 39.937000 1.137000 2 2
|
||||
rst_cnt[0] reg0_b0_al_u857.ib
|
||||
_al_u7_o reg0_b2|reg0_b3.ib
|
||||
|
||||
Timing path: reg0_b1_al_u862.clk->reg0_b2|reg0_b3
|
||||
reg0_b1_al_u862.clk
|
||||
reg0_b2|reg0_b3
|
||||
177 38.877000 39.937000 1.060000 2 2
|
||||
rst_cnt[1] reg0_b0_al_u857.imf
|
||||
_al_u7_o reg0_b2|reg0_b3.ib
|
||||
|
||||
|
||||
Endpoint: reg0_b7|reg0_b6
|
||||
207 38.777000 8 3
|
||||
Timing path: reg0_b1_al_u862.clk->reg0_b7|reg0_b6
|
||||
reg0_b1_al_u862.clk
|
||||
reg0_b7|reg0_b6
|
||||
209 38.777000 39.937000 1.160000 2 2
|
||||
rst_cnt[1] _al_u850.ib
|
||||
add0/net_cout5_lutinv reg0_b7|reg0_b6.ic
|
||||
|
||||
Timing path: reg0_b2|reg0_b3.clk->reg0_b7|reg0_b6
|
||||
reg0_b2|reg0_b3.clk
|
||||
reg0_b7|reg0_b6
|
||||
239 38.813000 39.937000 1.124000 2 2
|
||||
rst_cnt[2] _al_u850.ic
|
||||
add0/net_cout5_lutinv reg0_b7|reg0_b6.ic
|
||||
|
||||
Timing path: reg0_b0_al_u857.clk->reg0_b7|reg0_b6
|
||||
reg0_b0_al_u857.clk
|
||||
reg0_b7|reg0_b6
|
||||
269 38.821000 39.937000 1.116000 2 2
|
||||
rst_cnt[0] _al_u850.ia
|
||||
add0/net_cout5_lutinv reg0_b7|reg0_b6.ic
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
299 3
|
||||
Endpoint: reg0_b2|reg0_b3
|
||||
301 0.250000 5 3
|
||||
Timing path: reg0_b2|reg0_b3.clk->reg0_b2|reg0_b3
|
||||
reg0_b2|reg0_b3.clk
|
||||
reg0_b2|reg0_b3
|
||||
303 0.250000 0.000000 0.250000 1 1
|
||||
rst_cnt[3] reg0_b2|reg0_b3.ie
|
||||
|
||||
Timing path: reg0_b2|reg0_b3.clk->reg0_b2|reg0_b3
|
||||
reg0_b2|reg0_b3.clk
|
||||
reg0_b2|reg0_b3
|
||||
331 0.330000 0.000000 0.330000 1 1
|
||||
rst_cnt[2] reg0_b2|reg0_b3.ia
|
||||
|
||||
Timing path: reg0_b1_al_u862.clk->reg0_b2|reg0_b3
|
||||
reg0_b1_al_u862.clk
|
||||
reg0_b2|reg0_b3
|
||||
359 0.597000 0.000000 0.597000 2 2
|
||||
rst_cnt[1] reg0_b0_al_u857.imf
|
||||
_al_u7_o reg0_b2|reg0_b3.ib
|
||||
|
||||
|
||||
Endpoint: reg0_b1_al_u862
|
||||
389 0.278000 3 3
|
||||
Timing path: reg0_b7|reg0_b6.clk->reg0_b1_al_u862
|
||||
reg0_b7|reg0_b6.clk
|
||||
reg0_b1_al_u862
|
||||
391 0.278000 0.000000 0.278000 1 1
|
||||
rst_cnt[7] reg0_b1_al_u862.imf
|
||||
|
||||
Timing path: reg0_b1_al_u862.clk->reg0_b1_al_u862
|
||||
reg0_b1_al_u862.clk
|
||||
reg0_b1_al_u862
|
||||
419 0.309000 0.000000 0.309000 1 1
|
||||
rst_cnt[1] reg0_b1_al_u862.id
|
||||
|
||||
Timing path: reg0_b0_al_u857.clk->reg0_b1_al_u862
|
||||
reg0_b0_al_u857.clk
|
||||
reg0_b1_al_u862
|
||||
447 0.351000 0.000000 0.351000 1 1
|
||||
rst_cnt[0] reg0_b1_al_u862.ima
|
||||
|
||||
|
||||
Endpoint: reg0_b5|reg0_b4
|
||||
475 0.278000 7 3
|
||||
Timing path: reg0_b5|reg0_b4.clk->reg0_b5|reg0_b4
|
||||
reg0_b5|reg0_b4.clk
|
||||
reg0_b5|reg0_b4
|
||||
477 0.278000 0.000000 0.278000 1 1
|
||||
rst_cnt[5] reg0_b5|reg0_b4.imf
|
||||
|
||||
Timing path: reg0_b5|reg0_b4.clk->reg0_b5|reg0_b4
|
||||
reg0_b5|reg0_b4.clk
|
||||
reg0_b5|reg0_b4
|
||||
505 0.337000 0.000000 0.337000 1 1
|
||||
rst_cnt[4] reg0_b5|reg0_b4.ia
|
||||
|
||||
Timing path: reg0_b2|reg0_b3.clk->reg0_b5|reg0_b4
|
||||
reg0_b2|reg0_b3.clk
|
||||
reg0_b5|reg0_b4
|
||||
533 0.349000 0.000000 0.349000 1 1
|
||||
rst_cnt[2] reg0_b5|reg0_b4.ic
|
||||
|
||||
|
||||
|
||||
|
||||
clock: u0_clk/pll_inst.clkc[1]
|
||||
561 7924 1928 2
|
||||
Setup check
|
||||
571 3
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0
|
||||
571 17.249000 23 3
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0
|
||||
573 17.249000 19.937000 2.688000 5 5
|
||||
cw_top/wt_addr[13] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b13.ima
|
||||
_al_u96_o _al_u853.ia
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0.ib
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b9|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b9|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0
|
||||
609 17.272000 19.937000 2.665000 5 5
|
||||
cw_top/wt_addr[14] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b13.id
|
||||
_al_u96_o _al_u853.ia
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0.ib
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0
|
||||
645 17.630000 19.937000 2.307000 4 4
|
||||
wt_addr_10 _al_u853.ib
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b2|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b0.ib
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3
|
||||
679 17.249000 26 3
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3
|
||||
681 17.249000 19.937000 2.688000 5 5
|
||||
cw_top/wt_addr[13] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b13.ima
|
||||
_al_u96_o _al_u853.ia
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3.ib
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b9|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b9|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3
|
||||
717 17.272000 19.937000 2.665000 5 5
|
||||
cw_top/wt_addr[14] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b13.id
|
||||
_al_u96_o _al_u853.ia
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3.ib
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3
|
||||
753 17.630000 19.937000 2.307000 4 4
|
||||
wt_addr_10 _al_u853.ib
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b3.ib
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15
|
||||
787 17.249000 31 3
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b8|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b13.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15
|
||||
789 17.249000 19.937000 2.688000 5 5
|
||||
cw_top/wt_addr[13] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b13.ima
|
||||
_al_u96_o _al_u853.ia
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.ib
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b9|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b9|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b14.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15
|
||||
825 17.272000 19.937000 2.665000 5 5
|
||||
cw_top/wt_addr[14] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/wt_ce_reg|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b13.id
|
||||
_al_u96_o _al_u853.ia
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.ib
|
||||
|
||||
Timing path: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15
|
||||
861 17.630000 19.937000 2.307000 4 4
|
||||
wt_addr_10 _al_u853.ib
|
||||
_al_u97_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b6|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b5.ia
|
||||
_al_u99_o cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b4|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg0_b3.ia
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/n9 cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b10|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg2_b15.ib
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
895 3
|
||||
Endpoint: u2_ram/u2_wrrd/u_DM[1]
|
||||
897 0.177000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg20_b0|u2_ram/u2_wrrd/reg19_b0.clk->u2_ram/u2_wrrd/u_DM[1]
|
||||
u2_ram/u2_wrrd/reg20_b0|u2_ram/u2_wrrd/reg19_b0.clk
|
||||
u2_ram/u2_wrrd/u_DM[1]
|
||||
899 0.177000 0.000000 0.177000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_dm_6d[0] u2_ram/u2_wrrd/u_DM[1].doq[0]
|
||||
|
||||
|
||||
Endpoint: auto_chipwatcher_0_logicbram_2048x157_sub_000000_020
|
||||
927 0.177000 20 3
|
||||
Timing path: u1_app_wrrd/reg5_b9|u1_app_wrrd/reg5_b8.clk->auto_chipwatcher_0_logicbram_2048x157_sub_000000_020
|
||||
u1_app_wrrd/reg5_b9|u1_app_wrrd/reg5_b8.clk
|
||||
auto_chipwatcher_0_logicbram_2048x157_sub_000000_020
|
||||
929 0.177000 0.000000 0.177000 0 1
|
||||
u1_app_wrrd/App_rd_addr[9] auto_chipwatcher_0_logicbram_2048x157_sub_000000_020.dia[2]
|
||||
|
||||
Timing path: u1_app_wrrd/reg5_b9|u1_app_wrrd/reg5_b8.clk->auto_chipwatcher_0_logicbram_2048x157_sub_000000_020
|
||||
u1_app_wrrd/reg5_b9|u1_app_wrrd/reg5_b8.clk
|
||||
auto_chipwatcher_0_logicbram_2048x157_sub_000000_020
|
||||
957 0.180000 0.000000 0.180000 0 1
|
||||
u1_app_wrrd/App_rd_addr[8] auto_chipwatcher_0_logicbram_2048x157_sub_000000_020.dia[1]
|
||||
|
||||
Timing path: u1_app_wrrd/reg5_b7|u1_app_wrrd/reg5_b15.clk->auto_chipwatcher_0_logicbram_2048x157_sub_000000_020
|
||||
u1_app_wrrd/reg5_b7|u1_app_wrrd/reg5_b15.clk
|
||||
auto_chipwatcher_0_logicbram_2048x157_sub_000000_020
|
||||
985 0.247000 0.000000 0.247000 0 1
|
||||
u1_app_wrrd/App_rd_addr[7] auto_chipwatcher_0_logicbram_2048x157_sub_000000_020.dia[0]
|
||||
|
||||
|
||||
Endpoint: auto_chipwatcher_0_logicbram_2048x157_sub_000000_150
|
||||
1013 0.177000 7 3
|
||||
Timing path: u2_ram/u2_wrrd/reg45_b8|u2_ram/u2_wrrd/reg45_b62.clk->auto_chipwatcher_0_logicbram_2048x157_sub_000000_150
|
||||
u2_ram/u2_wrrd/reg45_b8|u2_ram/u2_wrrd/reg45_b62.clk
|
||||
auto_chipwatcher_0_logicbram_2048x157_sub_000000_150
|
||||
1015 0.177000 0.000000 0.177000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[8] auto_chipwatcher_0_logicbram_2048x157_sub_000000_150.dia[4]
|
||||
|
||||
Timing path: u2_ram/u2_wrrd/reg45_b9|u2_ram/u2_wrrd/reg45_b61.clk->auto_chipwatcher_0_logicbram_2048x157_sub_000000_150
|
||||
u2_ram/u2_wrrd/reg45_b9|u2_ram/u2_wrrd/reg45_b61.clk
|
||||
auto_chipwatcher_0_logicbram_2048x157_sub_000000_150
|
||||
1043 0.177000 0.000000 0.177000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[9] auto_chipwatcher_0_logicbram_2048x157_sub_000000_150.dia[5]
|
||||
|
||||
Timing path: u2_ram/u2_wrrd/reg45_b9|u2_ram/u2_wrrd/reg45_b61.clk->auto_chipwatcher_0_logicbram_2048x157_sub_000000_150
|
||||
u2_ram/u2_wrrd/reg45_b9|u2_ram/u2_wrrd/reg45_b61.clk
|
||||
auto_chipwatcher_0_logicbram_2048x157_sub_000000_150
|
||||
1071 0.180000 0.000000 0.180000 0 1
|
||||
u2_ram/u2_wrrd/Sdr_rd_dout[61] auto_chipwatcher_0_logicbram_2048x157_sub_000000_150.dia[0]
|
||||
|
||||
|
||||
|
||||
|
||||
clock: u0_clk/pll_inst.clkc[2]
|
||||
1099 132 132 2
|
||||
Setup check
|
||||
1109 3
|
||||
Endpoint: u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16
|
||||
1109 4.333000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b17|u2_ram/u2_wrrd/reg12_b16.clk->u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16
|
||||
u2_ram/u2_wrrd/reg12_b17|u2_ram/u2_wrrd/reg12_b16.clk
|
||||
u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16
|
||||
1111 4.333000 4.937000 0.604000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[17] u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16.ima
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16
|
||||
1139 4.340000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b17|u2_ram/u2_wrrd/reg12_b16.clk->u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16
|
||||
u2_ram/u2_wrrd/reg12_b17|u2_ram/u2_wrrd/reg12_b16.clk
|
||||
u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16
|
||||
1141 4.340000 4.937000 0.597000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[16] u2_ram/u2_wrrd/reg37_b17|u2_ram/u2_wrrd/reg37_b16.imb
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/reg37_b7_al_u824
|
||||
1169 4.368000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg12_b7_al_u699.clk->u2_ram/u2_wrrd/reg37_b7_al_u824
|
||||
u2_ram/u2_wrrd/reg12_b7_al_u699.clk
|
||||
u2_ram/u2_wrrd/reg37_b7_al_u824
|
||||
1171 4.368000 4.937000 0.569000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_din_7d[7] u2_ram/u2_wrrd/reg37_b7_al_u824.ima
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
1199 3
|
||||
Endpoint: u2_ram/u2_wrrd/u_DQ[8]
|
||||
1201 0.212000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg37_b8|u2_ram/u2_wrrd/reg37_b11.clk->u2_ram/u2_wrrd/u_DQ[8]
|
||||
u2_ram/u2_wrrd/reg37_b8|u2_ram/u2_wrrd/reg37_b11.clk
|
||||
u2_ram/u2_wrrd/u_DQ[8]
|
||||
1203 0.212000 0.000000 0.212000 0 1
|
||||
u2_ram/u2_wrrd/dqout_p[8] u2_ram/u2_wrrd/u_DQ[8].doq[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/u_DQ[10]
|
||||
1231 0.212000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg37_b10_al_u840.clk->u2_ram/u2_wrrd/u_DQ[10]
|
||||
u2_ram/u2_wrrd/reg37_b10_al_u840.clk
|
||||
u2_ram/u2_wrrd/u_DQ[10]
|
||||
1233 0.212000 0.000000 0.212000 0 1
|
||||
u2_ram/u2_wrrd/dqout_p[10] u2_ram/u2_wrrd/u_DQ[10].doq[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/u_DQ[20]
|
||||
1261 0.212000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg37_b20_al_u837.clk->u2_ram/u2_wrrd/u_DQ[20]
|
||||
u2_ram/u2_wrrd/reg37_b20_al_u837.clk
|
||||
u2_ram/u2_wrrd/u_DQ[20]
|
||||
1263 0.212000 0.000000 0.212000 0 1
|
||||
u2_ram/u2_wrrd/dqout_p[20] u2_ram/u2_wrrd/u_DQ[20].doq[0]
|
||||
|
||||
|
||||
|
||||
|
||||
clock: u0_clk/pll_inst.clkc[3]
|
||||
1291 12 12 2
|
||||
Setup check
|
||||
1301 3
|
||||
Endpoint: u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859
|
||||
1301 9.377000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/reg27_b7|u2_ram/u1_init_ref/reg6_b8.clk->u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859
|
||||
u2_ram/u2_wrrd/reg27_b7|u2_ram/u1_init_ref/reg6_b8.clk
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859
|
||||
1303 9.377000 9.937000 0.560000 0 1
|
||||
u2_ram/u2_wrrd/app_wr_en_sft[7] u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.ima
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/u_DQS[0]
|
||||
1331 17.896000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk->u2_ram/u2_wrrd/u_DQS[0]
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk
|
||||
u2_ram/u2_wrrd/u_DQS[0]
|
||||
1333 17.896000 20.000000 2.104000 0 1
|
||||
u2_ram/u2_wrrd/dqs_oddr_on u2_ram/u2_wrrd/u_DQS[0].doq[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/u_DQS[3]
|
||||
1361 18.456000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk->u2_ram/u2_wrrd/u_DQS[3]
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk
|
||||
u2_ram/u2_wrrd/u_DQS[3]
|
||||
1363 18.456000 20.000000 1.544000 0 1
|
||||
u2_ram/u2_wrrd/dqs_oddr_on u2_ram/u2_wrrd/u_DQS[3].doq[0]
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
1391 3
|
||||
Endpoint: u2_ram/u2_wrrd/u_DQS[2]
|
||||
1393 0.842000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk->u2_ram/u2_wrrd/u_DQS[2]
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk
|
||||
u2_ram/u2_wrrd/u_DQS[2]
|
||||
1395 0.842000 0.000000 0.842000 0 1
|
||||
u2_ram/u2_wrrd/dqs_oddr_on u2_ram/u2_wrrd/u_DQS[2].doq[0]
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/dqs_oddr_on_1d_reg_al_u864
|
||||
1423 1.025000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk->u2_ram/u2_wrrd/dqs_oddr_on_1d_reg_al_u864
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_1d_reg_al_u864
|
||||
1425 1.025000 0.000000 1.025000 0 1
|
||||
u2_ram/u2_wrrd/dqs_oddr_on u2_ram/u2_wrrd/dqs_oddr_on_1d_reg_al_u864.ima
|
||||
|
||||
|
||||
Endpoint: u2_ram/u2_wrrd/u_DQS[1]
|
||||
1453 1.087000 1 1
|
||||
Timing path: u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk->u2_ram/u2_wrrd/u_DQS[1]
|
||||
u2_ram/u2_wrrd/dqs_oddr_on_reg_al_u859.clk
|
||||
u2_ram/u2_wrrd/u_DQS[1]
|
||||
1455 1.087000 0.000000 1.087000 0 1
|
||||
u2_ram/u2_wrrd/dqs_oddr_on u2_ram/u2_wrrd/u_DQS[1].doq[0]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Timing group statistics:
|
||||
Clock constraints:
|
||||
Clock Name Min Period Max Freq Skew Fanout TNS
|
||||
u0_clk/pll_inst.clkc[1] (50.000MHz) 2.751ns 363.504MHz 0.000ns 567 0.000ns
|
||||
u0_clk/pll_inst.clkc[2] (50.000MHz) 15.667ns 63.828MHz 0.000ns 53 0.000ns
|
||||
u0_clk/pll_inst.clkc[3] (50.000MHz) 10.623ns 94.135MHz 0.000ns 6 0.000ns
|
||||
clk (25.000MHz) 1.286ns 777.605MHz 0.000ns 5 0.000ns
|
||||
Minimum input arrival time before clock: no constraint path
|
||||
Maximum output required time after clock: no constraint path
|
||||
Maximum combinational path delay: no constraint path
|
||||
Warning: No clock constraint on 4 clock net(s):
|
||||
jtck
|
||||
jtck_leading
|
||||
u2_ram/u2_wrrd/DQS_pad[0]
|
||||
u2_ram/u2_wrrd/DQS_pad[0]_created_gclknet
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
Clock Freq Max-Depth 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >19
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
u0_clk/pll_inst.clkc[1] 50.000MHz 5 158 217 20 1 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
u0_clk/pll_inst.clkc[2] 50.000MHz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
u0_clk/pll_inst.clkc[3] 50.000MHz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
clk 25.000MHz 2 2 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,40 @@
|
|||
standard
|
||||
***Report Model: top***
|
||||
|
||||
IO Statistics
|
||||
#IO 2
|
||||
#input 1
|
||||
#output 1
|
||||
#inout 0
|
||||
|
||||
Gate Statistics
|
||||
#Basic gates 1013
|
||||
#and 22
|
||||
#nand 0
|
||||
#or 15
|
||||
#nor 0
|
||||
#xor 0
|
||||
#xnor 0
|
||||
#buf 0
|
||||
#not 43
|
||||
#bufif1 18
|
||||
#MX21 28
|
||||
#FADD 0
|
||||
#DFF 887
|
||||
#LATCH 0
|
||||
#MACRO_ADD 12
|
||||
#MACRO_EQ 11
|
||||
#MACRO_MUX 97
|
||||
#MACRO_OTHERS 21
|
||||
|
||||
Report Hierarchy Area:
|
||||
+-------------------------------------------------------+
|
||||
|Instance |Module |gates |seq |macros |
|
||||
+-------------------------------------------------------+
|
||||
|top |top |126 |887 |44 |
|
||||
| u0_clk |clk_pll |0 |0 |1 |
|
||||
| u1_app_wrrd |app_wrrd |26 |158 |10 |
|
||||
| u2_ram |ddr1_as_ram |98 |721 |32 |
|
||||
| u1_init_ref |ddr1_init_ref |29 |70 |10 |
|
||||
| u2_wrrd |ddr1_wrrd |69 |651 |22 |
|
||||
+-------------------------------------------------------+
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,40 @@
|
|||
module CW_TOP_WRAPPER(jtdi, jtck, jrstn, jscan, jshift, jupdate, jtdo, non_bus_din, bus_din, trig_clk, wt_ce, wt_en, wt_addr);
|
||||
localparam DEFAULT_CTRL_REG_LEN = 34;
|
||||
localparam DEFAULT_STAT_REG_LEN = 18;
|
||||
localparam DEFAULT_STOP_LEN = 1365;
|
||||
localparam DEFAULT_NON_BUS_NODE_NUM = 3;
|
||||
localparam DEFAULT_BUS_NODE_NUM = 0;
|
||||
localparam DEFAULT_BUS_NUM = 0;
|
||||
input jtdi;
|
||||
input jtck;
|
||||
input jrstn;
|
||||
input [1:0] jscan;
|
||||
input jshift;
|
||||
input jupdate;
|
||||
output [1:0] jtdo;
|
||||
input trig_clk;
|
||||
input [DEFAULT_NON_BUS_NODE_NUM-1:0] non_bus_din;
|
||||
input [DEFAULT_BUS_NODE_NUM-1:0] bus_din;
|
||||
output wt_ce;
|
||||
output wt_en;
|
||||
output [15:0] wt_addr;
|
||||
|
||||
cwc_top #(.CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN), .STAT_REG_LEN(DEFAULT_STAT_REG_LEN), .STOP_LEN(DEFAULT_STOP_LEN), .NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM), .BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM), .BUS_NUM(DEFAULT_BUS_NUM))
|
||||
wrapper_cwc_top(
|
||||
.jtdi(jtdi),
|
||||
.jtck(jtck),
|
||||
.jrstn(jrstn),
|
||||
.jscan(jscan),
|
||||
.jshift(jshift),
|
||||
.jupdate(jupdate),
|
||||
.jtdo(jtdo),
|
||||
.non_bus_din(non_bus_din),
|
||||
.bus_din(bus_din),
|
||||
.trig_clk(trig_clk),
|
||||
.wt_ce(wt_ce),
|
||||
.wt_en(wt_en),
|
||||
.wt_addr(wt_addr)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,14 @@
|
|||
============================================================
|
||||
Tang Dynasty, V4.6.23147
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD4.6.23147/bin/td.exe
|
||||
Built at = 19:51:18 Sep 21 2020
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 00:32:46 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
GUI-8102 ERROR: Cannot find device:.
|
||||
GUI-8101 ERROR: import_device failed.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,33 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 11:20:51 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EQFP176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "import_db sdram_as_ram_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.0.25878.
|
||||
RUN-1001 : Database version number 46126.
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter place:timing_factor.
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter route:least_critical_net_perc.
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter route:most_critical_net_perc.
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter route:tactics.
|
||||
RUN-1001 : Import flow parameters
|
||||
RUN-1001 : Import ChipWatcher
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,39 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Feb 3 15:41:59 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EQFP176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device eagle_s20.db -package EQFP176" in 1.191381s wall, 1.343750s user + 0.250000s system = 1.593750s CPU (133.8%)
|
||||
|
||||
RUN-1004 : used memory is 148 MB, reserved memory is 99 MB, peak memory is 148 MB
|
||||
RUN-1002 : start command "import_db sdram_as_ram_pr.db"
|
||||
RUN-1001 : Importing database generated by Tang Dynasty, V5.0.25878.
|
||||
RUN-1001 : Database version number 46126.
|
||||
RUN-1001 : Import timing constraints
|
||||
RUN-1001 : Import IO constraints
|
||||
RUN-1001 : Import Inst constraints
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter place:timing_factor.
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter route:least_critical_net_perc.
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter route:most_critical_net_perc.
|
||||
RUN-6014 WARNING: Importing design, skipped an obsolete step parameter route:tactics.
|
||||
RUN-1001 : Import flow parameters
|
||||
RUN-1001 : Import ChipWatcher
|
||||
RUN-1003 : finish command "import_db sdram_as_ram_pr.db" in 2.519970s wall, 1.531250s user + 0.125000s system = 1.656250s CPU (65.7%)
|
||||
|
||||
RUN-1004 : used memory is 216 MB, reserved memory is 169 MB, peak memory is 216 MB
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,251 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.38542
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = D:/Anlogic/TD5.0.38542/bin/td.exe
|
||||
Built at = 15:50:25 Sep 18 2021
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Oct 11 20:45:22 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package EQFP176"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
|
||||
ARC-1001 : done | P10 | gpio
|
||||
ARC-1001 : program_b | P134 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
|
||||
ARC-1001 : ----------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_as_ram.enc.v
|
||||
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
|
||||
This product includes software developed by the OpenSSL Project
|
||||
for use in the OpenSSL Toolkit (http://www.openssl.org/)
|
||||
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
All rights reserved.
|
||||
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_as_ram.enc.v' in ../source_code/rtl/enc_file/sdr_as_ram.enc.v(142)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_init_ref.enc.v
|
||||
HDL-5007 WARNING: concatenation with unsized literal; will interpret as 32 bits in encrypted_text(0)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_init_ref.enc.v' in ../source_code/rtl/enc_file/sdr_init_ref.enc.v(153)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_wrrd.enc.v
|
||||
HDL-5007 WARNING: concatenation with unsized literal; will interpret as 32 bits in encrypted_text(0)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_wrrd.enc.v' in ../source_code/rtl/enc_file/sdr_wrrd.enc.v(245)
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file al_ip/dram_16x1.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_as_ram.enc.v
|
||||
HDL-5007 WARNING: macro 'DATA_WIDTH' redefined in ../source_code/rtl/enc_file/sdr_as_ram.enc.v(10)
|
||||
HDL-5007 WARNING: macro 'DM_WIDTH' redefined in ../source_code/rtl/enc_file/sdr_as_ram.enc.v(12)
|
||||
HDL-5007 WARNING: macro 'ROW_WIDTH' redefined in ../source_code/rtl/enc_file/sdr_as_ram.enc.v(13)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_as_ram.enc.v' in ../source_code/rtl/enc_file/sdr_as_ram.enc.v(142)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_init_ref.enc.v
|
||||
HDL-5007 WARNING: concatenation with unsized literal; will interpret as 32 bits in encrypted_text(0)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_init_ref.enc.v' in ../source_code/rtl/enc_file/sdr_init_ref.enc.v(153)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_wrrd.enc.v
|
||||
HDL-5007 WARNING: concatenation with unsized literal; will interpret as 32 bits in encrypted_text(0)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_wrrd.enc.v' in ../source_code/rtl/enc_file/sdr_wrrd.enc.v(245)
|
||||
RUN-1002 : start command "elaborate -top top"
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : default_reg_initial | auto | auto
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : elaborate module top in ../source_code/rtl/top.v(12)
|
||||
HDL-1007 : elaborate module clk_pll in al_ip/clk_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.0.38542/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=40,CLKC1_DIV=5,CLKC2_DIV=5,CLKC3_DIV=5,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=2,CLKC3_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=4,CLKC2_CPHASE=5,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.0.38542/arch/eagle_macro.v(929)
|
||||
HDL-1007 : elaborate module app_wrrd in ../source_code/rtl/app_wrrd.v(12)
|
||||
HDL-5007 WARNING: instantiate unknown module ddr1_as_ram in ../source_code/rtl/top.v(124)
|
||||
HDL-1007 : elaborate module EG_PHY_DDR_8M_16 in D:/Anlogic/TD5.0.38542/arch/eagle_macro.v(686)
|
||||
HDL-8007 ERROR: ddr1_as_ram(self_refresh_open=1'b0) is a black box
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,91 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Tue Jan 19 20:30:17 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_as_ram.enc.v
|
||||
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
|
||||
This product includes software developed by the OpenSSL Project
|
||||
for use in the OpenSSL Toolkit (http://www.openssl.org/)
|
||||
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
All rights reserved.
|
||||
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_as_ram.enc.v' in ../source_code/rtl/enc_file/sdr_as_ram.enc.v(142)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_init_ref.enc.v
|
||||
HDL-5007 WARNING: concatenation with unsized literal; will interpret as 32 bits in encrypted_text(0)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_init_ref.enc.v' in ../source_code/rtl/enc_file/sdr_init_ref.enc.v(153)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/enc_file/sdr_wrrd.enc.v
|
||||
HDL-5007 WARNING: concatenation with unsized literal; will interpret as 32 bits in encrypted_text(0)
|
||||
HDL-1007 : back to file '../source_code/rtl/enc_file/sdr_wrrd.enc.v' in ../source_code/rtl/enc_file/sdr_wrrd.enc.v(245)
|
||||
RUN-1001 : Project manager successfully analyzed 7 source files.
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Tue Jan 19 20:30:29 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package BG256 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/S11 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(24)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",REFCLK_DIV=2,CLKC0_DIV=84,CLKC1_DIV=7,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=7,CLKC0_CPHASE=83,CLKC1_CPHASE=6,CLKC2_CPHASE=6,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 8/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 8/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 8/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4S20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Tue Jan 19 20:45:59 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_s20.db -package BG256 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/S11 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device eagle_s20.db -package BG256 -basic" in 1.114631s wall, 1.140625s user + 0.078125s system = 1.218750s CPU (109.3%)
|
||||
|
||||
RUN-1004 : used memory is 166 MB, reserved memory is 100 MB, peak memory is 166 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(24)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",REFCLK_DIV=2,CLKC0_DIV=84,CLKC1_DIV=7,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC0_CPHASE=83,CLKC1_CPHASE=6,CLKC2_CPHASE=7,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 8/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 8/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 8/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4S20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Jan 20 11:49:50 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.300422s wall, 3.187500s user + 0.171875s system = 3.359375s CPU (101.8%)
|
||||
|
||||
RUN-1004 : used memory is 281 MB, reserved memory is 227 MB, peak memory is 281 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(22)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC0_CPHASE=9,CLKC0_DIV=10,CLKC0_DUTY_INT=5,CLKC0_ENABLE="ENABLE",FIN="100.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=1,ICP_CUR=13,GMC_GAIN=3,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 7/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Jan 20 11:50:21 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.238637s wall, 3.125000s user + 0.171875s system = 3.296875s CPU (101.8%)
|
||||
|
||||
RUN-1004 : used memory is 287 MB, reserved memory is 228 MB, peak memory is 287 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(24)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC2_FPHASE=7,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=6,CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC0_DUTY_INT=21,CLKC1_DUTY_INT=4,CLKC2_DUTY_INT=4,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,CLKC2_FPHASE_RSTSEL=1,INTPI=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Jan 20 14:18:47 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1002 : start command "set_param rtl keep_hierarchy flatten"
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | flatten | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_as_ram.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_as_ram.v' in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_init_ref.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_init_ref.v' in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_wrrd.v' in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
RUN-1001 : Project manager successfully analyzed 7 source files.
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Jan 20 15:14:24 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.430333s wall, 3.234375s user + 0.140625s system = 3.375000s CPU (98.4%)
|
||||
|
||||
RUN-1004 : used memory is 276 MB, reserved memory is 226 MB, peak memory is 276 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(24)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC2_FPHASE=2,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=6,CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC0_DUTY_INT=21,CLKC1_DUTY_INT=4,CLKC2_DUTY_INT=4,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,MPHASE_ENABLE="ENABLE",INTPI=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Jan 20 15:31:46 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.444249s wall, 3.390625s user + 0.031250s system = 3.421875s CPU (99.4%)
|
||||
|
||||
RUN-1004 : used memory is 272 MB, reserved memory is 227 MB, peak memory is 272 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(24)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC2_FPHASE=1,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC0_DUTY_INT=21,CLKC1_DUTY_INT=4,CLKC2_DUTY_INT=4,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,MPHASE_ENABLE="ENABLE",INTPI=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Jan 20 15:49:13 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.484845s wall, 3.421875s user + 0.125000s system = 3.546875s CPU (101.8%)
|
||||
|
||||
RUN-1004 : used memory is 280 MB, reserved memory is 225 MB, peak memory is 280 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(24)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC2_FPHASE=3,CLKC0_CPHASE=31,CLKC1_CPHASE=127,CLKC2_CPHASE=20,CLKC0_DIV=32,CLKC1_DIV=128,CLKC2_DIV=128,CLKC0_DUTY_INT=16,CLKC1_DUTY_INT=64,CLKC2_DUTY_INT=64,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Wed Jan 20 15:56:57 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_as_ram.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_as_ram.v' in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_init_ref.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_init_ref.v' in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_wrrd.v' in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
RUN-1001 : Project manager successfully analyzed 7 source files.
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 09:14:01 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.093301s wall, 2.984375s user + 0.203125s system = 3.187500s CPU (103.0%)
|
||||
|
||||
RUN-1004 : used memory is 287 MB, reserved memory is 227 MB, peak memory is 287 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(24)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC0_CPHASE=31,CLKC1_CPHASE=127,CLKC2_CPHASE=31,CLKC0_DIV=32,CLKC1_DIV=128,CLKC2_DIV=128,CLKC0_DUTY_INT=16,CLKC1_DUTY_INT=64,CLKC2_DUTY_INT=64,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 09:14:29 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.081453s wall, 3.046875s user + 0.093750s system = 3.140625s CPU (101.9%)
|
||||
|
||||
RUN-1004 : used memory is 287 MB, reserved memory is 227 MB, peak memory is 287 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC0_CPHASE=31,CLKC1_CPHASE=127,CLKC2_CPHASE=31,CLKC3_CPHASE=15,CLKC0_DIV=32,CLKC1_DIV=128,CLKC2_DIV=128,CLKC3_DIV=32,CLKC0_DUTY_INT=16,CLKC1_DUTY_INT=64,CLKC2_DUTY_INT=64,CLKC3_DUTY_INT=16,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 09:15:03 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file eg4_pll.v"
|
||||
HDL-1007 : analyze verilog file eg4_pll.v
|
||||
HDL-1007 : elaborate module eg4_pll in eg4_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is eg4_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "eg4_pll"
|
||||
SYN-1011 : Flatten model eg4_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog eg4_pll_sim.v"
|
||||
HDL-1201 : write out verilog file eg4_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/eg4_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 09:44:08 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file eg4_pll.v"
|
||||
HDL-1007 : analyze verilog file eg4_pll.v
|
||||
HDL-1007 : elaborate module eg4_pll in eg4_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is eg4_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "eg4_pll"
|
||||
SYN-1011 : Flatten model eg4_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog eg4_pll_sim.v"
|
||||
HDL-1201 : write out verilog file eg4_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/eg4_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 10:52:45 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.154817s wall, 3.109375s user + 0.109375s system = 3.218750s CPU (102.0%)
|
||||
|
||||
RUN-1004 : used memory is 287 MB, reserved memory is 227 MB, peak memory is 287 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC0_CPHASE=31,CLKC1_CPHASE=127,CLKC2_CPHASE=31,CLKC3_CPHASE=63,CLKC0_DIV=32,CLKC1_DIV=128,CLKC2_DIV=128,CLKC3_DIV=128,CLKC0_DUTY_INT=16,CLKC1_DUTY_INT=64,CLKC2_DUTY_INT=64,CLKC3_DUTY_INT=64,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 11:47:25 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.087957s wall, 2.984375s user + 0.156250s system = 3.140625s CPU (101.7%)
|
||||
|
||||
RUN-1004 : used memory is 288 MB, reserved memory is 228 MB, peak memory is 288 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC3_CPHASE=2,CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC0_DUTY_INT=21,CLKC1_DUTY_INT=4,CLKC2_DUTY_INT=4,CLKC3_DUTY_INT=4,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,MPHASE_ENABLE="ENABLE",CLKC2_FPHASE_RSTSEL=1,CLKC3_FPHASE_RSTSEL=1,INTPI=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 12:30:15 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.211889s wall, 3.046875s user + 0.218750s system = 3.265625s CPU (101.7%)
|
||||
|
||||
RUN-1004 : used memory is 284 MB, reserved memory is 228 MB, peak memory is 284 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC0_CPHASE=31,CLKC1_CPHASE=127,CLKC2_CPHASE=31,CLKC3_CPHASE=63,CLKC0_DIV=32,CLKC1_DIV=128,CLKC2_DIV=128,CLKC3_DIV=128,CLKC0_DUTY_INT=16,CLKC1_DUTY_INT=64,CLKC2_DUTY_INT=64,CLKC3_DUTY_INT=64,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 12:42:29 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 13:12:09 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.143578s wall, 3.031250s user + 0.187500s system = 3.218750s CPU (102.4%)
|
||||
|
||||
RUN-1004 : used memory is 287 MB, reserved memory is 227 MB, peak memory is 287 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC3_CPHASE=2,CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC0_DUTY_INT=21,CLKC1_DUTY_INT=4,CLKC2_DUTY_INT=4,CLKC3_DUTY_INT=4,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,MPHASE_ENABLE="ENABLE",CLKC2_FPHASE_RSTSEL=1,CLKC3_FPHASE_RSTSEL=1,INTPI=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 13:23:01 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.127412s wall, 3.093750s user + 0.125000s system = 3.218750s CPU (102.9%)
|
||||
|
||||
RUN-1004 : used memory is 289 MB, reserved memory is 227 MB, peak memory is 289 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC2_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=9,CLKC2_CPHASE=1,CLKC3_CPHASE=4,CLKC0_DIV=40,CLKC1_DIV=10,CLKC2_DIV=10,CLKC3_DIV=10,CLKC0_DUTY_INT=20,CLKC1_DUTY_INT=5,CLKC2_DUTY_INT=5,CLKC3_DUTY_INT=5,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,CLKC2_FPHASE_RSTSEL=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 17:15:07 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.357759s wall, 3.312500s user + 0.140625s system = 3.453125s CPU (102.8%)
|
||||
|
||||
RUN-1004 : used memory is 284 MB, reserved memory is 227 MB, peak memory is 284 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC0_CPHASE=39,CLKC1_CPHASE=1,CLKC2_CPHASE=4,CLKC3_CPHASE=9,CLKC0_DIV=40,CLKC1_DIV=2,CLKC2_DIV=20,CLKC3_DIV=20,CLKC0_DUTY_INT=20,CLKC2_DUTY_INT=10,CLKC3_DUTY_INT=10,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 17:32:17 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.286978s wall, 3.203125s user + 0.156250s system = 3.359375s CPU (102.2%)
|
||||
|
||||
RUN-1004 : used memory is 287 MB, reserved memory is 227 MB, peak memory is 287 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC0_CPHASE=39,CLKC1_CPHASE=19,CLKC2_CPHASE=4,CLKC3_CPHASE=9,CLKC0_DIV=40,CLKC1_DIV=20,CLKC2_DIV=20,CLKC3_DIV=20,CLKC0_DUTY_INT=20,CLKC1_DUTY_INT=10,CLKC2_DUTY_INT=10,CLKC3_DUTY_INT=10,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 18:17:56 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device ph1.db -package PH1A100GCG324 -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1001 : non_jtag_persist(none) | 36 IOs | gpio
|
||||
ARC-1001 : done | P10 | dedicate
|
||||
ARC-1001 : initn | P7 | dedicate
|
||||
ARC-1001 : programn | P9 | dedicate
|
||||
ARC-1001 : jtag | P8/E10/E12/E11/E13 | dedicate
|
||||
ARC-1001 : ---------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 8 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device ph1.db -package PH1A100GCG324 -basic" in 3.738039s wall, 3.671875s user + 0.156250s system = 3.828125s CPU (102.4%)
|
||||
|
||||
RUN-1004 : used memory is 284 MB, reserved memory is 227 MB, peak memory is 284 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module PH1_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(2867)
|
||||
HDL-1007 : elaborate module PH1_PHY_PLL(CLKC1_FPHASE=7,CLKC0_CPHASE=39,CLKC1_CPHASE=19,CLKC2_CPHASE=4,CLKC3_CPHASE=9,CLKC0_DIV=40,CLKC1_DIV=20,CLKC2_DIV=20,CLKC3_DIV=20,CLKC0_DUTY_INT=20,CLKC1_DUTY_INT=10,CLKC2_DUTY_INT=10,CLKC3_DUTY_INT=10,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FIN="25.000",PLL_USR_RST="ENABLE",PLL_FEED_TYPE="EXTERNAL",LPF_RES=3,ICP_CUR=11,GMC_GAIN=1,CLKC1_FPHASE_RSTSEL=1,SSC_RNGE=0) in C:/Anlogic/TD5.0.25878/arch/ph1_macro.v(1764)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{PH1A100GCG324(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 18:20:35 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="100.000",REFCLK_DIV=4,CLKC0_DIV=40,CLKC1_DIV=10,CLKC2_DIV=10,CLKC3_DIV=10,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=9,CLKC3_CPHASE=4,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Thu Jan 21 19:16:21 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="100.000",REFCLK_DIV=4,CLKC0_DIV=40,CLKC1_DIV=5,CLKC2_DIV=5,CLKC3_DIV=5,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=2,CLKC3_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=4,CLKC2_CPHASE=5,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Fri Jan 22 16:01:54 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_as_ram.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_as_ram.v' in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_init_ref.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_init_ref.v' in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_wrrd.v' in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
RUN-1001 : Project manager successfully analyzed 7 source files.
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Fri Jan 22 18:45:56 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=40,CLKC1_DIV=5,CLKC2_DIV=5,CLKC3_DIV=5,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=2,CLKC3_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=4,CLKC2_CPHASE=5,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Fri Jan 22 19:01:39 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 00:33:25 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_as_ram.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_as_ram.v' in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_init_ref.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_init_ref.v' in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_wrrd.v' in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
RUN-1001 : Project manager successfully analyzed 7 source files.
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 00:48:28 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=40,CLKC1_DIV=10,CLKC2_DIV=10,CLKC3_DIV=10,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=9,CLKC3_CPHASE=4,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 10:16:57 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(25)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 9/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 10:33:43 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC4_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC4_FPHASE=5,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 10:40:02 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file eg4_pll.v"
|
||||
HDL-1007 : analyze verilog file eg4_pll.v
|
||||
HDL-1007 : elaborate module eg4_pll in eg4_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=48,CLKC1_DIV=8,CLKC2_DIV=8,CLKC3_DIV=8,CLKC4_DIV=9,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=47,CLKC1_CPHASE=7,CLKC3_CPHASE=3,CLKC4_CPHASE=8,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is eg4_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "eg4_pll"
|
||||
SYN-1011 : Flatten model eg4_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog eg4_pll_sim.v"
|
||||
HDL-1201 : write out verilog file eg4_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/eg4_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 10:44:42 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC4_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC4_FPHASE=7,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,CLKC4_CPHASE=6,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 10:47:14 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC4_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC4_FPHASE=1,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,CLKC4_CPHASE=7,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 10:49:51 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC4_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC4_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,CLKC4_CPHASE=7,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Sun Jan 24 10:58:26 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC4_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC4_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,CLKC4_CPHASE=7,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Jan 25 10:54:56 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_as_ram.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_as_ram.v' in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_init_ref.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_init_ref.v' in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_wrrd.v' in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
RUN-1001 : Project manager successfully analyzed 7 source files.
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Jan 25 12:42:36 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=40,CLKC1_DIV=10,CLKC2_DIV=10,CLKC3_DIV=10,CLKC4_DIV=10,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=4,CLKC4_FPHASE=2,CLKC0_CPHASE=39,CLKC1_CPHASE=9,CLKC3_CPHASE=4,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Jan 25 14:41:15 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=40,CLKC1_DIV=20,CLKC2_DIV=20,CLKC3_DIV=20,CLKC4_DIV=20,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC4_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=19,CLKC2_CPHASE=4,CLKC3_CPHASE=9,CLKC4_CPHASE=3,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Jan 25 17:57:14 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "open_project sdram_as_ram.al"
|
||||
RUN-1001 : Print Global Property
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : message | standard | standard
|
||||
RUN-1001 : mixed_pack_place_flow | on | on
|
||||
RUN-1001 : syn_ip_flow | off | off
|
||||
RUN-1001 : thread | auto | auto
|
||||
RUN-1001 : -------------------------------------------------------
|
||||
RUN-1001 : Print Design Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : infer_add | on | on
|
||||
RUN-1001 : infer_fsm | off | off
|
||||
RUN-1001 : infer_mult | on | on
|
||||
RUN-1001 : infer_ram | on | on
|
||||
RUN-1001 : infer_reg | on | on
|
||||
RUN-1001 : infer_reg_init_value | on | on
|
||||
RUN-1001 : infer_rom | on | on
|
||||
RUN-1001 : infer_shifter | off | off
|
||||
RUN-1001 : map_dram | auto | auto
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
HDL-1007 : analyze verilog file al_ip/clk_pll.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/app_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/app_wrrd.v' in ../source_code/rtl/app_wrrd.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/top.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/top.v' in ../source_code/rtl/top.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/include/global_def.v
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_as_ram.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_as_ram.v' in ../source_code/rtl/for_enc/ddr1_as_ram.v(10)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_init_ref.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_init_ref.v' in ../source_code/rtl/for_enc/ddr1_init_ref.v(11)
|
||||
HDL-1007 : analyze verilog file ../source_code/rtl/for_enc/ddr1_wrrd.v
|
||||
HDL-1007 : analyze included file ../source_code/include/global_def.v in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
HDL-1007 : back to file '../source_code/rtl/for_enc/ddr1_wrrd.v' in ../source_code/rtl/for_enc/ddr1_wrrd.v(11)
|
||||
RUN-1001 : Project manager successfully analyzed 7 source files.
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Jan 25 18:28:42 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1003 : finish command "import_device eagle_20.db -package BGA256X -basic" in 1.525729s wall, 1.375000s user + 0.078125s system = 1.453125s CPU (95.2%)
|
||||
|
||||
RUN-1004 : used memory is 162 MB, reserved memory is 100 MB, peak memory is 162 MB
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=42,CLKC1_DIV=7,CLKC2_DIV=7,CLKC3_DIV=7,CLKC4_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=6,CLKC3_FPHASE=4,CLKC4_FPHASE=4,CLKC0_CPHASE=41,CLKC1_CPHASE=6,CLKC2_CPHASE=7,CLKC3_CPHASE=2,CLKC4_CPHASE=7,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Jan 25 18:59:37 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=40,CLKC1_DIV=10,CLKC2_DIV=10,CLKC3_DIV=10,CLKC4_DIV=10,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC2_FPHASE=4,CLKC4_FPHASE=2,CLKC0_CPHASE=39,CLKC1_CPHASE=9,CLKC3_CPHASE=4,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
============================================================
|
||||
Tang Dynasty, V5.0.25878
|
||||
Copyright: Shanghai Anlogic Infotech Co., Ltd.
|
||||
2011 - 2021
|
||||
Executable = C:/Anlogic/TD5.0.25878/bin/td.exe
|
||||
Run by = guo.xu
|
||||
Run Date = Mon Jan 25 19:03:40 2021
|
||||
|
||||
Run on = SHL-PF1LSH77
|
||||
============================================================
|
||||
RUN-001 : GUI based run...
|
||||
RUN-1002 : start command "import_device eagle_20.db -package BGA256X -basic"
|
||||
ARC-1001 : Device Initialization.
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : OPTION | IO | SETTING
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/M14 | gpio
|
||||
ARC-1001 : done | P13 | gpio
|
||||
ARC-1001 : program_b | T2 | dedicate
|
||||
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
|
||||
ARC-1001 : ------------------------------------------------------------------
|
||||
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
|
||||
RUN-1002 : start command "read_verilog -file clk_pll.v"
|
||||
HDL-1007 : analyze verilog file clk_pll.v
|
||||
HDL-1007 : elaborate module clk_pll in clk_pll.v(26)
|
||||
HDL-1007 : elaborate module EG_LOGIC_BUFG in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(8)
|
||||
HDL-1007 : elaborate module EG_PHY_PLL(FIN="25.000",CLKC0_DIV=40,CLKC1_DIV=20,CLKC2_DIV=20,CLKC3_DIV=20,CLKC4_DIV=20,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC4_FPHASE=4,CLKC0_CPHASE=39,CLKC1_CPHASE=19,CLKC2_CPHASE=4,CLKC3_CPHASE=9,CLKC4_CPHASE=3,GMC_GAIN=2,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=1,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in C:/Anlogic/TD5.0.25878/arch/eagle_macro.v(930)
|
||||
HDL-1200 : Current top model is clk_pll
|
||||
HDL-1100 : Inferred 0 RAMs.
|
||||
RUN-1002 : start command "optimize_rtl"
|
||||
RUN-1001 : Open license file C:/Anlogic/TD5.0.25878/license/Anlogic.lic
|
||||
RUN-1001 : Print Rtl Property
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
RUN-1001 : compress_add | ripple | ripple
|
||||
RUN-1001 : elf_sload | off | off
|
||||
RUN-1001 : fix_undriven | 0 | 0
|
||||
RUN-1001 : flatten | off | off
|
||||
RUN-1001 : gate_sharing | on | on
|
||||
RUN-1001 : hdl_warning_level | normal | normal
|
||||
RUN-1001 : impl_internal_tribuf | on | on
|
||||
RUN-1001 : impl_set_reset | on | on
|
||||
RUN-1001 : infer_gsr | off | off
|
||||
RUN-1001 : keep_hierarchy | auto | auto
|
||||
RUN-1001 : max_fanout | 9999 | 9999
|
||||
RUN-1001 : max_oh2bin_len | 10 | 10
|
||||
RUN-1001 : merge_equal | on | on
|
||||
RUN-1001 : merge_equiv | on | on
|
||||
RUN-1001 : merge_mux | off | off
|
||||
RUN-1001 : min_ce_fanout | 16 | 16
|
||||
RUN-1001 : min_ripple_len | auto | auto
|
||||
RUN-1001 : oh2bin_ratio | 0.08 | 0.08
|
||||
RUN-1001 : opt_adder_fanout | on | on
|
||||
RUN-1001 : opt_arith | on | on
|
||||
RUN-1001 : opt_big_gate | off | off
|
||||
RUN-1001 : opt_const | on | on
|
||||
RUN-1001 : opt_const_mult | on | on
|
||||
RUN-1001 : opt_lessthan | on | on
|
||||
RUN-1001 : opt_mux | off | off
|
||||
RUN-1001 : opt_ram | high | high
|
||||
RUN-1001 : rtl_sim_model | off | off
|
||||
RUN-1001 : seq_syn | on | on
|
||||
RUN-1001 : ------------------------------------------------------
|
||||
SYN-1012 : SanityCheck: Model "clk_pll"
|
||||
SYN-1011 : Flatten model clk_pll
|
||||
SYN-1014 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/0 useful/useless insts
|
||||
SYN-1015 : Optimize round 1, 1 better
|
||||
SYN-1014 : Optimize round 2
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
SYN-1015 : Optimize round 2, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 3/1 useful/useless insts
|
||||
RUN-1002 : start command "map_macro -nopad"
|
||||
RUN-1001 : Print Gate Property
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : Parameters | Settings | Default Values
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
RUN-1001 : auto_partition | fine | fine
|
||||
RUN-1001 : cascade_dsp | off | off
|
||||
RUN-1001 : cascade_eram | on | on
|
||||
RUN-1001 : gate_sim_model | off | off
|
||||
RUN-1001 : map_sim_model | off | off
|
||||
RUN-1001 : opt_area | medium | medium
|
||||
RUN-1001 : opt_timing | auto | auto
|
||||
RUN-1001 : pack_effort | medium | medium
|
||||
RUN-1001 : pack_lslice_ripple | on | on
|
||||
RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
|
||||
RUN-1001 : pack_seq_in_io | on | on
|
||||
RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
|
||||
RUN-1001 : report | standard | standard
|
||||
RUN-1001 : ----------------------------------------------------------
|
||||
SYN-2501 : Processed 0 LOGIC_BUF instances.
|
||||
SYN-2501 : 1 BUFG to GCLK
|
||||
SYN-2571 : Optimize after map_dsp, round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2571 : Optimize after map_dsp, round 1, 0 better
|
||||
SYN-2501 : Optimize round 1
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
SYN-2501 : Optimize round 1, 0 better
|
||||
SYN-1032 : 10/1 useful/useless nets, 4/1 useful/useless insts
|
||||
RUN-1002 : start command "write_verilog clk_pll_sim.v"
|
||||
HDL-1201 : write out verilog file clk_pll_sim.v
|
||||
GUI-2000 : Create ip file(s) successfully :{EG4X20BG256(F:/app/anlogic_app_demo/each_app/memory/APUG0xx_ddr1/APUG0xx_ddr1_eg4d/prj/al_ip/clk_pll.v)}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue