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lvds-mono-16m
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1.更新时序收敛；2.增加21号寄存器配置b面行.

This commit is contained in:
17828169534 2024-03-12 15:05:50 +08:00
parent 5fd76ad16c
commit 9287a41110
151 changed files with 230012 additions and 4853 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/hg_mp/drx_top/huagao_mipi_top.v
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@ -345,6 +345,28 @@ reg[31:0] mipi_rst_d0 ;
reg[1:0] ubus_lpclk_d0 , ubus_lpclk_d1 ;
wire O_clk_lp_p_sync;
wire O_clk_lp_n_sync;
cdc_sync # (
.DEPTH (20),
.WIDTH (13)
) u_O_clk_lp_p( /* synthesis keep_hierarchy=true */
.to_clk (clk_ubus ),
.rest_n (rst_n ),
.signal_from(O_clk_lp_p ),
.signal_to (O_clk_lp_p_sync )
);
cdc_sync # (
.DEPTH (20),
.WIDTH (13)
) u_O_clk_lp_n( /* synthesis keep_hierarchy=true */
.to_clk (clk_ubus ),
.rest_n (rst_n ),
.signal_from(O_clk_lp_n ),
.signal_to (O_clk_lp_n_sync )
);
always @ (posedge clk_ubus) begin
if (~rst_n) begin
@ -354,7 +376,7 @@ always @ (posedge clk_ubus) begin
else begin
//ubus_lpclk_d0 <= MP1_LPCLK ;
ubus_lpclk_d0 <= {O_clk_lp_p,O_clk_lp_n} ;
ubus_lpclk_d0 <= {O_clk_lp_p_sync,O_clk_lp_n_sync} ;
ubus_lpclk_d1 <= ubus_lpclk_d0 ;
end
end
@ -740,7 +762,7 @@ exdev_ctl #
.adc_freqdiv (adc_freqdiv ),
.line_sync (line_sycn_b),
.en_work (en_work_b ),
.bg_sp_t (bg_sp_t_a )
.bg_sp_t (bg_sp_t_b )
);

2
src/hg_mp/fe/rddpram_ctl.v
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@ -127,7 +127,7 @@ end
reg cis_sel_d0,cis_sel_d1;
always @ (posedge pclk ) begin
always @ (posedge clk ) begin
if (!reset_n)
begin
cis_sel_d0 <= 1'b0;

2
src/hg_mp/fe/rddpram_ctl_rev.v
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@ -127,7 +127,7 @@ end
reg cis_sel_d0,cis_sel_d1;
always @ (posedge pclk ) begin
always @ (posedge clk ) begin
if (!reset_n)
begin
cis_sel_d0 <= 1'b0;

4
src/hg_mp/local_bus/ubus_top.v
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@ -245,8 +245,8 @@ local_bus_slve_cis u_local_bus_slve_cis(
,.reg2nd_17 ( ) //output reg [31:0]
,.reg2nd_18 ( ) //output reg [31:0]
,.reg2nd_19 ( bg_sp_t_a ) //output reg [31:0]
,.reg2nd_20 ( bg_sp_t_b ) //output reg [31:0]
,.reg2nd_20 ( ) //output reg [31:0]
,.reg2nd_21 ( bg_sp_t_b )
);
assign debug = cis_sel;

7934
src/prj/td_project/al_devicechain/hg_anlogic_L1.svf Normal file
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File diff suppressed because it is too large Load Diff

6
src/prj/td_project/hg_anlogic.adc
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@ -62,10 +62,12 @@ set_inst_assignment {u_pll/pll_inst} {location = x40y0z0;}
create_bound { bound2 } -mode fixed -width 25 -height 25 -origin { 0 0 }
create_bound { bound3 } -mode fixed -width 18 -height 20 -origin { 23 0 }
create_bound { bound3 } -mode fixed -width 18 -height 30 -origin { 23 0 }
add_cells_to_bound -bound { bound2 } -cells { u_mipi_dphy_tx_wrapper }
add_cells_to_bound -bound { bound2 } -cells { U_rgb_to_csi_pakage }
#add_cells_to_bound -bound { bound2 } -cells { exdev_ctl_a }
#add_cells_to_bound -bound { bound2 } -cells { exdev_ctl_b }
add_cells_to_bound -bound { bound3 } -cells { u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper }
add_cells_to_bound -bound { bound3 } -cells { u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper }
#add_cells_to_bound -bound { bound3 } -cells {sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert }
#add_cells_to_bound -bound { bound3 } -cells {sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert }

3
src/prj/td_project/hg_anlogic.al
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@ -572,6 +572,9 @@
<BitgenProperty::GeneralOption>
<bin>on</bin>
</BitgenProperty::GeneralOption>
<PlaceProperty>
<opt_timing>high</opt_timing>
</PlaceProperty>
</Strategy>
</Run>
</Runs>

12
src/prj/td_project/hg_anlogic.sdc
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@ -10,7 +10,13 @@ create_generated_clock -name S_clk_x4 -source [get_pins {u_pll/pll_inst.clkc[0]}
create_generated_clock -name S_clk_x4_90d -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 90 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[3]}]
create_generated_clock -name a_sclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
set_false_path -from [get_regs {u_pixel_cdc/multipy_xy[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]}]
set_false_path -from [get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]}]
set_false_path -from [get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]}]
set_false_path -from [get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]}]
set_false_path -from [get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]}]
set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]}]
set_false_path -from [get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]}]
set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]}]
#set_input_delay -clock [get_clocks {clock_source}] 12.5 [get_ports {a_ad_sdi b_ad_sdi clock_source global_reset_n gpio_trigger onoff_in paper_in rxd_dsp scan_in}]
#set_input_delay -clock [get_clocks {a_lvds_clk_p}] 6.25 [get_ports {a_lvds_clk_p a_lvds_data_p a_lvds_data_p[0] a_lvds_data_p[1] a_lvds_data_p[2] a_lvds_data_p[3] a_lvds_data_p[4]}]
#set_input_delay -clock [get_clocks {b_lvds_clk_p}] 6.25 [get_ports {b_lvds_clk_p b_lvds_data_p b_lvds_data_p[0] b_lvds_data_p[1] b_lvds_data_p[2] b_lvds_data_p[3] b_lvds_data_p[4]}]
@ -22,3 +28,7 @@ create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_
set_false_path -from [get_regs {BUSY_MIPI}] -to [get_regs {BUSY_MIPI_sync_d0}]
set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {a_pclk_rstn}]
set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {b_pclk_rstn}]
#set_false_path -from [get_nets {u_bus_top/start_sp_a_tmp[*]}] -to [get_regs {u_bus_top/start_sp_a_sync1d_48m[*]}]
#set_false_path -from [get_nets {u_bus_top/start_sp_b_tmp[*]}] -to [get_regs {u_bus_top/start_sp_b_sync1d_48m[*]}]
set_false_path -from [get_nets {u_O_clk_lp_p/signal_from[*]}] -to [get_regs {u_O_clk_lp_p/temp[*]}]
set_false_path -from [get_nets {u_O_clk_lp_n/signal_from[*]}] -to [get_regs {u_O_clk_lp_n/temp[*]}]

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src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_094627.log Normal file
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src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_101346.log Normal file
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src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102305.log Normal file
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src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102726.log Normal file
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src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103254.log Normal file
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1830
src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103905.log Normal file
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src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_104647.log Normal file
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382
src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_105655.log Normal file
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@ -0,0 +1,382 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Mar 11 10:56:55 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.151544s wall, 2.093750s user + 0.062500s system = 2.156250s CPU (100.2%)
RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
RUN-1002 : start command "get_ports a_lvds_clk_p"
RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
RUN-1002 : start command "get_ports b_lvds_clk_p"
RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
RUN-1002 : start command "get_ports a_lvds_clk_p"
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
RUN-1002 : start command "get_ports b_lvds_clk_p"
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
RUN-1002 : start command "get_ports a_lvds_clk_p"
RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
RUN-1002 : start command "get_ports b_lvds_clk_p"
RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
RUN-1002 : start command "get_ports clock_source"
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
RUN-1002 : start command "set_false_path -from -to "
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
RUN-1002 : start command "set_false_path -setup -from -to "
RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
RUN-1002 : start command "set_false_path -setup -from -to "
RUN-1002 : start command "get_regs BUSY_MIPI"
RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
RUN-1002 : start command "set_false_path -from -to "
RUN-1002 : start command "get_regs clkubus_rstn"
RUN-1002 : start command "get_nets a_pclk_rstn"
RUN-1002 : start command "set_false_path -from -to "
RUN-1002 : start command "get_regs clkubus_rstn"
RUN-1002 : start command "get_nets b_pclk_rstn"
RUN-1002 : start command "set_false_path -from -to "
RUN-1002 : start command "place"
RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Place Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : detailed_place | on | on |
RUN-1001 : effort | medium | medium |
RUN-1001 : fix_hold | off | off |
RUN-1001 : legalization | ori | ori |
RUN-1001 : new_spreading | on | on |
RUN-1001 : opt_timing | medium | medium |
RUN-1001 : post_clock_route_opt | off | off |
RUN-1001 : pr_strategy | 1 | 1 |
RUN-1001 : relaxation | 1.00 | 1.00 |
RUN-1001 : retiming | off | off |
RUN-1001 : --------------------------------------------------------------
PHY-3001 : Placer runs in 8 thread(s).
RUN-1002 : start command "legalize_phy_inst"
SYN-1011 : Flatten model huagao_mipi_top
SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
SYN-5055 Similar messages will be suppressed.
RUN-1002 : start command "phys_opt -simplify_lut"
SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
SYN-4026 : Tagged 15 rtl::Net as clock net
SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
PHY-1001 : Populate physical database on model huagao_mipi_top.
RUN-1001 : There are total 17673 instances
RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
RUN-1001 : There are total 20251 nets
RUN-6004 WARNING: There are 20 nets with only 1 pin.
RUN-1001 : 13316 nets have 2 pins
RUN-1001 : 5518 nets have [3 - 5] pins
RUN-1001 : 1004 nets have [6 - 10] pins
RUN-1001 : 162 nets have [11 - 20] pins
RUN-1001 : 177 nets have [21 - 99] pins
RUN-1001 : 54 nets have 100+ pins
PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
RUN-1001 : Report Control nets information:
RUN-1001 : DFF Distribution
RUN-1001 : ----------------------------------
RUN-1001 : CE | SSR | ASR | DFF Count
RUN-1001 : ----------------------------------
RUN-1001 : No | No | No | 793
RUN-1001 : No | No | Yes | 1968
RUN-1001 : No | Yes | No | 3473
RUN-1001 : Yes | No | No | 64
RUN-1001 : Yes | No | Yes | 72
RUN-1001 : Yes | Yes | No | 2673
RUN-1001 : ----------------------------------
RUN-0007 : Control Group Statistic
RUN-0007 : ---------------------------
RUN-0007 : #CLK | #CE | #SSR/ASR
RUN-0007 : ---------------------------
RUN-0007 : 12 | 76 | 57
RUN-0007 : ---------------------------
RUN-0007 : Control Set = 142
PHY-3001 : Initial placement ...
USR-8086 ERROR: Failed to add cell sampling_fe_b/u_sort_rev/u_data_prebuffer_rev/ram_switch/insert to bound bound3: Please force keep hierarchy in source if necessary.
PHY-9101 ERROR: Initial place errored out.
RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_105655.log"

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@ -0,0 +1,426 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Mar 11 15:15:37 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-5007 WARNING: 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(297)
HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(297)
HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(297)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(333)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(334)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(333)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(334)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "elaborate -top huagao_mipi_top"
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(333)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(334)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
HDL-8007 ERROR: external reference 'set_flag_2d' remains unresolved in ../../../../hg_mp/fe/sort.v(333)
HDL-1007 : module 'sort' remains a black box due to errors in its contents in ../../../../hg_mp/fe/sort.v(1)
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_151537.log"

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============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Tue Mar 12 10:09:46 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-5007 WARNING: data object 'DVAL' is already declared in ../../../../hg_mp/fe/read_ram_data.v(120)
HDL-1007 : previous declaration of 'DVAL' is from here in ../../../../hg_mp/fe/read_ram_data.v(31)
HDL-5007 WARNING: second declaration of 'DVAL' is ignored in ../../../../hg_mp/fe/read_ram_data.v(120)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(130)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(133)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(134)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(135)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(136)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(130)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(133)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(134)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(135)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(136)
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "elaborate -top huagao_mipi_top"
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(130)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(133)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(134)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(135)
HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(136)
HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
HDL-8007 ERROR: external reference 'DVAL_tmp' remains unresolved in ../../../../hg_mp/fe/read_ram_data.v(130)
HDL-1007 : module 'read_ram_data' remains a black box due to errors in its contents in ../../../../hg_mp/fe/read_ram_data.v(1)
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_100945.log"

1871
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