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对译码数据进行同步处理：修改A_sp_pad引脚；

This commit is contained in:
17828169534 2024-03-19 15:10:48 +08:00
parent 77e52e2321
commit 9ca6f89b22
203 changed files with 281027 additions and 5104 deletions
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14
src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.ipc Normal file
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@ -0,0 +1,14 @@
<?xml version='1.0' encoding='UTF-8'?>
<ODDRConfig>
<GeneralConfig>
<Type>EG_LOGIC_ODDR</Type>
<Device>EG4D20EG176</Device>
<create_VHDL>true</create_VHDL>
<inst>lvds_iddr</inst>
<ASYNCRST>ENABLE</ASYNCRST>
</GeneralConfig>
<GeneratedFiles>
<Verilog Enable="true">lvds_iddr.v</Verilog>
<VHDL Enable="false">lvds_iddr.vhd</VHDL>
</GeneratedFiles>
</ODDRConfig>

30
src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.v Normal file
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@ -0,0 +1,30 @@
/************************************************************\
** Copyright (c) 2012-2023 Anlogic Inc.
** All Right Reserved.\
\************************************************************/
/************************************************************\
** Log : This file is generated by Anlogic IP Generator.
** File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.v
** Date : 2024 03 18
** TD version : 5.6.71036
\************************************************************/
`timescale 1ns / 1ps
module lvds_iddr ( q, clk, d1, d0, rst );
output q;
input clk;
input d1;
input d0;
input rst;
EG_LOGIC_ODDR #(
.ASYNCRST("ENABLE"))
oddr (
.q(q),
.clk(clk),
.d1(d1),
.d0(d0),
.rst(rst));
endmodule

42
src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.vhd Normal file
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@ -0,0 +1,42 @@
--------------------------------------------------------------
-- Copyright (c) 2012-2023 Anlogic Inc.
-- All Right Reserved.
--------------------------------------------------------------
-- Log : This file is generated by Anlogic IP Generator.
-- File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.vhd
-- Date : 2024 03 18
-- TD version : 5.6.71036
--------------------------------------------------------------
LIBRARY ieee;
USE work.ALL;
USE ieee.std_logic_1164.all;
LIBRARY eagle_macro;
USE eagle_macro.EAGLE_COMPONENTS.all;
ENTITY lvds_iddr IS
PORT (
q : OUT STD_LOGIC;
clk : IN STD_LOGIC;
d1 : IN STD_LOGIC;
d0 : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END lvds_iddr;
ARCHITECTURE struct OF lvds_iddr IS
BEGIN
inst : EG_LOGIC_ODDR
GENERIC MAP (
ASYNCRST => "ENABLE"
)
PORT MAP (
q => q,
clk => clk,
d1 => d1,
d0 => d0,
rst => rst
);
END struct;

4
src/hg_mp/anlogic_ip/pll/pll.v
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@ -4,8 +4,8 @@
\************************************************************/
/************************************************************\
** Log : This file is generated by Anlogic IP Generator.
** File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value/src/hg_mp/anlogic_ip/pll/pll.v
** Date : 2024 01 18
** File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/pll/pll.v
** Date : 2024 03 18
** TD version : 5.6.71036
\************************************************************/

233
src/hg_mp/drx_top/huagao_mipi_top.v
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@ -160,6 +160,8 @@ assign rst_sys_n = (pll_locked0&pll_locked1&pll_locked2);
assign rst_n = pll_locked0;
assign sys_initial_done = pll_locked0;
assign clk_ubus = clk_adc;
//=================================================
//A SIDE
@ -169,7 +171,7 @@ wire a_vs,a_cl1,a_cl0,a_en,a_ch;
wire [29:0] a_rgb;
wire [4:0] a_lvds_flag;
assign a_lvds_flag = {a_vs,a_cl1,a_cl0,a_en,a_ch};
lvds_rx ua_lvds_rx
@ -191,22 +193,117 @@ lvds_rx ua_lvds_rx
.rgb (a_rgb )// assign rgb = {r[9:0],g[9:0],b[9:0]};
);/* synthesis keep_hierarchy=false */
//=================================================
//B SIDE
//=================================================
reg a_vs_sync_d1;
reg a_vs_sync_d2;
reg a_vs_sync_d3;
reg a_cl0_sync_d1;
reg a_cl0_sync_d2;
reg a_cl0_sync_d3;
reg a_en_sync_d1;
reg a_en_sync_d2;
reg a_en_sync_d3;
reg a_cl1_sync_d1;
reg a_cl1_sync_d2;
reg a_cl1_sync_d3;
reg a_ch_sync_d1;
reg a_ch_sync_d2;
reg a_ch_sync_d3;
reg [29:0] a_rgb_sync_d1;
reg [29:0] a_rgb_sync_d2;
reg [29:0] a_rgb_sync_d3;
assign a_lvds_flag = {a_vs_sync_d2,a_cl1_sync_d2,a_cl0_sync_d2,a_en_sync_d2,a_ch_sync_d2};
always @ (posedge a_pclk) begin
if (~rst_n) begin
a_vs_sync_d1<=1'b0;
a_vs_sync_d2<=1'b0;
a_vs_sync_d3<=1'b0;
end
else begin
a_vs_sync_d1<=a_vs;
a_vs_sync_d2<=a_vs_sync_d1;
a_vs_sync_d3<=a_vs_sync_d2;
end
end
always @ (posedge a_pclk) begin
if (~rst_n) begin
a_cl0_sync_d1<=1'b0;
a_cl0_sync_d2<=1'b0;
a_cl0_sync_d3<=1'b0;
end
else begin
a_cl0_sync_d1<=a_cl0;
a_cl0_sync_d2<=a_cl0_sync_d1;
a_cl0_sync_d3<=a_cl0_sync_d2;
end
end
always @ (posedge a_pclk) begin
if (~rst_n) begin
a_en_sync_d1<=1'b0;
a_en_sync_d2<=1'b0;
a_en_sync_d3<=1'b0;
end
else begin
a_en_sync_d1<=a_en;
a_en_sync_d2<=a_en_sync_d1;
a_en_sync_d3<=a_en_sync_d2;
end
end
always @ (posedge a_pclk) begin
if (~rst_n) begin
a_cl1_sync_d1<=1'b0;
a_cl1_sync_d2<=1'b0;
a_cl1_sync_d3<=1'b0;
end
else begin
a_cl1_sync_d1<=a_cl1;
a_cl1_sync_d2<=a_cl1_sync_d1;
a_cl1_sync_d3<=a_cl1_sync_d2;
end
end
always @ (posedge a_pclk) begin
if (~rst_n) begin
a_ch_sync_d1<=1'b0;
a_ch_sync_d2<=1'b0;
a_ch_sync_d3<=1'b0;
end
else begin
a_ch_sync_d1<=a_ch;
a_ch_sync_d2<=a_ch_sync_d1;
a_ch_sync_d3<=a_ch_sync_d2;
end
end
always @ (posedge a_pclk) begin
if (~rst_n) begin
a_rgb_sync_d1<=1'b0;
a_rgb_sync_d2<=1'b0;
a_rgb_sync_d3<=1'b0;
end
else begin
a_rgb_sync_d1<=a_rgb;
a_rgb_sync_d2<=a_rgb_sync_d1;
a_rgb_sync_d3<=a_rgb_sync_d2;
end
end
wire b_vs,b_cl1,b_cl0,b_en,b_ch;
wire [29:0] b_rgb;
wire [4:0] b_lvds_flag;
assign b_lvds_flag = {b_vs,b_cl1,b_cl0,b_en,b_ch};
//=================================================
//B SIDE
//=================================================
lvds_rx ub_lvds_rx
(
// lvds
.lvds_clk (b_lvds_clk_p ),
.lvds_data (b_lvds_data_p ),
.lvds_data (b_lvds_data_p ),
// pll
.rst (rst_sys ),
.sclk (b_sclk ), // sclk = pclk * 3.5
@ -221,6 +318,103 @@ lvds_rx ub_lvds_rx
.rgb (b_rgb )// assign rgb = {r[9:0],g[9:0],b[9:0]};
);/* synthesis keep_hierarchy=false */
reg b_vs_sync_d1;
reg b_vs_sync_d2;
reg b_vs_sync_d3;
reg b_cl0_sync_d1;
reg b_cl0_sync_d2;
reg b_cl0_sync_d3;
reg b_en_sync_d1;
reg b_en_sync_d2;
reg b_en_sync_d3;
reg b_cl1_sync_d1;
reg b_cl1_sync_d2;
reg b_cl1_sync_d3;
reg b_ch_sync_d1;
reg b_ch_sync_d2;
reg b_ch_sync_d3;
reg [29:0] b_rgb_sync_d1;
reg [29:0] b_rgb_sync_d2;
reg [29:0] b_rgb_sync_d3;
assign b_lvds_flag = {b_vs_sync_d2,b_cl1_sync_d2,b_cl0_sync_d2,b_en_sync_d2,b_ch_sync_d2};
always @ (posedge b_pclk) begin
if (~rst_n) begin
b_vs_sync_d1<=1'b0;
b_vs_sync_d2<=1'b0;
b_vs_sync_d3<=1'b0;
end
else begin
b_vs_sync_d1<=b_vs;
b_vs_sync_d2<=b_vs_sync_d1;
b_vs_sync_d3<=b_vs_sync_d2;
end
end
always @ (posedge b_pclk) begin
if (~rst_n) begin
b_cl0_sync_d1<=1'b0;
b_cl0_sync_d2<=1'b0;
b_cl0_sync_d3<=1'b0;
end
else begin
b_cl0_sync_d1<=b_cl0;
b_cl0_sync_d2<=b_cl0_sync_d1;
b_cl0_sync_d3<=b_cl0_sync_d2;
end
end
always @ (posedge b_pclk) begin
if (~rst_n) begin
b_en_sync_d1<=1'b0;
b_en_sync_d2<=1'b0;
b_en_sync_d3<=1'b0;
end
else begin
b_en_sync_d1<=b_en;
b_en_sync_d2<=b_en_sync_d1;
b_en_sync_d3<=b_en_sync_d2;
end
end
always @ (posedge b_pclk) begin
if (~rst_n) begin
b_cl1_sync_d1<=1'b0;
b_cl1_sync_d2<=1'b0;
b_cl1_sync_d3<=1'b0;
end
else begin
b_cl1_sync_d1<=b_cl1;
b_cl1_sync_d2<=b_cl1_sync_d1;
b_cl1_sync_d3<=b_cl1_sync_d2;
end
end
always @ (posedge b_pclk) begin
if (~rst_n) begin
b_ch_sync_d1<=1'b0;
b_ch_sync_d2<=1'b0;
b_ch_sync_d3<=1'b0;
end
else begin
b_ch_sync_d1<=b_ch;
b_ch_sync_d2<=b_ch_sync_d1;
b_ch_sync_d3<=b_ch_sync_d2;
end
end
always @ (posedge b_pclk) begin
if (~rst_n) begin
b_rgb_sync_d1<=1'b0;
b_rgb_sync_d2<=1'b0;
b_rgb_sync_d3<=1'b0;
end
else begin
b_rgb_sync_d1<=b_rgb;
b_rgb_sync_d2<=b_rgb_sync_d1;
b_rgb_sync_d3<=b_rgb_sync_d2;
end
end
//=================================================
//MIPI PHY
//=================================================
@ -348,7 +542,7 @@ reg[1:0] ubus_lpclk_d0 , ubus_lpclk_d1 ;
wire O_clk_lp_p_sync;
wire O_clk_lp_n_sync;
cdc_sync # (
.DEPTH (20),
.DEPTH (3),
.WIDTH (1)
) u_O_clk_lp_p( /* synthesis keep_hierarchy=true */
.to_clk (clk_ubus ),
@ -358,7 +552,7 @@ cdc_sync # (
);
cdc_sync # (
.DEPTH (20),
.DEPTH (3),
.WIDTH (1)
) u_O_clk_lp_n( /* synthesis keep_hierarchy=true */
.to_clk (clk_ubus ),
@ -587,7 +781,7 @@ always @ (posedge clk_ubus ) begin
BUSY_MIPI_sync_d1 <= 1'b0;
end
else begin
BUSY_MIPI_sync_d0 <= BUSY_MIPI_sync;
BUSY_MIPI_sync_d0 <= BUSY_MIPI;
BUSY_MIPI_sync_d1 <= BUSY_MIPI_sync_d0;
end
end
@ -898,8 +1092,8 @@ always @ (posedge b_pclk) begin
test_data_b <= {test_data_b[29:20] + 1,test_data_b[19:10] + 1,test_data_b[9:0] + 1};
end
assign idata_a = sync_test_en_a ? test_data_a : a_rgb;
assign idata_b = sync_test_en_b ? test_data_b : b_rgb;
assign idata_a = sync_test_en_a ? test_data_a : a_rgb_sync_d2;
assign idata_b = sync_test_en_b ? test_data_b : b_rgb_sync_d2;
//=================================================
// Sampling A side
@ -1416,6 +1610,7 @@ reg[15:0] mipi_pixel_y_d0,mipi_pixel_y_d1;
reg[YPIXEL_WIDTH_TOTAL-1:0] a_mipi_total_num_d0,a_mipi_total_num_d1;
reg[23:0] PIXDATA_MIPI;
wire eot_flag;
wire [2:0]debug_4;
rgb_to_csi_pakage U_rgb_to_csi_pakage
(
@ -1434,8 +1629,10 @@ rgb_to_csi_pakage U_rgb_to_csi_pakage
.O_hs_last ( S_hs_last ),
.O_hs_data ( S_hs_data ),
.frame_end_time ( frame_end_time ),
.eot_flag ( eot_flag )
.eot_flag ( eot_flag ),
.debug(debug_4)
);
reg [31:0] rgb_pac_cnt;
reg S_hs_valid_1d;
reg S_hs_valid_2d;
@ -1728,12 +1925,12 @@ always @(*) begin
end
assign debug[0] = a_vs ;
assign debug[1] = BUSY_MIPI;
assign debug[2] = BUSY_MIPI_sync ;
assign debug[3] = debug_1[1];
assign debug[4] = debug_1[0] ;
assign debug[1] = sync_eot;
assign debug[2] = mipi_lpclk_d1 == 2'b11 ? 1 : 0 ;
assign debug[3] = debug_4[1] ;
assign debug[4] = debug_4[0] ;
assign debug[5] = FV_MIPI ;
assign debug[6] = debug_1[4] ;
assign debug[6] = debug_4[2] ;
assign debug[7] = LV_MIPI;

76
src/hg_mp/fe/ad_sampling.v
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@ -216,7 +216,7 @@ always @ (posedge pclk ) begin
{line_sycn_3d,line_sycn_2d,line_sycn_1d} <= {line_sycn_2d,line_sycn_1d,line_sycn} ;
end
assign line_sycn_fall = (~line_sycn_3d) & line_sycn_2d;
assign line_sycn_fall = (~line_sycn_2d) & line_sycn_3d;
always @ (posedge pclk ) begin
if (!reset_n)
@ -252,18 +252,84 @@ assign debug[3] = lvds_flag == 5'b10011 ? 1 : 0;
assign debug[4] = lvds_flag == 5'b10110 ? 1 : 0;
assign debug[5] = lvds_flag == 5'b11010 ? 1 : 0;
reg [4:0] lvds_flag_d1;
reg [4:0] lvds_flag_d2;
reg [4:0] lvds_flag_d3;
reg line_sycn_flag_1;
reg line_sycn_flag_2;
reg line_sycn_flag_3;
always @ (posedge pclk )
begin
if (!reset_n) begin
lvds_flag_d1<=5'b0;
lvds_flag_d2<=5'b0;
lvds_flag_d3<=5'b0;
end
else begin
lvds_flag_d1<=lvds_flag;
lvds_flag_d2<=lvds_flag_d1;
lvds_flag_d3<=lvds_flag_d2;
end
end
always @ (posedge pclk )
begin
if (!reset_n)
line_sycn_flag_1 <= 1'b0;
else if (~sync_soft_n)
line_sycn_flag_1 <= 1'b0;
else if(lvds_flag == set_flag)
line_sycn_flag_1 <= 1'b1;
else if(cs == 1'b0)
line_sycn_flag_1 <= 1'b0;
else
line_sycn_flag_1 <= line_sycn_flag_1;
end
always @ (posedge pclk )
begin
if (!reset_n)
line_sycn_flag_2 <= 1'b0;
else if (~sync_soft_n)
line_sycn_flag_2 <= 1'b0;
else if(lvds_flag_d1 == set_flag)
line_sycn_flag_2 <= 1'b1;
else if(cs == 1'b0)
line_sycn_flag_2 <= 1'b0;
else
line_sycn_flag_2 <= line_sycn_flag_2;
end
always @ (posedge pclk )
begin
if (!reset_n)
line_sycn_flag_3 <= 1'b0;
else if (~sync_soft_n)
line_sycn_flag_3 <= 1'b0;
else if(lvds_flag_d2 == set_flag)
line_sycn_flag_3 <= 1'b1;
else if(cs == 1'b0)
line_sycn_flag_3 <= 1'b0;
else
line_sycn_flag_3 <= line_sycn_flag_3;
end
always @ (posedge pclk )
begin
if (!reset_n)
line_sycn <= 1'b0;
else if (~sync_soft_n)
line_sycn <= 1'b0;
else if(lvds_flag == set_flag)
line_sycn <= 1'b1;
line_sycn <= 1'b0;
else if(cs == 1'b0)
line_sycn <= 1'b0;
else
line_sycn <= line_sycn;
line_sycn <= line_sycn_flag_1 & line_sycn_flag_2 &line_sycn_flag_3;
end

43
src/hg_mp/fe/fifo_adc.v
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@ -40,6 +40,46 @@ localparam WR_FIFO = 3'b100;
reg [PBUFF_LENGTH_WIDTH+3-1:0] cnt;
reg [4:0]data_CTL_ADC_d1,data_CTL_ADC_d2;
reg line_sync_flag,line_sync_flag1,line_sync_flag2;
always @(posedge dataclk_ADC)
if(~rst_n) begin
data_CTL_ADC_d1 <= 5'd0;
data_CTL_ADC_d2 <= 5'd0;
end
else begin
data_CTL_ADC_d1 <= data_CTL_ADC;
data_CTL_ADC_d2 <= data_CTL_ADC_d1;
end
always @(posedge dataclk_ADC)begin
if(~rst_n)
line_sync_flag<=1'b0;
else if(data_CTL_ADC == PBUFF_DATA_CONTROL)
line_sync_flag<=1'b1;
else
line_sync_flag<=1'b0;
end
always @(posedge dataclk_ADC)begin
if(~rst_n)
line_sync_flag1<=1'b0;
else if(data_CTL_ADC_d1 == PBUFF_DATA_CONTROL)
line_sync_flag1<=1'b1;
else
line_sync_flag1<=1'b0;
end
always @(posedge dataclk_ADC)begin
if(~rst_n)
line_sync_flag2<=1'b0;
else if(data_CTL_ADC_d2 == PBUFF_DATA_CONTROL)
line_sync_flag2<=1'b1;
else
line_sync_flag2<=1'b0;
end
always @(posedge dataclk_ADC)
if(~rst_n) begin
@ -66,7 +106,8 @@ reg [PBUFF_LENGTH_WIDTH+3-1:0] cnt;
START:begin
cnt <= 'd0;
if(data_CTL_ADC == PBUFF_DATA_CONTROL)begin
//if(data_CTL_ADC == PBUFF_DATA_CONTROL)begin
if(line_sync_flag & line_sync_flag1 & line_sync_flag2)begin
rd_en <= 1'b1;
ADC_STATE <= WR_FIFO;
fifoA_ADC <= dataA_ADC;

2
src/hg_mp/local_bus/uart_2dsp_6M_921600.v
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@ -1,6 +1,6 @@
module uart_2dsp
#(
parameter BF_N = 5,
parameter BF_N = 4,
parameter CLKFREQ = 6000000,
parameter BAUDRATE = 921600

2
src/hg_mp/local_bus/ubus_top.v
View File

@ -215,7 +215,7 @@ local_bus_slve_cis u_local_bus_slve_cis(
//,.nd2reg_0 ( scan_status_sync3d_8m ) //input [31:0]
,.nd2reg_0 ( adc_cfg_data_o_sync3d_8m) //input [31:0]
,.nd2reg_1 ( 32'h000a0002 ) //input [31:0]
,.nd2reg_1 ( 32'h000a0004 ) //input [31:0]
,.nd2reg_2 ( lv_cnt2bus_sync3d ) //input [31:0]
,.nd2reg_3 ( fr_cnt2bus_sync3d ) //input [31:0]
,.nd2reg_4 ( lv_cnt_a_sync3d ) //input [31:0]

7
src/hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
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@ -31,7 +31,8 @@ module rgb_to_csi_pakage
output wire O_hs_last,
output reg[31:0] O_hs_data,
input [15:0] frame_end_time,
output reg eot_flag
output reg eot_flag,
output wire [2:0] debug
);
parameter DPI200_DEPTH = 816;
@ -505,7 +506,9 @@ else
eot_flag <= ~S_frame_end_delay_en_r[1] & S_frame_end_delay_en_r[3];
end
assign debug[0] = S_frame_end_delay_en;
assign debug[1] = S_frame_end_delay_cnt == frame_end_time ? 1 : 0 ;
assign debug[2] = S_frame_end_delay_cnt == 0 ? 1 : 0 ;
always @ (posedge I_pixel_clk) begin

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src/prj/td_project/SchematicImage.png
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4
src/prj/td_project/hg_anlogic.adc
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@ -23,7 +23,7 @@ set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; P
set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { b_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { a_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { b_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
@ -61,7 +61,7 @@ set_pin_assignment { txd_dsp } { LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVEST
set_inst_assignment {u_pll/pll_inst} {location = x40y0z0;}
create_bound { bound2 } -mode fixed -width 25 -height 25 -origin { 0 0 }
create_bound { bound2 } -mode fixed -width 26 -height 25 -origin { 0 0 }
create_bound { bound3 } -mode fixed -width 18 -height 30 -origin { 23 0 }
add_cells_to_bound -bound { bound2 } -cells { u_mipi_dphy_tx_wrapper }
add_cells_to_bound -bound { bound2 } -cells { U_rgb_to_csi_pakage }

4
src/prj/td_project/hg_anlogic.al
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@ -565,7 +565,11 @@
</Run>
<Run Name="phy_1" Type="PhysicalDesign" ConstraintSet="constraint_1" Description="" SynRun="syn_1" Active="true">
<Strategy Name="Default_PhysicalDesign_Strategy">
<BitgenProperty::GeneralOption>
<bin>on</bin>
</BitgenProperty::GeneralOption>
<PlaceProperty>
<effort>high</effort>
<opt_timing>high</opt_timing>
</PlaceProperty>
</Strategy>

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@ -0,0 +1,258 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Fri Mar 15 14:04:09 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "import_db hg_anlogic_pr.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
PHY-5010 Similar messages will be suppressed.
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
PHY-1001 : eco open net = 0
PHY-1001 : 508 feed throughs used by 381 nets
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db hg_anlogic_pr.db" in 12.512183s wall, 12.171875s user + 0.265625s system = 12.437500s CPU (99.4%)
RUN-1004 : used memory is 793 MB, reserved memory is 785 MB, peak memory is 820 MB
RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
BIT-1003 : Start to generate bitstream.
BIT-1002 : Init instances with 8 threads.
BIT-1002 : Init instances completely, inst num: 6785
BIT-1002 : Init pips with 8 threads.
BIT-1002 : Init pips completely, net num: 17854, pip num: 166832
BIT-1002 : Init feedthrough with 8 threads.
BIT-1002 : Init feedthrough completely, num: 508
BIT-1003 : Multithreading accelaration with 8 threads.
BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 466630 bits set as '1'.
BIT-1004 : the usercode register value: 00000000101110110000000000000000
BIT-1004 : PLL setting string = 1011
BIT-1004 : Generate bits file hg_anlogic.bit.
BIT-1004 : Generate bin file hg_anlogic.bin.
RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.992985s wall, 62.046875s user + 0.156250s system = 62.203125s CPU (622.5%)
RUN-1004 : used memory is 819 MB, reserved memory is 821 MB, peak memory is 1086 MB
RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_140409.log"

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@ -0,0 +1,696 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Mar 18 10:11:38 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "import_db hg_anlogic_place.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db hg_anlogic_place.db" in 2.742081s wall, 2.609375s user + 0.140625s system = 2.750000s CPU (100.3%)
RUN-1004 : used memory is 374 MB, reserved memory is 353 MB, peak memory is 379 MB
RUN-1002 : start command "route"
RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1002 : start command "set_param route opt_timing high"
RUN-1002 : start command "set_param route priority routability"
RUN-1001 : Print Route Property
RUN-1001 : ----------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ----------------------------------------------------------
RUN-1001 : effort | medium | medium |
RUN-1001 : fix_hold | off | off |
RUN-1001 : opt_timing | high | medium | *
RUN-1001 : phy_sim_model | off | off |
RUN-1001 : priority | routability | timing | *
RUN-1001 : swap_pin | on | on |
RUN-1001 : ----------------------------------------------------------
PHY-1001 : Route runs in 8 thread(s)
RUN-1001 : There are total 6851 instances
RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
RUN-1001 : There are total 17983 nets
RUN-6002 WARNING: There are 1 undriven nets.
RUN-6004 WARNING: There are 21 nets with only 1 pin.
RUN-1001 : 10075 nets have 2 pins
RUN-1001 : 6508 nets have [3 - 5] pins
RUN-1001 : 742 nets have [6 - 10] pins
RUN-1001 : 311 nets have [11 - 20] pins
RUN-1001 : 318 nets have [21 - 99] pins
RUN-1001 : 8 nets have 100+ pins
RUN-1002 : start command "start_timer -report"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72045, tnet num: 17805, tinst num: 6849, tnode num: 94791, tedge num: 119669.
TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
TMR-2501 : Timing graph initialized successfully.
RUN-1003 : finish command "start_timer -report" in 1.661386s wall, 1.625000s user + 0.031250s system = 1.656250s CPU (99.7%)
RUN-1004 : used memory is 501 MB, reserved memory is 484 MB, peak memory is 501 MB
PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
TMR-2503 : Start to update net delay, extr mode = 3.
TMR-2504 : Update delay of 17805 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 3.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 2 constraints in total.
TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
PHY-1001 : Start global routing, caller is route ...
PHY-1001 : Routability prioritized.
RUN-1001 : Generating global routing grids ...
RUN-1001 : Building simple global routing graph ...
PHY-1001 : Generate routing nets ...
PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
PHY-1001 : Global iterations in 8 thread ...
PHY-1002 : len = 846032, over cnt = 2656(7%), over = 4489, worst = 9
PHY-1002 : len = 864952, over cnt = 1635(4%), over = 2372, worst = 9
PHY-1002 : len = 888664, over cnt = 404(1%), over = 544, worst = 7
PHY-1002 : len = 896896, over cnt = 21(0%), over = 32, worst = 7
PHY-1002 : len = 897232, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End global iterations; 3.414847s wall, 4.468750s user + 0.062500s system = 4.531250s CPU (132.7%)
PHY-1001 : Congestion index: top1 = 55.52, top5 = 50.19, top10 = 46.84, top15 = 44.60.
PHY-1001 : End global routing; 3.712590s wall, 4.734375s user + 0.078125s system = 4.812500s CPU (129.6%)
PHY-1001 : Start detail routing ...
PHY-1001 : Routability prioritized.
PHY-1001 : Current memory(MB): used = 668, reserve = 656, peak = 668.
PHY-1001 : Detailed router is running in normal mode.
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
PHY-5010 Similar messages will be suppressed.
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
PHY-1001 : Current memory(MB): used = 964, reserve = 958, peak = 964.
PHY-1001 : End build detailed router design. 4.327209s wall, 4.281250s user + 0.046875s system = 4.328125s CPU (100.0%)
PHY-1001 : Detail Route ...
PHY-1001 : ===== Detail Route Phase 1 =====
PHY-1001 : Clock net routing.....
PHY-1001 : Routed 0% nets.
PHY-1022 : len = 267368, over cnt = 4(0%), over = 4, worst = 1, crit = 0
PHY-1001 : End initial clock net routed; 6.235930s wall, 6.187500s user + 0.031250s system = 6.218750s CPU (99.7%)
PHY-1001 : Ripup-reroute.....
PHY-1001 : ===== DR Iter 1 =====
PHY-1022 : len = 267424, over cnt = 0(0%), over = 0, worst = 0, crit = 0
PHY-1001 : End DR Iter 1; 0.523152s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (101.5%)
PHY-1001 : Current memory(MB): used = 1001, reserve = 995, peak = 1001.
PHY-1001 : End phase 1; 6.771743s wall, 6.718750s user + 0.031250s system = 6.750000s CPU (99.7%)
PHY-1001 : ===== Detail Route Phase 2 =====
PHY-1001 : Initial routing.....
PHY-1001 : Routed 44% nets.
PHY-1001 : Routed 52% nets.
PHY-1001 : Routed 61% nets.
PHY-1001 : Routed 74% nets.
PHY-1001 : Routed 93% nets.
PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
PHY-1001 : Current memory(MB): used = 1021, reserve = 1016, peak = 1021.
PHY-1001 : End initial routed; 32.520606s wall, 69.328125s user + 0.359375s system = 69.687500s CPU (214.3%)
PHY-1001 : Current memory(MB): used = 1021, reserve = 1016, peak = 1021.
PHY-1001 : End phase 2; 32.520650s wall, 69.328125s user + 0.359375s system = 69.687500s CPU (214.3%)
PHY-1001 : ===== Detail Route Phase 3 =====
PHY-1001 : Ripup-reroute.....
PHY-1001 : ===== DR Iter 1 =====
PHY-1022 : len = 2.21129e+06, over cnt = 697(0%), over = 697, worst = 1, crit = 0
PHY-1001 : End DR Iter 1; 2.084650s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (167.9%)
PHY-1001 : ===== DR Iter 2 =====
PHY-1022 : len = 2.21005e+06, over cnt = 197(0%), over = 197, worst = 1, crit = 0
PHY-1001 : End DR Iter 2; 0.783919s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (155.5%)
PHY-1001 : ===== DR Iter 3 =====
PHY-1022 : len = 2.20993e+06, over cnt = 61(0%), over = 61, worst = 1, crit = 0
PHY-1001 : End DR Iter 3; 0.519143s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (129.4%)
PHY-1001 : ===== DR Iter 4 =====
PHY-1022 : len = 2.21079e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
PHY-1001 : End DR Iter 4; 0.275660s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (119.0%)
PHY-1001 : ===== DR Iter 5 =====
PHY-1022 : len = 2.21089e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
PHY-1001 : End DR Iter 5; 0.279901s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (122.8%)
PHY-1001 : ===== DR Iter 6 =====
PHY-1022 : len = 2.21089e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
PHY-1001 : End DR Iter 6; 0.266985s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.5%)
PHY-1001 : ===== DR Iter 7 =====
PHY-1022 : len = 2.21089e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
PHY-1001 : End DR Iter 7; 0.428085s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.2%)
PHY-1001 : ===== DR Iter 8 =====
PHY-1022 : len = 2.2109e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
PHY-1001 : End DR Iter 8; 0.196943s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (111.1%)
PHY-1001 : ==== DR Iter 9 ====
PHY-1022 : len = 2.21091e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
PHY-1001 : End DR Iter 9; 0.206867s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.2%)
PHY-1001 : Commit to database.....
PHY-1001 : 588 feed throughs used by 424 nets
PHY-1001 : End commit to database; 2.337004s wall, 2.265625s user + 0.062500s system = 2.328125s CPU (99.6%)
PHY-1001 : Current memory(MB): used = 1123, reserve = 1122, peak = 1123.
PHY-1001 : End phase 3; 7.824634s wall, 9.890625s user + 0.062500s system = 9.953125s CPU (127.2%)
PHY-1003 : Routed, final wirelength = 2.21091e+06
PHY-1001 : Current memory(MB): used = 1127, reserve = 1127, peak = 1127.
PHY-1001 : End export database. 0.065240s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.8%)
PHY-1001 : End detail routing; 51.877298s wall, 90.640625s user + 0.515625s system = 91.156250s CPU (175.7%)
RUN-1003 : finish command "route" in 58.331756s wall, 98.031250s user + 0.671875s system = 98.703125s CPU (169.2%)
RUN-1004 : used memory is 888 MB, reserved memory is 893 MB, peak memory is 1127 MB
RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
RUN-1001 : standard
***Report Model: huagao_mipi_top Device: EG4D20EG176***
IO Statistics
#IO 61
#input 21
#output 40
#inout 0
Utilization Statistics
#lut 10176 out of 19600 51.92%
#reg 9605 out of 19600 49.01%
#le 12565
#lut only 2960 out of 12565 23.56%
#reg only 2389 out of 12565 19.01%
#lut&reg 7216 out of 12565 57.43%
#dsp 3 out of 29 10.34%
#bram 54 out of 64 84.38%
#bram9k 50
#fifo9k 4
#bram32k 4 out of 16 25.00%
#pad 75 out of 130 57.69%
#ireg 13
#oreg 21
#treg 0
#pll 3 out of 4 75.00%
#gclk 6 out of 16 37.50%
Clock Resource Statistics
Index ClockNet Type DriverType Driver Fanout
#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1801
#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1451
#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1331
#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 929
#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/current_state[0]_syn_405.q0 136
#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28
#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg2_syn_159.f1 3
#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_eot_min/reg1_syn_320.f0 3
#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
paper_in INPUT P107 LVCMOS25 N/A N/A NONE
rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
a_sp_sampling OUTPUT P15 LVCMOS25 8 N/A OREG
b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
fan_pwm OUTPUT P39 LVCMOS25 8 N/A NONE
frame_indicator OUTPUT P32 LVCMOS25 8 N/A OREG
onoff_out OUTPUT P148 LVCMOS33 8 N/A NONE
paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
scan_out OUTPUT P118 LVCMOS25 8 N/A NONE
sys_initial_done OUTPUT P106 LVCMOS25 8 N/A NONE
txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
Report Hierarchy Area:
+---------------------------------------------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+---------------------------------------------------------------------------------------------------------+
|top |huagao_mipi_top |12565 |9149 |1027 |9639 |58 |3 |
| U_rgb_to_csi_pakage |rgb_to_csi_pakage |539 |450 |23 |441 |4 |1 |
| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |92 |4 |87 |4 |0 |
| U_crc16_24b |crc16_24b |50 |50 |0 |24 |0 |0 |
| U_ecc_gen |ecc_gen |12 |12 |0 |8 |0 |0 |
| exdev_ctl_a |exdev_ctl |763 |389 |96 |582 |0 |0 |
| u_ADconfig |AD_config |188 |124 |25 |146 |0 |0 |
| u_gen_sp |gen_sp |257 |152 |71 |118 |0 |0 |
| exdev_ctl_b |exdev_ctl |732 |367 |96 |543 |0 |0 |
| u_ADconfig |AD_config |161 |110 |25 |116 |0 |0 |
| u_gen_sp |gen_sp |264 |168 |71 |120 |0 |0 |
| sampling_fe_a |sampling_fe |3081 |2437 |306 |2126 |25 |0 |
| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
| u_ad_sampling |ad_sampling |190 |99 |17 |162 |0 |0 |
| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
| u_sort |sort |2856 |2326 |289 |1929 |25 |0 |
| rddpram_ctl |rddpram_ctl |4 |2 |0 |4 |0 |0 |
| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
| u0_wrsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
| u_data_prebuffer |data_prebuffer |2406 |2021 |253 |1556 |22 |0 |
| channelPart |channel_part_8478 |147 |135 |3 |142 |0 |0 |
| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |0 |
| ram_switch |ram_switch |1880 |1574 |197 |1149 |0 |0 |
| adc_addr_gen |adc_addr_gen |221 |194 |27 |114 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |17 |0 |0 |
| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |17 |0 |0 |
| [4]$ch_addr_gen |ch_addr_gen |23 |20 |3 |10 |0 |0 |
| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
| insert |insert |946 |667 |170 |639 |0 |0 |
| ram_switch_state |ram_switch_state |713 |713 |0 |396 |0 |0 |
| read_ram_i |read_ram |287 |234 |44 |192 |0 |0 |
| read_ram_addr |read_ram_addr |229 |189 |40 |150 |0 |0 |
| read_ram_data |read_ram_data |55 |42 |4 |39 |0 |0 |
| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u_transfer_300_to_200 |transfer_300_to_200 |328 |226 |36 |270 |3 |0 |
| u0_soft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
| sampling_fe_b |sampling_fe_rev |3256 |2498 |349 |2115 |25 |1 |
| u0_soft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
| u_ad_sampling |ad_sampling |189 |106 |17 |160 |0 |0 |
| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
| u_sort |sort_rev |3034 |2385 |332 |1922 |25 |1 |
| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
| u_data_prebuffer_rev |data_prebuffer_rev |2579 |2042 |290 |1557 |22 |1 |
| channelPart |channel_part_8478 |135 |125 |3 |128 |0 |0 |
| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
| ram_switch |ram_switch |1988 |1585 |197 |1149 |0 |0 |
| adc_addr_gen |adc_addr_gen |203 |176 |27 |98 |0 |0 |
| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |6 |0 |0 |
| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |6 |0 |0 |
| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
| insert |insert |971 |598 |170 |682 |0 |0 |
| ram_switch_state |ram_switch_state |814 |811 |0 |369 |0 |0 |
| read_ram_i |read_ram_rev |370 |263 |81 |210 |0 |0 |
| read_ram_addr |read_ram_addr_rev |314 |229 |73 |169 |0 |0 |
| read_ram_data |read_ram_data_rev |56 |34 |8 |41 |0 |0 |
| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
|...... |...... |- |- |- |- |- |- |
+---------------------------------------------------------------------------------------------------------+
DataNet Average Fanout:
Index Fanout Nets
#1 1 10013
#2 2 4263
#3 3 1670
#4 4 572
#5 5-10 791
#6 11-50 565
#7 51-100 12
#8 >500 1
Average 2.72
RUN-1002 : start command "export_db hg_anlogic_pr.db"
RUN-1001 : Exported /
RUN-1001 : Exported flow parameters
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported timing constraints
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.205464s wall, 3.718750s user + 0.015625s system = 3.734375s CPU (169.3%)
RUN-1004 : used memory is 910 MB, reserved memory is 915 MB, peak memory is 1127 MB
RUN-1002 : start command "start_timer"
TMR-2505 : Start building timing graph for model huagao_mipi_top.
TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72045, tnet num: 17805, tinst num: 6849, tnode num: 94791, tedge num: 119669.
TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
TMR-2501 : Timing graph initialized successfully.
RUN-1003 : finish command "start_timer" in 1.689250s wall, 1.671875s user + 0.015625s system = 1.687500s CPU (99.9%)
RUN-1004 : used memory is 955 MB, reserved memory is 953 MB, peak memory is 1127 MB
RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
TMR-2503 : Start to update net delay, extr mode = 6.
TMR-2504 : Update delay of 17805 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 6.
TMR-3001 : Initiate 12 clocks from SDC.
TMR-3004 : Map sdc constraints, there are 2 constraints in total.
TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
TMR-3506 : Start to generate timing report.
TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
TMR-5009 WARNING: No clock constraint on 3 clock net(s):
exdev_ctl_a/u_ADconfig/clk_config_syn_4
exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
TMR-3508 : Export timing summary.
TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.581854s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.8%)
RUN-1004 : used memory is 1046 MB, reserved memory is 1046 MB, peak memory is 1127 MB
RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_101138.log"

257
src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101250.log Normal file
View File

@ -0,0 +1,257 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Mar 18 10:12:51 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "import_db hg_anlogic_pr.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
PHY-5010 Similar messages will be suppressed.
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
PHY-1001 : eco open net = 0
PHY-1001 : 588 feed throughs used by 424 nets
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db hg_anlogic_pr.db" in 12.902920s wall, 12.468750s user + 0.218750s system = 12.687500s CPU (98.3%)
RUN-1004 : used memory is 792 MB, reserved memory is 785 MB, peak memory is 819 MB
RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
BIT-1003 : Start to generate bitstream.
BIT-1002 : Init instances with 8 threads.
BIT-1002 : Init instances completely, inst num: 6849
BIT-1002 : Init pips with 8 threads.
BIT-1002 : Init pips completely, net num: 17983, pip num: 167676
BIT-1002 : Init feedthrough with 8 threads.
BIT-1002 : Init feedthrough completely, num: 588
BIT-1003 : Multithreading accelaration with 8 threads.
BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 468383 bits set as '1'.
BIT-1004 : the usercode register value: 00000000101110110000000000000000
BIT-1004 : PLL setting string = 1011
BIT-1004 : Generate bits file hg_anlogic.bit.
RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.289372s wall, 65.015625s user + 0.453125s system = 65.468750s CPU (636.3%)
RUN-1004 : used memory is 815 MB, reserved memory is 824 MB, peak memory is 1085 MB
RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_101250.log"

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@ -0,0 +1,258 @@
============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Mon Mar 18 11:09:56 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "import_db hg_anlogic_pr.db"
RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
RUN-1001 : Database version number 46146.
RUN-1001 : Import flow parameters
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
PHY-5010 Similar messages will be suppressed.
PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
PHY-1001 : eco open net = 0
PHY-1001 : 538 feed throughs used by 420 nets
RUN-1001 : Import timing constraints
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
RUN-1003 : finish command "import_db hg_anlogic_pr.db" in 12.576825s wall, 12.328125s user + 0.203125s system = 12.531250s CPU (99.6%)
RUN-1004 : used memory is 793 MB, reserved memory is 787 MB, peak memory is 819 MB
RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
BIT-1003 : Start to generate bitstream.
BIT-1002 : Init instances with 8 threads.
BIT-1002 : Init instances completely, inst num: 6714
BIT-1002 : Init pips with 8 threads.
BIT-1002 : Init pips completely, net num: 17938, pip num: 167961
BIT-1002 : Init feedthrough with 8 threads.
BIT-1002 : Init feedthrough completely, num: 538
BIT-1003 : Multithreading accelaration with 8 threads.
BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 468879 bits set as '1'.
BIT-1004 : the usercode register value: 00000000101110110000000000000000
BIT-1004 : PLL setting string = 1011
BIT-1004 : Generate bits file hg_anlogic.bit.
BIT-1004 : Generate bin file hg_anlogic.bin.
RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.847542s wall, 62.078125s user + 0.312500s system = 62.390625s CPU (633.6%)
RUN-1004 : used memory is 817 MB, reserved memory is 821 MB, peak memory is 1085 MB
RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_110956.log"

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============================================================
Tang Dynasty, V5.6.71036
Copyright (c) 2012-2023 Anlogic Inc.
Executable = D:/Anlogic/TD5.6.2/bin/td.exe
Built at = 20:34:38 Mar 21 2023
Run by = holdtecs
Run Date = Thu Mar 14 15:48:07 2024
Run on = DESKTOP-5MQL5VE
============================================================
RUN-1002 : start command "open_project hg_anlogic.prj"
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
This product includes software developed by the OpenSSL Project
for use in the OpenSSL Toolkit (http://www.openssl.org/)
Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
All rights reserved.
This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
RUN-1001 : Project manager successfully analyzed 61 source files.
RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
ARC-1001 : Device Initialization.
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ----------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
ARC-1001 : done | P10 | gpio
ARC-1001 : program_b | P134 | dedicate
ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
ARC-1001 : ----------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "elaborate -top huagao_mipi_top"
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Rtl Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : compress_add | ripple | ripple |
RUN-1001 : elf_sload | off | off |
RUN-1001 : fix_undriven | 0 | 0 |
RUN-1001 : flatten | off | off |
RUN-1001 : gate_sharing | on | on |
RUN-1001 : hdl_warning_level | normal | normal |
RUN-1001 : impl_internal_tribuf | on | on |
RUN-1001 : impl_set_reset | on | on |
RUN-1001 : infer_gsr | off | off |
RUN-1001 : keep_hierarchy | auto | auto |
RUN-1001 : max_fanout | 9999 | 9999 |
RUN-1001 : max_oh2bin_len | 10 | 10 |
RUN-1001 : merge_equal | on | on |
RUN-1001 : merge_equiv | on | on |
RUN-1001 : merge_mux | off | off |
RUN-1001 : min_control_set | 8 | 8 |
RUN-1001 : min_ripple_len | auto | auto |
RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
RUN-1001 : opt_adder_fanout | on | on |
RUN-1001 : opt_arith | on | on |
RUN-1001 : opt_big_gate | off | off |
RUN-1001 : opt_const | on | on |
RUN-1001 : opt_const_mult | on | on |
RUN-1001 : opt_lessthan | on | on |
RUN-1001 : opt_mux | off | off |
RUN-1001 : opt_ram | high | high |
RUN-1001 : rtl_sim_model | off | off |
RUN-1001 : seq_syn | on | on |
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Print Global Property
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : message | standard | standard |
RUN-1001 : mixed_pack_place_flow | on | on |
RUN-1001 : qor_monitor | off | off |
RUN-1001 : syn_ip_flow | off | off |
RUN-1001 : thread | auto | auto |
RUN-1001 : ---------------------------------------------------------------
RUN-1001 : Print Design Property
RUN-1001 : --------------------------------------------------------------
RUN-1001 : Parameters | Settings | Default Values | Note
RUN-1001 : --------------------------------------------------------------
RUN-1001 : default_reg_initial | auto | auto |
RUN-1001 : infer_add | on | on |
RUN-1001 : infer_fsm | off | off |
RUN-1001 : infer_mult | on | on |
RUN-1001 : infer_ram | on | on |
RUN-1001 : infer_reg | on | on |
RUN-1001 : infer_reg_init_value | on | on |
RUN-1001 : infer_rom | on | on |
RUN-1001 : infer_shifter | on | on |
RUN-1001 : --------------------------------------------------------------
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
HDL-5007 WARNING: actual bit length 3 differs from formal bit length 5 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(141)
HDL-8007 ERROR: net 'debug[2]' is constantly driven from multiple places in ../../../../hg_mp/fe/sampling_fe.v(95)
HDL-8007 ERROR: found another driver here in ../../../../hg_mp/fe/sampling_fe.v(121)
HDL-1007 : module 'sampling_fe' remains a black box due to errors in its contents in ../../../../hg_mp/fe/sampling_fe.v(1)
HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
HDL-5007 WARNING: actual bit length 6 differs from formal bit length 3 for port 'debug' in ../../../../hg_mp/fe/sampling_fe_rev.v(115)
HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_154806.log"

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