diff --git a/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.ipc b/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.ipc
new file mode 100644
index 0000000..adbb6c2
--- /dev/null
+++ b/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.ipc
@@ -0,0 +1,14 @@
+
+
+
+ EG_LOGIC_ODDR
+ EG4D20EG176
+ true
+ lvds_iddr
+ ENABLE
+
+
+ lvds_iddr.v
+ lvds_iddr.vhd
+
+
diff --git a/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.v b/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.v
new file mode 100644
index 0000000..2f7390a
--- /dev/null
+++ b/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.v
@@ -0,0 +1,30 @@
+/************************************************************\
+ ** Copyright (c) 2012-2023 Anlogic Inc.
+ ** All Right Reserved.\
+\************************************************************/
+/************************************************************\
+ ** Log : This file is generated by Anlogic IP Generator.
+ ** File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.v
+ ** Date : 2024 03 18
+ ** TD version : 5.6.71036
+\************************************************************/
+
+`timescale 1ns / 1ps
+
+module lvds_iddr ( q, clk, d1, d0, rst );
+output q;
+input clk;
+input d1;
+input d0;
+input rst;
+
+ EG_LOGIC_ODDR #(
+ .ASYNCRST("ENABLE"))
+ oddr (
+ .q(q),
+ .clk(clk),
+ .d1(d1),
+ .d0(d0),
+ .rst(rst));
+
+endmodule
\ No newline at end of file
diff --git a/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.vhd b/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.vhd
new file mode 100644
index 0000000..8598b61
--- /dev/null
+++ b/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.vhd
@@ -0,0 +1,42 @@
+--------------------------------------------------------------
+ -- Copyright (c) 2012-2023 Anlogic Inc.
+ -- All Right Reserved.
+--------------------------------------------------------------
+ -- Log : This file is generated by Anlogic IP Generator.
+ -- File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/lvds_iddr/lvds_iddr.vhd
+ -- Date : 2024 03 18
+ -- TD version : 5.6.71036
+--------------------------------------------------------------
+
+LIBRARY ieee;
+USE work.ALL;
+ USE ieee.std_logic_1164.all;
+LIBRARY eagle_macro;
+ USE eagle_macro.EAGLE_COMPONENTS.all;
+
+ENTITY lvds_iddr IS
+PORT (
+ q : OUT STD_LOGIC;
+ clk : IN STD_LOGIC;
+ d1 : IN STD_LOGIC;
+ d0 : IN STD_LOGIC;
+ rst : IN STD_LOGIC
+ );
+END lvds_iddr;
+
+ARCHITECTURE struct OF lvds_iddr IS
+
+ BEGIN
+ inst : EG_LOGIC_ODDR
+ GENERIC MAP (
+ ASYNCRST => "ENABLE"
+ )
+ PORT MAP (
+ q => q,
+ clk => clk,
+ d1 => d1,
+ d0 => d0,
+ rst => rst
+ );
+
+END struct;
diff --git a/src/hg_mp/anlogic_ip/pll/pll.v b/src/hg_mp/anlogic_ip/pll/pll.v
index 8bb8788..01d1a75 100644
--- a/src/hg_mp/anlogic_ip/pll/pll.v
+++ b/src/hg_mp/anlogic_ip/pll/pll.v
@@ -4,8 +4,8 @@
\************************************************************/
/************************************************************\
** Log : This file is generated by Anlogic IP Generator.
- ** File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value/src/hg_mp/anlogic_ip/pll/pll.v
- ** Date : 2024 01 18
+ ** File : D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/pll/pll.v
+ ** Date : 2024 03 18
** TD version : 5.6.71036
\************************************************************/
diff --git a/src/hg_mp/drx_top/huagao_mipi_top.v b/src/hg_mp/drx_top/huagao_mipi_top.v
index 5ce6234..cdb0ddc 100644
--- a/src/hg_mp/drx_top/huagao_mipi_top.v
+++ b/src/hg_mp/drx_top/huagao_mipi_top.v
@@ -160,6 +160,8 @@ assign rst_sys_n = (pll_locked0&pll_locked1&pll_locked2);
assign rst_n = pll_locked0;
assign sys_initial_done = pll_locked0;
+
+
assign clk_ubus = clk_adc;
//=================================================
//A SIDE
@@ -169,7 +171,7 @@ wire a_vs,a_cl1,a_cl0,a_en,a_ch;
wire [29:0] a_rgb;
wire [4:0] a_lvds_flag;
-assign a_lvds_flag = {a_vs,a_cl1,a_cl0,a_en,a_ch};
+
lvds_rx ua_lvds_rx
@@ -191,22 +193,117 @@ lvds_rx ua_lvds_rx
.rgb (a_rgb )// assign rgb = {r[9:0],g[9:0],b[9:0]};
);/* synthesis keep_hierarchy=false */
-//=================================================
-//B SIDE
-//=================================================
-
+reg a_vs_sync_d1;
+reg a_vs_sync_d2;
+reg a_vs_sync_d3;
+reg a_cl0_sync_d1;
+reg a_cl0_sync_d2;
+reg a_cl0_sync_d3;
+reg a_en_sync_d1;
+reg a_en_sync_d2;
+reg a_en_sync_d3;
+reg a_cl1_sync_d1;
+reg a_cl1_sync_d2;
+reg a_cl1_sync_d3;
+reg a_ch_sync_d1;
+reg a_ch_sync_d2;
+reg a_ch_sync_d3;
+reg [29:0] a_rgb_sync_d1;
+reg [29:0] a_rgb_sync_d2;
+reg [29:0] a_rgb_sync_d3;
+assign a_lvds_flag = {a_vs_sync_d2,a_cl1_sync_d2,a_cl0_sync_d2,a_en_sync_d2,a_ch_sync_d2};
+always @ (posedge a_pclk) begin
+ if (~rst_n) begin
+ a_vs_sync_d1<=1'b0;
+ a_vs_sync_d2<=1'b0;
+ a_vs_sync_d3<=1'b0;
+ end
+ else begin
+ a_vs_sync_d1<=a_vs;
+ a_vs_sync_d2<=a_vs_sync_d1;
+ a_vs_sync_d3<=a_vs_sync_d2;
+ end
+ end
+
+ always @ (posedge a_pclk) begin
+ if (~rst_n) begin
+ a_cl0_sync_d1<=1'b0;
+ a_cl0_sync_d2<=1'b0;
+ a_cl0_sync_d3<=1'b0;
+ end
+ else begin
+ a_cl0_sync_d1<=a_cl0;
+ a_cl0_sync_d2<=a_cl0_sync_d1;
+ a_cl0_sync_d3<=a_cl0_sync_d2;
+ end
+ end
+
+ always @ (posedge a_pclk) begin
+ if (~rst_n) begin
+ a_en_sync_d1<=1'b0;
+ a_en_sync_d2<=1'b0;
+ a_en_sync_d3<=1'b0;
+ end
+ else begin
+ a_en_sync_d1<=a_en;
+ a_en_sync_d2<=a_en_sync_d1;
+ a_en_sync_d3<=a_en_sync_d2;
+ end
+ end
+
+ always @ (posedge a_pclk) begin
+ if (~rst_n) begin
+ a_cl1_sync_d1<=1'b0;
+ a_cl1_sync_d2<=1'b0;
+ a_cl1_sync_d3<=1'b0;
+ end
+ else begin
+ a_cl1_sync_d1<=a_cl1;
+ a_cl1_sync_d2<=a_cl1_sync_d1;
+ a_cl1_sync_d3<=a_cl1_sync_d2;
+ end
+ end
+
+ always @ (posedge a_pclk) begin
+ if (~rst_n) begin
+ a_ch_sync_d1<=1'b0;
+ a_ch_sync_d2<=1'b0;
+ a_ch_sync_d3<=1'b0;
+ end
+ else begin
+ a_ch_sync_d1<=a_ch;
+ a_ch_sync_d2<=a_ch_sync_d1;
+ a_ch_sync_d3<=a_ch_sync_d2;
+ end
+ end
+
+ always @ (posedge a_pclk) begin
+ if (~rst_n) begin
+ a_rgb_sync_d1<=1'b0;
+ a_rgb_sync_d2<=1'b0;
+ a_rgb_sync_d3<=1'b0;
+ end
+ else begin
+ a_rgb_sync_d1<=a_rgb;
+ a_rgb_sync_d2<=a_rgb_sync_d1;
+ a_rgb_sync_d3<=a_rgb_sync_d2;
+ end
+ end
+
wire b_vs,b_cl1,b_cl0,b_en,b_ch;
wire [29:0] b_rgb;
wire [4:0] b_lvds_flag;
-assign b_lvds_flag = {b_vs,b_cl1,b_cl0,b_en,b_ch};
+//=================================================
+//B SIDE
+//=================================================
lvds_rx ub_lvds_rx
(
// lvds
.lvds_clk (b_lvds_clk_p ),
- .lvds_data (b_lvds_data_p ),
+ .lvds_data (b_lvds_data_p ),
// pll
.rst (rst_sys ),
.sclk (b_sclk ), // sclk = pclk * 3.5
@@ -221,6 +318,103 @@ lvds_rx ub_lvds_rx
.rgb (b_rgb )// assign rgb = {r[9:0],g[9:0],b[9:0]};
);/* synthesis keep_hierarchy=false */
+reg b_vs_sync_d1;
+reg b_vs_sync_d2;
+reg b_vs_sync_d3;
+reg b_cl0_sync_d1;
+reg b_cl0_sync_d2;
+reg b_cl0_sync_d3;
+reg b_en_sync_d1;
+reg b_en_sync_d2;
+reg b_en_sync_d3;
+reg b_cl1_sync_d1;
+reg b_cl1_sync_d2;
+reg b_cl1_sync_d3;
+reg b_ch_sync_d1;
+reg b_ch_sync_d2;
+reg b_ch_sync_d3;
+reg [29:0] b_rgb_sync_d1;
+reg [29:0] b_rgb_sync_d2;
+reg [29:0] b_rgb_sync_d3;
+assign b_lvds_flag = {b_vs_sync_d2,b_cl1_sync_d2,b_cl0_sync_d2,b_en_sync_d2,b_ch_sync_d2};
+
+always @ (posedge b_pclk) begin
+ if (~rst_n) begin
+ b_vs_sync_d1<=1'b0;
+ b_vs_sync_d2<=1'b0;
+ b_vs_sync_d3<=1'b0;
+ end
+ else begin
+ b_vs_sync_d1<=b_vs;
+ b_vs_sync_d2<=b_vs_sync_d1;
+ b_vs_sync_d3<=b_vs_sync_d2;
+ end
+ end
+
+ always @ (posedge b_pclk) begin
+ if (~rst_n) begin
+ b_cl0_sync_d1<=1'b0;
+ b_cl0_sync_d2<=1'b0;
+ b_cl0_sync_d3<=1'b0;
+ end
+ else begin
+ b_cl0_sync_d1<=b_cl0;
+ b_cl0_sync_d2<=b_cl0_sync_d1;
+ b_cl0_sync_d3<=b_cl0_sync_d2;
+ end
+ end
+
+ always @ (posedge b_pclk) begin
+ if (~rst_n) begin
+ b_en_sync_d1<=1'b0;
+ b_en_sync_d2<=1'b0;
+ b_en_sync_d3<=1'b0;
+ end
+ else begin
+ b_en_sync_d1<=b_en;
+ b_en_sync_d2<=b_en_sync_d1;
+ b_en_sync_d3<=b_en_sync_d2;
+ end
+ end
+
+ always @ (posedge b_pclk) begin
+ if (~rst_n) begin
+ b_cl1_sync_d1<=1'b0;
+ b_cl1_sync_d2<=1'b0;
+ b_cl1_sync_d3<=1'b0;
+ end
+ else begin
+ b_cl1_sync_d1<=b_cl1;
+ b_cl1_sync_d2<=b_cl1_sync_d1;
+ b_cl1_sync_d3<=b_cl1_sync_d2;
+ end
+ end
+
+ always @ (posedge b_pclk) begin
+ if (~rst_n) begin
+ b_ch_sync_d1<=1'b0;
+ b_ch_sync_d2<=1'b0;
+ b_ch_sync_d3<=1'b0;
+ end
+ else begin
+ b_ch_sync_d1<=b_ch;
+ b_ch_sync_d2<=b_ch_sync_d1;
+ b_ch_sync_d3<=b_ch_sync_d2;
+ end
+ end
+
+ always @ (posedge b_pclk) begin
+ if (~rst_n) begin
+ b_rgb_sync_d1<=1'b0;
+ b_rgb_sync_d2<=1'b0;
+ b_rgb_sync_d3<=1'b0;
+ end
+ else begin
+ b_rgb_sync_d1<=b_rgb;
+ b_rgb_sync_d2<=b_rgb_sync_d1;
+ b_rgb_sync_d3<=b_rgb_sync_d2;
+ end
+ end
//=================================================
//MIPI PHY
//=================================================
@@ -348,7 +542,7 @@ reg[1:0] ubus_lpclk_d0 , ubus_lpclk_d1 ;
wire O_clk_lp_p_sync;
wire O_clk_lp_n_sync;
cdc_sync # (
- .DEPTH (20),
+ .DEPTH (3),
.WIDTH (1)
) u_O_clk_lp_p( /* synthesis keep_hierarchy=true */
.to_clk (clk_ubus ),
@@ -358,7 +552,7 @@ cdc_sync # (
);
cdc_sync # (
- .DEPTH (20),
+ .DEPTH (3),
.WIDTH (1)
) u_O_clk_lp_n( /* synthesis keep_hierarchy=true */
.to_clk (clk_ubus ),
@@ -587,7 +781,7 @@ always @ (posedge clk_ubus ) begin
BUSY_MIPI_sync_d1 <= 1'b0;
end
else begin
- BUSY_MIPI_sync_d0 <= BUSY_MIPI_sync;
+ BUSY_MIPI_sync_d0 <= BUSY_MIPI;
BUSY_MIPI_sync_d1 <= BUSY_MIPI_sync_d0;
end
end
@@ -898,8 +1092,8 @@ always @ (posedge b_pclk) begin
test_data_b <= {test_data_b[29:20] + 1,test_data_b[19:10] + 1,test_data_b[9:0] + 1};
end
-assign idata_a = sync_test_en_a ? test_data_a : a_rgb;
-assign idata_b = sync_test_en_b ? test_data_b : b_rgb;
+assign idata_a = sync_test_en_a ? test_data_a : a_rgb_sync_d2;
+assign idata_b = sync_test_en_b ? test_data_b : b_rgb_sync_d2;
//=================================================
// Sampling A side
@@ -1416,6 +1610,7 @@ reg[15:0] mipi_pixel_y_d0,mipi_pixel_y_d1;
reg[YPIXEL_WIDTH_TOTAL-1:0] a_mipi_total_num_d0,a_mipi_total_num_d1;
reg[23:0] PIXDATA_MIPI;
wire eot_flag;
+wire [2:0]debug_4;
rgb_to_csi_pakage U_rgb_to_csi_pakage
(
@@ -1434,8 +1629,10 @@ rgb_to_csi_pakage U_rgb_to_csi_pakage
.O_hs_last ( S_hs_last ),
.O_hs_data ( S_hs_data ),
.frame_end_time ( frame_end_time ),
- .eot_flag ( eot_flag )
+ .eot_flag ( eot_flag ),
+ .debug(debug_4)
);
+
reg [31:0] rgb_pac_cnt;
reg S_hs_valid_1d;
reg S_hs_valid_2d;
@@ -1728,12 +1925,12 @@ always @(*) begin
end
assign debug[0] = a_vs ;
-assign debug[1] = BUSY_MIPI;
-assign debug[2] = BUSY_MIPI_sync ;
-assign debug[3] = debug_1[1];
-assign debug[4] = debug_1[0] ;
+assign debug[1] = sync_eot;
+assign debug[2] = mipi_lpclk_d1 == 2'b11 ? 1 : 0 ;
+assign debug[3] = debug_4[1] ;
+assign debug[4] = debug_4[0] ;
assign debug[5] = FV_MIPI ;
-assign debug[6] = debug_1[4] ;
+assign debug[6] = debug_4[2] ;
assign debug[7] = LV_MIPI;
diff --git a/src/hg_mp/fe/ad_sampling.v b/src/hg_mp/fe/ad_sampling.v
index e47afea..d82cc83 100644
--- a/src/hg_mp/fe/ad_sampling.v
+++ b/src/hg_mp/fe/ad_sampling.v
@@ -216,7 +216,7 @@ always @ (posedge pclk ) begin
{line_sycn_3d,line_sycn_2d,line_sycn_1d} <= {line_sycn_2d,line_sycn_1d,line_sycn} ;
end
-assign line_sycn_fall = (~line_sycn_3d) & line_sycn_2d;
+assign line_sycn_fall = (~line_sycn_2d) & line_sycn_3d;
always @ (posedge pclk ) begin
if (!reset_n)
@@ -252,18 +252,84 @@ assign debug[3] = lvds_flag == 5'b10011 ? 1 : 0;
assign debug[4] = lvds_flag == 5'b10110 ? 1 : 0;
assign debug[5] = lvds_flag == 5'b11010 ? 1 : 0;
+reg [4:0] lvds_flag_d1;
+reg [4:0] lvds_flag_d2;
+reg [4:0] lvds_flag_d3;
+
+reg line_sycn_flag_1;
+reg line_sycn_flag_2;
+reg line_sycn_flag_3;
+
+always @ (posedge pclk )
+begin
+ if (!reset_n) begin
+ lvds_flag_d1<=5'b0;
+ lvds_flag_d2<=5'b0;
+ lvds_flag_d3<=5'b0;
+end
+ else begin
+ lvds_flag_d1<=lvds_flag;
+ lvds_flag_d2<=lvds_flag_d1;
+ lvds_flag_d3<=lvds_flag_d2;
+end
+end
+
+always @ (posedge pclk )
+begin
+ if (!reset_n)
+ line_sycn_flag_1 <= 1'b0;
+ else if (~sync_soft_n)
+ line_sycn_flag_1 <= 1'b0;
+ else if(lvds_flag == set_flag)
+ line_sycn_flag_1 <= 1'b1;
+ else if(cs == 1'b0)
+ line_sycn_flag_1 <= 1'b0;
+ else
+ line_sycn_flag_1 <= line_sycn_flag_1;
+
+end
+
+always @ (posedge pclk )
+begin
+ if (!reset_n)
+ line_sycn_flag_2 <= 1'b0;
+ else if (~sync_soft_n)
+ line_sycn_flag_2 <= 1'b0;
+ else if(lvds_flag_d1 == set_flag)
+ line_sycn_flag_2 <= 1'b1;
+ else if(cs == 1'b0)
+ line_sycn_flag_2 <= 1'b0;
+ else
+ line_sycn_flag_2 <= line_sycn_flag_2;
+
+end
+
+always @ (posedge pclk )
+begin
+ if (!reset_n)
+ line_sycn_flag_3 <= 1'b0;
+ else if (~sync_soft_n)
+ line_sycn_flag_3 <= 1'b0;
+ else if(lvds_flag_d2 == set_flag)
+ line_sycn_flag_3 <= 1'b1;
+ else if(cs == 1'b0)
+ line_sycn_flag_3 <= 1'b0;
+ else
+ line_sycn_flag_3 <= line_sycn_flag_3;
+
+end
+
+
always @ (posedge pclk )
begin
if (!reset_n)
line_sycn <= 1'b0;
else if (~sync_soft_n)
- line_sycn <= 1'b0;
- else if(lvds_flag == set_flag)
- line_sycn <= 1'b1;
+ line_sycn <= 1'b0;
else if(cs == 1'b0)
line_sycn <= 1'b0;
else
- line_sycn <= line_sycn;
+ line_sycn <= line_sycn_flag_1 & line_sycn_flag_2 &line_sycn_flag_3;
end
diff --git a/src/hg_mp/fe/fifo_adc.v b/src/hg_mp/fe/fifo_adc.v
index 52f29ed..fc8a1f8 100644
--- a/src/hg_mp/fe/fifo_adc.v
+++ b/src/hg_mp/fe/fifo_adc.v
@@ -40,6 +40,46 @@ localparam WR_FIFO = 3'b100;
reg [PBUFF_LENGTH_WIDTH+3-1:0] cnt;
+reg [4:0]data_CTL_ADC_d1,data_CTL_ADC_d2;
+reg line_sync_flag,line_sync_flag1,line_sync_flag2;
+
+always @(posedge dataclk_ADC)
+ if(~rst_n) begin
+ data_CTL_ADC_d1 <= 5'd0;
+ data_CTL_ADC_d2 <= 5'd0;
+ end
+ else begin
+ data_CTL_ADC_d1 <= data_CTL_ADC;
+ data_CTL_ADC_d2 <= data_CTL_ADC_d1;
+ end
+
+always @(posedge dataclk_ADC)begin
+ if(~rst_n)
+ line_sync_flag<=1'b0;
+ else if(data_CTL_ADC == PBUFF_DATA_CONTROL)
+ line_sync_flag<=1'b1;
+ else
+ line_sync_flag<=1'b0;
+ end
+
+ always @(posedge dataclk_ADC)begin
+ if(~rst_n)
+ line_sync_flag1<=1'b0;
+ else if(data_CTL_ADC_d1 == PBUFF_DATA_CONTROL)
+ line_sync_flag1<=1'b1;
+ else
+ line_sync_flag1<=1'b0;
+ end
+
+ always @(posedge dataclk_ADC)begin
+ if(~rst_n)
+ line_sync_flag2<=1'b0;
+ else if(data_CTL_ADC_d2 == PBUFF_DATA_CONTROL)
+ line_sync_flag2<=1'b1;
+ else
+ line_sync_flag2<=1'b0;
+ end
+
always @(posedge dataclk_ADC)
if(~rst_n) begin
@@ -66,7 +106,8 @@ reg [PBUFF_LENGTH_WIDTH+3-1:0] cnt;
START:begin
cnt <= 'd0;
- if(data_CTL_ADC == PBUFF_DATA_CONTROL)begin
+ //if(data_CTL_ADC == PBUFF_DATA_CONTROL)begin
+ if(line_sync_flag & line_sync_flag1 & line_sync_flag2)begin
rd_en <= 1'b1;
ADC_STATE <= WR_FIFO;
fifoA_ADC <= dataA_ADC;
diff --git a/src/hg_mp/local_bus/uart_2dsp_6M_921600.v b/src/hg_mp/local_bus/uart_2dsp_6M_921600.v
index 9fbb036..3461faa 100644
--- a/src/hg_mp/local_bus/uart_2dsp_6M_921600.v
+++ b/src/hg_mp/local_bus/uart_2dsp_6M_921600.v
@@ -1,6 +1,6 @@
module uart_2dsp
#(
- parameter BF_N = 5,
+ parameter BF_N = 4,
parameter CLKFREQ = 6000000,
parameter BAUDRATE = 921600
diff --git a/src/hg_mp/local_bus/ubus_top.v b/src/hg_mp/local_bus/ubus_top.v
index 72d67b3..2718e3d 100644
--- a/src/hg_mp/local_bus/ubus_top.v
+++ b/src/hg_mp/local_bus/ubus_top.v
@@ -215,7 +215,7 @@ local_bus_slve_cis u_local_bus_slve_cis(
//,.nd2reg_0 ( scan_status_sync3d_8m ) //input [31:0]
,.nd2reg_0 ( adc_cfg_data_o_sync3d_8m) //input [31:0]
- ,.nd2reg_1 ( 32'h000a0002 ) //input [31:0]
+ ,.nd2reg_1 ( 32'h000a0004 ) //input [31:0]
,.nd2reg_2 ( lv_cnt2bus_sync3d ) //input [31:0]
,.nd2reg_3 ( fr_cnt2bus_sync3d ) //input [31:0]
,.nd2reg_4 ( lv_cnt_a_sync3d ) //input [31:0]
diff --git a/src/hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v b/src/hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
index 5c9613f..5a7205f 100644
--- a/src/hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+++ b/src/hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
@@ -31,7 +31,8 @@ module rgb_to_csi_pakage
output wire O_hs_last,
output reg[31:0] O_hs_data,
input [15:0] frame_end_time,
- output reg eot_flag
+ output reg eot_flag,
+ output wire [2:0] debug
);
parameter DPI200_DEPTH = 816;
@@ -505,7 +506,9 @@ else
eot_flag <= ~S_frame_end_delay_en_r[1] & S_frame_end_delay_en_r[3];
end
-
+assign debug[0] = S_frame_end_delay_en;
+assign debug[1] = S_frame_end_delay_cnt == frame_end_time ? 1 : 0 ;
+assign debug[2] = S_frame_end_delay_cnt == 0 ? 1 : 0 ;
always @ (posedge I_pixel_clk) begin
diff --git a/src/prj/td_project/SchematicImage.png b/src/prj/td_project/SchematicImage.png
index 577a0ee..68e204c 100644
Binary files a/src/prj/td_project/SchematicImage.png and b/src/prj/td_project/SchematicImage.png differ
diff --git a/src/prj/td_project/hg_anlogic.adc b/src/prj/td_project/hg_anlogic.adc
index 223992b..044f2df 100644
--- a/src/prj/td_project/hg_anlogic.adc
+++ b/src/prj/td_project/hg_anlogic.adc
@@ -23,7 +23,7 @@ set_pin_assignment { a_lvds_data_p[1] } { LOCATION = P26; IOSTANDARD = LVDS25; P
set_pin_assignment { a_lvds_data_p[2] } { LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[3] } { LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
set_pin_assignment { a_lvds_data_p[4] } { LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; }
-set_pin_assignment { b_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
+set_pin_assignment { a_sp_pad } { LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sck } { LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
set_pin_assignment { b_ad_sdi } { LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; }
set_pin_assignment { b_ad_sdo } { LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; }
@@ -61,7 +61,7 @@ set_pin_assignment { txd_dsp } { LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVEST
set_inst_assignment {u_pll/pll_inst} {location = x40y0z0;}
-create_bound { bound2 } -mode fixed -width 25 -height 25 -origin { 0 0 }
+create_bound { bound2 } -mode fixed -width 26 -height 25 -origin { 0 0 }
create_bound { bound3 } -mode fixed -width 18 -height 30 -origin { 23 0 }
add_cells_to_bound -bound { bound2 } -cells { u_mipi_dphy_tx_wrapper }
add_cells_to_bound -bound { bound2 } -cells { U_rgb_to_csi_pakage }
diff --git a/src/prj/td_project/hg_anlogic.al b/src/prj/td_project/hg_anlogic.al
index 469d00d..dd7db3a 100644
--- a/src/prj/td_project/hg_anlogic.al
+++ b/src/prj/td_project/hg_anlogic.al
@@ -565,7 +565,11 @@
+
+ on
+
+ high
high
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_150114.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_150114.log
new file mode 100644
index 0000000..952cef6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_150114.log
@@ -0,0 +1,2104 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:01:14 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.229697s wall, 2.156250s user + 0.062500s system = 2.218750s CPU (99.5%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 322 MB, peak memory is 351 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 2.3889 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 2.3889 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18983 instances
+RUN-0007 : 8654 luts, 9108 seqs, 699 mslices, 374 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21561 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14216 nets have 2 pins
+RUN-1001 : 5913 nets have [3 - 5] pins
+RUN-1001 : 873 nets have [6 - 10] pins
+RUN-1001 : 301 nets have [11 - 20] pins
+RUN-1001 : 186 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2033
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18981 instances, 8654 luts, 9108 seqs, 1073 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5968 pins
+PHY-0007 : Cell area utilization is 55%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 90907, tnet num: 21383, tinst num: 18981, tnode num: 121192, tedge num: 145787.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.178075s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (99.5%)
+
+RUN-1004 : used memory is 550 MB, reserved memory is 533 MB, peak memory is 550 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21383 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.011290s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (100.2%)
+
+PHY-3001 : Found 1248 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.25395e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18981.
+PHY-3001 : Level 1 #clusters 2461.
+PHY-3001 : End clustering; 0.146741s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (117.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.44083e+06, overlap = 550.562
+PHY-3002 : Step(2): len = 1.08804e+06, overlap = 640.594
+PHY-3002 : Step(3): len = 872518, overlap = 765.906
+PHY-3002 : Step(4): len = 712634, overlap = 808.156
+PHY-3002 : Step(5): len = 568039, overlap = 917.781
+PHY-3002 : Step(6): len = 486497, overlap = 980.781
+PHY-3002 : Step(7): len = 407204, overlap = 1059.69
+PHY-3002 : Step(8): len = 357700, overlap = 1120.16
+PHY-3002 : Step(9): len = 318694, overlap = 1174.53
+PHY-3002 : Step(10): len = 285511, overlap = 1221.81
+PHY-3002 : Step(11): len = 262282, overlap = 1269.53
+PHY-3002 : Step(12): len = 239386, overlap = 1330.34
+PHY-3002 : Step(13): len = 226145, overlap = 1375.12
+PHY-3002 : Step(14): len = 213634, overlap = 1416.47
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.14328e-06
+PHY-3002 : Step(15): len = 212449, overlap = 1380.38
+PHY-3002 : Step(16): len = 244669, overlap = 1268.41
+PHY-3002 : Step(17): len = 248016, overlap = 1242.19
+PHY-3002 : Step(18): len = 248640, overlap = 1191.75
+PHY-3002 : Step(19): len = 243317, overlap = 1151
+PHY-3002 : Step(20): len = 239793, overlap = 1148.72
+PHY-3002 : Step(21): len = 235085, overlap = 1152.25
+PHY-3002 : Step(22): len = 232052, overlap = 1135.28
+PHY-3002 : Step(23): len = 227560, overlap = 1123.97
+PHY-3002 : Step(24): len = 226260, overlap = 1111.81
+PHY-3002 : Step(25): len = 223932, overlap = 1092.09
+PHY-3002 : Step(26): len = 222962, overlap = 1094.22
+PHY-3002 : Step(27): len = 220760, overlap = 1109.72
+PHY-3002 : Step(28): len = 220414, overlap = 1111.03
+PHY-3002 : Step(29): len = 217787, overlap = 1107.62
+PHY-3002 : Step(30): len = 216471, overlap = 1098.69
+PHY-3002 : Step(31): len = 215250, overlap = 1098.84
+PHY-3002 : Step(32): len = 215070, overlap = 1104.72
+PHY-3002 : Step(33): len = 213208, overlap = 1109.91
+PHY-3002 : Step(34): len = 212011, overlap = 1096.5
+PHY-3002 : Step(35): len = 210454, overlap = 1094.84
+PHY-3002 : Step(36): len = 209889, overlap = 1110.09
+PHY-3002 : Step(37): len = 209110, overlap = 1098.88
+PHY-3002 : Step(38): len = 207876, overlap = 1082.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.28655e-06
+PHY-3002 : Step(39): len = 215059, overlap = 1046.84
+PHY-3002 : Step(40): len = 229922, overlap = 991.938
+PHY-3002 : Step(41): len = 235988, overlap = 954.031
+PHY-3002 : Step(42): len = 240440, overlap = 948.188
+PHY-3002 : Step(43): len = 241430, overlap = 942.5
+PHY-3002 : Step(44): len = 242615, overlap = 941.344
+PHY-3002 : Step(45): len = 241476, overlap = 950.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.57311e-06
+PHY-3002 : Step(46): len = 258889, overlap = 883.938
+PHY-3002 : Step(47): len = 281684, overlap = 810.969
+PHY-3002 : Step(48): len = 291365, overlap = 768.312
+PHY-3002 : Step(49): len = 293681, overlap = 742.438
+PHY-3002 : Step(50): len = 292442, overlap = 739.094
+PHY-3002 : Step(51): len = 289762, overlap = 718.125
+PHY-3002 : Step(52): len = 288165, overlap = 701.25
+PHY-3002 : Step(53): len = 288048, overlap = 683.125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.14621e-06
+PHY-3002 : Step(54): len = 309228, overlap = 631.219
+PHY-3002 : Step(55): len = 330066, overlap = 594.781
+PHY-3002 : Step(56): len = 337243, overlap = 571.781
+PHY-3002 : Step(57): len = 337982, overlap = 538.906
+PHY-3002 : Step(58): len = 335733, overlap = 532.312
+PHY-3002 : Step(59): len = 334808, overlap = 520.469
+PHY-3002 : Step(60): len = 334759, overlap = 506.906
+PHY-3002 : Step(61): len = 334676, overlap = 501.594
+PHY-3002 : Step(62): len = 334454, overlap = 489.625
+PHY-3002 : Step(63): len = 334533, overlap = 466
+PHY-3002 : Step(64): len = 333641, overlap = 457.969
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.82924e-05
+PHY-3002 : Step(65): len = 353568, overlap = 450.75
+PHY-3002 : Step(66): len = 369909, overlap = 431.188
+PHY-3002 : Step(67): len = 372656, overlap = 400.781
+PHY-3002 : Step(68): len = 373108, overlap = 384.906
+PHY-3002 : Step(69): len = 372055, overlap = 395.75
+PHY-3002 : Step(70): len = 373347, overlap = 404.406
+PHY-3002 : Step(71): len = 372987, overlap = 389.688
+PHY-3002 : Step(72): len = 374794, overlap = 379.625
+PHY-3002 : Step(73): len = 373957, overlap = 377.75
+PHY-3002 : Step(74): len = 373941, overlap = 359.344
+PHY-3002 : Step(75): len = 373785, overlap = 357.625
+PHY-3002 : Step(76): len = 374973, overlap = 373.219
+PHY-3002 : Step(77): len = 375131, overlap = 381.469
+PHY-3002 : Step(78): len = 375822, overlap = 375.906
+PHY-3002 : Step(79): len = 373969, overlap = 377.562
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.65849e-05
+PHY-3002 : Step(80): len = 392730, overlap = 365.312
+PHY-3002 : Step(81): len = 405924, overlap = 340.281
+PHY-3002 : Step(82): len = 406253, overlap = 344.062
+PHY-3002 : Step(83): len = 404442, overlap = 343.875
+PHY-3002 : Step(84): len = 404026, overlap = 343.781
+PHY-3002 : Step(85): len = 405236, overlap = 331.25
+PHY-3002 : Step(86): len = 406428, overlap = 321.094
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.31697e-05
+PHY-3002 : Step(87): len = 420404, overlap = 312.5
+PHY-3002 : Step(88): len = 433317, overlap = 295.375
+PHY-3002 : Step(89): len = 435908, overlap = 283.281
+PHY-3002 : Step(90): len = 438676, overlap = 267.125
+PHY-3002 : Step(91): len = 440660, overlap = 273.531
+PHY-3002 : Step(92): len = 443406, overlap = 278.625
+PHY-3002 : Step(93): len = 441156, overlap = 271.406
+PHY-3002 : Step(94): len = 442177, overlap = 253.125
+PHY-3002 : Step(95): len = 442785, overlap = 254.469
+PHY-3002 : Step(96): len = 444266, overlap = 253.156
+PHY-3002 : Step(97): len = 441191, overlap = 248.594
+PHY-3002 : Step(98): len = 440948, overlap = 239.156
+PHY-3002 : Step(99): len = 441196, overlap = 239.344
+PHY-3002 : Step(100): len = 442844, overlap = 237.344
+PHY-3002 : Step(101): len = 441231, overlap = 238.312
+PHY-3002 : Step(102): len = 441870, overlap = 232.969
+PHY-3002 : Step(103): len = 441218, overlap = 241.531
+PHY-3002 : Step(104): len = 441767, overlap = 248.031
+PHY-3002 : Step(105): len = 440052, overlap = 235
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000140343
+PHY-3002 : Step(106): len = 450977, overlap = 227.844
+PHY-3002 : Step(107): len = 457726, overlap = 223.375
+PHY-3002 : Step(108): len = 457327, overlap = 216
+PHY-3002 : Step(109): len = 457408, overlap = 208.188
+PHY-3002 : Step(110): len = 460056, overlap = 202.812
+PHY-3002 : Step(111): len = 463304, overlap = 208.344
+PHY-3002 : Step(112): len = 463131, overlap = 213.938
+PHY-3002 : Step(113): len = 464997, overlap = 210.438
+PHY-3002 : Step(114): len = 466260, overlap = 204.375
+PHY-3002 : Step(115): len = 467633, overlap = 197.781
+PHY-3002 : Step(116): len = 466402, overlap = 193.188
+PHY-3002 : Step(117): len = 466483, overlap = 193.188
+PHY-3002 : Step(118): len = 467148, overlap = 199.156
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000280687
+PHY-3002 : Step(119): len = 474122, overlap = 204.75
+PHY-3002 : Step(120): len = 482027, overlap = 187.812
+PHY-3002 : Step(121): len = 484887, overlap = 183.094
+PHY-3002 : Step(122): len = 486345, overlap = 174.188
+PHY-3002 : Step(123): len = 488268, overlap = 170.469
+PHY-3002 : Step(124): len = 488966, overlap = 173.156
+PHY-3002 : Step(125): len = 489675, overlap = 164.125
+PHY-3002 : Step(126): len = 494084, overlap = 149.531
+PHY-3002 : Step(127): len = 498585, overlap = 169.844
+PHY-3002 : Step(128): len = 500890, overlap = 161.625
+PHY-3002 : Step(129): len = 502223, overlap = 157
+PHY-3002 : Step(130): len = 502437, overlap = 154.875
+PHY-3002 : Step(131): len = 500411, overlap = 145.875
+PHY-3002 : Step(132): len = 499480, overlap = 147.969
+PHY-3002 : Step(133): len = 497276, overlap = 148.906
+PHY-3002 : Step(134): len = 496276, overlap = 151.656
+PHY-3002 : Step(135): len = 495144, overlap = 146.875
+PHY-3002 : Step(136): len = 494491, overlap = 144.469
+PHY-3002 : Step(137): len = 493867, overlap = 148.969
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000561373
+PHY-3002 : Step(138): len = 497701, overlap = 146.719
+PHY-3002 : Step(139): len = 501696, overlap = 141.438
+PHY-3002 : Step(140): len = 502541, overlap = 146.594
+PHY-3002 : Step(141): len = 503059, overlap = 144.312
+PHY-3002 : Step(142): len = 503713, overlap = 144.156
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000991218
+PHY-3002 : Step(143): len = 506299, overlap = 147.625
+PHY-3002 : Step(144): len = 509153, overlap = 152.844
+PHY-3002 : Step(145): len = 509506, overlap = 148.969
+PHY-3002 : Step(146): len = 510003, overlap = 139.625
+PHY-3002 : Step(147): len = 511594, overlap = 141.219
+PHY-3002 : Step(148): len = 513119, overlap = 142.5
+PHY-3002 : Step(149): len = 514325, overlap = 148.156
+PHY-3002 : Step(150): len = 515706, overlap = 147.062
+PHY-3002 : Step(151): len = 516513, overlap = 148.938
+PHY-3002 : Step(152): len = 517201, overlap = 149.656
+PHY-3002 : Step(153): len = 517233, overlap = 147.656
+PHY-3002 : Step(154): len = 517457, overlap = 143.344
+PHY-3002 : Step(155): len = 517684, overlap = 145.125
+PHY-3002 : Step(156): len = 517832, overlap = 144.094
+PHY-3002 : Step(157): len = 517702, overlap = 144.312
+PHY-3002 : Step(158): len = 517611, overlap = 144.969
+PHY-3002 : Step(159): len = 517422, overlap = 144.906
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00163813
+PHY-3002 : Step(160): len = 518711, overlap = 146.406
+PHY-3002 : Step(161): len = 520024, overlap = 141.406
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015033s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (311.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21561.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 684432, over cnt = 1474(4%), over = 6499, worst = 34
+PHY-1001 : End global iterations; 0.825518s wall, 1.062500s user + 0.062500s system = 1.125000s CPU (136.3%)
+
+PHY-1001 : Congestion index: top1 = 73.71, top5 = 56.91, top10 = 49.61, top15 = 44.62.
+PHY-3001 : End congestion estimation; 1.081081s wall, 1.265625s user + 0.093750s system = 1.359375s CPU (125.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21383 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.908817s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.29478e-05
+PHY-3002 : Step(162): len = 613589, overlap = 96.6562
+PHY-3002 : Step(163): len = 626306, overlap = 85.5
+PHY-3002 : Step(164): len = 611228, overlap = 86.25
+PHY-3002 : Step(165): len = 608072, overlap = 81.7188
+PHY-3002 : Step(166): len = 599589, overlap = 83.375
+PHY-3002 : Step(167): len = 599156, overlap = 79.5
+PHY-3002 : Step(168): len = 594706, overlap = 76.5
+PHY-3002 : Step(169): len = 594070, overlap = 73.9375
+PHY-3002 : Step(170): len = 590568, overlap = 74.0625
+PHY-3002 : Step(171): len = 587865, overlap = 73.3438
+PHY-3002 : Step(172): len = 585555, overlap = 73.0312
+PHY-3002 : Step(173): len = 585331, overlap = 69.8438
+PHY-3002 : Step(174): len = 582676, overlap = 71
+PHY-3002 : Step(175): len = 583042, overlap = 71.3125
+PHY-3002 : Step(176): len = 579707, overlap = 73.375
+PHY-3002 : Step(177): len = 578805, overlap = 71.5312
+PHY-3002 : Step(178): len = 576846, overlap = 75.1562
+PHY-3002 : Step(179): len = 574494, overlap = 71.2188
+PHY-3002 : Step(180): len = 572234, overlap = 71.7812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000185896
+PHY-3002 : Step(181): len = 573070, overlap = 72.375
+PHY-3002 : Step(182): len = 573070, overlap = 72.375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 170/21561.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 667232, over cnt = 2528(7%), over = 10349, worst = 31
+PHY-1001 : End global iterations; 1.520382s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (126.4%)
+
+PHY-1001 : Congestion index: top1 = 74.46, top5 = 61.13, top10 = 54.35, top15 = 49.88.
+PHY-3001 : End congestion estimation; 1.873806s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (121.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21383 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.977958s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.61168e-05
+PHY-3002 : Step(183): len = 576534, overlap = 355.531
+PHY-3002 : Step(184): len = 579105, overlap = 345
+PHY-3002 : Step(185): len = 574880, overlap = 336.469
+PHY-3002 : Step(186): len = 577080, overlap = 325.625
+PHY-3002 : Step(187): len = 578755, overlap = 302.688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000132234
+PHY-3002 : Step(188): len = 575183, overlap = 298.469
+PHY-3002 : Step(189): len = 578892, overlap = 287.875
+PHY-3002 : Step(190): len = 585805, overlap = 275.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000264467
+PHY-3002 : Step(191): len = 588319, overlap = 263.875
+PHY-3002 : Step(192): len = 595512, overlap = 254.312
+PHY-3002 : Step(193): len = 610496, overlap = 232.125
+PHY-3002 : Step(194): len = 609380, overlap = 226.656
+PHY-3002 : Step(195): len = 609546, overlap = 225.531
+PHY-3002 : Step(196): len = 605323, overlap = 218.562
+PHY-3002 : Step(197): len = 604801, overlap = 213.938
+PHY-3002 : Step(198): len = 601036, overlap = 211.344
+PHY-3002 : Step(199): len = 599780, overlap = 203.406
+PHY-3002 : Step(200): len = 599863, overlap = 200.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000528935
+PHY-3002 : Step(201): len = 603937, overlap = 196.188
+PHY-3002 : Step(202): len = 609710, overlap = 192.219
+PHY-3002 : Step(203): len = 614837, overlap = 189.594
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00105787
+PHY-3002 : Step(204): len = 616598, overlap = 185.031
+PHY-3002 : Step(205): len = 621741, overlap = 174
+PHY-3002 : Step(206): len = 628206, overlap = 157.312
+PHY-3002 : Step(207): len = 632261, overlap = 150.062
+PHY-3002 : Step(208): len = 634731, overlap = 139.281
+PHY-3002 : Step(209): len = 636143, overlap = 136.688
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00178889
+PHY-3002 : Step(210): len = 637630, overlap = 134.719
+PHY-3002 : Step(211): len = 640198, overlap = 126.688
+PHY-3002 : Step(212): len = 643527, overlap = 122.875
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 90907, tnet num: 21383, tinst num: 18981, tnode num: 121192, tedge num: 145787.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.497356s wall, 1.484375s user + 0.015625s system = 1.500000s CPU (100.2%)
+
+RUN-1004 : used memory is 591 MB, reserved memory is 580 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 535.19 peak overflow 3.44
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1084/21561.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765992, over cnt = 3364(9%), over = 12077, worst = 23
+PHY-1001 : End global iterations; 1.356107s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 68.17, top5 = 57.95, top10 = 52.91, top15 = 49.67.
+PHY-1001 : End incremental global routing; 1.676113s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (128.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21383 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.963713s wall, 0.937500s user + 0.031250s system = 0.968750s CPU (100.5%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18852 has valid locations, 373 needs to be replaced
+PHY-3001 : design contains 19310 instances, 8734 luts, 9357 seqs, 1073 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6098 pins
+PHY-3001 : Found 1255 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 674506
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17620/21890.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 784840, over cnt = 3397(9%), over = 12161, worst = 22
+PHY-1001 : End global iterations; 0.268415s wall, 0.437500s user + 0.046875s system = 0.484375s CPU (180.5%)
+
+PHY-1001 : Congestion index: top1 = 67.78, top5 = 58.12, top10 = 53.17, top15 = 49.95.
+PHY-3001 : End congestion estimation; 0.533566s wall, 0.687500s user + 0.046875s system = 0.734375s CPU (137.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92246, tnet num: 21712, tinst num: 19310, tnode num: 123286, tedge num: 147807.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.515176s wall, 1.484375s user + 0.031250s system = 1.515625s CPU (100.0%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 653 MB, peak memory is 744 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21712 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.522817s wall, 2.484375s user + 0.031250s system = 2.515625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(213): len = 673187, overlap = 1.0625
+PHY-3002 : Step(214): len = 673472, overlap = 1.0625
+PHY-3002 : Step(215): len = 673277, overlap = 1.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17692/21890.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 780032, over cnt = 3441(9%), over = 12276, worst = 24
+PHY-1001 : End global iterations; 0.232163s wall, 0.359375s user + 0.031250s system = 0.390625s CPU (168.3%)
+
+PHY-1001 : Congestion index: top1 = 69.03, top5 = 58.48, top10 = 53.40, top15 = 50.15.
+PHY-3001 : End congestion estimation; 0.495510s wall, 0.625000s user + 0.031250s system = 0.656250s CPU (132.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21712 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.007800s wall, 0.984375s user + 0.031250s system = 1.015625s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000351257
+PHY-3002 : Step(216): len = 673497, overlap = 125.938
+PHY-3002 : Step(217): len = 674078, overlap = 125.531
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000702513
+PHY-3002 : Step(218): len = 674177, overlap = 126.312
+PHY-3002 : Step(219): len = 674471, overlap = 126.594
+PHY-3001 : Final: Len = 674471, Over = 126.594
+PHY-3001 : End incremental placement; 5.232179s wall, 5.578125s user + 0.203125s system = 5.781250s CPU (110.5%)
+
+OPT-1001 : Total overflow 543.66 peak overflow 3.44
+OPT-1001 : End high-fanout net optimization; 8.475513s wall, 9.359375s user + 0.250000s system = 9.609375s CPU (113.4%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 741, peak = 765.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17679/21890.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 785424, over cnt = 3374(9%), over = 10905, worst = 22
+PHY-1002 : len = 840648, over cnt = 2422(6%), over = 5924, worst = 22
+PHY-1002 : len = 887368, over cnt = 1204(3%), over = 2462, worst = 14
+PHY-1002 : len = 914808, over cnt = 546(1%), over = 1083, worst = 14
+PHY-1002 : len = 940200, over cnt = 5(0%), over = 7, worst = 3
+PHY-1001 : End global iterations; 2.023816s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 60.54, top5 = 53.14, top10 = 49.54, top15 = 47.28.
+OPT-1001 : End congestion update; 2.302560s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (130.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21712 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.847292s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.6%)
+
+OPT-0007 : Start: WNS -3998 TNS -2440918 NUM_FEPS 1064
+OPT-0007 : Iter 1: improved WNS -3798 TNS -2427372 NUM_FEPS 1064 with 70 cells processed and 4082 slack improved
+OPT-0007 : Iter 2: improved WNS -3682 TNS -2434502 NUM_FEPS 1064 with 57 cells processed and 2042 slack improved
+OPT-0007 : Iter 3: improved WNS -3648 TNS -2431706 NUM_FEPS 1064 with 49 cells processed and 1698 slack improved
+OPT-0007 : Iter 4: improved WNS -3648 TNS -2434584 NUM_FEPS 1064 with 27 cells processed and 410 slack improved
+OPT-0007 : Iter 5: improved WNS -3648 TNS -2429880 NUM_FEPS 1064 with 3 cells processed and 384 slack improved
+OPT-1001 : End bottleneck based optimization; 3.879631s wall, 4.562500s user + 0.015625s system = 4.578125s CPU (118.0%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 721, peak = 765.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17835/21895.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940488, over cnt = 272(0%), over = 340, worst = 3
+PHY-1002 : len = 940056, over cnt = 177(0%), over = 202, worst = 3
+PHY-1002 : len = 941608, over cnt = 16(0%), over = 17, worst = 2
+PHY-1002 : len = 941920, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 941960, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.855273s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (109.6%)
+
+PHY-1001 : Congestion index: top1 = 60.41, top5 = 53.20, top10 = 49.62, top15 = 47.35.
+OPT-1001 : End congestion update; 1.133916s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (106.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21717 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.855108s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.5%)
+
+OPT-0007 : Start: WNS -3648 TNS -2429880 NUM_FEPS 1064
+OPT-0007 : Iter 1: improved WNS -3632 TNS -2424878 NUM_FEPS 1064 with 36 cells processed and 2182 slack improved
+OPT-0007 : Iter 2: improved WNS -3614 TNS -2423998 NUM_FEPS 1064 with 19 cells processed and 1200 slack improved
+OPT-0007 : Iter 3: improved WNS -3614 TNS -2423998 NUM_FEPS 1064 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.285041s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (103.3%)
+
+OPT-1001 : Current memory(MB): used = 722, reserve = 717, peak = 765.
+OPT-1001 : End physical optimization; 16.456634s wall, 18.156250s user + 0.312500s system = 18.468750s CPU (112.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8734 LUT to BLE ...
+SYN-4008 : Packed 8734 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6227 remaining SEQ's ...
+SYN-4005 : Packed 4505 SEQ with LUT/SLICE
+SYN-4006 : 1390 single LUT's are left
+SYN-4006 : 1722 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10456/14309 primitive instances ...
+PHY-3001 : End packing; 1.759552s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7319 instances
+RUN-1001 : 3586 mslices, 3585 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18893 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10362 nets have 2 pins
+RUN-1001 : 6625 nets have [3 - 5] pins
+RUN-1001 : 965 nets have [6 - 10] pins
+RUN-1001 : 490 nets have [11 - 20] pins
+RUN-1001 : 420 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7317 instances, 7171 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3612 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 681023, Over = 328.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7868/18893.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 864112, over cnt = 2310(6%), over = 3918, worst = 9
+PHY-1002 : len = 874216, over cnt = 1559(4%), over = 2310, worst = 9
+PHY-1002 : len = 894248, over cnt = 513(1%), over = 693, worst = 6
+PHY-1002 : len = 904600, over cnt = 85(0%), over = 111, worst = 4
+PHY-1002 : len = 907104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.777952s wall, 2.578125s user + 0.015625s system = 2.593750s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 60.22, top5 = 52.57, top10 = 48.85, top15 = 46.53.
+PHY-3001 : End congestion estimation; 2.214455s wall, 3.015625s user + 0.015625s system = 3.031250s CPU (136.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81547, tnet num: 18715, tinst num: 7317, tnode num: 104564, tedge num: 136846.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.757184s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (99.6%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 642 MB, peak memory is 765 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.706194s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.7577e-05
+PHY-3002 : Step(220): len = 663951, overlap = 339.5
+PHY-3002 : Step(221): len = 652929, overlap = 361.75
+PHY-3002 : Step(222): len = 645786, overlap = 384
+PHY-3002 : Step(223): len = 640922, overlap = 393.75
+PHY-3002 : Step(224): len = 638180, overlap = 397.75
+PHY-3002 : Step(225): len = 635393, overlap = 396.25
+PHY-3002 : Step(226): len = 635294, overlap = 391.5
+PHY-3002 : Step(227): len = 632030, overlap = 391.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.5154e-05
+PHY-3002 : Step(228): len = 635531, overlap = 386.75
+PHY-3002 : Step(229): len = 641515, overlap = 382.5
+PHY-3002 : Step(230): len = 642775, overlap = 374.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000190308
+PHY-3002 : Step(231): len = 652974, overlap = 364
+PHY-3002 : Step(232): len = 661003, overlap = 352.5
+PHY-3002 : Step(233): len = 660488, overlap = 349.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000380616
+PHY-3002 : Step(234): len = 668773, overlap = 330.75
+PHY-3002 : Step(235): len = 678940, overlap = 310
+PHY-3002 : Step(236): len = 678189, overlap = 309.5
+PHY-3002 : Step(237): len = 678175, overlap = 304.25
+PHY-3002 : Step(238): len = 680105, overlap = 297.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000693477
+PHY-3002 : Step(239): len = 685115, overlap = 291.5
+PHY-3002 : Step(240): len = 691013, overlap = 285.25
+PHY-3002 : Step(241): len = 695181, overlap = 280.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.344684s wall, 0.343750s user + 0.500000s system = 0.843750s CPU (244.8%)
+
+PHY-3001 : Trial Legalized: Len = 785762
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 700/18893.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926336, over cnt = 3223(9%), over = 5508, worst = 9
+PHY-1002 : len = 947512, over cnt = 2000(5%), over = 3002, worst = 8
+PHY-1002 : len = 976928, over cnt = 608(1%), over = 865, worst = 8
+PHY-1002 : len = 992560, over cnt = 27(0%), over = 29, worst = 2
+PHY-1002 : len = 993912, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.474550s wall, 3.890625s user + 0.031250s system = 3.921875s CPU (158.5%)
+
+PHY-1001 : Congestion index: top1 = 58.45, top5 = 53.34, top10 = 50.40, top15 = 48.39.
+PHY-3001 : End congestion estimation; 2.939675s wall, 4.343750s user + 0.031250s system = 4.375000s CPU (148.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.944857s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000199806
+PHY-3002 : Step(242): len = 743527, overlap = 86.75
+PHY-3002 : Step(243): len = 721017, overlap = 145.75
+PHY-3002 : Step(244): len = 703708, overlap = 191.5
+PHY-3002 : Step(245): len = 694093, overlap = 223
+PHY-3002 : Step(246): len = 688218, overlap = 248
+PHY-3002 : Step(247): len = 684877, overlap = 267.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000399611
+PHY-3002 : Step(248): len = 690503, overlap = 257.25
+PHY-3002 : Step(249): len = 695226, overlap = 249.25
+PHY-3002 : Step(250): len = 696635, overlap = 240.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000799223
+PHY-3002 : Step(251): len = 699426, overlap = 240
+PHY-3002 : Step(252): len = 704744, overlap = 233.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034597s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.3%)
+
+PHY-3001 : Legalized: Len = 745813, Over = 0
+PHY-3001 : Spreading special nets. 591 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.139926s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.5%)
+
+PHY-3001 : 929 instances has been re-located, deltaX = 384, deltaY = 534, maxDist = 4.
+PHY-3001 : Final: Len = 762757, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81547, tnet num: 18715, tinst num: 7320, tnode num: 104564, tedge num: 136846.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.064756s wall, 2.031250s user + 0.046875s system = 2.078125s CPU (100.6%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 645 MB, peak memory is 766 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4866/18893.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922096, over cnt = 3025(8%), over = 4918, worst = 7
+PHY-1002 : len = 937880, over cnt = 1940(5%), over = 2762, worst = 5
+PHY-1002 : len = 961008, over cnt = 793(2%), over = 1047, worst = 5
+PHY-1002 : len = 971040, over cnt = 335(0%), over = 435, worst = 5
+PHY-1002 : len = 979400, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.185626s wall, 3.265625s user + 0.031250s system = 3.296875s CPU (150.8%)
+
+PHY-1001 : Congestion index: top1 = 56.81, top5 = 52.38, top10 = 49.65, top15 = 47.74.
+PHY-1001 : End incremental global routing; 2.569176s wall, 3.640625s user + 0.031250s system = 3.671875s CPU (142.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.958922s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (101.0%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7228 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 7337 instances, 7188 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 765779
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17220/18910.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 982544, over cnt = 70(0%), over = 99, worst = 6
+PHY-1002 : len = 982776, over cnt = 28(0%), over = 34, worst = 3
+PHY-1002 : len = 983032, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 983176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.658192s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (102.1%)
+
+PHY-1001 : Congestion index: top1 = 56.81, top5 = 52.41, top10 = 49.71, top15 = 47.82.
+PHY-3001 : End congestion estimation; 1.003116s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (101.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81716, tnet num: 18732, tinst num: 7337, tnode num: 104771, tedge num: 137067.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.994751s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (100.3%)
+
+RUN-1004 : used memory is 683 MB, reserved memory is 684 MB, peak memory is 771 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18732 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.003651s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(253): len = 764947, overlap = 0.5
+PHY-3002 : Step(254): len = 765010, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17208/18910.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 982280, over cnt = 60(0%), over = 77, worst = 3
+PHY-1002 : len = 982328, over cnt = 21(0%), over = 24, worst = 2
+PHY-1002 : len = 982456, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 982456, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 982488, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.856373s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (104.0%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 52.50, top10 = 49.73, top15 = 47.85.
+PHY-3001 : End congestion estimation; 1.206466s wall, 1.218750s user + 0.015625s system = 1.234375s CPU (102.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18732 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.970565s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000376605
+PHY-3002 : Step(255): len = 764743, overlap = 2
+PHY-3002 : Step(256): len = 764959, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005500s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 765088, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064903s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 765178, Over = 0
+PHY-3001 : End incremental placement; 6.693653s wall, 6.937500s user + 0.062500s system = 7.000000s CPU (104.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.778546s wall, 12.093750s user + 0.093750s system = 12.187500s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 770, reserve = 768, peak = 786.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17164/18910.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 982776, over cnt = 91(0%), over = 111, worst = 3
+PHY-1002 : len = 982512, over cnt = 43(0%), over = 50, worst = 3
+PHY-1002 : len = 982816, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 983032, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 983104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.881381s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (108.1%)
+
+PHY-1001 : Congestion index: top1 = 56.75, top5 = 52.36, top10 = 49.66, top15 = 47.79.
+OPT-1001 : End congestion update; 1.221622s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (104.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18732 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.801074s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.5%)
+
+OPT-0007 : Start: WNS -4357 TNS -2244471 NUM_FEPS 987
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7249 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7337 instances, 7188 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 765366, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068534s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.2%)
+
+PHY-3001 : 31 instances has been re-located, deltaX = 14, deltaY = 19, maxDist = 2.
+PHY-3001 : Final: Len = 766158, Over = 0
+PHY-3001 : End incremental legalization; 0.427002s wall, 0.484375s user + 0.031250s system = 0.515625s CPU (120.8%)
+
+OPT-0007 : Iter 1: improved WNS -3907 TNS -2224061 NUM_FEPS 987 with 52 cells processed and 6335 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7249 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7337 instances, 7188 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 766022, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063200s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.9%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 9, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 766596, Over = 0
+PHY-3001 : End incremental legalization; 0.456954s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (123.1%)
+
+OPT-0007 : Iter 2: improved WNS -3907 TNS -2218037 NUM_FEPS 987 with 33 cells processed and 3505 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7249 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7337 instances, 7188 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 766240, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063922s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.8%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 10, maxDist = 4.
+PHY-3001 : Final: Len = 766784, Over = 0
+PHY-3001 : End incremental legalization; 0.459495s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.0%)
+
+OPT-0007 : Iter 3: improved WNS -3907 TNS -2218506 NUM_FEPS 987 with 17 cells processed and 1105 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7249 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7337 instances, 7188 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 766724, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064593s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.8%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 3, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 767094, Over = 0
+PHY-3001 : End incremental legalization; 0.458663s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (126.0%)
+
+OPT-0007 : Iter 4: improved WNS -3907 TNS -2217968 NUM_FEPS 987 with 11 cells processed and 1119 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7249 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7337 instances, 7188 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3679 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 766838, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064320s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 4.
+PHY-3001 : Final: Len = 767230, Over = 0
+PHY-3001 : End incremental legalization; 0.502571s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (102.6%)
+
+OPT-0007 : Iter 5: improved WNS -3907 TNS -2218160 NUM_FEPS 987 with 8 cells processed and 191 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7250 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7338 instances, 7189 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3680 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 767216, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063816s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.9%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 767252, Over = 0
+PHY-3001 : End incremental legalization; 0.418009s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.2%)
+
+OPT-0007 : Iter 6: improved WNS -3907 TNS -2216506 NUM_FEPS 987 with 1 cells processed and 135 slack improved
+OPT-1001 : End bottleneck based optimization; 6.075447s wall, 6.359375s user + 0.062500s system = 6.421875s CPU (105.7%)
+
+OPT-1001 : Current memory(MB): used = 773, reserve = 769, peak = 786.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16799/18911.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 983376, over cnt = 377(1%), over = 503, worst = 6
+PHY-1002 : len = 983960, over cnt = 247(0%), over = 290, worst = 4
+PHY-1002 : len = 986016, over cnt = 73(0%), over = 78, worst = 4
+PHY-1002 : len = 986976, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 987224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.995001s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (111.5%)
+
+PHY-1001 : Congestion index: top1 = 57.18, top5 = 52.51, top10 = 49.81, top15 = 47.89.
+OPT-1001 : End congestion update; 1.351460s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (108.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18733 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.822612s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.7%)
+
+OPT-0007 : Start: WNS -3907 TNS -2224087 NUM_FEPS 987
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7250 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7338 instances, 7189 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3680 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 767978, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065287s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 8, deltaY = 17, maxDist = 2.
+PHY-3001 : Final: Len = 768378, Over = 0
+PHY-3001 : End incremental legalization; 0.412875s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.2%)
+
+OPT-0007 : Iter 1: improved WNS -3807 TNS -2219477 NUM_FEPS 987 with 41 cells processed and 3358 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7250 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7338 instances, 7189 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3680 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 768364, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062477s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.0%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 768522, Over = 0
+PHY-3001 : End incremental legalization; 0.408784s wall, 0.390625s user + 0.046875s system = 0.437500s CPU (107.0%)
+
+OPT-0007 : Iter 2: improved WNS -3807 TNS -2220235 NUM_FEPS 987 with 15 cells processed and 618 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7250 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7338 instances, 7189 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3680 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 768450, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063943s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.7%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 768612, Over = 0
+PHY-3001 : End incremental legalization; 0.414915s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (124.3%)
+
+OPT-0007 : Iter 3: improved WNS -3807 TNS -2220085 NUM_FEPS 987 with 9 cells processed and 496 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7250 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7338 instances, 7189 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3680 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 768444, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062273s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.4%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 3, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 768530, Over = 0
+PHY-3001 : End incremental legalization; 0.410438s wall, 0.406250s user + 0.046875s system = 0.453125s CPU (110.4%)
+
+OPT-0007 : Iter 4: improved WNS -3807 TNS -2220085 NUM_FEPS 987 with 5 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 4.459873s wall, 4.781250s user + 0.093750s system = 4.875000s CPU (109.3%)
+
+OPT-1001 : Current memory(MB): used = 773, reserve = 770, peak = 786.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18733 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.796873s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16944/18911.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 987184, over cnt = 195(0%), over = 249, worst = 4
+PHY-1002 : len = 986984, over cnt = 104(0%), over = 109, worst = 3
+PHY-1002 : len = 987768, over cnt = 43(0%), over = 45, worst = 3
+PHY-1002 : len = 988144, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 988600, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.914982s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (109.3%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 52.41, top10 = 49.73, top15 = 47.84.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18733 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.796516s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.0%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -3844 TNS -2221070 NUM_FEPS 987
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.896552
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -3844ps with logic level 5
+RUN-1001 : #2 path slack -3807ps with logic level 5
+RUN-1001 : #3 path slack -3807ps with logic level 5
+RUN-1001 : #4 path slack -3794ps with logic level 5
+RUN-1001 : 0 HFN exist on timing critical paths out of 18911 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18911 nets
+OPT-1001 : End physical optimization; 26.642557s wall, 28.593750s user + 0.312500s system = 28.906250s CPU (108.5%)
+
+RUN-1003 : finish command "place" in 72.854319s wall, 102.656250s user + 5.390625s system = 108.046875s CPU (148.3%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 636 MB, peak memory is 786 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.742311s wall, 3.062500s user + 0.031250s system = 3.093750s CPU (177.6%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 637 MB, peak memory is 786 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7340 instances
+RUN-1001 : 3596 mslices, 3593 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18911 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10361 nets have 2 pins
+RUN-1001 : 6618 nets have [3 - 5] pins
+RUN-1001 : 980 nets have [6 - 10] pins
+RUN-1001 : 494 nets have [11 - 20] pins
+RUN-1001 : 430 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81721, tnet num: 18733, tinst num: 7338, tnode num: 104780, tedge num: 137075.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.772116s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (100.5%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 618 MB, peak memory is 786 MB
+PHY-1001 : 3596 mslices, 3593 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18733 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896232, over cnt = 3249(9%), over = 5469, worst = 9
+PHY-1002 : len = 920672, over cnt = 1991(5%), over = 2794, worst = 6
+PHY-1002 : len = 945928, over cnt = 710(2%), over = 948, worst = 5
+PHY-1002 : len = 962784, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 963192, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.458874s wall, 4.734375s user + 0.031250s system = 4.765625s CPU (137.8%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 51.79, top10 = 49.05, top15 = 47.10.
+PHY-1001 : End global routing; 3.828962s wall, 5.078125s user + 0.046875s system = 5.125000s CPU (133.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 749, reserve = 757, peak = 786.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1031, peak = 1025.
+PHY-1001 : End build detailed router design. 4.081803s wall, 4.031250s user + 0.046875s system = 4.078125s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 281208, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.172043s wall, 5.156250s user + 0.015625s system = 5.171875s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 281264, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.451499s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1062, reserve = 1069, peak = 1062.
+PHY-1001 : End phase 1; 5.635530s wall, 5.625000s user + 0.015625s system = 5.640625s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 35% nets.
+PHY-1001 : Routed 41% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.59962e+06, over cnt = 2553(0%), over = 2568, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1083, reserve = 1089, peak = 1083.
+PHY-1001 : End initial routed; 27.309747s wall, 58.640625s user + 0.312500s system = 58.953125s CPU (215.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2812/17836(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.939 | -3409.354 | 989
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.625910s wall, 3.593750s user + 0.031250s system = 3.625000s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1091, reserve = 1101, peak = 1091.
+PHY-1001 : End phase 2; 30.935722s wall, 62.234375s user + 0.343750s system = 62.578125s CPU (202.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 61 pins with SWNS -5.826ns STNS -3400.238ns FEP 989.
+PHY-1001 : End OPT Iter 1; 0.375300s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.9%)
+
+PHY-1022 : len = 2.60001e+06, over cnt = 2592(0%), over = 2608, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.672474s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.5472e+06, over cnt = 1012(0%), over = 1013, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.512090s wall, 4.343750s user + 0.000000s system = 4.343750s CPU (172.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53867e+06, over cnt = 334(0%), over = 334, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.298664s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (142.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.54005e+06, over cnt = 44(0%), over = 44, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.794595s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (114.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.54057e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.418168s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (108.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.54065e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.317163s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (103.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.54065e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.443468s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.54065e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.811045s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.54061e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.190349s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.54062e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.199109s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (109.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.54062e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.227727s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.54062e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.245914s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.54062e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.328166s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.54066e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.190047s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (106.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.54066e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.183369s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2812/17836(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.826 | -3400.563 | 989
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.652415s wall, 3.640625s user + 0.000000s system = 3.640625s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 889 feed throughs used by 620 nets
+PHY-1001 : End commit to database; 2.489368s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1201, reserve = 1210, peak = 1201.
+PHY-1001 : End phase 3; 15.410714s wall, 17.906250s user + 0.031250s system = 17.937500s CPU (116.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 110 pins with SWNS -5.606ns STNS -3393.033ns FEP 989.
+PHY-1001 : End OPT Iter 1; 0.575931s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (100.4%)
+
+PHY-1022 : len = 2.54076e+06, over cnt = 45(0%), over = 45, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.842905s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.606ns, -3393.033ns, 989}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.54051e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.196011s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.54044e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.176947s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2812/17836(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.664 | -3397.588 | 989
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.734688s wall, 3.734375s user + 0.000000s system = 3.734375s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 906 feed throughs used by 637 nets
+PHY-1001 : End commit to database; 2.596754s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1212, reserve = 1222, peak = 1212.
+PHY-1001 : End phase 4; 7.601579s wall, 7.593750s user + 0.000000s system = 7.593750s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.54044e+06
+PHY-1001 : Current memory(MB): used = 1217, reserve = 1227, peak = 1217.
+PHY-1001 : End export database. 0.158760s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.4%)
+
+PHY-1001 : End detail routing; 64.242918s wall, 97.984375s user + 0.437500s system = 98.421875s CPU (153.2%)
+
+RUN-1003 : finish command "route" in 71.110718s wall, 106.078125s user + 0.500000s system = 106.578125s CPU (149.9%)
+
+RUN-1004 : used memory is 1082 MB, reserved memory is 1105 MB, peak memory is 1218 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 11778 out of 19600 60.09%
+#reg 9497 out of 19600 48.45%
+#le 13434
+ #lut only 3937 out of 13434 29.31%
+ #reg only 1656 out of 13434 12.33%
+ #lut® 7841 out of 13434 58.37%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1789
+#2 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1459
+#3 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1443
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 999
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 132
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/u_ADconfig/reg1_syn_205.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/u_ADconfig/reg1_syn_202.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P32 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P69 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P112 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P114 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P6 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P66 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P16 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P169 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |13434 |10753 |1025 |9531 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |528 |472 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |95 |4 |86 |4 |0 |
+| U_crc16_24b |crc16_24b |40 |40 |0 |26 |0 |0 |
+| U_ecc_gen |ecc_gen |8 |8 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |766 |492 |96 |584 |0 |0 |
+| u_ADconfig |AD_config |185 |147 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |262 |163 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |738 |466 |96 |559 |0 |0 |
+| u_ADconfig |AD_config |174 |125 |25 |132 |0 |0 |
+| u_gen_sp |gen_sp |251 |159 |71 |114 |0 |0 |
+| sampling_fe_a |sampling_fe |3130 |2510 |306 |2117 |25 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |179 |97 |17 |147 |0 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_sort |sort |2916 |2401 |289 |1935 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2513 |2060 |253 |1624 |22 |0 |
+| channelPart |channel_part_8478 |169 |153 |3 |144 |0 |0 |
+| fifo_adc |fifo_adc |65 |56 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1972 |1617 |197 |1205 |0 |0 |
+| adc_addr_gen |adc_addr_gen |248 |211 |27 |128 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |17 |4 |3 |13 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| insert |insert |1013 |703 |170 |716 |0 |0 |
+| ram_switch_state |ram_switch_state |711 |703 |0 |361 |0 |0 |
+| read_ram_i |read_ram |260 |210 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |211 |171 |40 |150 |0 |0 |
+| read_ram_data |read_ram_data |47 |38 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |338 |286 |36 |248 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |4117 |3497 |346 |2091 |25 |1 |
+| u0_soft_n |cdc_sync |10 |2 |0 |10 |0 |0 |
+| u_ad_sampling |ad_sampling |173 |102 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |3905 |3373 |329 |1911 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |7 |2 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |3485 |3018 |287 |1568 |22 |1 |
+| channelPart |channel_part_8478 |270 |261 |3 |134 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |43 |0 |1 |
+| ram_switch |ram_switch |2757 |2424 |197 |1143 |0 |0 |
+| adc_addr_gen |adc_addr_gen |257 |227 |27 |126 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |17 |11 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |34 |31 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |28 |25 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |11 |0 |0 |
+| insert |insert |959 |657 |170 |638 |0 |0 |
+| ram_switch_state |ram_switch_state |1541 |1540 |0 |379 |0 |0 |
+| read_ram_i |read_ram_rev |344 |233 |78 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |204 |70 |161 |0 |0 |
+| read_ram_data |read_ram_data_rev |58 |29 |8 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10299
+ #2 2 4649
+ #3 3 1224
+ #4 4 742
+ #5 5-10 1099
+ #6 11-50 772
+ #7 51-100 30
+ #8 >500 1
+ Average 3.04
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.172320s wall, 3.796875s user + 0.000000s system = 3.796875s CPU (174.8%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1107 MB, peak memory is 1218 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81721, tnet num: 18733, tinst num: 7338, tnode num: 104780, tedge num: 137075.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.700006s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (100.2%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1112 MB, peak memory is 1218 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18733 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.598810s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (99.7%)
+
+RUN-1004 : used memory is 1132 MB, reserved memory is 1154 MB, peak memory is 1218 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7338
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18911, pip num: 192577
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 906
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3256 valid insts, and 535200 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.422463s wall, 70.015625s user + 0.140625s system = 70.156250s CPU (673.1%)
+
+RUN-1004 : used memory is 1330 MB, reserved memory is 1334 MB, peak memory is 1445 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_150114.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_152204.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_152204.log
new file mode 100644
index 0000000..c581e54
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_152204.log
@@ -0,0 +1,2041 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:22:04 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.332360s wall, 2.234375s user + 0.093750s system = 2.328125s CPU (99.8%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 322 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 2.3889 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 2.3889 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 19025 instances
+RUN-0007 : 8698 luts, 9106 seqs, 699 mslices, 374 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21603 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14274 nets have 2 pins
+RUN-1001 : 5887 nets have [3 - 5] pins
+RUN-1001 : 876 nets have [6 - 10] pins
+RUN-1001 : 310 nets have [11 - 20] pins
+RUN-1001 : 184 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2031
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 19023 instances, 8698 luts, 9106 seqs, 1073 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5966 pins
+PHY-0007 : Cell area utilization is 55%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91087, tnet num: 21425, tinst num: 19023, tnode num: 121366, tedge num: 146063.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.209395s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.5%)
+
+RUN-1004 : used memory is 551 MB, reserved memory is 534 MB, peak memory is 551 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.076745s wall, 2.015625s user + 0.062500s system = 2.078125s CPU (100.1%)
+
+PHY-3001 : Found 1241 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.29069e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 19023.
+PHY-3001 : Level 1 #clusters 2508.
+PHY-3001 : End clustering; 0.153826s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (121.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.44428e+06, overlap = 573.688
+PHY-3002 : Step(2): len = 1.06226e+06, overlap = 629.094
+PHY-3002 : Step(3): len = 900351, overlap = 730.875
+PHY-3002 : Step(4): len = 717267, overlap = 799
+PHY-3002 : Step(5): len = 561078, overlap = 888.875
+PHY-3002 : Step(6): len = 480397, overlap = 1007.91
+PHY-3002 : Step(7): len = 415260, overlap = 1089.25
+PHY-3002 : Step(8): len = 358841, overlap = 1143
+PHY-3002 : Step(9): len = 319196, overlap = 1194.34
+PHY-3002 : Step(10): len = 282786, overlap = 1230.47
+PHY-3002 : Step(11): len = 261240, overlap = 1279.59
+PHY-3002 : Step(12): len = 237591, overlap = 1307.16
+PHY-3002 : Step(13): len = 221587, overlap = 1345.25
+PHY-3002 : Step(14): len = 204742, overlap = 1383.78
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.08028e-06
+PHY-3002 : Step(15): len = 202500, overlap = 1354.66
+PHY-3002 : Step(16): len = 230812, overlap = 1286.84
+PHY-3002 : Step(17): len = 235511, overlap = 1251.88
+PHY-3002 : Step(18): len = 235986, overlap = 1196.38
+PHY-3002 : Step(19): len = 231939, overlap = 1164.59
+PHY-3002 : Step(20): len = 227431, overlap = 1161.62
+PHY-3002 : Step(21): len = 221000, overlap = 1170.53
+PHY-3002 : Step(22): len = 217678, overlap = 1163.31
+PHY-3002 : Step(23): len = 214519, overlap = 1158.44
+PHY-3002 : Step(24): len = 212400, overlap = 1141.16
+PHY-3002 : Step(25): len = 208965, overlap = 1133.59
+PHY-3002 : Step(26): len = 207993, overlap = 1128.66
+PHY-3002 : Step(27): len = 206791, overlap = 1111.44
+PHY-3002 : Step(28): len = 205899, overlap = 1095.69
+PHY-3002 : Step(29): len = 204296, overlap = 1090.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.16057e-06
+PHY-3002 : Step(30): len = 211213, overlap = 1073.53
+PHY-3002 : Step(31): len = 229504, overlap = 1016.56
+PHY-3002 : Step(32): len = 236533, overlap = 998.094
+PHY-3002 : Step(33): len = 239812, overlap = 965.219
+PHY-3002 : Step(34): len = 241090, overlap = 951.156
+PHY-3002 : Step(35): len = 241353, overlap = 949.375
+PHY-3002 : Step(36): len = 239610, overlap = 946.219
+PHY-3002 : Step(37): len = 238342, overlap = 945.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.32113e-06
+PHY-3002 : Step(38): len = 253006, overlap = 911.812
+PHY-3002 : Step(39): len = 273359, overlap = 826.094
+PHY-3002 : Step(40): len = 279658, overlap = 780.219
+PHY-3002 : Step(41): len = 283051, overlap = 764.906
+PHY-3002 : Step(42): len = 282055, overlap = 739.625
+PHY-3002 : Step(43): len = 282301, overlap = 751.406
+PHY-3002 : Step(44): len = 281859, overlap = 744.406
+PHY-3002 : Step(45): len = 281671, overlap = 738.969
+PHY-3002 : Step(46): len = 280791, overlap = 751.062
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.64226e-06
+PHY-3002 : Step(47): len = 303536, overlap = 698.938
+PHY-3002 : Step(48): len = 323699, overlap = 623.875
+PHY-3002 : Step(49): len = 330300, overlap = 582.219
+PHY-3002 : Step(50): len = 331703, overlap = 555.75
+PHY-3002 : Step(51): len = 328503, overlap = 560.656
+PHY-3002 : Step(52): len = 327761, overlap = 538.625
+PHY-3002 : Step(53): len = 327941, overlap = 522.312
+PHY-3002 : Step(54): len = 328351, overlap = 521.719
+PHY-3002 : Step(55): len = 328682, overlap = 510.156
+PHY-3002 : Step(56): len = 328653, overlap = 507.312
+PHY-3002 : Step(57): len = 328853, overlap = 518.25
+PHY-3002 : Step(58): len = 329590, overlap = 496.281
+PHY-3002 : Step(59): len = 330163, overlap = 504
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.72845e-05
+PHY-3002 : Step(60): len = 349038, overlap = 446.344
+PHY-3002 : Step(61): len = 364668, overlap = 391.125
+PHY-3002 : Step(62): len = 368759, overlap = 377.375
+PHY-3002 : Step(63): len = 369869, overlap = 379.469
+PHY-3002 : Step(64): len = 369155, overlap = 376.125
+PHY-3002 : Step(65): len = 368727, overlap = 378.375
+PHY-3002 : Step(66): len = 368480, overlap = 358.688
+PHY-3002 : Step(67): len = 369263, overlap = 360.281
+PHY-3002 : Step(68): len = 368745, overlap = 353.875
+PHY-3002 : Step(69): len = 369651, overlap = 347.875
+PHY-3002 : Step(70): len = 369375, overlap = 352.594
+PHY-3002 : Step(71): len = 370339, overlap = 345.5
+PHY-3002 : Step(72): len = 368596, overlap = 361.156
+PHY-3002 : Step(73): len = 369269, overlap = 357.75
+PHY-3002 : Step(74): len = 368956, overlap = 361.188
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.45691e-05
+PHY-3002 : Step(75): len = 388196, overlap = 350.719
+PHY-3002 : Step(76): len = 400649, overlap = 325.031
+PHY-3002 : Step(77): len = 401037, overlap = 330.188
+PHY-3002 : Step(78): len = 400538, overlap = 318.594
+PHY-3002 : Step(79): len = 400883, overlap = 326.781
+PHY-3002 : Step(80): len = 402931, overlap = 328.5
+PHY-3002 : Step(81): len = 402274, overlap = 325.031
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.91381e-05
+PHY-3002 : Step(82): len = 417264, overlap = 284.188
+PHY-3002 : Step(83): len = 429215, overlap = 237.875
+PHY-3002 : Step(84): len = 431858, overlap = 249.938
+PHY-3002 : Step(85): len = 432357, overlap = 258.125
+PHY-3002 : Step(86): len = 433735, overlap = 254.469
+PHY-3002 : Step(87): len = 436767, overlap = 253.094
+PHY-3002 : Step(88): len = 436090, overlap = 247.75
+PHY-3002 : Step(89): len = 437585, overlap = 250.5
+PHY-3002 : Step(90): len = 438124, overlap = 240.688
+PHY-3002 : Step(91): len = 438322, overlap = 234.938
+PHY-3002 : Step(92): len = 435767, overlap = 234.75
+PHY-3002 : Step(93): len = 435694, overlap = 237.125
+PHY-3002 : Step(94): len = 435744, overlap = 250.219
+PHY-3002 : Step(95): len = 436312, overlap = 254.25
+PHY-3002 : Step(96): len = 434559, overlap = 262.875
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000135024
+PHY-3002 : Step(97): len = 445178, overlap = 243.156
+PHY-3002 : Step(98): len = 453508, overlap = 241.438
+PHY-3002 : Step(99): len = 454681, overlap = 223.281
+PHY-3002 : Step(100): len = 455609, overlap = 218.031
+PHY-3002 : Step(101): len = 457079, overlap = 218.562
+PHY-3002 : Step(102): len = 458055, overlap = 219.781
+PHY-3002 : Step(103): len = 456688, overlap = 218.406
+PHY-3002 : Step(104): len = 457151, overlap = 221
+PHY-3002 : Step(105): len = 457717, overlap = 216.781
+PHY-3002 : Step(106): len = 458446, overlap = 201.75
+PHY-3002 : Step(107): len = 457348, overlap = 211.438
+PHY-3002 : Step(108): len = 458358, overlap = 201.969
+PHY-3002 : Step(109): len = 459389, overlap = 208.781
+PHY-3002 : Step(110): len = 460289, overlap = 203.812
+PHY-3002 : Step(111): len = 457749, overlap = 200.969
+PHY-3002 : Step(112): len = 457170, overlap = 192.312
+PHY-3002 : Step(113): len = 457878, overlap = 188.312
+PHY-3002 : Step(114): len = 458509, overlap = 188.312
+PHY-3002 : Step(115): len = 457144, overlap = 182.344
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000253532
+PHY-3002 : Step(116): len = 463147, overlap = 196.312
+PHY-3002 : Step(117): len = 469921, overlap = 203.5
+PHY-3002 : Step(118): len = 470982, overlap = 199.812
+PHY-3002 : Step(119): len = 471275, overlap = 198.438
+PHY-3002 : Step(120): len = 472231, overlap = 192.438
+PHY-3002 : Step(121): len = 472754, overlap = 196.094
+PHY-3002 : Step(122): len = 471628, overlap = 191.969
+PHY-3002 : Step(123): len = 471542, overlap = 192.906
+PHY-3002 : Step(124): len = 471983, overlap = 190.125
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000482082
+PHY-3002 : Step(125): len = 476247, overlap = 191.906
+PHY-3002 : Step(126): len = 482610, overlap = 182.656
+PHY-3002 : Step(127): len = 484681, overlap = 169.406
+PHY-3002 : Step(128): len = 486925, overlap = 163.875
+PHY-3002 : Step(129): len = 488352, overlap = 168.375
+PHY-3002 : Step(130): len = 489423, overlap = 174.688
+PHY-3002 : Step(131): len = 488550, overlap = 168.438
+PHY-3002 : Step(132): len = 487793, overlap = 171.406
+PHY-3002 : Step(133): len = 488248, overlap = 174.375
+PHY-3002 : Step(134): len = 489031, overlap = 171.688
+PHY-3002 : Step(135): len = 488681, overlap = 175.875
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000780008
+PHY-3002 : Step(136): len = 490083, overlap = 173.938
+PHY-3002 : Step(137): len = 491296, overlap = 175.469
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012773s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (367.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 650056, over cnt = 1427(4%), over = 6749, worst = 47
+PHY-1001 : End global iterations; 0.824721s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (128.8%)
+
+PHY-1001 : Congestion index: top1 = 78.51, top5 = 58.41, top10 = 49.66, top15 = 44.31.
+PHY-3001 : End congestion estimation; 1.090318s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (123.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.968128s wall, 0.921875s user + 0.046875s system = 0.968750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.62707e-05
+PHY-3002 : Step(138): len = 586029, overlap = 128.969
+PHY-3002 : Step(139): len = 599911, overlap = 103
+PHY-3002 : Step(140): len = 585802, overlap = 103.969
+PHY-3002 : Step(141): len = 582412, overlap = 99.6875
+PHY-3002 : Step(142): len = 574869, overlap = 97.4375
+PHY-3002 : Step(143): len = 573008, overlap = 93.625
+PHY-3002 : Step(144): len = 570548, overlap = 92.0625
+PHY-3002 : Step(145): len = 566052, overlap = 94.6562
+PHY-3002 : Step(146): len = 564790, overlap = 94.7812
+PHY-3002 : Step(147): len = 561285, overlap = 95.9062
+PHY-3002 : Step(148): len = 558710, overlap = 94.8438
+PHY-3002 : Step(149): len = 557590, overlap = 90.4688
+PHY-3002 : Step(150): len = 557307, overlap = 87.1875
+PHY-3002 : Step(151): len = 553801, overlap = 86.4062
+PHY-3002 : Step(152): len = 552104, overlap = 86.9062
+PHY-3002 : Step(153): len = 549667, overlap = 87.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000132541
+PHY-3002 : Step(154): len = 549979, overlap = 86.9062
+PHY-3002 : Step(155): len = 549979, overlap = 86.9062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000216014
+PHY-3002 : Step(156): len = 556049, overlap = 86.5
+PHY-3002 : Step(157): len = 560209, overlap = 86.1562
+PHY-3002 : Step(158): len = 567641, overlap = 80.4062
+PHY-3002 : Step(159): len = 577269, overlap = 75.6875
+PHY-3002 : Step(160): len = 584615, overlap = 79.7188
+PHY-3002 : Step(161): len = 581830, overlap = 83.7188
+PHY-3002 : Step(162): len = 579609, overlap = 84.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 169/21603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 667640, over cnt = 2531(7%), over = 10839, worst = 37
+PHY-1001 : End global iterations; 1.545630s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (130.4%)
+
+PHY-1001 : Congestion index: top1 = 77.84, top5 = 62.54, top10 = 55.16, top15 = 50.62.
+PHY-3001 : End congestion estimation; 1.855878s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (125.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.973734s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.10217e-05
+PHY-3002 : Step(163): len = 577836, overlap = 415.188
+PHY-3002 : Step(164): len = 582064, overlap = 383.438
+PHY-3002 : Step(165): len = 576887, overlap = 354.219
+PHY-3002 : Step(166): len = 576404, overlap = 323.906
+PHY-3002 : Step(167): len = 570779, overlap = 309.281
+PHY-3002 : Step(168): len = 567999, overlap = 295.281
+PHY-3002 : Step(169): len = 564830, overlap = 290.562
+PHY-3002 : Step(170): len = 562481, overlap = 280.375
+PHY-3002 : Step(171): len = 561083, overlap = 270.469
+PHY-3002 : Step(172): len = 557901, overlap = 268.344
+PHY-3002 : Step(173): len = 556462, overlap = 267.25
+PHY-3002 : Step(174): len = 553956, overlap = 270.938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000142043
+PHY-3002 : Step(175): len = 553100, overlap = 274.656
+PHY-3002 : Step(176): len = 554460, overlap = 274.375
+PHY-3002 : Step(177): len = 558343, overlap = 267.125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000284087
+PHY-3002 : Step(178): len = 562294, overlap = 260.062
+PHY-3002 : Step(179): len = 567283, overlap = 253.531
+PHY-3002 : Step(180): len = 578255, overlap = 240.719
+PHY-3002 : Step(181): len = 577511, overlap = 242.094
+PHY-3002 : Step(182): len = 577658, overlap = 241.281
+PHY-3002 : Step(183): len = 577897, overlap = 238.844
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000568174
+PHY-3002 : Step(184): len = 583226, overlap = 230.844
+PHY-3002 : Step(185): len = 592530, overlap = 215.969
+PHY-3002 : Step(186): len = 600160, overlap = 204.656
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00113635
+PHY-3002 : Step(187): len = 599767, overlap = 200.469
+PHY-3002 : Step(188): len = 604018, overlap = 184.906
+PHY-3002 : Step(189): len = 612612, overlap = 169.469
+PHY-3002 : Step(190): len = 616754, overlap = 162.375
+PHY-3002 : Step(191): len = 619128, overlap = 154.312
+PHY-3002 : Step(192): len = 618967, overlap = 151.125
+PHY-3002 : Step(193): len = 618374, overlap = 145.5
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91087, tnet num: 21425, tinst num: 19023, tnode num: 121366, tedge num: 146063.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.549104s wall, 1.500000s user + 0.062500s system = 1.562500s CPU (100.9%)
+
+RUN-1004 : used memory is 593 MB, reserved memory is 581 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 563.72 peak overflow 4.66
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 720/21603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733456, over cnt = 3224(9%), over = 11963, worst = 24
+PHY-1001 : End global iterations; 1.348030s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 68.73, top5 = 57.76, top10 = 52.37, top15 = 48.94.
+PHY-1001 : End incremental global routing; 1.685478s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (135.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.011224s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (98.9%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18894 has valid locations, 359 needs to be replaced
+PHY-3001 : design contains 19338 instances, 8782 luts, 9337 seqs, 1073 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6089 pins
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 649120
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17382/21918.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 752840, over cnt = 3253(9%), over = 12165, worst = 24
+PHY-1001 : End global iterations; 0.261703s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (143.3%)
+
+PHY-1001 : Congestion index: top1 = 68.58, top5 = 58.09, top10 = 52.82, top15 = 49.44.
+PHY-3001 : End congestion estimation; 0.531470s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (123.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92371, tnet num: 21740, tinst num: 19338, tnode num: 123353, tedge num: 148001.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.509426s wall, 1.468750s user + 0.046875s system = 1.515625s CPU (100.4%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 647 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21740 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.949319s wall, 2.906250s user + 0.046875s system = 2.953125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(194): len = 647759, overlap = 0
+PHY-3002 : Step(195): len = 647934, overlap = 0
+PHY-3002 : Step(196): len = 647279, overlap = 0
+PHY-3002 : Step(197): len = 647389, overlap = 0
+PHY-3002 : Step(198): len = 647730, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17424/21918.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 748008, over cnt = 3244(9%), over = 12236, worst = 24
+PHY-1001 : End global iterations; 0.269508s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (116.0%)
+
+PHY-1001 : Congestion index: top1 = 68.94, top5 = 58.50, top10 = 53.07, top15 = 49.69.
+PHY-3001 : End congestion estimation; 0.564598s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (107.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21740 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.056928s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000245224
+PHY-3002 : Step(199): len = 647785, overlap = 148.75
+PHY-3002 : Step(200): len = 647884, overlap = 148.938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000485951
+PHY-3002 : Step(201): len = 648077, overlap = 148.938
+PHY-3002 : Step(202): len = 648676, overlap = 148.75
+PHY-3001 : Final: Len = 648676, Over = 148.75
+PHY-3001 : End incremental placement; 5.897846s wall, 6.421875s user + 0.218750s system = 6.640625s CPU (112.6%)
+
+OPT-1001 : Total overflow 573.00 peak overflow 4.66
+OPT-1001 : End high-fanout net optimization; 9.517133s wall, 10.671875s user + 0.234375s system = 10.906250s CPU (114.6%)
+
+OPT-1001 : Current memory(MB): used = 746, reserve = 741, peak = 765.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17460/21918.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753520, over cnt = 3216(9%), over = 10902, worst = 24
+PHY-1002 : len = 816448, over cnt = 2236(6%), over = 5188, worst = 22
+PHY-1002 : len = 855192, over cnt = 1185(3%), over = 2434, worst = 15
+PHY-1002 : len = 897632, over cnt = 267(0%), over = 416, worst = 11
+PHY-1002 : len = 906576, over cnt = 27(0%), over = 30, worst = 3
+PHY-1001 : End global iterations; 2.102356s wall, 2.921875s user + 0.015625s system = 2.937500s CPU (139.7%)
+
+PHY-1001 : Congestion index: top1 = 59.94, top5 = 52.55, top10 = 48.93, top15 = 46.74.
+OPT-1001 : End congestion update; 2.381704s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (135.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21740 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.900885s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.9%)
+
+OPT-0007 : Start: WNS -3898 TNS -2379750 NUM_FEPS 1064
+OPT-0007 : Iter 1: improved WNS -3798 TNS -2353910 NUM_FEPS 1064 with 98 cells processed and 3700 slack improved
+OPT-0007 : Iter 2: improved WNS -3798 TNS -2353780 NUM_FEPS 1064 with 60 cells processed and 1652 slack improved
+OPT-0007 : Iter 3: improved WNS -3798 TNS -2353654 NUM_FEPS 1064 with 21 cells processed and 400 slack improved
+OPT-0007 : Iter 4: improved WNS -3798 TNS -2349436 NUM_FEPS 1064 with 1 cells processed and 108 slack improved
+OPT-1001 : End bottleneck based optimization; 3.853478s wall, 4.671875s user + 0.015625s system = 4.687500s CPU (121.6%)
+
+OPT-1001 : Current memory(MB): used = 723, reserve = 719, peak = 765.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17596/21919.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906672, over cnt = 282(0%), over = 360, worst = 4
+PHY-1002 : len = 906080, over cnt = 159(0%), over = 183, worst = 4
+PHY-1002 : len = 906688, over cnt = 89(0%), over = 101, worst = 3
+PHY-1002 : len = 907232, over cnt = 57(0%), over = 61, worst = 3
+PHY-1002 : len = 908592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.854087s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (106.1%)
+
+PHY-1001 : Congestion index: top1 = 59.83, top5 = 52.40, top10 = 48.84, top15 = 46.68.
+OPT-1001 : End congestion update; 1.144302s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (105.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21741 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.892641s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.8%)
+
+OPT-0007 : Start: WNS -3798 TNS -2349436 NUM_FEPS 1064
+OPT-0007 : Iter 1: improved WNS -3798 TNS -2344830 NUM_FEPS 1064 with 36 cells processed and 2614 slack improved
+OPT-0007 : Iter 2: improved WNS -3798 TNS -2344830 NUM_FEPS 1064 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.209430s wall, 2.234375s user + 0.031250s system = 2.265625s CPU (102.5%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 727, peak = 765.
+OPT-1001 : End physical optimization; 17.476809s wall, 19.406250s user + 0.375000s system = 19.781250s CPU (113.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8782 LUT to BLE ...
+SYN-4008 : Packed 8782 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6203 remaining SEQ's ...
+SYN-4005 : Packed 4457 SEQ with LUT/SLICE
+SYN-4006 : 1485 single LUT's are left
+SYN-4006 : 1746 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10528/14381 primitive instances ...
+PHY-3001 : End packing; 1.891631s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7325 instances
+RUN-1001 : 3589 mslices, 3588 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18917 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10407 nets have 2 pins
+RUN-1001 : 6620 nets have [3 - 5] pins
+RUN-1001 : 973 nets have [6 - 10] pins
+RUN-1001 : 477 nets have [11 - 20] pins
+RUN-1001 : 409 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7323 instances, 7177 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3645 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 657288, Over = 344.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7921/18917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838840, over cnt = 2318(6%), over = 3905, worst = 7
+PHY-1002 : len = 849840, over cnt = 1430(4%), over = 2049, worst = 7
+PHY-1002 : len = 863056, over cnt = 659(1%), over = 924, worst = 6
+PHY-1002 : len = 877728, over cnt = 105(0%), over = 128, worst = 5
+PHY-1002 : len = 880672, over cnt = 3(0%), over = 4, worst = 2
+PHY-1001 : End global iterations; 1.940598s wall, 2.546875s user + 0.031250s system = 2.578125s CPU (132.9%)
+
+PHY-1001 : Congestion index: top1 = 59.72, top5 = 52.66, top10 = 48.79, top15 = 46.38.
+PHY-3001 : End congestion estimation; 2.375532s wall, 2.968750s user + 0.031250s system = 3.000000s CPU (126.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81655, tnet num: 18739, tinst num: 7323, tnode num: 104721, tedge num: 136944.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.779466s wall, 1.750000s user + 0.031250s system = 1.781250s CPU (100.1%)
+
+RUN-1004 : used memory is 648 MB, reserved memory is 652 MB, peak memory is 765 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.773843s wall, 2.734375s user + 0.031250s system = 2.765625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.55271e-05
+PHY-3002 : Step(203): len = 640503, overlap = 354.25
+PHY-3002 : Step(204): len = 630798, overlap = 361.5
+PHY-3002 : Step(205): len = 624672, overlap = 380.75
+PHY-3002 : Step(206): len = 620089, overlap = 397.25
+PHY-3002 : Step(207): len = 616458, overlap = 405.25
+PHY-3002 : Step(208): len = 613553, overlap = 412.75
+PHY-3002 : Step(209): len = 610955, overlap = 417
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.10542e-05
+PHY-3002 : Step(210): len = 615797, overlap = 406.5
+PHY-3002 : Step(211): len = 621030, overlap = 396.25
+PHY-3002 : Step(212): len = 621127, overlap = 388.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000182108
+PHY-3002 : Step(213): len = 632542, overlap = 371
+PHY-3002 : Step(214): len = 641423, overlap = 351.5
+PHY-3002 : Step(215): len = 639567, overlap = 350.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000364217
+PHY-3002 : Step(216): len = 646101, overlap = 338.25
+PHY-3002 : Step(217): len = 658873, overlap = 317
+PHY-3002 : Step(218): len = 659729, overlap = 298.5
+PHY-3002 : Step(219): len = 658629, overlap = 301
+PHY-3002 : Step(220): len = 657961, overlap = 301.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000599163
+PHY-3002 : Step(221): len = 662341, overlap = 293
+PHY-3002 : Step(222): len = 666528, overlap = 290.25
+PHY-3002 : Step(223): len = 671563, overlap = 278.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.355246s wall, 0.375000s user + 0.546875s system = 0.921875s CPU (259.5%)
+
+PHY-3001 : Trial Legalized: Len = 765436
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 902/18917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908168, over cnt = 3236(9%), over = 5495, worst = 7
+PHY-1002 : len = 927376, over cnt = 2132(6%), over = 3202, worst = 6
+PHY-1002 : len = 947088, over cnt = 1195(3%), over = 1702, worst = 6
+PHY-1002 : len = 969088, over cnt = 276(0%), over = 380, worst = 5
+PHY-1002 : len = 978664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.849042s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 58.45, top5 = 53.21, top10 = 49.94, top15 = 47.90.
+PHY-3001 : End congestion estimation; 3.366822s wall, 4.609375s user + 0.015625s system = 4.625000s CPU (137.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.995328s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000214156
+PHY-3002 : Step(224): len = 721971, overlap = 87
+PHY-3002 : Step(225): len = 700215, overlap = 143.75
+PHY-3002 : Step(226): len = 682893, overlap = 201.75
+PHY-3002 : Step(227): len = 673046, overlap = 243.75
+PHY-3002 : Step(228): len = 667680, overlap = 277.75
+PHY-3002 : Step(229): len = 664999, overlap = 283
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000428312
+PHY-3002 : Step(230): len = 668699, overlap = 273.5
+PHY-3002 : Step(231): len = 673903, overlap = 267.5
+PHY-3002 : Step(232): len = 676912, overlap = 256.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000856624
+PHY-3002 : Step(233): len = 679169, overlap = 256
+PHY-3002 : Step(234): len = 687142, overlap = 241.25
+PHY-3002 : Step(235): len = 690431, overlap = 234.25
+PHY-3002 : Step(236): len = 691585, overlap = 235.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037357s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (83.7%)
+
+PHY-3001 : Legalized: Len = 734327, Over = 0
+PHY-3001 : Spreading special nets. 600 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.138495s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.5%)
+
+PHY-3001 : 927 instances has been re-located, deltaX = 345, deltaY = 568, maxDist = 5.
+PHY-3001 : Final: Len = 750165, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81655, tnet num: 18739, tinst num: 7326, tnode num: 104721, tedge num: 136944.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.024465s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (99.6%)
+
+RUN-1004 : used memory is 665 MB, reserved memory is 684 MB, peak memory is 769 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4491/18917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 907880, over cnt = 3069(8%), over = 4989, worst = 7
+PHY-1002 : len = 923632, over cnt = 1983(5%), over = 2816, worst = 5
+PHY-1002 : len = 943264, over cnt = 898(2%), over = 1262, worst = 5
+PHY-1002 : len = 954304, over cnt = 476(1%), over = 698, worst = 5
+PHY-1002 : len = 966264, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations; 2.546515s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (141.7%)
+
+PHY-1001 : Congestion index: top1 = 57.59, top5 = 52.44, top10 = 49.47, top15 = 47.39.
+PHY-1001 : End incremental global routing; 2.961196s wall, 4.000000s user + 0.015625s system = 4.015625s CPU (135.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.031814s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (99.9%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7234 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 7343 instances, 7194 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3711 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 753182
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17214/18930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 969680, over cnt = 75(0%), over = 87, worst = 4
+PHY-1002 : len = 969744, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 969944, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 969944, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 970072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.923039s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 57.59, top5 = 52.47, top10 = 49.48, top15 = 47.42.
+PHY-3001 : End congestion estimation; 1.300761s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (104.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81822, tnet num: 18752, tinst num: 7343, tnode num: 104930, tedge num: 137154.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.046321s wall, 1.984375s user + 0.046875s system = 2.031250s CPU (99.3%)
+
+RUN-1004 : used memory is 699 MB, reserved memory is 706 MB, peak memory is 773 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.063442s wall, 3.015625s user + 0.046875s system = 3.062500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(237): len = 752190, overlap = 0
+PHY-3002 : Step(238): len = 751945, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17206/18930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 967952, over cnt = 54(0%), over = 68, worst = 3
+PHY-1002 : len = 968064, over cnt = 27(0%), over = 29, worst = 2
+PHY-1002 : len = 968344, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 968376, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 968392, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.864333s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (104.8%)
+
+PHY-1001 : Congestion index: top1 = 57.59, top5 = 52.47, top10 = 49.49, top15 = 47.42.
+PHY-3001 : End congestion estimation; 1.220029s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (103.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.997611s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000807838
+PHY-3002 : Step(239): len = 751798, overlap = 1.5
+PHY-3002 : Step(240): len = 751822, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005862s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (266.5%)
+
+PHY-3001 : Legalized: Len = 751898, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067789s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (115.2%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 1.
+PHY-3001 : Final: Len = 752024, Over = 0
+PHY-3001 : End incremental placement; 7.128703s wall, 7.281250s user + 0.140625s system = 7.421875s CPU (104.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.713083s wall, 12.890625s user + 0.156250s system = 13.046875s CPU (111.4%)
+
+OPT-1001 : Current memory(MB): used = 786, reserve = 787, peak = 790.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17196/18930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 968752, over cnt = 33(0%), over = 41, worst = 3
+PHY-1002 : len = 968728, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 968880, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 968936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.654366s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (100.3%)
+
+PHY-1001 : Congestion index: top1 = 57.67, top5 = 52.48, top10 = 49.48, top15 = 47.42.
+OPT-1001 : End congestion update; 1.003299s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.826903s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.1%)
+
+OPT-0007 : Start: WNS -4058 TNS -2263423 NUM_FEPS 985
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7255 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7343 instances, 7194 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3711 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 752449, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067968s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.0%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 9, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 752955, Over = 0
+PHY-3001 : End incremental legalization; 0.443303s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (116.3%)
+
+OPT-0007 : Iter 1: improved WNS -3808 TNS -2250368 NUM_FEPS 985 with 45 cells processed and 5441 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7255 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7343 instances, 7194 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3711 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 753135, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065764s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (118.8%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 6, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 753071, Over = 0
+PHY-3001 : End incremental legalization; 0.433733s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.3%)
+
+OPT-0007 : Iter 2: improved WNS -3808 TNS -2244819 NUM_FEPS 985 with 20 cells processed and 2772 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7255 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7343 instances, 7194 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3711 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 753349, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069957s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (89.3%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 7, deltaY = 14, maxDist = 4.
+PHY-3001 : Final: Len = 753489, Over = 0
+PHY-3001 : End incremental legalization; 0.432273s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.2%)
+
+OPT-0007 : Iter 3: improved WNS -3808 TNS -2241859 NUM_FEPS 985 with 20 cells processed and 1616 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7255 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7343 instances, 7194 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3711 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 753559, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.075603s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (103.3%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 3, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 753479, Over = 0
+PHY-3001 : End incremental legalization; 0.487313s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.4%)
+
+OPT-0007 : Iter 4: improved WNS -3808 TNS -2241142 NUM_FEPS 985 with 10 cells processed and 1066 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7255 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7343 instances, 7194 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3711 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 753717, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064104s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (121.9%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 2, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 753623, Over = 0
+PHY-3001 : End incremental legalization; 0.414659s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.0%)
+
+OPT-0007 : Iter 5: improved WNS -3808 TNS -2240522 NUM_FEPS 985 with 8 cells processed and 350 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7260 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7348 instances, 7199 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3713 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 753872, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063805s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.0%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 3, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 753932, Over = 0
+PHY-3001 : End incremental legalization; 0.421485s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.1%)
+
+OPT-0007 : Iter 6: improved WNS -3808 TNS -2237800 NUM_FEPS 985 with 4 cells processed and 450 slack improved
+OPT-1001 : End bottleneck based optimization; 5.725732s wall, 6.078125s user + 0.015625s system = 6.093750s CPU (106.4%)
+
+OPT-1001 : Current memory(MB): used = 786, reserve = 787, peak = 790.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16830/18933.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 969480, over cnt = 400(1%), over = 499, worst = 5
+PHY-1002 : len = 969800, over cnt = 229(0%), over = 260, worst = 3
+PHY-1002 : len = 971952, over cnt = 63(0%), over = 67, worst = 3
+PHY-1002 : len = 972736, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 973160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.008800s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (111.5%)
+
+PHY-1001 : Congestion index: top1 = 57.93, top5 = 52.65, top10 = 49.57, top15 = 47.57.
+OPT-1001 : End congestion update; 1.349478s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (108.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.814531s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.8%)
+
+OPT-0007 : Start: WNS -3854 TNS -2240807 NUM_FEPS 985
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7260 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7348 instances, 7199 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3713 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 754664, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064938s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.2%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 6, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 754824, Over = 0
+PHY-3001 : End incremental legalization; 0.410485s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (152.3%)
+
+OPT-0007 : Iter 1: improved WNS -3854 TNS -2237216 NUM_FEPS 985 with 32 cells processed and 2493 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7260 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7348 instances, 7199 slices, 222 macros(1073 instances: 699 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3713 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 755002, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062161s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 0, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 754948, Over = 0
+PHY-3001 : End incremental legalization; 0.415509s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.8%)
+
+OPT-0007 : Iter 2: improved WNS -3854 TNS -2236816 NUM_FEPS 985 with 13 cells processed and 400 slack improved
+OPT-0007 : Iter 3: improved WNS -3854 TNS -2236816 NUM_FEPS 985 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.349784s wall, 3.656250s user + 0.015625s system = 3.671875s CPU (109.6%)
+
+OPT-1001 : Current memory(MB): used = 786, reserve = 787, peak = 790.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.806171s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17027/18933.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 973544, over cnt = 111(0%), over = 145, worst = 4
+PHY-1002 : len = 973632, over cnt = 65(0%), over = 74, worst = 3
+PHY-1002 : len = 974136, over cnt = 28(0%), over = 30, worst = 2
+PHY-1002 : len = 974440, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 974792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.873640s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (109.1%)
+
+PHY-1001 : Congestion index: top1 = 57.93, top5 = 52.63, top10 = 49.54, top15 = 47.54.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.802144s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -3854 TNS -2237513 NUM_FEPS 985
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 57.586207
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -3854ps with logic level 5
+RUN-1001 : #2 path slack -3854ps with logic level 5
+RUN-1001 : #3 path slack -3808ps with logic level 5
+RUN-1001 : #4 path slack -3807ps with logic level 5
+RUN-1001 : #5 path slack -3794ps with logic level 5
+RUN-1001 : 0 HFN exist on timing critical paths out of 18933 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18933 nets
+OPT-1001 : End physical optimization; 26.052382s wall, 28.015625s user + 0.203125s system = 28.218750s CPU (108.3%)
+
+RUN-1003 : finish command "place" in 75.944766s wall, 105.781250s user + 5.578125s system = 111.359375s CPU (146.6%)
+
+RUN-1004 : used memory is 686 MB, reserved memory is 686 MB, peak memory is 790 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.777413s wall, 3.093750s user + 0.031250s system = 3.125000s CPU (175.8%)
+
+RUN-1004 : used memory is 686 MB, reserved memory is 687 MB, peak memory is 790 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7350 instances
+RUN-1001 : 3597 mslices, 3602 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18933 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10396 nets have 2 pins
+RUN-1001 : 6624 nets have [3 - 5] pins
+RUN-1001 : 983 nets have [6 - 10] pins
+RUN-1001 : 482 nets have [11 - 20] pins
+RUN-1001 : 420 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81874, tnet num: 18755, tinst num: 7348, tnode num: 104996, tedge num: 137216.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.734719s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (100.0%)
+
+RUN-1004 : used memory is 698 MB, reserved memory is 706 MB, peak memory is 790 MB
+PHY-1001 : 3597 mslices, 3602 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18755 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 882000, over cnt = 3305(9%), over = 5531, worst = 7
+PHY-1002 : len = 902312, over cnt = 2131(6%), over = 3183, worst = 6
+PHY-1002 : len = 934648, over cnt = 631(1%), over = 852, worst = 6
+PHY-1002 : len = 950248, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 950680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.341198s wall, 4.531250s user + 0.031250s system = 4.562500s CPU (136.6%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 51.83, top10 = 48.84, top15 = 46.87.
+PHY-1001 : End global routing; 3.695377s wall, 4.890625s user + 0.031250s system = 4.921875s CPU (133.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 757, reserve = 762, peak = 790.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1036, peak = 1031.
+PHY-1001 : End build detailed router design. 4.079565s wall, 4.031250s user + 0.062500s system = 4.093750s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 276616, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.815047s wall, 4.812500s user + 0.000000s system = 4.812500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 276672, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.458711s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.8%)
+
+PHY-1001 : Current memory(MB): used = 1067, reserve = 1072, peak = 1067.
+PHY-1001 : End phase 1; 5.285849s wall, 5.281250s user + 0.000000s system = 5.281250s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 35% nets.
+PHY-1001 : Routed 41% nets.
+PHY-1001 : Routed 50% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.60012e+06, over cnt = 2298(0%), over = 2307, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1087, reserve = 1090, peak = 1087.
+PHY-1001 : End initial routed; 24.940419s wall, 51.843750s user + 0.093750s system = 51.937500s CPU (208.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2854/17858(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -6.154 | -3421.237 | 990
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.484547s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1097, reserve = 1101, peak = 1097.
+PHY-1001 : End phase 2; 28.425032s wall, 55.328125s user + 0.093750s system = 55.421875s CPU (195.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 51 pins with SWNS -5.854ns STNS -3414.934ns FEP 986.
+PHY-1001 : End OPT Iter 1; 0.315149s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.2%)
+
+PHY-1022 : len = 2.6005e+06, over cnt = 2327(0%), over = 2337, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.599627s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (101.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.5527e+06, over cnt = 898(0%), over = 902, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.079427s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (161.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.54545e+06, over cnt = 228(0%), over = 228, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.265514s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (138.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.5454e+06, over cnt = 62(0%), over = 62, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.670467s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (114.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.54601e+06, over cnt = 18(0%), over = 18, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.672816s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (113.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.54634e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.713341s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.54626e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.662791s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.54635e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 1.067757s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.54641e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.212965s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (110.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.54634e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.199293s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.54638e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.231640s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.54637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.198677s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (110.1%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.54637e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 12; 0.246614s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2850/17858(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.940 | -3417.180 | 986
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.475963s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 841 feed throughs used by 598 nets
+PHY-1001 : End commit to database; 2.461732s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1208, reserve = 1215, peak = 1208.
+PHY-1001 : End phase 3; 15.195398s wall, 17.203125s user + 0.000000s system = 17.203125s CPU (113.2%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 41 pins with SWNS -5.765ns STNS -3414.307ns FEP 986.
+PHY-1001 : End OPT Iter 1; 0.304940s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (97.4%)
+
+PHY-1022 : len = 2.54642e+06, over cnt = 16(0%), over = 16, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.596118s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (99.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.765ns, -3414.307ns, 986}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.54625e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.194247s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.54622e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.190823s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2850/17858(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.765 | -3415.195 | 986
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.472203s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 845 feed throughs used by 602 nets
+PHY-1001 : End commit to database; 2.592667s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1218, reserve = 1225, peak = 1218.
+PHY-1001 : End phase 4; 7.100917s wall, 7.109375s user + 0.000000s system = 7.109375s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.54622e+06
+PHY-1001 : Current memory(MB): used = 1223, reserve = 1231, peak = 1223.
+PHY-1001 : End export database. 0.067197s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (116.3%)
+
+PHY-1001 : End detail routing; 60.570374s wall, 89.421875s user + 0.156250s system = 89.578125s CPU (147.9%)
+
+RUN-1003 : finish command "route" in 67.156523s wall, 97.171875s user + 0.218750s system = 97.390625s CPU (145.0%)
+
+RUN-1004 : used memory is 1143 MB, reserved memory is 1152 MB, peak memory is 1223 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 11798 out of 19600 60.19%
+#reg 9471 out of 19600 48.32%
+#le 13490
+ #lut only 4019 out of 13490 29.79%
+ #reg only 1692 out of 13490 12.54%
+ #lut® 7779 out of 13490 57.66%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1806
+#2 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1459
+#3 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1451
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 1000
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 135
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 73
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 67
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/reg2_syn_161.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg46_syn_214.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P35 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P66 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P163 LVCMOS33 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P162 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P8 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P11 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |13490 |10773 |1025 |9505 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |511 |434 |23 |432 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |79 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |33 |33 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |10 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |762 |483 |96 |572 |0 |0 |
+| u_ADconfig |AD_config |191 |144 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |265 |151 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |737 |423 |96 |556 |0 |0 |
+| u_ADconfig |AD_config |173 |129 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |257 |140 |71 |119 |0 |0 |
+| sampling_fe_a |sampling_fe |3157 |2545 |306 |2150 |25 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |172 |114 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_sort |sort |2953 |2420 |289 |1977 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |1 |0 |1 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2571 |2114 |253 |1658 |22 |0 |
+| channelPart |channel_part_8478 |161 |152 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |70 |61 |9 |42 |0 |0 |
+| ram_switch |ram_switch |2038 |1670 |197 |1251 |0 |0 |
+| adc_addr_gen |adc_addr_gen |238 |210 |27 |130 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |17 |14 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |27 |24 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |29 |26 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |993 |660 |170 |693 |0 |0 |
+| ram_switch_state |ram_switch_state |807 |800 |0 |428 |0 |0 |
+| read_ram_i |read_ram |256 |206 |44 |183 |0 |0 |
+| read_ram_addr |read_ram_addr |211 |171 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |42 |33 |4 |31 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |305 |243 |36 |254 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |4178 |3539 |346 |2076 |25 |1 |
+| u0_soft_n |cdc_sync |7 |4 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |173 |97 |17 |138 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort_rev |3968 |3429 |329 |1901 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |6 |1 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |3536 |3079 |287 |1570 |22 |1 |
+| channelPart |channel_part_8478 |257 |252 |3 |141 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |44 |0 |1 |
+| ram_switch |ram_switch |2833 |2501 |197 |1143 |0 |0 |
+| adc_addr_gen |adc_addr_gen |235 |207 |27 |113 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |8 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |10 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |17 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |937 |633 |170 |614 |0 |0 |
+| ram_switch_state |ram_switch_state |1661 |1661 |0 |416 |0 |0 |
+| read_ram_i |read_ram_rev |342 |240 |78 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |288 |207 |70 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |54 |33 |8 |38 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10334
+ #2 2 4657
+ #3 3 1237
+ #4 4 727
+ #5 5-10 1101
+ #6 11-50 749
+ #7 51-100 32
+ #8 >500 1
+ Average 3.04
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.166163s wall, 3.796875s user + 0.015625s system = 3.812500s CPU (176.0%)
+
+RUN-1004 : used memory is 1144 MB, reserved memory is 1154 MB, peak memory is 1223 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81874, tnet num: 18755, tinst num: 7348, tnode num: 104996, tedge num: 137216.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.730605s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.3%)
+
+RUN-1004 : used memory is 1151 MB, reserved memory is 1161 MB, peak memory is 1223 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18755 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.563559s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.9%)
+
+RUN-1004 : used memory is 1152 MB, reserved memory is 1162 MB, peak memory is 1223 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7348
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18933, pip num: 192574
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 845
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3255 valid insts, and 534774 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.976729s wall, 75.656250s user + 0.140625s system = 75.796875s CPU (690.5%)
+
+RUN-1004 : used memory is 1334 MB, reserved memory is 1338 MB, peak memory is 1450 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_152204.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_153107.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_153107.log
new file mode 100644
index 0000000..2b7d7c5
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_153107.log
@@ -0,0 +1,2190 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:31:07 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.178924s wall, 2.109375s user + 0.062500s system = 2.171875s CPU (99.7%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 315 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17987 instances
+RUN-0007 : 7662 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20565 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13088 nets have 2 pins
+RUN-1001 : 6442 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 178 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17985 instances, 7662 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83999, tnet num: 20387, tinst num: 17985, tnode num: 114266, tedge num: 133954.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.137747s wall, 1.062500s user + 0.062500s system = 1.125000s CPU (98.9%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 514 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.957552s wall, 1.875000s user + 0.078125s system = 1.953125s CPU (99.8%)
+
+PHY-3001 : Found 1252 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.04709e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17985.
+PHY-3001 : Level 1 #clusters 2093.
+PHY-3001 : End clustering; 0.127535s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32153e+06, overlap = 454.281
+PHY-3002 : Step(2): len = 1.22336e+06, overlap = 498.031
+PHY-3002 : Step(3): len = 865736, overlap = 561.156
+PHY-3002 : Step(4): len = 794082, overlap = 610.406
+PHY-3002 : Step(5): len = 611119, overlap = 754.531
+PHY-3002 : Step(6): len = 539691, overlap = 801.375
+PHY-3002 : Step(7): len = 462772, overlap = 904.469
+PHY-3002 : Step(8): len = 414645, overlap = 940.125
+PHY-3002 : Step(9): len = 382084, overlap = 1007.16
+PHY-3002 : Step(10): len = 348412, overlap = 1058.81
+PHY-3002 : Step(11): len = 319713, overlap = 1087.34
+PHY-3002 : Step(12): len = 285101, overlap = 1139.75
+PHY-3002 : Step(13): len = 271590, overlap = 1194.16
+PHY-3002 : Step(14): len = 239354, overlap = 1276.62
+PHY-3002 : Step(15): len = 225261, overlap = 1306.19
+PHY-3002 : Step(16): len = 197792, overlap = 1346.31
+PHY-3002 : Step(17): len = 193175, overlap = 1356.59
+PHY-3002 : Step(18): len = 172105, overlap = 1378.81
+PHY-3002 : Step(19): len = 167653, overlap = 1405.72
+PHY-3002 : Step(20): len = 151262, overlap = 1442.38
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.21019e-06
+PHY-3002 : Step(21): len = 153356, overlap = 1398.62
+PHY-3002 : Step(22): len = 186579, overlap = 1254.44
+PHY-3002 : Step(23): len = 197752, overlap = 1194.81
+PHY-3002 : Step(24): len = 206211, overlap = 1158.94
+PHY-3002 : Step(25): len = 204887, overlap = 1143.59
+PHY-3002 : Step(26): len = 204973, overlap = 1140.03
+PHY-3002 : Step(27): len = 200489, overlap = 1151.84
+PHY-3002 : Step(28): len = 198315, overlap = 1155.53
+PHY-3002 : Step(29): len = 195079, overlap = 1131.19
+PHY-3002 : Step(30): len = 194530, overlap = 1114.34
+PHY-3002 : Step(31): len = 192202, overlap = 1107.62
+PHY-3002 : Step(32): len = 190962, overlap = 1113.91
+PHY-3002 : Step(33): len = 189192, overlap = 1114.59
+PHY-3002 : Step(34): len = 188940, overlap = 1098.03
+PHY-3002 : Step(35): len = 188303, overlap = 1103.22
+PHY-3002 : Step(36): len = 189128, overlap = 1105.91
+PHY-3002 : Step(37): len = 188540, overlap = 1091.97
+PHY-3002 : Step(38): len = 189795, overlap = 1049.69
+PHY-3002 : Step(39): len = 189266, overlap = 1033.94
+PHY-3002 : Step(40): len = 188850, overlap = 1035.91
+PHY-3002 : Step(41): len = 187392, overlap = 1051.06
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.42038e-06
+PHY-3002 : Step(42): len = 193766, overlap = 1046.75
+PHY-3002 : Step(43): len = 206493, overlap = 1010.44
+PHY-3002 : Step(44): len = 209323, overlap = 982.406
+PHY-3002 : Step(45): len = 213601, overlap = 948.844
+PHY-3002 : Step(46): len = 215731, overlap = 942.938
+PHY-3002 : Step(47): len = 216163, overlap = 951.031
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.84077e-06
+PHY-3002 : Step(48): len = 226572, overlap = 918.875
+PHY-3002 : Step(49): len = 246937, overlap = 892.281
+PHY-3002 : Step(50): len = 256057, overlap = 850.188
+PHY-3002 : Step(51): len = 260519, overlap = 810.188
+PHY-3002 : Step(52): len = 260159, overlap = 793.875
+PHY-3002 : Step(53): len = 260273, overlap = 778.156
+PHY-3002 : Step(54): len = 258478, overlap = 744.969
+PHY-3002 : Step(55): len = 256626, overlap = 745.156
+PHY-3002 : Step(56): len = 256517, overlap = 746.219
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.68154e-06
+PHY-3002 : Step(57): len = 269863, overlap = 722.312
+PHY-3002 : Step(58): len = 288907, overlap = 640
+PHY-3002 : Step(59): len = 300210, overlap = 571.594
+PHY-3002 : Step(60): len = 306866, overlap = 537.906
+PHY-3002 : Step(61): len = 307083, overlap = 541.719
+PHY-3002 : Step(62): len = 309324, overlap = 512.781
+PHY-3002 : Step(63): len = 306802, overlap = 505.219
+PHY-3002 : Step(64): len = 305600, overlap = 504.906
+PHY-3002 : Step(65): len = 304432, overlap = 521.281
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.93631e-05
+PHY-3002 : Step(66): len = 321107, overlap = 483.281
+PHY-3002 : Step(67): len = 335523, overlap = 465.156
+PHY-3002 : Step(68): len = 338542, overlap = 448.188
+PHY-3002 : Step(69): len = 342071, overlap = 455.406
+PHY-3002 : Step(70): len = 340230, overlap = 418.062
+PHY-3002 : Step(71): len = 341271, overlap = 421.531
+PHY-3002 : Step(72): len = 341094, overlap = 403.5
+PHY-3002 : Step(73): len = 343854, overlap = 391.062
+PHY-3002 : Step(74): len = 344245, overlap = 388.062
+PHY-3002 : Step(75): len = 344848, overlap = 389.594
+PHY-3002 : Step(76): len = 343943, overlap = 377.625
+PHY-3002 : Step(77): len = 344267, overlap = 370.344
+PHY-3002 : Step(78): len = 344584, overlap = 366.156
+PHY-3002 : Step(79): len = 344117, overlap = 373.969
+PHY-3002 : Step(80): len = 342697, overlap = 373.781
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.87261e-05
+PHY-3002 : Step(81): len = 356790, overlap = 343.094
+PHY-3002 : Step(82): len = 365756, overlap = 327.719
+PHY-3002 : Step(83): len = 369028, overlap = 320.25
+PHY-3002 : Step(84): len = 369873, overlap = 309.906
+PHY-3002 : Step(85): len = 370314, overlap = 306.344
+PHY-3002 : Step(86): len = 371930, overlap = 295.125
+PHY-3002 : Step(87): len = 370971, overlap = 275.25
+PHY-3002 : Step(88): len = 375174, overlap = 268.125
+PHY-3002 : Step(89): len = 377809, overlap = 263.375
+PHY-3002 : Step(90): len = 379723, overlap = 264.75
+PHY-3002 : Step(91): len = 379047, overlap = 266.156
+PHY-3002 : Step(92): len = 380631, overlap = 270.531
+PHY-3002 : Step(93): len = 381368, overlap = 267.312
+PHY-3002 : Step(94): len = 383564, overlap = 264.719
+PHY-3002 : Step(95): len = 383350, overlap = 265.219
+PHY-3002 : Step(96): len = 383356, overlap = 264.344
+PHY-3002 : Step(97): len = 383793, overlap = 263.125
+PHY-3002 : Step(98): len = 384043, overlap = 258
+PHY-3002 : Step(99): len = 382719, overlap = 245.594
+PHY-3002 : Step(100): len = 383434, overlap = 244.531
+PHY-3002 : Step(101): len = 382815, overlap = 242.969
+PHY-3002 : Step(102): len = 383910, overlap = 248.094
+PHY-3002 : Step(103): len = 381868, overlap = 240.375
+PHY-3002 : Step(104): len = 382653, overlap = 235.344
+PHY-3002 : Step(105): len = 382722, overlap = 240.75
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.74523e-05
+PHY-3002 : Step(106): len = 397287, overlap = 232.156
+PHY-3002 : Step(107): len = 407159, overlap = 223.094
+PHY-3002 : Step(108): len = 407424, overlap = 222.938
+PHY-3002 : Step(109): len = 408115, overlap = 217.469
+PHY-3002 : Step(110): len = 408832, overlap = 220.062
+PHY-3002 : Step(111): len = 410440, overlap = 209.5
+PHY-3002 : Step(112): len = 410033, overlap = 212.719
+PHY-3002 : Step(113): len = 411115, overlap = 214.375
+PHY-3002 : Step(114): len = 412134, overlap = 209.938
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154905
+PHY-3002 : Step(115): len = 424282, overlap = 217.844
+PHY-3002 : Step(116): len = 433471, overlap = 208.812
+PHY-3002 : Step(117): len = 433664, overlap = 207.969
+PHY-3002 : Step(118): len = 435444, overlap = 196.938
+PHY-3002 : Step(119): len = 439019, overlap = 190.5
+PHY-3002 : Step(120): len = 442451, overlap = 187.75
+PHY-3002 : Step(121): len = 440783, overlap = 180.719
+PHY-3002 : Step(122): len = 441167, overlap = 183.469
+PHY-3002 : Step(123): len = 443662, overlap = 166.344
+PHY-3002 : Step(124): len = 445738, overlap = 165.094
+PHY-3002 : Step(125): len = 443357, overlap = 160.75
+PHY-3002 : Step(126): len = 442712, overlap = 161.938
+PHY-3002 : Step(127): len = 444030, overlap = 160.875
+PHY-3002 : Step(128): len = 445978, overlap = 163.75
+PHY-3002 : Step(129): len = 444987, overlap = 158.406
+PHY-3002 : Step(130): len = 445469, overlap = 155.656
+PHY-3002 : Step(131): len = 446530, overlap = 161.812
+PHY-3002 : Step(132): len = 447153, overlap = 163.562
+PHY-3002 : Step(133): len = 445973, overlap = 163.219
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000287854
+PHY-3002 : Step(134): len = 453659, overlap = 158.719
+PHY-3002 : Step(135): len = 460356, overlap = 161
+PHY-3002 : Step(136): len = 461057, overlap = 156.469
+PHY-3002 : Step(137): len = 462774, overlap = 160.375
+PHY-3002 : Step(138): len = 466526, overlap = 162.469
+PHY-3002 : Step(139): len = 470195, overlap = 155.812
+PHY-3002 : Step(140): len = 469666, overlap = 159.781
+PHY-3002 : Step(141): len = 470169, overlap = 167.469
+PHY-3002 : Step(142): len = 471605, overlap = 169.062
+PHY-3002 : Step(143): len = 472607, overlap = 171.969
+PHY-3002 : Step(144): len = 470850, overlap = 171.75
+PHY-3002 : Step(145): len = 470522, overlap = 179.5
+PHY-3002 : Step(146): len = 472033, overlap = 184.438
+PHY-3002 : Step(147): len = 472515, overlap = 183.625
+PHY-3002 : Step(148): len = 471346, overlap = 183.156
+PHY-3002 : Step(149): len = 471175, overlap = 183.469
+PHY-3002 : Step(150): len = 472345, overlap = 183.062
+PHY-3002 : Step(151): len = 474427, overlap = 184.469
+PHY-3002 : Step(152): len = 473063, overlap = 186.875
+PHY-3002 : Step(153): len = 472992, overlap = 186.906
+PHY-3002 : Step(154): len = 473490, overlap = 188.125
+PHY-3002 : Step(155): len = 473857, overlap = 191.188
+PHY-3002 : Step(156): len = 473320, overlap = 186
+PHY-3002 : Step(157): len = 473390, overlap = 187.844
+PHY-3002 : Step(158): len = 474503, overlap = 194.562
+PHY-3002 : Step(159): len = 475554, overlap = 187.062
+PHY-3002 : Step(160): len = 474632, overlap = 187.594
+PHY-3002 : Step(161): len = 474632, overlap = 187.594
+PHY-3002 : Step(162): len = 474755, overlap = 188.844
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000520569
+PHY-3002 : Step(163): len = 481289, overlap = 198.125
+PHY-3002 : Step(164): len = 489056, overlap = 187.438
+PHY-3002 : Step(165): len = 490417, overlap = 182.188
+PHY-3002 : Step(166): len = 491678, overlap = 171.688
+PHY-3002 : Step(167): len = 494895, overlap = 179.938
+PHY-3002 : Step(168): len = 496316, overlap = 179.812
+PHY-3002 : Step(169): len = 493556, overlap = 174.719
+PHY-3002 : Step(170): len = 493024, overlap = 172.969
+PHY-3002 : Step(171): len = 495366, overlap = 164.031
+PHY-3002 : Step(172): len = 497445, overlap = 153.312
+PHY-3002 : Step(173): len = 496553, overlap = 156.562
+PHY-3002 : Step(174): len = 496635, overlap = 152.75
+PHY-3002 : Step(175): len = 498310, overlap = 149.938
+PHY-3002 : Step(176): len = 499363, overlap = 147.562
+PHY-3002 : Step(177): len = 498743, overlap = 149.719
+PHY-3002 : Step(178): len = 498799, overlap = 145.812
+PHY-3002 : Step(179): len = 499372, overlap = 143.875
+PHY-3002 : Step(180): len = 499636, overlap = 147.969
+PHY-3002 : Step(181): len = 499495, overlap = 149.75
+PHY-3002 : Step(182): len = 499791, overlap = 148.312
+PHY-3002 : Step(183): len = 500532, overlap = 148.188
+PHY-3002 : Step(184): len = 500806, overlap = 151.906
+PHY-3002 : Step(185): len = 500113, overlap = 149.688
+PHY-3002 : Step(186): len = 499999, overlap = 152.875
+PHY-3002 : Step(187): len = 500573, overlap = 153.625
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000996236
+PHY-3002 : Step(188): len = 504185, overlap = 150.281
+PHY-3002 : Step(189): len = 510511, overlap = 138.125
+PHY-3002 : Step(190): len = 512470, overlap = 134.094
+PHY-3002 : Step(191): len = 513755, overlap = 133
+PHY-3002 : Step(192): len = 514832, overlap = 133.156
+PHY-3002 : Step(193): len = 515388, overlap = 133
+PHY-3002 : Step(194): len = 515089, overlap = 128.594
+PHY-3002 : Step(195): len = 515066, overlap = 126.469
+PHY-3002 : Step(196): len = 515655, overlap = 130.438
+PHY-3002 : Step(197): len = 516176, overlap = 130.719
+PHY-3002 : Step(198): len = 516592, overlap = 129.25
+PHY-3002 : Step(199): len = 516717, overlap = 129.438
+PHY-3002 : Step(200): len = 516670, overlap = 134.406
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00171148
+PHY-3002 : Step(201): len = 519271, overlap = 131.156
+PHY-3002 : Step(202): len = 522985, overlap = 130.125
+PHY-3002 : Step(203): len = 523785, overlap = 130.656
+PHY-3002 : Step(204): len = 524288, overlap = 128.281
+PHY-3002 : Step(205): len = 525127, overlap = 131.25
+PHY-3002 : Step(206): len = 525790, overlap = 130
+PHY-3002 : Step(207): len = 526658, overlap = 130.844
+PHY-3002 : Step(208): len = 528114, overlap = 131.562
+PHY-3002 : Step(209): len = 529431, overlap = 130.125
+PHY-3002 : Step(210): len = 530192, overlap = 126.656
+PHY-3002 : Step(211): len = 530513, overlap = 126.594
+PHY-3002 : Step(212): len = 530755, overlap = 131.312
+PHY-3002 : Step(213): len = 531287, overlap = 129.281
+PHY-3002 : Step(214): len = 531812, overlap = 128.875
+PHY-3002 : Step(215): len = 531829, overlap = 129.75
+PHY-3002 : Step(216): len = 531908, overlap = 129.688
+PHY-3002 : Step(217): len = 532740, overlap = 126.875
+PHY-3002 : Step(218): len = 533259, overlap = 123.562
+PHY-3002 : Step(219): len = 533035, overlap = 124.781
+PHY-3002 : Step(220): len = 533035, overlap = 124.781
+PHY-3002 : Step(221): len = 533134, overlap = 124.719
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013532s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (115.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710688, over cnt = 1617(4%), over = 7397, worst = 36
+PHY-1001 : End global iterations; 0.655044s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 84.25, top5 = 62.94, top10 = 53.26, top15 = 47.34.
+PHY-3001 : End congestion estimation; 0.927442s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (126.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.879636s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001519
+PHY-3002 : Step(222): len = 647869, overlap = 73.8125
+PHY-3002 : Step(223): len = 646613, overlap = 78.875
+PHY-3002 : Step(224): len = 639545, overlap = 84.9688
+PHY-3002 : Step(225): len = 635233, overlap = 81.8125
+PHY-3002 : Step(226): len = 636716, overlap = 67.8438
+PHY-3002 : Step(227): len = 639817, overlap = 59.6562
+PHY-3002 : Step(228): len = 637029, overlap = 58.25
+PHY-3002 : Step(229): len = 634130, overlap = 57.0938
+PHY-3002 : Step(230): len = 632229, overlap = 50.5625
+PHY-3002 : Step(231): len = 630604, overlap = 45.125
+PHY-3002 : Step(232): len = 628270, overlap = 43.375
+PHY-3002 : Step(233): len = 626213, overlap = 43.3438
+PHY-3002 : Step(234): len = 625050, overlap = 43.5
+PHY-3002 : Step(235): len = 628222, overlap = 36.25
+PHY-3002 : Step(236): len = 628134, overlap = 32.6875
+PHY-3002 : Step(237): len = 626822, overlap = 33.0312
+PHY-3002 : Step(238): len = 625425, overlap = 33.0938
+PHY-3002 : Step(239): len = 625324, overlap = 34.125
+PHY-3002 : Step(240): len = 623940, overlap = 32.8438
+PHY-3002 : Step(241): len = 622491, overlap = 32.2188
+PHY-3002 : Step(242): len = 620667, overlap = 30.3125
+PHY-3002 : Step(243): len = 621122, overlap = 36.5312
+PHY-3002 : Step(244): len = 620153, overlap = 36.625
+PHY-3002 : Step(245): len = 618679, overlap = 40.2812
+PHY-3002 : Step(246): len = 617465, overlap = 40.625
+PHY-3002 : Step(247): len = 617743, overlap = 40.5625
+PHY-3002 : Step(248): len = 616563, overlap = 42.125
+PHY-3002 : Step(249): len = 615910, overlap = 42.8438
+PHY-3002 : Step(250): len = 614074, overlap = 42.8125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000303799
+PHY-3002 : Step(251): len = 616277, overlap = 42.8438
+PHY-3002 : Step(252): len = 619151, overlap = 42.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 108/20565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 703416, over cnt = 2653(7%), over = 11448, worst = 69
+PHY-1001 : End global iterations; 1.593836s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (133.3%)
+
+PHY-1001 : Congestion index: top1 = 82.63, top5 = 65.66, top10 = 57.18, top15 = 51.91.
+PHY-3001 : End congestion estimation; 1.861947s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (128.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.110581s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.19607e-05
+PHY-3002 : Step(253): len = 616751, overlap = 275.688
+PHY-3002 : Step(254): len = 620541, overlap = 206.844
+PHY-3002 : Step(255): len = 619790, overlap = 203.781
+PHY-3002 : Step(256): len = 615749, overlap = 190.438
+PHY-3002 : Step(257): len = 613037, overlap = 169.688
+PHY-3002 : Step(258): len = 611362, overlap = 162.375
+PHY-3002 : Step(259): len = 607867, overlap = 160.469
+PHY-3002 : Step(260): len = 606318, overlap = 155.219
+PHY-3002 : Step(261): len = 605330, overlap = 155.062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000183921
+PHY-3002 : Step(262): len = 604145, overlap = 152
+PHY-3002 : Step(263): len = 606409, overlap = 146.656
+PHY-3002 : Step(264): len = 608223, overlap = 138.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000367843
+PHY-3002 : Step(265): len = 616500, overlap = 121.5
+PHY-3002 : Step(266): len = 625479, overlap = 105.031
+PHY-3002 : Step(267): len = 631776, overlap = 98.0312
+PHY-3002 : Step(268): len = 630889, overlap = 97.875
+PHY-3002 : Step(269): len = 628756, overlap = 92.0938
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83999, tnet num: 20387, tinst num: 17985, tnode num: 114266, tedge num: 133954.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.434038s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.2%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 562 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 410.06 peak overflow 3.31
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1603/20565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725984, over cnt = 2976(8%), over = 10930, worst = 24
+PHY-1001 : End global iterations; 1.166425s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (147.4%)
+
+PHY-1001 : Congestion index: top1 = 73.17, top5 = 57.04, top10 = 50.54, top15 = 46.92.
+PHY-1001 : End incremental global routing; 1.496313s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (135.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.101418s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (100.7%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 302 needs to be replaced
+PHY-3001 : design contains 18240 instances, 7747 luts, 9272 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6072 pins
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 651242
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16940/20820.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740544, over cnt = 3033(8%), over = 10907, worst = 24
+PHY-1001 : End global iterations; 0.226606s wall, 0.328125s user + 0.031250s system = 0.359375s CPU (158.6%)
+
+PHY-1001 : Congestion index: top1 = 72.76, top5 = 57.00, top10 = 50.78, top15 = 47.27.
+PHY-3001 : End congestion estimation; 0.489285s wall, 0.578125s user + 0.046875s system = 0.625000s CPU (127.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85020, tnet num: 20642, tinst num: 18240, tnode num: 115812, tedge num: 135486.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.481192s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (100.2%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 610 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.446085s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 650301, overlap = 0.125
+PHY-3002 : Step(271): len = 649831, overlap = 0.4375
+PHY-3002 : Step(272): len = 649457, overlap = 0.125
+PHY-3002 : Step(273): len = 649226, overlap = 0.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17017/20820.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737264, over cnt = 3014(8%), over = 10963, worst = 24
+PHY-1001 : End global iterations; 0.188909s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 73.60, top5 = 57.07, top10 = 50.78, top15 = 47.27.
+PHY-3001 : End congestion estimation; 0.462205s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (101.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.958725s wall, 0.937500s user + 0.031250s system = 0.968750s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000478718
+PHY-3002 : Step(274): len = 649205, overlap = 93.9062
+PHY-3002 : Step(275): len = 649398, overlap = 93.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000957436
+PHY-3002 : Step(276): len = 649545, overlap = 93.5625
+PHY-3002 : Step(277): len = 650171, overlap = 93.2812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00183245
+PHY-3002 : Step(278): len = 650445, overlap = 93.375
+PHY-3002 : Step(279): len = 651041, overlap = 92.8125
+PHY-3001 : Final: Len = 651041, Over = 92.8125
+PHY-3001 : End incremental placement; 5.124914s wall, 5.250000s user + 0.265625s system = 5.515625s CPU (107.6%)
+
+OPT-1001 : Total overflow 415.22 peak overflow 3.31
+OPT-1001 : End high-fanout net optimization; 8.383742s wall, 9.125000s user + 0.296875s system = 9.421875s CPU (112.4%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 708, peak = 732.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16959/20820.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741384, over cnt = 2959(8%), over = 9899, worst = 24
+PHY-1002 : len = 792192, over cnt = 2017(5%), over = 5041, worst = 20
+PHY-1002 : len = 826272, over cnt = 945(2%), over = 2301, worst = 18
+PHY-1002 : len = 860464, over cnt = 102(0%), over = 180, worst = 12
+PHY-1002 : len = 862656, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.886171s wall, 2.625000s user + 0.015625s system = 2.640625s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 57.74, top5 = 50.40, top10 = 46.60, top15 = 44.18.
+OPT-1001 : End congestion update; 2.140032s wall, 2.875000s user + 0.015625s system = 2.890625s CPU (135.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.797022s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.0%)
+
+OPT-0007 : Start: WNS -44 TNS -88 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 122 cells processed and 19150 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 44 cells processed and 2950 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 350 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 800 slack improved
+OPT-1001 : End bottleneck based optimization; 3.350584s wall, 4.093750s user + 0.015625s system = 4.109375s CPU (122.6%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 689, peak = 732.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17000/20826.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863024, over cnt = 91(0%), over = 126, worst = 4
+PHY-1002 : len = 862352, over cnt = 51(0%), over = 63, worst = 3
+PHY-1002 : len = 862504, over cnt = 34(0%), over = 41, worst = 3
+PHY-1002 : len = 863128, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 863160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.747444s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (112.9%)
+
+PHY-1001 : Congestion index: top1 = 58.02, top5 = 50.57, top10 = 46.67, top15 = 44.21.
+OPT-1001 : End congestion update; 1.035270s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (108.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20648 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.805323s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.0%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 25 cells processed and 8700 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.963752s wall, 2.015625s user + 0.015625s system = 2.031250s CPU (103.4%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 693, peak = 732.
+OPT-1001 : End physical optimization; 15.439105s wall, 17.062500s user + 0.359375s system = 17.421875s CPU (112.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7747 LUT to BLE ...
+SYN-4008 : Packed 7747 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6143 remaining SEQ's ...
+SYN-4005 : Packed 3846 SEQ with LUT/SLICE
+SYN-4006 : 1046 single LUT's are left
+SYN-4006 : 2297 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10044/13899 primitive instances ...
+PHY-3001 : End packing; 1.578835s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6759 instances
+RUN-1001 : 3305 mslices, 3306 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17819 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9968 nets have 2 pins
+RUN-1001 : 6496 nets have [3 - 5] pins
+RUN-1001 : 736 nets have [6 - 10] pins
+RUN-1001 : 285 nets have [11 - 20] pins
+RUN-1001 : 301 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6757 instances, 6611 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3484 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 662917, Over = 221
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7745/17819.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 814448, over cnt = 1970(5%), over = 3199, worst = 9
+PHY-1002 : len = 823336, over cnt = 1236(3%), over = 1711, worst = 9
+PHY-1002 : len = 836648, over cnt = 408(1%), over = 557, worst = 7
+PHY-1002 : len = 842680, over cnt = 156(0%), over = 216, worst = 5
+PHY-1002 : len = 846736, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.676556s wall, 2.328125s user + 0.031250s system = 2.359375s CPU (140.7%)
+
+PHY-1001 : Congestion index: top1 = 57.78, top5 = 50.51, top10 = 46.62, top15 = 44.09.
+PHY-3001 : End congestion estimation; 2.061389s wall, 2.718750s user + 0.031250s system = 2.750000s CPU (133.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71298, tnet num: 17641, tinst num: 6757, tnode num: 93557, tedge num: 118513.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.569750s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.5%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 607 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.452213s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.41492e-05
+PHY-3002 : Step(280): len = 650707, overlap = 229.5
+PHY-3002 : Step(281): len = 644067, overlap = 231.25
+PHY-3002 : Step(282): len = 639649, overlap = 229
+PHY-3002 : Step(283): len = 636262, overlap = 237.75
+PHY-3002 : Step(284): len = 633236, overlap = 242.5
+PHY-3002 : Step(285): len = 630116, overlap = 246.25
+PHY-3002 : Step(286): len = 627211, overlap = 247.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000108298
+PHY-3002 : Step(287): len = 630605, overlap = 239.5
+PHY-3002 : Step(288): len = 632858, overlap = 237
+PHY-3002 : Step(289): len = 633449, overlap = 238.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000216597
+PHY-3002 : Step(290): len = 641261, overlap = 222.5
+PHY-3002 : Step(291): len = 649359, overlap = 210.75
+PHY-3002 : Step(292): len = 648684, overlap = 213
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.371979s wall, 0.328125s user + 0.656250s system = 0.984375s CPU (264.6%)
+
+PHY-3001 : Trial Legalized: Len = 733375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 968/17819.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841912, over cnt = 2601(7%), over = 4357, worst = 9
+PHY-1002 : len = 857592, over cnt = 1666(4%), over = 2453, worst = 7
+PHY-1002 : len = 876264, over cnt = 704(2%), over = 1029, worst = 7
+PHY-1002 : len = 886568, over cnt = 292(0%), over = 434, worst = 7
+PHY-1002 : len = 894032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.354229s wall, 3.406250s user + 0.078125s system = 3.484375s CPU (148.0%)
+
+PHY-1001 : Congestion index: top1 = 56.25, top5 = 50.14, top10 = 47.02, top15 = 44.93.
+PHY-3001 : End congestion estimation; 2.801213s wall, 3.859375s user + 0.078125s system = 3.937500s CPU (140.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.835039s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000163731
+PHY-3002 : Step(293): len = 705969, overlap = 40.25
+PHY-3002 : Step(294): len = 689533, overlap = 65.25
+PHY-3002 : Step(295): len = 675893, overlap = 94.25
+PHY-3002 : Step(296): len = 667776, overlap = 113
+PHY-3002 : Step(297): len = 662852, overlap = 123.25
+PHY-3002 : Step(298): len = 659841, overlap = 136.75
+PHY-3002 : Step(299): len = 658251, overlap = 145.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000327461
+PHY-3002 : Step(300): len = 662347, overlap = 140.25
+PHY-3002 : Step(301): len = 666598, overlap = 137.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000654923
+PHY-3002 : Step(302): len = 671053, overlap = 132.75
+PHY-3002 : Step(303): len = 680771, overlap = 128.25
+PHY-3002 : Step(304): len = 681476, overlap = 125.75
+PHY-3002 : Step(305): len = 681779, overlap = 132.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034571s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.4%)
+
+PHY-3001 : Legalized: Len = 712068, Over = 0
+PHY-3001 : Spreading special nets. 386 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.101648s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (92.2%)
+
+PHY-3001 : 564 instances has been re-located, deltaX = 194, deltaY = 328, maxDist = 3.
+PHY-3001 : Final: Len = 720905, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71298, tnet num: 17641, tinst num: 6760, tnode num: 93557, tedge num: 118513.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.815060s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.7%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 628 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3685/17819.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838920, over cnt = 2404(6%), over = 3969, worst = 8
+PHY-1002 : len = 852648, over cnt = 1441(4%), over = 2163, worst = 7
+PHY-1002 : len = 871904, over cnt = 493(1%), over = 676, worst = 6
+PHY-1002 : len = 881008, over cnt = 76(0%), over = 100, worst = 4
+PHY-1002 : len = 882776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.938522s wall, 2.796875s user + 0.031250s system = 2.828125s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.49, top15 = 43.38.
+PHY-1001 : End incremental global routing; 2.313704s wall, 3.156250s user + 0.031250s system = 3.187500s CPU (137.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.826986s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6668 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 724327
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16200/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886488, over cnt = 75(0%), over = 85, worst = 3
+PHY-1002 : len = 886536, over cnt = 37(0%), over = 38, worst = 2
+PHY-1002 : len = 886880, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 886888, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 886936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.755788s wall, 0.781250s user + 0.031250s system = 0.812500s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.57, top15 = 43.47.
+PHY-3001 : End congestion estimation; 1.057961s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (104.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71487, tnet num: 17671, tinst num: 6779, tnode num: 93791, tedge num: 118765.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.821361s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.4%)
+
+RUN-1004 : used memory is 649 MB, reserved memory is 648 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.020856s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(306): len = 724327, overlap = 0
+PHY-3002 : Step(307): len = 724327, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.125434s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.7%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.57, top15 = 43.47.
+PHY-3001 : End congestion estimation; 0.440705s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.820696s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000460749
+PHY-3002 : Step(308): len = 724327, overlap = 0
+PHY-3002 : Step(309): len = 724327, overlap = 0
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005770s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 724301, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061195s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.1%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 724319, Over = 0
+PHY-3001 : End incremental placement; 5.792716s wall, 5.812500s user + 0.031250s system = 5.843750s CPU (100.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.395307s wall, 10.250000s user + 0.062500s system = 10.312500s CPU (109.8%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16207/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 887064, over cnt = 13(0%), over = 17, worst = 3
+PHY-1002 : len = 887056, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 887192, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 887208, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.560671s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (105.9%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.56, top15 = 43.47.
+OPT-1001 : End congestion update; 0.874946s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.685105s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.3%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730011, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059718s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%)
+
+PHY-3001 : 37 instances has been re-located, deltaX = 15, deltaY = 29, maxDist = 2.
+PHY-3001 : Final: Len = 730717, Over = 0
+PHY-3001 : End incremental legalization; 0.361096s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (125.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 52 cells processed and 20554 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730601, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058057s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.7%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 7, deltaY = 12, maxDist = 4.
+PHY-3001 : Final: Len = 730927, Over = 0
+PHY-3001 : End incremental legalization; 0.361446s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (129.7%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 26 cells processed and 2806 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730923, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057145s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.0%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 6, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 731139, Over = 0
+PHY-3001 : End incremental legalization; 0.356482s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (153.4%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 1210 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 731762, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058832s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 731784, Over = 0
+PHY-3001 : End incremental legalization; 0.364419s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.6%)
+
+OPT-0007 : Iter 4: improved WNS 71 TNS 0 NUM_FEPS 0 with 5 cells processed and 500 slack improved
+OPT-1001 : End bottleneck based optimization; 3.525450s wall, 4.046875s user + 0.015625s system = 4.062500s CPU (115.2%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15820/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 894680, over cnt = 154(0%), over = 205, worst = 5
+PHY-1002 : len = 894944, over cnt = 87(0%), over = 106, worst = 5
+PHY-1002 : len = 895392, over cnt = 21(0%), over = 23, worst = 2
+PHY-1002 : len = 895584, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 895800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.770544s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (117.6%)
+
+PHY-1001 : Congestion index: top1 = 54.44, top5 = 48.72, top10 = 45.62, top15 = 43.54.
+OPT-1001 : End congestion update; 1.068672s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (112.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.690649s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.8%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 732158, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057256s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.2%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 10, deltaY = 9, maxDist = 5.
+PHY-3001 : Final: Len = 732786, Over = 0
+PHY-3001 : End incremental legalization; 0.360551s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 2650 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.242873s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (108.0%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 734.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.685844s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (98.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16144/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896584, over cnt = 40(0%), over = 46, worst = 3
+PHY-1002 : len = 896504, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 896552, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 896808, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.736146s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.689133s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.344828
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 732786, Over = 0
+PHY-3001 : End spreading; 0.056334s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.9%)
+
+PHY-3001 : Final: Len = 732786, Over = 0
+PHY-3001 : End incremental legalization; 0.362105s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.687454s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.0%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126907s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.5%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+OPT-1001 : End congestion update; 0.424402s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.724556s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 732770, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.055587s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (112.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 732786, Over = 0
+PHY-3001 : End incremental legalization; 0.372284s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (117.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.661165s wall, 1.812500s user + 0.015625s system = 1.828125s CPU (110.1%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127098s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.3%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+OPT-1001 : End congestion update; 0.424804s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.685458s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.3%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.264118s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 734.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.683139s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 734.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.689835s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.7%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.123917s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (100.9%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+RUN-1001 : End congestion update; 0.426152s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.0%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.119209s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.1%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 734.
+OPT-1001 : End physical optimization; 25.545330s wall, 27.390625s user + 0.125000s system = 27.515625s CPU (107.7%)
+
+RUN-1003 : finish command "place" in 68.947115s wall, 96.765625s user + 5.437500s system = 102.203125s CPU (148.2%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 634 MB, peak memory is 734 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.654928s wall, 2.843750s user + 0.046875s system = 2.890625s CPU (174.7%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 635 MB, peak memory is 734 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6787 instances
+RUN-1001 : 3319 mslices, 3317 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17854 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9976 nets have 2 pins
+RUN-1001 : 6502 nets have [3 - 5] pins
+RUN-1001 : 744 nets have [6 - 10] pins
+RUN-1001 : 289 nets have [11 - 20] pins
+RUN-1001 : 314 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71537, tnet num: 17676, tinst num: 6785, tnode num: 93861, tedge num: 118841.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.536287s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.7%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 655 MB, peak memory is 734 MB
+PHY-1001 : 3319 mslices, 3317 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 830312, over cnt = 2619(7%), over = 4410, worst = 9
+PHY-1002 : len = 846104, over cnt = 1755(4%), over = 2653, worst = 8
+PHY-1002 : len = 862128, over cnt = 971(2%), over = 1435, worst = 6
+PHY-1002 : len = 885176, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 885400, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.789895s wall, 3.843750s user + 0.046875s system = 3.890625s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 54.72, top5 = 48.76, top10 = 45.46, top15 = 43.38.
+PHY-1001 : End global routing; 3.105756s wall, 4.171875s user + 0.046875s system = 4.218750s CPU (135.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 707, peak = 734.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 984, reserve = 983, peak = 984.
+PHY-1001 : End build detailed router design. 3.997453s wall, 3.984375s user + 0.015625s system = 4.000000s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266240, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.258921s wall, 5.250000s user + 0.000000s system = 5.250000s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266296, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.426435s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.9%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1018, peak = 1018.
+PHY-1001 : End phase 1; 5.698389s wall, 5.687500s user + 0.000000s system = 5.687500s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24995e+06, over cnt = 1702(0%), over = 1706, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1031, peak = 1032.
+PHY-1001 : End initial routed; 24.584457s wall, 54.484375s user + 0.281250s system = 54.765625s CPU (222.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16776(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.947 | -0.947 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.117651s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1045, peak = 1045.
+PHY-1001 : End phase 2; 27.702170s wall, 57.593750s user + 0.296875s system = 57.890625s CPU (209.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.133607s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.3%)
+
+PHY-1022 : len = 2.24995e+06, over cnt = 1703(0%), over = 1707, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.384525s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.22148e+06, over cnt = 644(0%), over = 645, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.209916s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (161.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.21816e+06, over cnt = 118(0%), over = 118, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.640384s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (163.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.21888e+06, over cnt = 27(0%), over = 27, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.272031s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (132.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2193e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.237605s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (118.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.219250s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.235133s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.277681s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (101.3%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.173256s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.173137s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.204350s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.224476s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (111.4%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.296685s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.21933e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.169870s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.21931e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.159432s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16776(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.131141s wall, 3.125000s user + 0.000000s system = 3.125000s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 508 feed throughs used by 381 nets
+PHY-1001 : End commit to database; 2.153644s wall, 2.109375s user + 0.031250s system = 2.140625s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1143, reserve = 1147, peak = 1143.
+PHY-1001 : End phase 3; 10.565801s wall, 11.796875s user + 0.046875s system = 11.843750s CPU (112.1%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.136837s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.8%)
+
+PHY-1022 : len = 2.21931e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.374880s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.805ns, -0.805ns, 1}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2193e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.164897s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (104.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16776(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.947 | -0.947 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.145315s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1156, peak = 1152.
+PHY-1001 : End phase 4; 3.730427s wall, 3.734375s user + 0.000000s system = 3.734375s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.2193e+06
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1156, peak = 1152.
+PHY-1001 : End export database. 0.057195s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.0%)
+
+PHY-1001 : End detail routing; 52.136879s wall, 83.234375s user + 0.359375s system = 83.593750s CPU (160.3%)
+
+RUN-1003 : finish command "route" in 57.790370s wall, 89.906250s user + 0.437500s system = 90.343750s CPU (156.3%)
+
+RUN-1004 : used memory is 1080 MB, reserved memory is 1082 MB, peak memory is 1152 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10181 out of 19600 51.94%
+#reg 9426 out of 19600 48.09%
+#le 12449
+ #lut only 3023 out of 12449 24.28%
+ #reg only 2268 out of 12449 18.22%
+ #lut® 7158 out of 12449 57.50%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1783
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1374
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1268
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 960
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg0_syn_140.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_381.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P11 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P119 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P140 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12449 |9154 |1027 |9460 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |542 |448 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |102 |4 |94 |4 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |6 |0 |0 |
+| U_crc16_24b |crc16_24b |34 |34 |0 |19 |0 |0 |
+| exdev_ctl_a |exdev_ctl |763 |384 |96 |581 |0 |0 |
+| u_ADconfig |AD_config |189 |108 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |256 |165 |71 |118 |0 |0 |
+| exdev_ctl_b |exdev_ctl |744 |356 |96 |567 |0 |0 |
+| u_ADconfig |AD_config |176 |94 |25 |131 |0 |0 |
+| u_gen_sp |gen_sp |251 |151 |71 |119 |0 |0 |
+| sampling_fe_a |sampling_fe |2985 |2409 |306 |2065 |25 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |165 |117 |17 |136 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2790 |2274 |289 |1899 |25 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2371 |1946 |253 |1556 |22 |0 |
+| channelPart |channel_part_8478 |145 |141 |3 |137 |0 |0 |
+| fifo_adc |fifo_adc |52 |43 |9 |37 |0 |0 |
+| ram_switch |ram_switch |1860 |1503 |197 |1163 |0 |0 |
+| adc_addr_gen |adc_addr_gen |220 |193 |27 |116 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |982 |655 |170 |677 |0 |0 |
+| ram_switch_state |ram_switch_state |658 |655 |0 |370 |0 |0 |
+| read_ram_i |read_ram |283 |238 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |232 |192 |40 |153 |0 |0 |
+| read_ram_data |read_ram_data |50 |45 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |321 |235 |36 |276 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3240 |2551 |349 |2052 |25 |1 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |182 |102 |17 |152 |0 |0 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_sort |sort_rev |3022 |2433 |332 |1864 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2599 |2106 |290 |1505 |22 |1 |
+| channelPart |channel_part_8478 |124 |120 |3 |119 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 |
+| ram_switch |ram_switch |2021 |1673 |197 |1103 |0 |0 |
+| adc_addr_gen |adc_addr_gen |205 |178 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |7 |0 |0 |
+| insert |insert |969 |648 |170 |671 |0 |0 |
+| ram_switch_state |ram_switch_state |847 |847 |0 |327 |0 |0 |
+| read_ram_i |read_ram_rev |363 |244 |81 |211 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |298 |213 |73 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |65 |31 |8 |46 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9914
+ #2 2 4230
+ #3 3 1690
+ #4 4 579
+ #5 5-10 783
+ #6 11-50 550
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.014560s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (174.5%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1083 MB, peak memory is 1152 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71537, tnet num: 17676, tinst num: 6785, tnode num: 93861, tedge num: 118841.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.537592s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.6%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1088 MB, peak memory is 1152 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.397831s wall, 1.359375s user + 0.031250s system = 1.390625s CPU (99.5%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1091 MB, peak memory is 1152 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6785
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17854, pip num: 166832
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 508
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 466630 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.442253s wall, 64.656250s user + 0.093750s system = 64.750000s CPU (685.7%)
+
+RUN-1004 : used memory is 1246 MB, reserved memory is 1246 MB, peak memory is 1362 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_153107.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_154137.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_154137.log
new file mode 100644
index 0000000..347ae2f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_154137.log
@@ -0,0 +1,1990 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:41:38 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.204955s wall, 2.109375s user + 0.093750s system = 2.203125s CPU (99.9%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 315 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17999 instances
+RUN-0007 : 7674 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20577 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13091 nets have 2 pins
+RUN-1001 : 6451 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17997 instances, 7674 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.157526s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (99.9%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 514 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.931582s wall, 1.859375s user + 0.062500s system = 1.921875s CPU (99.5%)
+
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.97121e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17997.
+PHY-3001 : Level 1 #clusters 2088.
+PHY-3001 : End clustering; 0.125798s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (111.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31482e+06, overlap = 442.125
+PHY-3002 : Step(2): len = 1.22899e+06, overlap = 487.75
+PHY-3002 : Step(3): len = 877442, overlap = 563.5
+PHY-3002 : Step(4): len = 801289, overlap = 594.094
+PHY-3002 : Step(5): len = 643593, overlap = 744.188
+PHY-3002 : Step(6): len = 571466, overlap = 799.562
+PHY-3002 : Step(7): len = 487557, overlap = 867.25
+PHY-3002 : Step(8): len = 441949, overlap = 922.188
+PHY-3002 : Step(9): len = 403126, overlap = 985.781
+PHY-3002 : Step(10): len = 365940, overlap = 1048.38
+PHY-3002 : Step(11): len = 326618, overlap = 1111.94
+PHY-3002 : Step(12): len = 298627, overlap = 1133.25
+PHY-3002 : Step(13): len = 276167, overlap = 1203.5
+PHY-3002 : Step(14): len = 244447, overlap = 1274.78
+PHY-3002 : Step(15): len = 231999, overlap = 1339.09
+PHY-3002 : Step(16): len = 209427, overlap = 1358.12
+PHY-3002 : Step(17): len = 194807, overlap = 1344.31
+PHY-3002 : Step(18): len = 171058, overlap = 1396.69
+PHY-3002 : Step(19): len = 160579, overlap = 1414.75
+PHY-3002 : Step(20): len = 149083, overlap = 1445.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.24902e-06
+PHY-3002 : Step(21): len = 150445, overlap = 1412.44
+PHY-3002 : Step(22): len = 185898, overlap = 1262.78
+PHY-3002 : Step(23): len = 197759, overlap = 1218.62
+PHY-3002 : Step(24): len = 204132, overlap = 1151.09
+PHY-3002 : Step(25): len = 202527, overlap = 1110.5
+PHY-3002 : Step(26): len = 201904, overlap = 1091.72
+PHY-3002 : Step(27): len = 199160, overlap = 1089.28
+PHY-3002 : Step(28): len = 196040, overlap = 1086.28
+PHY-3002 : Step(29): len = 195219, overlap = 1083.72
+PHY-3002 : Step(30): len = 194405, overlap = 1067.31
+PHY-3002 : Step(31): len = 193251, overlap = 1053.19
+PHY-3002 : Step(32): len = 191212, overlap = 1036.78
+PHY-3002 : Step(33): len = 190542, overlap = 1032.38
+PHY-3002 : Step(34): len = 188674, overlap = 1039.62
+PHY-3002 : Step(35): len = 186799, overlap = 1053.97
+PHY-3002 : Step(36): len = 185187, overlap = 1058.19
+PHY-3002 : Step(37): len = 182828, overlap = 1041.06
+PHY-3002 : Step(38): len = 182581, overlap = 1042.16
+PHY-3002 : Step(39): len = 181592, overlap = 1032.88
+PHY-3002 : Step(40): len = 181024, overlap = 1039.5
+PHY-3002 : Step(41): len = 179468, overlap = 1036.16
+PHY-3002 : Step(42): len = 178402, overlap = 1037.28
+PHY-3002 : Step(43): len = 177137, overlap = 1045
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.49804e-06
+PHY-3002 : Step(44): len = 181367, overlap = 1036.12
+PHY-3002 : Step(45): len = 192904, overlap = 1044.75
+PHY-3002 : Step(46): len = 196497, overlap = 1012.78
+PHY-3002 : Step(47): len = 200859, overlap = 1000.84
+PHY-3002 : Step(48): len = 203251, overlap = 939.531
+PHY-3002 : Step(49): len = 205334, overlap = 910.094
+PHY-3002 : Step(50): len = 204884, overlap = 903.562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.99609e-06
+PHY-3002 : Step(51): len = 213263, overlap = 861.562
+PHY-3002 : Step(52): len = 228954, overlap = 807.688
+PHY-3002 : Step(53): len = 238486, overlap = 770.875
+PHY-3002 : Step(54): len = 246463, overlap = 763.688
+PHY-3002 : Step(55): len = 249433, overlap = 755.625
+PHY-3002 : Step(56): len = 251699, overlap = 757.75
+PHY-3002 : Step(57): len = 249892, overlap = 753.781
+PHY-3002 : Step(58): len = 250506, overlap = 761.875
+PHY-3002 : Step(59): len = 249667, overlap = 747.125
+PHY-3002 : Step(60): len = 248533, overlap = 743.781
+PHY-3002 : Step(61): len = 247500, overlap = 743.656
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.99217e-06
+PHY-3002 : Step(62): len = 262401, overlap = 700.125
+PHY-3002 : Step(63): len = 276907, overlap = 626.125
+PHY-3002 : Step(64): len = 282073, overlap = 595.25
+PHY-3002 : Step(65): len = 286336, overlap = 590.688
+PHY-3002 : Step(66): len = 287680, overlap = 589.844
+PHY-3002 : Step(67): len = 288593, overlap = 569.406
+PHY-3002 : Step(68): len = 287280, overlap = 584.812
+PHY-3002 : Step(69): len = 288285, overlap = 563.188
+PHY-3002 : Step(70): len = 288513, overlap = 566.469
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.99843e-05
+PHY-3002 : Step(71): len = 303595, overlap = 493.781
+PHY-3002 : Step(72): len = 317353, overlap = 472.062
+PHY-3002 : Step(73): len = 323219, overlap = 463.5
+PHY-3002 : Step(74): len = 328732, overlap = 429.625
+PHY-3002 : Step(75): len = 330479, overlap = 375.875
+PHY-3002 : Step(76): len = 333540, overlap = 370.688
+PHY-3002 : Step(77): len = 336474, overlap = 361.844
+PHY-3002 : Step(78): len = 338100, overlap = 365.812
+PHY-3002 : Step(79): len = 337706, overlap = 381.094
+PHY-3002 : Step(80): len = 337809, overlap = 393.812
+PHY-3002 : Step(81): len = 336881, overlap = 385.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.99687e-05
+PHY-3002 : Step(82): len = 352080, overlap = 394.969
+PHY-3002 : Step(83): len = 365108, overlap = 391.531
+PHY-3002 : Step(84): len = 367421, overlap = 362.344
+PHY-3002 : Step(85): len = 368559, overlap = 340.562
+PHY-3002 : Step(86): len = 370693, overlap = 330.125
+PHY-3002 : Step(87): len = 373419, overlap = 317.594
+PHY-3002 : Step(88): len = 373946, overlap = 310.5
+PHY-3002 : Step(89): len = 376010, overlap = 298.969
+PHY-3002 : Step(90): len = 379843, overlap = 298.688
+PHY-3002 : Step(91): len = 382828, overlap = 298.969
+PHY-3002 : Step(92): len = 380626, overlap = 277.781
+PHY-3002 : Step(93): len = 381229, overlap = 271.594
+PHY-3002 : Step(94): len = 382691, overlap = 269.969
+PHY-3002 : Step(95): len = 381718, overlap = 265.719
+PHY-3002 : Step(96): len = 379948, overlap = 272.625
+PHY-3002 : Step(97): len = 380777, overlap = 280.469
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.99374e-05
+PHY-3002 : Step(98): len = 395240, overlap = 269.219
+PHY-3002 : Step(99): len = 406724, overlap = 248.375
+PHY-3002 : Step(100): len = 404855, overlap = 240.062
+PHY-3002 : Step(101): len = 406641, overlap = 240.719
+PHY-3002 : Step(102): len = 411999, overlap = 235.719
+PHY-3002 : Step(103): len = 414805, overlap = 241.594
+PHY-3002 : Step(104): len = 410284, overlap = 230.375
+PHY-3002 : Step(105): len = 409999, overlap = 226.906
+PHY-3002 : Step(106): len = 411548, overlap = 232.656
+PHY-3002 : Step(107): len = 413336, overlap = 233.375
+PHY-3002 : Step(108): len = 409116, overlap = 226.5
+PHY-3002 : Step(109): len = 409127, overlap = 230.875
+PHY-3002 : Step(110): len = 410415, overlap = 231.156
+PHY-3002 : Step(111): len = 411513, overlap = 230.625
+PHY-3002 : Step(112): len = 408239, overlap = 223.094
+PHY-3002 : Step(113): len = 407833, overlap = 223.125
+PHY-3002 : Step(114): len = 409174, overlap = 217.906
+PHY-3002 : Step(115): len = 411227, overlap = 228.531
+PHY-3002 : Step(116): len = 408999, overlap = 213.5
+PHY-3002 : Step(117): len = 409449, overlap = 219.875
+PHY-3002 : Step(118): len = 410169, overlap = 215.5
+PHY-3002 : Step(119): len = 410805, overlap = 214.875
+PHY-3002 : Step(120): len = 408854, overlap = 215.875
+PHY-3002 : Step(121): len = 409142, overlap = 220.906
+PHY-3002 : Step(122): len = 410507, overlap = 219.531
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000159875
+PHY-3002 : Step(123): len = 422471, overlap = 214.219
+PHY-3002 : Step(124): len = 430979, overlap = 210.375
+PHY-3002 : Step(125): len = 429083, overlap = 203.688
+PHY-3002 : Step(126): len = 429864, overlap = 209.094
+PHY-3002 : Step(127): len = 435322, overlap = 196.594
+PHY-3002 : Step(128): len = 439233, overlap = 196.219
+PHY-3002 : Step(129): len = 436326, overlap = 190.75
+PHY-3002 : Step(130): len = 437063, overlap = 192.219
+PHY-3002 : Step(131): len = 439077, overlap = 191.781
+PHY-3002 : Step(132): len = 440717, overlap = 200.656
+PHY-3002 : Step(133): len = 439312, overlap = 191.438
+PHY-3002 : Step(134): len = 439448, overlap = 190.969
+PHY-3002 : Step(135): len = 440847, overlap = 195.438
+PHY-3002 : Step(136): len = 441876, overlap = 194.25
+PHY-3002 : Step(137): len = 440199, overlap = 198.906
+PHY-3002 : Step(138): len = 440008, overlap = 198.156
+PHY-3002 : Step(139): len = 440753, overlap = 195.312
+PHY-3002 : Step(140): len = 441023, overlap = 196.5
+PHY-3002 : Step(141): len = 440351, overlap = 192.375
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000305382
+PHY-3002 : Step(142): len = 449315, overlap = 197.531
+PHY-3002 : Step(143): len = 457366, overlap = 182.719
+PHY-3002 : Step(144): len = 457809, overlap = 176.406
+PHY-3002 : Step(145): len = 458754, overlap = 169.188
+PHY-3002 : Step(146): len = 462014, overlap = 164.438
+PHY-3002 : Step(147): len = 464354, overlap = 159.375
+PHY-3002 : Step(148): len = 462604, overlap = 153.406
+PHY-3002 : Step(149): len = 462283, overlap = 159.031
+PHY-3002 : Step(150): len = 465311, overlap = 154.625
+PHY-3002 : Step(151): len = 468198, overlap = 156.531
+PHY-3002 : Step(152): len = 465817, overlap = 158.094
+PHY-3002 : Step(153): len = 465593, overlap = 161.281
+PHY-3002 : Step(154): len = 468457, overlap = 168.719
+PHY-3002 : Step(155): len = 470336, overlap = 168.094
+PHY-3002 : Step(156): len = 468420, overlap = 167.719
+PHY-3002 : Step(157): len = 468050, overlap = 168.719
+PHY-3002 : Step(158): len = 469452, overlap = 164
+PHY-3002 : Step(159): len = 470189, overlap = 167.719
+PHY-3002 : Step(160): len = 469102, overlap = 174.219
+PHY-3002 : Step(161): len = 469244, overlap = 178.719
+PHY-3002 : Step(162): len = 470940, overlap = 175.594
+PHY-3002 : Step(163): len = 471904, overlap = 176.812
+PHY-3002 : Step(164): len = 469847, overlap = 179.938
+PHY-3002 : Step(165): len = 469559, overlap = 178
+PHY-3002 : Step(166): len = 471194, overlap = 180.062
+PHY-3002 : Step(167): len = 472425, overlap = 183.031
+PHY-3002 : Step(168): len = 470887, overlap = 183.531
+PHY-3002 : Step(169): len = 470751, overlap = 183.625
+PHY-3002 : Step(170): len = 471647, overlap = 189.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000577667
+PHY-3002 : Step(171): len = 478244, overlap = 179.031
+PHY-3002 : Step(172): len = 486798, overlap = 168.5
+PHY-3002 : Step(173): len = 490380, overlap = 163.594
+PHY-3002 : Step(174): len = 493506, overlap = 161.75
+PHY-3002 : Step(175): len = 497416, overlap = 161.156
+PHY-3002 : Step(176): len = 499972, overlap = 161.844
+PHY-3002 : Step(177): len = 497979, overlap = 155.375
+PHY-3002 : Step(178): len = 497497, overlap = 149.844
+PHY-3002 : Step(179): len = 498991, overlap = 157.469
+PHY-3002 : Step(180): len = 499697, overlap = 160.938
+PHY-3002 : Step(181): len = 498383, overlap = 160.312
+PHY-3002 : Step(182): len = 498043, overlap = 161.656
+PHY-3002 : Step(183): len = 499066, overlap = 167.625
+PHY-3002 : Step(184): len = 499688, overlap = 168.281
+PHY-3002 : Step(185): len = 498730, overlap = 165.031
+PHY-3002 : Step(186): len = 498595, overlap = 159.719
+PHY-3002 : Step(187): len = 500150, overlap = 163.125
+PHY-3002 : Step(188): len = 501097, overlap = 167.281
+PHY-3002 : Step(189): len = 500562, overlap = 157.219
+PHY-3002 : Step(190): len = 500595, overlap = 155.188
+PHY-3002 : Step(191): len = 501482, overlap = 166.719
+PHY-3002 : Step(192): len = 501807, overlap = 167.312
+PHY-3002 : Step(193): len = 501249, overlap = 162.062
+PHY-3002 : Step(194): len = 501264, overlap = 158.719
+PHY-3002 : Step(195): len = 501954, overlap = 161.469
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00107028
+PHY-3002 : Step(196): len = 505721, overlap = 159.406
+PHY-3002 : Step(197): len = 511338, overlap = 150.469
+PHY-3002 : Step(198): len = 512611, overlap = 145.219
+PHY-3002 : Step(199): len = 513528, overlap = 148.594
+PHY-3002 : Step(200): len = 515100, overlap = 140.438
+PHY-3002 : Step(201): len = 515955, overlap = 138.375
+PHY-3002 : Step(202): len = 515774, overlap = 136.938
+PHY-3002 : Step(203): len = 515829, overlap = 138.25
+PHY-3002 : Step(204): len = 516843, overlap = 133.812
+PHY-3002 : Step(205): len = 517548, overlap = 138
+PHY-3002 : Step(206): len = 517250, overlap = 143.438
+PHY-3002 : Step(207): len = 517168, overlap = 143.438
+PHY-3002 : Step(208): len = 517392, overlap = 137.031
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013571s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (115.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 689056, over cnt = 1533(4%), over = 7153, worst = 41
+PHY-1001 : End global iterations; 0.693694s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (144.2%)
+
+PHY-1001 : Congestion index: top1 = 82.74, top5 = 61.17, top10 = 51.75, top15 = 46.08.
+PHY-3001 : End congestion estimation; 0.920826s wall, 1.187500s user + 0.031250s system = 1.218750s CPU (132.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.832797s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000125154
+PHY-3002 : Step(209): len = 623885, overlap = 82.4062
+PHY-3002 : Step(210): len = 623553, overlap = 75.5312
+PHY-3002 : Step(211): len = 616349, overlap = 71.1562
+PHY-3002 : Step(212): len = 611700, overlap = 70.5938
+PHY-3002 : Step(213): len = 611422, overlap = 66.375
+PHY-3002 : Step(214): len = 612892, overlap = 61.2812
+PHY-3002 : Step(215): len = 608600, overlap = 53.5312
+PHY-3002 : Step(216): len = 605273, overlap = 47.8438
+PHY-3002 : Step(217): len = 603735, overlap = 46.4688
+PHY-3002 : Step(218): len = 601618, overlap = 47.125
+PHY-3002 : Step(219): len = 598637, overlap = 44.0625
+PHY-3002 : Step(220): len = 596702, overlap = 40
+PHY-3002 : Step(221): len = 595990, overlap = 36.5
+PHY-3002 : Step(222): len = 596392, overlap = 40.8438
+PHY-3002 : Step(223): len = 597475, overlap = 40.1875
+PHY-3002 : Step(224): len = 597067, overlap = 42.8438
+PHY-3002 : Step(225): len = 596122, overlap = 49.625
+PHY-3002 : Step(226): len = 596198, overlap = 55
+PHY-3002 : Step(227): len = 594956, overlap = 58.5938
+PHY-3002 : Step(228): len = 593514, overlap = 60.4688
+PHY-3002 : Step(229): len = 592558, overlap = 58.1875
+PHY-3002 : Step(230): len = 592532, overlap = 57.75
+PHY-3002 : Step(231): len = 591392, overlap = 60.3125
+PHY-3002 : Step(232): len = 589952, overlap = 59.6562
+PHY-3002 : Step(233): len = 588119, overlap = 59.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000250307
+PHY-3002 : Step(234): len = 592144, overlap = 56.4062
+PHY-3002 : Step(235): len = 594802, overlap = 56.1562
+PHY-3002 : Step(236): len = 596959, overlap = 55.9375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000455054
+PHY-3002 : Step(237): len = 601387, overlap = 56.2812
+PHY-3002 : Step(238): len = 614744, overlap = 50.125
+PHY-3002 : Step(239): len = 620060, overlap = 47.375
+PHY-3002 : Step(240): len = 622850, overlap = 45.9375
+PHY-3002 : Step(241): len = 626338, overlap = 42.8125
+PHY-3002 : Step(242): len = 627959, overlap = 38.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 56/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708152, over cnt = 2683(7%), over = 12234, worst = 42
+PHY-1001 : End global iterations; 1.520404s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (130.5%)
+
+PHY-1001 : Congestion index: top1 = 86.06, top5 = 66.82, top10 = 58.27, top15 = 53.06.
+PHY-3001 : End congestion estimation; 1.789579s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (125.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.877734s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000110034
+PHY-3002 : Step(243): len = 621923, overlap = 248.969
+PHY-3002 : Step(244): len = 621790, overlap = 189.781
+PHY-3002 : Step(245): len = 616790, overlap = 176.312
+PHY-3002 : Step(246): len = 612321, overlap = 165.875
+PHY-3002 : Step(247): len = 608613, overlap = 149.688
+PHY-3002 : Step(248): len = 605249, overlap = 138.281
+PHY-3002 : Step(249): len = 602192, overlap = 131.062
+PHY-3002 : Step(250): len = 598107, overlap = 123.875
+PHY-3002 : Step(251): len = 595706, overlap = 114.562
+PHY-3002 : Step(252): len = 594317, overlap = 113.844
+PHY-3002 : Step(253): len = 590625, overlap = 115.438
+PHY-3002 : Step(254): len = 587535, overlap = 113.062
+PHY-3002 : Step(255): len = 585219, overlap = 111.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000220068
+PHY-3002 : Step(256): len = 586358, overlap = 107.469
+PHY-3002 : Step(257): len = 589166, overlap = 105.844
+PHY-3002 : Step(258): len = 590697, overlap = 100.812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000440135
+PHY-3002 : Step(259): len = 594602, overlap = 96.6562
+PHY-3002 : Step(260): len = 600766, overlap = 89.6875
+PHY-3002 : Step(261): len = 602173, overlap = 87.8125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000813956
+PHY-3002 : Step(262): len = 606192, overlap = 86.5625
+PHY-3002 : Step(263): len = 614466, overlap = 79.6875
+PHY-3002 : Step(264): len = 618714, overlap = 71.625
+PHY-3002 : Step(265): len = 621192, overlap = 65.625
+PHY-3002 : Step(266): len = 622669, overlap = 63.5938
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.457599s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.7%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 561 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 388.03 peak overflow 2.88
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 901/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719056, over cnt = 3061(8%), over = 10955, worst = 21
+PHY-1001 : End global iterations; 1.257639s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (145.4%)
+
+PHY-1001 : Congestion index: top1 = 68.08, top5 = 56.30, top10 = 50.55, top15 = 47.06.
+PHY-1001 : End incremental global routing; 1.587282s wall, 2.140625s user + 0.000000s system = 2.140625s CPU (134.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.926177s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (101.2%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17865 has valid locations, 314 needs to be replaced
+PHY-3001 : design contains 18264 instances, 7784 luts, 9259 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6074 pins
+PHY-3001 : Found 1268 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 645931
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17257/20844.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733640, over cnt = 3108(8%), over = 11070, worst = 21
+PHY-1001 : End global iterations; 0.238476s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (150.7%)
+
+PHY-1001 : Congestion index: top1 = 68.49, top5 = 56.56, top10 = 50.85, top15 = 47.41.
+PHY-3001 : End congestion estimation; 0.504078s wall, 0.609375s user + 0.015625s system = 0.625000s CPU (124.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85096, tnet num: 20666, tinst num: 18264, tnode num: 115859, tedge num: 135590.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.489105s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (99.7%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 611 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20666 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.445384s wall, 2.359375s user + 0.078125s system = 2.437500s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(267): len = 644902, overlap = 0.25
+PHY-3002 : Step(268): len = 644623, overlap = 0.1875
+PHY-3002 : Step(269): len = 644432, overlap = 0.125
+PHY-3002 : Step(270): len = 644142, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17323/20844.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730360, over cnt = 3098(8%), over = 11127, worst = 21
+PHY-1001 : End global iterations; 0.218582s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (128.7%)
+
+PHY-1001 : Congestion index: top1 = 69.25, top5 = 57.23, top10 = 51.39, top15 = 47.72.
+PHY-3001 : End congestion estimation; 0.497120s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (113.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20666 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.915274s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000450219
+PHY-3002 : Step(271): len = 643686, overlap = 66.6562
+PHY-3002 : Step(272): len = 643615, overlap = 66.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000900438
+PHY-3002 : Step(273): len = 644008, overlap = 66.2812
+PHY-3002 : Step(274): len = 644465, overlap = 65.5625
+PHY-3001 : Final: Len = 644465, Over = 65.5625
+PHY-3001 : End incremental placement; 5.077811s wall, 5.359375s user + 0.312500s system = 5.671875s CPU (111.7%)
+
+OPT-1001 : Total overflow 393.44 peak overflow 2.88
+OPT-1001 : End high-fanout net optimization; 8.124819s wall, 9.093750s user + 0.312500s system = 9.406250s CPU (115.8%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 708, peak = 732.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17310/20844.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733696, over cnt = 3060(8%), over = 10100, worst = 21
+PHY-1002 : len = 789096, over cnt = 2062(5%), over = 4791, worst = 19
+PHY-1002 : len = 822096, over cnt = 980(2%), over = 2173, worst = 19
+PHY-1002 : len = 844384, over cnt = 331(0%), over = 680, worst = 19
+PHY-1002 : len = 855856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.005954s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (139.4%)
+
+PHY-1001 : Congestion index: top1 = 55.65, top5 = 49.35, top10 = 45.95, top15 = 43.82.
+OPT-1001 : End congestion update; 2.261656s wall, 3.046875s user + 0.015625s system = 3.062500s CPU (135.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20666 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.823561s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (98.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 139 cells processed and 18000 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 19 cells processed and 2500 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 9 cells processed and 800 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved
+OPT-1001 : End bottleneck based optimization; 3.511382s wall, 4.296875s user + 0.015625s system = 4.312500s CPU (122.8%)
+
+OPT-1001 : Current memory(MB): used = 692, reserve = 693, peak = 732.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17330/20849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856464, over cnt = 89(0%), over = 124, worst = 3
+PHY-1002 : len = 856408, over cnt = 36(0%), over = 44, worst = 3
+PHY-1002 : len = 856664, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 856744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 856920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.849878s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (103.0%)
+
+PHY-1001 : Congestion index: top1 = 55.69, top5 = 49.32, top10 = 46.04, top15 = 43.84.
+OPT-1001 : End congestion update; 1.133787s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (102.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.797757s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 6250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.048415s wall, 2.078125s user + 0.000000s system = 2.078125s CPU (101.5%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 697, peak = 732.
+OPT-1001 : End physical optimization; 15.449977s wall, 17.281250s user + 0.375000s system = 17.656250s CPU (114.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7784 LUT to BLE ...
+SYN-4008 : Packed 7784 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6129 remaining SEQ's ...
+SYN-4005 : Packed 3958 SEQ with LUT/SLICE
+SYN-4006 : 989 single LUT's are left
+SYN-4006 : 2171 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9955/13810 primitive instances ...
+PHY-3001 : End packing; 1.659795s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6736 instances
+RUN-1001 : 3294 mslices, 3294 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17843 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9976 nets have 2 pins
+RUN-1001 : 6511 nets have [3 - 5] pins
+RUN-1001 : 733 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 285 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6734 instances, 6588 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3494 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 653777, Over = 208
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7620/17843.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 804008, over cnt = 1906(5%), over = 3111, worst = 8
+PHY-1002 : len = 810480, over cnt = 1215(3%), over = 1735, worst = 8
+PHY-1002 : len = 823816, over cnt = 495(1%), over = 656, worst = 5
+PHY-1002 : len = 831992, over cnt = 130(0%), over = 171, worst = 5
+PHY-1002 : len = 834536, over cnt = 13(0%), over = 22, worst = 4
+PHY-1001 : End global iterations; 1.540951s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (140.9%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 49.40, top10 = 45.75, top15 = 43.44.
+PHY-3001 : End congestion estimation; 1.921758s wall, 2.531250s user + 0.015625s system = 2.546875s CPU (132.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71379, tnet num: 17665, tinst num: 6734, tnode num: 93621, tedge num: 118596.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.552277s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.7%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 616 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17665 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.438305s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.08833e-05
+PHY-3002 : Step(275): len = 641670, overlap = 200
+PHY-3002 : Step(276): len = 634720, overlap = 204.25
+PHY-3002 : Step(277): len = 630144, overlap = 213
+PHY-3002 : Step(278): len = 626841, overlap = 226.25
+PHY-3002 : Step(279): len = 624144, overlap = 232
+PHY-3002 : Step(280): len = 621661, overlap = 234.75
+PHY-3002 : Step(281): len = 619598, overlap = 231.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000121767
+PHY-3002 : Step(282): len = 621181, overlap = 224
+PHY-3002 : Step(283): len = 624866, overlap = 218.75
+PHY-3002 : Step(284): len = 627686, overlap = 211.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000243533
+PHY-3002 : Step(285): len = 632892, overlap = 208.75
+PHY-3002 : Step(286): len = 638372, overlap = 199.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000487066
+PHY-3002 : Step(287): len = 643371, overlap = 191.5
+PHY-3002 : Step(288): len = 654948, overlap = 178.25
+PHY-3002 : Step(289): len = 655325, overlap = 178.5
+PHY-3002 : Step(290): len = 654365, overlap = 173.25
+PHY-3002 : Step(291): len = 654550, overlap = 170.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.383736s wall, 0.390625s user + 0.593750s system = 0.984375s CPU (256.5%)
+
+PHY-3001 : Trial Legalized: Len = 726596
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 952/17843.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840408, over cnt = 2590(7%), over = 4250, worst = 8
+PHY-1002 : len = 856000, over cnt = 1568(4%), over = 2202, worst = 6
+PHY-1002 : len = 877128, over cnt = 459(1%), over = 608, worst = 5
+PHY-1002 : len = 887312, over cnt = 39(0%), over = 40, worst = 2
+PHY-1002 : len = 888384, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.250973s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (143.0%)
+
+PHY-1001 : Congestion index: top1 = 53.53, top5 = 48.44, top10 = 45.85, top15 = 44.02.
+PHY-3001 : End congestion estimation; 2.689179s wall, 3.656250s user + 0.000000s system = 3.656250s CPU (136.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17665 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.847816s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000173011
+PHY-3002 : Step(292): len = 700958, overlap = 35
+PHY-3002 : Step(293): len = 685818, overlap = 58
+PHY-3002 : Step(294): len = 672151, overlap = 84
+PHY-3002 : Step(295): len = 663514, overlap = 109.25
+PHY-3002 : Step(296): len = 655572, overlap = 140.75
+PHY-3002 : Step(297): len = 652121, overlap = 153
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000346022
+PHY-3002 : Step(298): len = 655572, overlap = 145.75
+PHY-3002 : Step(299): len = 658506, overlap = 143.5
+PHY-3002 : Step(300): len = 660652, overlap = 142.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000692044
+PHY-3002 : Step(301): len = 662540, overlap = 135.25
+PHY-3002 : Step(302): len = 667120, overlap = 126.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032655s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (95.7%)
+
+PHY-3001 : Legalized: Len = 695631, Over = 0
+PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.094540s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (99.2%)
+
+PHY-3001 : 594 instances has been re-located, deltaX = 195, deltaY = 335, maxDist = 2.
+PHY-3001 : Final: Len = 703991, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71379, tnet num: 17665, tinst num: 6737, tnode num: 93621, tedge num: 118596.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.810572s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (100.1%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 642 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4877/17843.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 831672, over cnt = 2327(6%), over = 3720, worst = 7
+PHY-1002 : len = 844832, over cnt = 1293(3%), over = 1774, worst = 6
+PHY-1002 : len = 857632, over cnt = 536(1%), over = 736, worst = 6
+PHY-1002 : len = 862648, over cnt = 300(0%), over = 416, worst = 6
+PHY-1002 : len = 869288, over cnt = 7(0%), over = 7, worst = 1
+PHY-1001 : End global iterations; 1.813180s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (146.5%)
+
+PHY-1001 : Congestion index: top1 = 52.61, top5 = 47.72, top10 = 44.84, top15 = 42.96.
+PHY-1001 : End incremental global routing; 2.166899s wall, 3.000000s user + 0.015625s system = 3.015625s CPU (139.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17665 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.824255s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (100.5%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6756 instances, 6607 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 708671
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16248/17863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874776, over cnt = 88(0%), over = 115, worst = 4
+PHY-1002 : len = 875024, over cnt = 38(0%), over = 43, worst = 3
+PHY-1002 : len = 875424, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 875560, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 875608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.741861s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 52.74, top5 = 47.79, top10 = 44.98, top15 = 43.11.
+PHY-3001 : End congestion estimation; 1.037614s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (105.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71551, tnet num: 17685, tinst num: 6756, tnode num: 93831, tedge num: 118825.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.781063s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (100.0%)
+
+RUN-1004 : used memory is 650 MB, reserved memory is 641 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.623511s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(303): len = 708091, overlap = 0
+PHY-3002 : Step(304): len = 707686, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16246/17863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874072, over cnt = 57(0%), over = 79, worst = 4
+PHY-1002 : len = 874184, over cnt = 26(0%), over = 31, worst = 3
+PHY-1002 : len = 874376, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 874504, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 874520, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.717635s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 52.52, top5 = 47.78, top10 = 44.89, top15 = 43.02.
+PHY-3001 : End congestion estimation; 1.015366s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (104.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.854241s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000505955
+PHY-3002 : Step(305): len = 707545, overlap = 0.5
+PHY-3002 : Step(306): len = 707381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005938s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 707434, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062734s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.6%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 6, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 707766, Over = 0
+PHY-3001 : End incremental placement; 6.002135s wall, 6.218750s user + 0.062500s system = 6.281250s CPU (104.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.458992s wall, 10.468750s user + 0.109375s system = 10.578125s CPU (111.8%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16219/17863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874312, over cnt = 72(0%), over = 87, worst = 5
+PHY-1002 : len = 874464, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 874608, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 874792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.570953s wall, 0.609375s user + 0.015625s system = 0.625000s CPU (109.5%)
+
+PHY-1001 : Congestion index: top1 = 52.54, top5 = 47.76, top10 = 44.94, top15 = 43.07.
+OPT-1001 : End congestion update; 0.873206s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (107.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.686573s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.1%)
+
+OPT-0007 : Start: WNS -129 TNS -129 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6668 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6756 instances, 6607 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 714281, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059613s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.8%)
+
+PHY-3001 : 37 instances has been re-located, deltaX = 12, deltaY = 36, maxDist = 3.
+PHY-3001 : Final: Len = 714857, Over = 0
+PHY-3001 : End incremental legalization; 0.363606s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 58 cells processed and 20611 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6668 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6756 instances, 6607 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 715493, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060019s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.1%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 11, deltaY = 5, maxDist = 4.
+PHY-3001 : Final: Len = 715823, Over = 0
+PHY-3001 : End incremental legalization; 0.368228s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.8%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 24 cells processed and 2032 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6676 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6764 instances, 6615 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 717179, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056534s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.6%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 2, deltaY = 14, maxDist = 2.
+PHY-3001 : Final: Len = 717613, Over = 0
+PHY-3001 : End incremental legalization; 0.363135s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.0%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 8 cells processed and 1338 slack improved
+OPT-1001 : End bottleneck based optimization; 3.058496s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (105.8%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15873/17867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 884472, over cnt = 180(0%), over = 230, worst = 4
+PHY-1002 : len = 884696, over cnt = 100(0%), over = 106, worst = 2
+PHY-1002 : len = 885696, over cnt = 27(0%), over = 29, worst = 2
+PHY-1002 : len = 885984, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 886016, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.802397s wall, 0.843750s user + 0.062500s system = 0.906250s CPU (112.9%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.83, top10 = 45.07, top15 = 43.25.
+OPT-1001 : End congestion update; 1.104862s wall, 1.156250s user + 0.062500s system = 1.218750s CPU (110.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.690905s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.5%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6676 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6764 instances, 6615 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 717527, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056878s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.4%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 4.
+PHY-3001 : Final: Len = 717735, Over = 0
+PHY-3001 : End incremental legalization; 0.363547s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (137.5%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 2350 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.276686s wall, 2.468750s user + 0.062500s system = 2.531250s CPU (111.2%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.690772s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16224/17867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886008, over cnt = 28(0%), over = 29, worst = 2
+PHY-1002 : len = 886000, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 886136, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 886184, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 886272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.729260s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.81, top10 = 45.07, top15 = 43.25.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.688392s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.034483
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 19.251278s wall, 20.625000s user + 0.203125s system = 20.828125s CPU (108.2%)
+
+RUN-1003 : finish command "place" in 63.293749s wall, 92.031250s user + 5.812500s system = 97.843750s CPU (154.6%)
+
+RUN-1004 : used memory is 678 MB, reserved memory is 681 MB, peak memory is 735 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.715536s wall, 2.906250s user + 0.015625s system = 2.921875s CPU (170.3%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 682 MB, peak memory is 735 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6766 instances
+RUN-1001 : 3304 mslices, 3311 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17867 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9968 nets have 2 pins
+RUN-1001 : 6519 nets have [3 - 5] pins
+RUN-1001 : 740 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 295 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71621, tnet num: 17689, tinst num: 6764, tnode num: 93925, tedge num: 118924.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.562969s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (101.0%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 653 MB, peak memory is 735 MB
+PHY-1001 : 3304 mslices, 3311 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 818720, over cnt = 2583(7%), over = 4209, worst = 8
+PHY-1002 : len = 836088, over cnt = 1547(4%), over = 2220, worst = 6
+PHY-1002 : len = 856424, over cnt = 501(1%), over = 702, worst = 5
+PHY-1002 : len = 868088, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 868232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.919979s wall, 3.890625s user + 0.031250s system = 3.921875s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 52.56, top5 = 47.56, top10 = 44.82, top15 = 42.92.
+PHY-1001 : End global routing; 3.269425s wall, 4.203125s user + 0.062500s system = 4.265625s CPU (130.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 708, reserve = 704, peak = 735.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 978, reserve = 978, peak = 978.
+PHY-1001 : End build detailed router design. 3.956288s wall, 3.906250s user + 0.046875s system = 3.953125s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 269424, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.048830s wall, 5.046875s user + 0.000000s system = 5.046875s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 269480, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.423528s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1015, reserve = 1015, peak = 1015.
+PHY-1001 : End phase 1; 5.484374s wall, 5.484375s user + 0.000000s system = 5.484375s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.23296e+06, over cnt = 1864(0%), over = 1876, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1029, reserve = 1028, peak = 1029.
+PHY-1001 : End initial routed; 23.302550s wall, 54.687500s user + 0.281250s system = 54.968750s CPU (235.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16790(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.808 | -0.808 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.230062s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1040, peak = 1040.
+PHY-1001 : End phase 2; 26.532677s wall, 57.921875s user + 0.281250s system = 58.203125s CPU (219.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.802ns STNS -0.802ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.140479s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.1%)
+
+PHY-1022 : len = 2.23298e+06, over cnt = 1865(0%), over = 1877, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.405647s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.19628e+06, over cnt = 629(0%), over = 629, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.645920s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (174.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.1947e+06, over cnt = 129(0%), over = 129, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.644609s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (160.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.19472e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.344185s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (113.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.19494e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.197343s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (126.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.19501e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.209706s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.19506e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 6; 0.181386s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16790(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.802 | -0.802 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.177148s wall, 3.156250s user + 0.000000s system = 3.156250s CPU (99.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 604 feed throughs used by 428 nets
+PHY-1001 : End commit to database; 2.186003s wall, 2.171875s user + 0.015625s system = 2.187500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1140, reserve = 1143, peak = 1140.
+PHY-1001 : End phase 3; 9.399190s wall, 11.046875s user + 0.031250s system = 11.078125s CPU (117.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.802ns STNS -0.802ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.130898s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.5%)
+
+PHY-1022 : len = 2.19506e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.363649s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.802ns, -0.802ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16790(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.802 | -0.802 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.187353s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 604 feed throughs used by 428 nets
+PHY-1001 : End commit to database; 2.246724s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1149, reserve = 1152, peak = 1149.
+PHY-1001 : End phase 4; 5.822095s wall, 5.812500s user + 0.015625s system = 5.828125s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.19506e+06
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1154, peak = 1151.
+PHY-1001 : End export database. 0.151389s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.2%)
+
+PHY-1001 : End detail routing; 51.743817s wall, 84.734375s user + 0.375000s system = 85.109375s CPU (164.5%)
+
+RUN-1003 : finish command "route" in 57.622982s wall, 91.546875s user + 0.437500s system = 91.984375s CPU (159.6%)
+
+RUN-1004 : used memory is 1079 MB, reserved memory is 1082 MB, peak memory is 1151 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10220 out of 19600 52.14%
+#reg 9406 out of 19600 47.99%
+#le 12357
+ #lut only 2951 out of 12357 23.88%
+ #reg only 2137 out of 12357 17.29%
+ #lut® 7269 out of 12357 58.82%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1797
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1369
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1272
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 959
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 135
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg0_syn_146.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_283.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P118 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P110 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P143 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12357 |9193 |1027 |9440 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |536 |459 |23 |437 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |86 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |41 |41 |0 |21 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |747 |379 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |180 |124 |25 |138 |0 |0 |
+| u_gen_sp |gen_sp |256 |148 |71 |124 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |352 |96 |568 |0 |0 |
+| u_ADconfig |AD_config |175 |95 |25 |133 |0 |0 |
+| u_gen_sp |gen_sp |247 |150 |71 |114 |0 |0 |
+| sampling_fe_a |sampling_fe |3037 |2457 |306 |2099 |25 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |179 |100 |17 |149 |0 |0 |
+| u0_soft_n |cdc_sync |6 |0 |0 |6 |0 |0 |
+| u_sort |sort |2829 |2348 |289 |1921 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |0 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |8 |4 |0 |8 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2399 |2045 |253 |1560 |22 |0 |
+| channelPart |channel_part_8478 |133 |125 |3 |129 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |41 |0 |0 |
+| ram_switch |ram_switch |1890 |1608 |197 |1171 |0 |0 |
+| adc_addr_gen |adc_addr_gen |230 |203 |27 |129 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |17 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| insert |insert |926 |671 |170 |633 |0 |0 |
+| ram_switch_state |ram_switch_state |734 |734 |0 |409 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |196 |0 |0 |
+| read_ram_addr |read_ram_addr |225 |185 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |50 |43 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |333 |233 |36 |279 |3 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3208 |2502 |349 |2076 |25 |1 |
+| u0_soft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |173 |82 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u_sort |sort_rev |3001 |2403 |332 |1898 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |4 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2579 |2081 |290 |1542 |22 |1 |
+| channelPart |channel_part_8478 |133 |123 |3 |129 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |42 |0 |1 |
+| ram_switch |ram_switch |1994 |1631 |197 |1128 |0 |0 |
+| adc_addr_gen |adc_addr_gen |198 |171 |27 |96 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |5 |0 |0 |
+| insert |insert |982 |646 |170 |696 |0 |0 |
+| ram_switch_state |ram_switch_state |814 |814 |0 |336 |0 |0 |
+| read_ram_i |read_ram_rev |363 |258 |81 |214 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |303 |223 |73 |171 |0 |0 |
+| read_ram_data |read_ram_data_rev |60 |35 |8 |43 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9906
+ #2 2 4224
+ #3 3 1698
+ #4 4 594
+ #5 5-10 786
+ #6 11-50 550
+ #7 51-100 13
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.270420s wall, 3.468750s user + 0.031250s system = 3.500000s CPU (154.2%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1083 MB, peak memory is 1151 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71621, tnet num: 17689, tinst num: 6764, tnode num: 93925, tedge num: 118924.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.572928s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.3%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1088 MB, peak memory is 1151 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.417312s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (100.3%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1090 MB, peak memory is 1151 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6764
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17867, pip num: 166736
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 604
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 467100 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.932507s wall, 67.281250s user + 0.140625s system = 67.421875s CPU (678.8%)
+
+RUN-1004 : used memory is 1244 MB, reserved memory is 1245 MB, peak memory is 1359 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_154137.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_154943.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_154943.log
new file mode 100644
index 0000000..d1c8be7
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_154943.log
@@ -0,0 +1,2000 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:49:43 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.202889s wall, 2.140625s user + 0.062500s system = 2.203125s CPU (100.0%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 316 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18004 instances
+RUN-0007 : 7679 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20582 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13122 nets have 2 pins
+RUN-1001 : 6382 nets have [3 - 5] pins
+RUN-1001 : 654 nets have [6 - 10] pins
+RUN-1001 : 184 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18002 instances, 7679 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84366, tnet num: 20404, tinst num: 18002, tnode num: 114618, tedge num: 134654.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.132632s wall, 1.093750s user + 0.031250s system = 1.125000s CPU (99.3%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 515 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20404 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.901148s wall, 1.812500s user + 0.093750s system = 1.906250s CPU (100.3%)
+
+PHY-3001 : Found 1246 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.02606e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18002.
+PHY-3001 : Level 1 #clusters 1980.
+PHY-3001 : End clustering; 0.131631s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (118.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.3245e+06, overlap = 399.75
+PHY-3002 : Step(2): len = 1.22354e+06, overlap = 463.031
+PHY-3002 : Step(3): len = 842738, overlap = 602.125
+PHY-3002 : Step(4): len = 781538, overlap = 658.531
+PHY-3002 : Step(5): len = 594055, overlap = 796.594
+PHY-3002 : Step(6): len = 524710, overlap = 860.25
+PHY-3002 : Step(7): len = 456045, overlap = 937.938
+PHY-3002 : Step(8): len = 415048, overlap = 1029.16
+PHY-3002 : Step(9): len = 386465, overlap = 1076.78
+PHY-3002 : Step(10): len = 355683, overlap = 1089.28
+PHY-3002 : Step(11): len = 323136, overlap = 1122.06
+PHY-3002 : Step(12): len = 298134, overlap = 1178.69
+PHY-3002 : Step(13): len = 273904, overlap = 1239.34
+PHY-3002 : Step(14): len = 257154, overlap = 1267.84
+PHY-3002 : Step(15): len = 236904, overlap = 1312.16
+PHY-3002 : Step(16): len = 224539, overlap = 1352.22
+PHY-3002 : Step(17): len = 202575, overlap = 1372.91
+PHY-3002 : Step(18): len = 190823, overlap = 1398.75
+PHY-3002 : Step(19): len = 175761, overlap = 1435.38
+PHY-3002 : Step(20): len = 160606, overlap = 1435.41
+PHY-3002 : Step(21): len = 152962, overlap = 1422.72
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.96072e-07
+PHY-3002 : Step(22): len = 153664, overlap = 1409.53
+PHY-3002 : Step(23): len = 186738, overlap = 1291.66
+PHY-3002 : Step(24): len = 190912, overlap = 1229.94
+PHY-3002 : Step(25): len = 198420, overlap = 1224.59
+PHY-3002 : Step(26): len = 196036, overlap = 1185.75
+PHY-3002 : Step(27): len = 196543, overlap = 1160.62
+PHY-3002 : Step(28): len = 193874, overlap = 1154.16
+PHY-3002 : Step(29): len = 194124, overlap = 1102.69
+PHY-3002 : Step(30): len = 191300, overlap = 1121.94
+PHY-3002 : Step(31): len = 190190, overlap = 1135.31
+PHY-3002 : Step(32): len = 186986, overlap = 1145.47
+PHY-3002 : Step(33): len = 185424, overlap = 1133.53
+PHY-3002 : Step(34): len = 183001, overlap = 1099.06
+PHY-3002 : Step(35): len = 181926, overlap = 1072.16
+PHY-3002 : Step(36): len = 180045, overlap = 1070.84
+PHY-3002 : Step(37): len = 179391, overlap = 1078.22
+PHY-3002 : Step(38): len = 177996, overlap = 1073.41
+PHY-3002 : Step(39): len = 176233, overlap = 1075.41
+PHY-3002 : Step(40): len = 174902, overlap = 1070.69
+PHY-3002 : Step(41): len = 172390, overlap = 1067.12
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.99214e-06
+PHY-3002 : Step(42): len = 174572, overlap = 1052.19
+PHY-3002 : Step(43): len = 187018, overlap = 1023.31
+PHY-3002 : Step(44): len = 193769, overlap = 1006.81
+PHY-3002 : Step(45): len = 199297, overlap = 988.938
+PHY-3002 : Step(46): len = 200201, overlap = 982.469
+PHY-3002 : Step(47): len = 200495, overlap = 983.188
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.98429e-06
+PHY-3002 : Step(48): len = 207844, overlap = 962.75
+PHY-3002 : Step(49): len = 223459, overlap = 904.031
+PHY-3002 : Step(50): len = 230419, overlap = 879.781
+PHY-3002 : Step(51): len = 236400, overlap = 827.781
+PHY-3002 : Step(52): len = 237198, overlap = 805.906
+PHY-3002 : Step(53): len = 236086, overlap = 797.844
+PHY-3002 : Step(54): len = 233978, overlap = 800.219
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.96858e-06
+PHY-3002 : Step(55): len = 245607, overlap = 766.094
+PHY-3002 : Step(56): len = 264480, overlap = 675.375
+PHY-3002 : Step(57): len = 274110, overlap = 609.156
+PHY-3002 : Step(58): len = 281648, overlap = 590.031
+PHY-3002 : Step(59): len = 284352, overlap = 574.062
+PHY-3002 : Step(60): len = 285629, overlap = 580.562
+PHY-3002 : Step(61): len = 283890, overlap = 551.5
+PHY-3002 : Step(62): len = 283381, overlap = 531.844
+PHY-3002 : Step(63): len = 283612, overlap = 520.062
+PHY-3002 : Step(64): len = 283116, overlap = 503.094
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.59372e-05
+PHY-3002 : Step(65): len = 298651, overlap = 461.344
+PHY-3002 : Step(66): len = 310660, overlap = 437
+PHY-3002 : Step(67): len = 313398, overlap = 421.594
+PHY-3002 : Step(68): len = 318511, overlap = 419.125
+PHY-3002 : Step(69): len = 320844, overlap = 413.031
+PHY-3002 : Step(70): len = 323333, overlap = 399.25
+PHY-3002 : Step(71): len = 321899, overlap = 397.344
+PHY-3002 : Step(72): len = 321728, overlap = 388.562
+PHY-3002 : Step(73): len = 322331, overlap = 370.656
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.18743e-05
+PHY-3002 : Step(74): len = 336595, overlap = 357.031
+PHY-3002 : Step(75): len = 347578, overlap = 348.812
+PHY-3002 : Step(76): len = 350866, overlap = 339.25
+PHY-3002 : Step(77): len = 353479, overlap = 327.969
+PHY-3002 : Step(78): len = 356473, overlap = 310.281
+PHY-3002 : Step(79): len = 360603, overlap = 299.656
+PHY-3002 : Step(80): len = 360267, overlap = 306.594
+PHY-3002 : Step(81): len = 362085, overlap = 314.969
+PHY-3002 : Step(82): len = 362294, overlap = 308.094
+PHY-3002 : Step(83): len = 365153, overlap = 299.594
+PHY-3002 : Step(84): len = 365261, overlap = 309.312
+PHY-3002 : Step(85): len = 367349, overlap = 304.5
+PHY-3002 : Step(86): len = 366249, overlap = 327.156
+PHY-3002 : Step(87): len = 369069, overlap = 331.844
+PHY-3002 : Step(88): len = 367823, overlap = 317.531
+PHY-3002 : Step(89): len = 367748, overlap = 318.938
+PHY-3002 : Step(90): len = 367902, overlap = 323.5
+PHY-3002 : Step(91): len = 368661, overlap = 324.969
+PHY-3002 : Step(92): len = 365915, overlap = 326.594
+PHY-3002 : Step(93): len = 365562, overlap = 330
+PHY-3002 : Step(94): len = 364169, overlap = 332.719
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.37486e-05
+PHY-3002 : Step(95): len = 381494, overlap = 327.781
+PHY-3002 : Step(96): len = 390816, overlap = 316.969
+PHY-3002 : Step(97): len = 389780, overlap = 296.25
+PHY-3002 : Step(98): len = 390933, overlap = 287.75
+PHY-3002 : Step(99): len = 394578, overlap = 272.656
+PHY-3002 : Step(100): len = 397912, overlap = 270.188
+PHY-3002 : Step(101): len = 395766, overlap = 241.156
+PHY-3002 : Step(102): len = 396567, overlap = 236.625
+PHY-3002 : Step(103): len = 397858, overlap = 241.188
+PHY-3002 : Step(104): len = 398940, overlap = 246.812
+PHY-3002 : Step(105): len = 395976, overlap = 233.062
+PHY-3002 : Step(106): len = 395193, overlap = 247.062
+PHY-3002 : Step(107): len = 396062, overlap = 256.875
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000127497
+PHY-3002 : Step(108): len = 409754, overlap = 253.5
+PHY-3002 : Step(109): len = 417825, overlap = 242.781
+PHY-3002 : Step(110): len = 417897, overlap = 245.469
+PHY-3002 : Step(111): len = 420755, overlap = 247.594
+PHY-3002 : Step(112): len = 425313, overlap = 231.219
+PHY-3002 : Step(113): len = 428507, overlap = 225.031
+PHY-3002 : Step(114): len = 427353, overlap = 208.188
+PHY-3002 : Step(115): len = 428604, overlap = 209.875
+PHY-3002 : Step(116): len = 431094, overlap = 202.344
+PHY-3002 : Step(117): len = 432812, overlap = 200.344
+PHY-3002 : Step(118): len = 430575, overlap = 198.875
+PHY-3002 : Step(119): len = 431080, overlap = 203.219
+PHY-3002 : Step(120): len = 432951, overlap = 197.719
+PHY-3002 : Step(121): len = 434625, overlap = 202
+PHY-3002 : Step(122): len = 433047, overlap = 203.344
+PHY-3002 : Step(123): len = 433339, overlap = 211.875
+PHY-3002 : Step(124): len = 435164, overlap = 208.531
+PHY-3002 : Step(125): len = 436562, overlap = 205.344
+PHY-3002 : Step(126): len = 434817, overlap = 207.719
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000246331
+PHY-3002 : Step(127): len = 444024, overlap = 194.031
+PHY-3002 : Step(128): len = 452908, overlap = 189.594
+PHY-3002 : Step(129): len = 454664, overlap = 182.281
+PHY-3002 : Step(130): len = 456090, overlap = 177.188
+PHY-3002 : Step(131): len = 459192, overlap = 180.844
+PHY-3002 : Step(132): len = 460733, overlap = 172.531
+PHY-3002 : Step(133): len = 459312, overlap = 167.656
+PHY-3002 : Step(134): len = 459918, overlap = 161.344
+PHY-3002 : Step(135): len = 461675, overlap = 166.125
+PHY-3002 : Step(136): len = 462994, overlap = 164.031
+PHY-3002 : Step(137): len = 461822, overlap = 164.875
+PHY-3002 : Step(138): len = 462273, overlap = 170.719
+PHY-3002 : Step(139): len = 464894, overlap = 166.688
+PHY-3002 : Step(140): len = 466707, overlap = 165.688
+PHY-3002 : Step(141): len = 465098, overlap = 169.5
+PHY-3002 : Step(142): len = 464861, overlap = 166.719
+PHY-3002 : Step(143): len = 466341, overlap = 165.438
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000488619
+PHY-3002 : Step(144): len = 472808, overlap = 159.438
+PHY-3002 : Step(145): len = 482673, overlap = 151.188
+PHY-3002 : Step(146): len = 485315, overlap = 147.688
+PHY-3002 : Step(147): len = 486966, overlap = 143.625
+PHY-3002 : Step(148): len = 489307, overlap = 140.969
+PHY-3002 : Step(149): len = 490622, overlap = 141.969
+PHY-3002 : Step(150): len = 489332, overlap = 140.406
+PHY-3002 : Step(151): len = 489067, overlap = 144.312
+PHY-3002 : Step(152): len = 490246, overlap = 139.938
+PHY-3002 : Step(153): len = 491136, overlap = 136.438
+PHY-3002 : Step(154): len = 490382, overlap = 136.219
+PHY-3002 : Step(155): len = 490287, overlap = 134.688
+PHY-3002 : Step(156): len = 491473, overlap = 138.75
+PHY-3002 : Step(157): len = 492359, overlap = 141.75
+PHY-3002 : Step(158): len = 491534, overlap = 139.938
+PHY-3002 : Step(159): len = 491470, overlap = 140.75
+PHY-3002 : Step(160): len = 492886, overlap = 143
+PHY-3002 : Step(161): len = 493826, overlap = 140.469
+PHY-3002 : Step(162): len = 493163, overlap = 143.188
+PHY-3002 : Step(163): len = 493041, overlap = 139.406
+PHY-3002 : Step(164): len = 493634, overlap = 141.656
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000930412
+PHY-3002 : Step(165): len = 498156, overlap = 135.062
+PHY-3002 : Step(166): len = 505516, overlap = 124.938
+PHY-3002 : Step(167): len = 508321, overlap = 123.719
+PHY-3002 : Step(168): len = 510056, overlap = 121.781
+PHY-3002 : Step(169): len = 511090, overlap = 118.781
+PHY-3002 : Step(170): len = 511588, overlap = 118.406
+PHY-3002 : Step(171): len = 511340, overlap = 121.938
+PHY-3002 : Step(172): len = 511531, overlap = 123.562
+PHY-3002 : Step(173): len = 513041, overlap = 120.562
+PHY-3002 : Step(174): len = 514647, overlap = 123.375
+PHY-3002 : Step(175): len = 515117, overlap = 120.531
+PHY-3002 : Step(176): len = 515450, overlap = 119.469
+PHY-3002 : Step(177): len = 516008, overlap = 119.438
+PHY-3002 : Step(178): len = 516396, overlap = 118.156
+PHY-3002 : Step(179): len = 516193, overlap = 115.75
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0016195
+PHY-3002 : Step(180): len = 519272, overlap = 113.156
+PHY-3002 : Step(181): len = 523911, overlap = 106.406
+PHY-3002 : Step(182): len = 524609, overlap = 106.375
+PHY-3002 : Step(183): len = 524931, overlap = 105.281
+PHY-3002 : Step(184): len = 525969, overlap = 106
+PHY-3002 : Step(185): len = 526600, overlap = 106.094
+PHY-3002 : Step(186): len = 526712, overlap = 106.75
+PHY-3002 : Step(187): len = 526822, overlap = 105.656
+PHY-3002 : Step(188): len = 527313, overlap = 105.188
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012957s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (120.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20582.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 728952, over cnt = 1673(4%), over = 7252, worst = 51
+PHY-1001 : End global iterations; 0.774660s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 76.57, top5 = 61.24, top10 = 52.68, top15 = 47.26.
+PHY-3001 : End congestion estimation; 0.992481s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (130.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20404 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.876655s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000131834
+PHY-3002 : Step(189): len = 656647, overlap = 37
+PHY-3002 : Step(190): len = 661897, overlap = 42.375
+PHY-3002 : Step(191): len = 662810, overlap = 41.625
+PHY-3002 : Step(192): len = 658367, overlap = 35.6875
+PHY-3002 : Step(193): len = 653014, overlap = 35.1875
+PHY-3002 : Step(194): len = 649328, overlap = 34.625
+PHY-3002 : Step(195): len = 648474, overlap = 34.75
+PHY-3002 : Step(196): len = 647595, overlap = 28.8125
+PHY-3002 : Step(197): len = 648659, overlap = 28.1875
+PHY-3002 : Step(198): len = 647624, overlap = 31.5
+PHY-3002 : Step(199): len = 647118, overlap = 30.6875
+PHY-3002 : Step(200): len = 646834, overlap = 29
+PHY-3002 : Step(201): len = 649793, overlap = 27.4375
+PHY-3002 : Step(202): len = 650185, overlap = 25.25
+PHY-3002 : Step(203): len = 649135, overlap = 25.0312
+PHY-3002 : Step(204): len = 649359, overlap = 27.875
+PHY-3002 : Step(205): len = 648501, overlap = 31.375
+PHY-3002 : Step(206): len = 649222, overlap = 31.4062
+PHY-3002 : Step(207): len = 646895, overlap = 33.6562
+PHY-3002 : Step(208): len = 645142, overlap = 35.25
+PHY-3002 : Step(209): len = 644880, overlap = 35.875
+PHY-3002 : Step(210): len = 642210, overlap = 35.1875
+PHY-3002 : Step(211): len = 641602, overlap = 36.1562
+PHY-3002 : Step(212): len = 639473, overlap = 37.125
+PHY-3002 : Step(213): len = 638633, overlap = 38.7188
+PHY-3002 : Step(214): len = 636822, overlap = 40.2188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000263669
+PHY-3002 : Step(215): len = 640410, overlap = 38
+PHY-3002 : Step(216): len = 643980, overlap = 38.7188
+PHY-3002 : Step(217): len = 652408, overlap = 38.6562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000527337
+PHY-3002 : Step(218): len = 657988, overlap = 37.4062
+PHY-3002 : Step(219): len = 669746, overlap = 37.875
+PHY-3002 : Step(220): len = 683804, overlap = 39.2188
+PHY-3002 : Step(221): len = 687529, overlap = 41.9062
+PHY-3002 : Step(222): len = 690321, overlap = 43.8438
+PHY-3002 : Step(223): len = 690869, overlap = 45.875
+PHY-3002 : Step(224): len = 692834, overlap = 41.9062
+PHY-3002 : Step(225): len = 693517, overlap = 41.7812
+PHY-3002 : Step(226): len = 693972, overlap = 39.4062
+PHY-3002 : Step(227): len = 694439, overlap = 38.8438
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00105467
+PHY-3002 : Step(228): len = 698047, overlap = 41.7188
+PHY-3002 : Step(229): len = 703838, overlap = 42.8438
+PHY-3002 : Step(230): len = 706780, overlap = 41.0625
+PHY-3002 : Step(231): len = 710732, overlap = 39.5938
+PHY-3002 : Step(232): len = 713966, overlap = 38.5625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00179
+PHY-3002 : Step(233): len = 717001, overlap = 38.4375
+PHY-3002 : Step(234): len = 723710, overlap = 43.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 67/20582.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 811952, over cnt = 2833(8%), over = 13764, worst = 48
+PHY-1001 : End global iterations; 1.555764s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 88.32, top5 = 71.70, top10 = 63.07, top15 = 57.55.
+PHY-3001 : End congestion estimation; 1.837606s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (129.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20404 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.876139s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000131214
+PHY-3002 : Step(235): len = 713169, overlap = 264.812
+PHY-3002 : Step(236): len = 711392, overlap = 204.656
+PHY-3002 : Step(237): len = 698534, overlap = 174.094
+PHY-3002 : Step(238): len = 689743, overlap = 157.031
+PHY-3002 : Step(239): len = 680653, overlap = 141.281
+PHY-3002 : Step(240): len = 673029, overlap = 126.969
+PHY-3002 : Step(241): len = 666955, overlap = 116.406
+PHY-3002 : Step(242): len = 660812, overlap = 115.656
+PHY-3002 : Step(243): len = 656491, overlap = 111.125
+PHY-3002 : Step(244): len = 651168, overlap = 106.469
+PHY-3002 : Step(245): len = 646846, overlap = 109.781
+PHY-3002 : Step(246): len = 643431, overlap = 118
+PHY-3002 : Step(247): len = 639900, overlap = 121.875
+PHY-3002 : Step(248): len = 636844, overlap = 122.656
+PHY-3002 : Step(249): len = 634278, overlap = 133.031
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000262428
+PHY-3002 : Step(250): len = 635571, overlap = 126.281
+PHY-3002 : Step(251): len = 637409, overlap = 123.125
+PHY-3002 : Step(252): len = 637056, overlap = 118.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000524857
+PHY-3002 : Step(253): len = 643292, overlap = 110.219
+PHY-3002 : Step(254): len = 649908, overlap = 102.938
+PHY-3002 : Step(255): len = 653127, overlap = 97.7188
+PHY-3002 : Step(256): len = 654032, overlap = 94.9062
+PHY-3002 : Step(257): len = 655616, overlap = 91.4375
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84366, tnet num: 20404, tinst num: 18002, tnode num: 114618, tedge num: 134654.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.407469s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (99.9%)
+
+RUN-1004 : used memory is 579 MB, reserved memory is 566 MB, peak memory is 712 MB
+OPT-1001 : Total overflow 423.31 peak overflow 4.16
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 536/20582.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 760800, over cnt = 3132(8%), over = 11055, worst = 25
+PHY-1001 : End global iterations; 1.414847s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (139.1%)
+
+PHY-1001 : Congestion index: top1 = 70.82, top5 = 58.36, top10 = 52.39, top15 = 48.67.
+PHY-1001 : End incremental global routing; 1.741382s wall, 2.281250s user + 0.015625s system = 2.296875s CPU (131.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20404 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.893163s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.7%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17873 has valid locations, 303 needs to be replaced
+PHY-3001 : design contains 18261 instances, 7767 luts, 9273 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6074 pins
+PHY-3001 : Found 1255 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 678762
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16873/20841.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 773920, over cnt = 3142(8%), over = 11097, worst = 25
+PHY-1001 : End global iterations; 0.239843s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (136.8%)
+
+PHY-1001 : Congestion index: top1 = 70.30, top5 = 58.28, top10 = 52.41, top15 = 48.82.
+PHY-3001 : End congestion estimation; 0.491031s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (114.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85398, tnet num: 20663, tinst num: 18261, tnode num: 116177, tedge num: 136200.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.424368s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (100.9%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 620 MB, peak memory is 719 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20663 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.715825s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(258): len = 677793, overlap = 2.25
+PHY-3002 : Step(259): len = 677514, overlap = 2.25
+PHY-3002 : Step(260): len = 677150, overlap = 2.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16954/20841.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 771288, over cnt = 3164(8%), over = 11200, worst = 25
+PHY-1001 : End global iterations; 0.197368s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (110.8%)
+
+PHY-1001 : Congestion index: top1 = 71.03, top5 = 58.71, top10 = 52.67, top15 = 49.10.
+PHY-3001 : End congestion estimation; 0.450854s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (107.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20663 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.910708s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000308213
+PHY-3002 : Step(261): len = 676928, overlap = 93.3125
+PHY-3002 : Step(262): len = 676980, overlap = 93.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000616425
+PHY-3002 : Step(263): len = 677250, overlap = 94.1875
+PHY-3002 : Step(264): len = 677526, overlap = 94.1875
+PHY-3001 : Final: Len = 677526, Over = 94.1875
+PHY-3001 : End incremental placement; 5.176898s wall, 5.406250s user + 0.125000s system = 5.531250s CPU (106.8%)
+
+OPT-1001 : Total overflow 429.34 peak overflow 4.16
+OPT-1001 : End high-fanout net optimization; 8.481801s wall, 9.250000s user + 0.140625s system = 9.390625s CPU (110.7%)
+
+OPT-1001 : Current memory(MB): used = 721, reserve = 713, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16927/20841.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 773488, over cnt = 3091(8%), over = 10122, worst = 25
+PHY-1002 : len = 824560, over cnt = 2063(5%), over = 5039, worst = 22
+PHY-1002 : len = 860896, over cnt = 1083(3%), over = 2349, worst = 16
+PHY-1002 : len = 877712, over cnt = 529(1%), over = 1130, worst = 16
+PHY-1002 : len = 895792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.738553s wall, 2.312500s user + 0.046875s system = 2.359375s CPU (135.7%)
+
+PHY-1001 : Congestion index: top1 = 59.66, top5 = 51.79, top10 = 47.91, top15 = 45.52.
+OPT-1001 : End congestion update; 1.997864s wall, 2.578125s user + 0.046875s system = 2.625000s CPU (131.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20663 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804599s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 112 cells processed and 22563 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 15 cells processed and 800 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 150 slack improved
+OPT-1001 : End bottleneck based optimization; 3.120633s wall, 3.703125s user + 0.046875s system = 3.750000s CPU (120.2%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 710, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16991/20842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896224, over cnt = 87(0%), over = 112, worst = 3
+PHY-1002 : len = 895816, over cnt = 40(0%), over = 43, worst = 3
+PHY-1002 : len = 896224, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 896400, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 896400, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.708804s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.2%)
+
+PHY-1001 : Congestion index: top1 = 59.48, top5 = 51.87, top10 = 48.00, top15 = 45.56.
+OPT-1001 : End congestion update; 0.967827s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (100.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.776789s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.6%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 32 cells processed and 4650 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.865709s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 710, peak = 737.
+OPT-1001 : End physical optimization; 15.174331s wall, 16.593750s user + 0.203125s system = 16.796875s CPU (110.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7767 LUT to BLE ...
+SYN-4008 : Packed 7767 LUT and 3134 SEQ to BLE.
+SYN-4003 : Packing 6140 remaining SEQ's ...
+SYN-4005 : Packed 4065 SEQ with LUT/SLICE
+SYN-4006 : 863 single LUT's are left
+SYN-4006 : 2075 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9842/13697 primitive instances ...
+PHY-3001 : End packing; 1.592866s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6688 instances
+RUN-1001 : 3270 mslices, 3270 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17835 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9975 nets have 2 pins
+RUN-1001 : 6463 nets have [3 - 5] pins
+RUN-1001 : 759 nets have [6 - 10] pins
+RUN-1001 : 315 nets have [11 - 20] pins
+RUN-1001 : 291 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6686 instances, 6540 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3499 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 687081, Over = 225.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7511/17835.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844768, over cnt = 2058(5%), over = 3357, worst = 7
+PHY-1002 : len = 853360, over cnt = 1307(3%), over = 1872, worst = 6
+PHY-1002 : len = 865048, over cnt = 645(1%), over = 895, worst = 6
+PHY-1002 : len = 875584, over cnt = 190(0%), over = 254, worst = 6
+PHY-1002 : len = 881296, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.592158s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (145.2%)
+
+PHY-1001 : Congestion index: top1 = 60.15, top5 = 51.51, top10 = 47.57, top15 = 45.02.
+PHY-3001 : End congestion estimation; 1.974768s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (136.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71680, tnet num: 17657, tinst num: 6686, tnode num: 93897, tedge num: 119283.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.568732s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.6%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 620 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17657 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.413877s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.15094e-05
+PHY-3002 : Step(265): len = 675244, overlap = 221
+PHY-3002 : Step(266): len = 669174, overlap = 228
+PHY-3002 : Step(267): len = 665393, overlap = 237.25
+PHY-3002 : Step(268): len = 662091, overlap = 239.75
+PHY-3002 : Step(269): len = 659455, overlap = 247.25
+PHY-3002 : Step(270): len = 656999, overlap = 255.75
+PHY-3002 : Step(271): len = 655298, overlap = 250.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103019
+PHY-3002 : Step(272): len = 657896, overlap = 235.5
+PHY-3002 : Step(273): len = 662619, overlap = 218.5
+PHY-3002 : Step(274): len = 664641, overlap = 215.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000206038
+PHY-3002 : Step(275): len = 670700, overlap = 205.5
+PHY-3002 : Step(276): len = 677196, overlap = 197.25
+PHY-3002 : Step(277): len = 677607, overlap = 193.25
+PHY-3002 : Step(278): len = 678203, overlap = 188.5
+PHY-3002 : Step(279): len = 678624, overlap = 185.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.426004s wall, 0.390625s user + 0.500000s system = 0.890625s CPU (209.1%)
+
+PHY-3001 : Trial Legalized: Len = 763420
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 924/17835.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879232, over cnt = 2667(7%), over = 4533, worst = 7
+PHY-1002 : len = 898960, over cnt = 1535(4%), over = 2136, worst = 6
+PHY-1002 : len = 914344, over cnt = 672(1%), over = 928, worst = 6
+PHY-1002 : len = 926264, over cnt = 245(0%), over = 339, worst = 4
+PHY-1002 : len = 931544, over cnt = 11(0%), over = 15, worst = 4
+PHY-1001 : End global iterations; 2.412617s wall, 3.437500s user + 0.031250s system = 3.468750s CPU (143.8%)
+
+PHY-1001 : Congestion index: top1 = 59.44, top5 = 52.11, top10 = 48.24, top15 = 45.90.
+PHY-3001 : End congestion estimation; 2.874975s wall, 3.890625s user + 0.031250s system = 3.921875s CPU (136.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17657 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.836933s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160543
+PHY-3002 : Step(280): len = 735080, overlap = 36.5
+PHY-3002 : Step(281): len = 717106, overlap = 57.25
+PHY-3002 : Step(282): len = 705304, overlap = 79.5
+PHY-3002 : Step(283): len = 697300, overlap = 97.25
+PHY-3002 : Step(284): len = 691261, overlap = 120.75
+PHY-3002 : Step(285): len = 687969, overlap = 138.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000321086
+PHY-3002 : Step(286): len = 692567, overlap = 128
+PHY-3002 : Step(287): len = 696469, overlap = 123.5
+PHY-3002 : Step(288): len = 697553, overlap = 125.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000642171
+PHY-3002 : Step(289): len = 700976, overlap = 122.5
+PHY-3002 : Step(290): len = 708612, overlap = 118.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033122s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (94.3%)
+
+PHY-3001 : Legalized: Len = 736125, Over = 0
+PHY-3001 : Spreading special nets. 473 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.099864s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (93.9%)
+
+PHY-3001 : 685 instances has been re-located, deltaX = 189, deltaY = 401, maxDist = 2.
+PHY-3001 : Final: Len = 747395, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71680, tnet num: 17657, tinst num: 6689, tnode num: 93897, tedge num: 119283.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.822928s wall, 1.781250s user + 0.046875s system = 1.828125s CPU (100.3%)
+
+RUN-1004 : used memory is 635 MB, reserved memory is 656 MB, peak memory is 737 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4418/17835.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 877720, over cnt = 2456(6%), over = 3855, worst = 8
+PHY-1002 : len = 890752, over cnt = 1442(4%), over = 2004, worst = 8
+PHY-1002 : len = 904728, over cnt = 643(1%), over = 869, worst = 8
+PHY-1002 : len = 910688, over cnt = 303(0%), over = 420, worst = 4
+PHY-1002 : len = 917600, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.045203s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (145.2%)
+
+PHY-1001 : Congestion index: top1 = 55.11, top5 = 48.91, top10 = 45.82, top15 = 43.77.
+PHY-1001 : End incremental global routing; 2.400933s wall, 3.296875s user + 0.031250s system = 3.328125s CPU (138.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17657 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.836465s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (99.0%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6597 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6712 instances, 6563 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 751199
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16311/17866.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922264, over cnt = 77(0%), over = 89, worst = 3
+PHY-1002 : len = 922296, over cnt = 50(0%), over = 52, worst = 2
+PHY-1002 : len = 922776, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 922872, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 922936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.755439s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (105.5%)
+
+PHY-1001 : Congestion index: top1 = 55.13, top5 = 48.97, top10 = 45.87, top15 = 43.84.
+PHY-3001 : End congestion estimation; 1.076883s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (104.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71890, tnet num: 17688, tinst num: 6712, tnode num: 94165, tedge num: 119559.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.789814s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (99.5%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 667 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17688 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.647807s wall, 2.625000s user + 0.015625s system = 2.640625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(291): len = 750531, overlap = 0
+PHY-3002 : Step(292): len = 749911, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16300/17866.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920480, over cnt = 67(0%), over = 88, worst = 6
+PHY-1002 : len = 920648, over cnt = 33(0%), over = 35, worst = 2
+PHY-1002 : len = 920976, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 921096, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.609326s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (102.6%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 48.99, top10 = 45.88, top15 = 43.85.
+PHY-3001 : End congestion estimation; 0.910572s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (101.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17688 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.834193s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00017609
+PHY-3002 : Step(293): len = 749914, overlap = 1.75
+PHY-3002 : Step(294): len = 750001, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005531s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 750006, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060026s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.1%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 5, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 750204, Over = 0
+PHY-3001 : End incremental placement; 5.952674s wall, 6.078125s user + 0.109375s system = 6.187500s CPU (103.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.667799s wall, 10.765625s user + 0.171875s system = 10.937500s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 736, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16257/17866.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 921088, over cnt = 69(0%), over = 83, worst = 3
+PHY-1002 : len = 921280, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 921632, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 921616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.590540s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (108.5%)
+
+PHY-1001 : Congestion index: top1 = 55.43, top5 = 48.99, top10 = 45.86, top15 = 43.84.
+OPT-1001 : End congestion update; 0.890754s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (105.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17688 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.695889s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.8%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6624 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6712 instances, 6563 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 756703, Over = 0
+PHY-3001 : Spreading special nets. 29 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061878s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.0%)
+
+PHY-3001 : 43 instances has been re-located, deltaX = 29, deltaY = 21, maxDist = 4.
+PHY-3001 : Final: Len = 757771, Over = 0
+PHY-3001 : End incremental legalization; 0.372811s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.6%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 58 cells processed and 20324 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6624 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6712 instances, 6563 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758617, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059234s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.5%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 18, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 758915, Over = 0
+PHY-3001 : End incremental legalization; 0.405218s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.4%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 2498 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6624 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6712 instances, 6563 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 757523, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060001s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.2%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 9, deltaY = 18, maxDist = 3.
+PHY-3001 : Final: Len = 757925, Over = 0
+PHY-3001 : End incremental legalization; 0.377791s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.3%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 18 cells processed and 1400 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6629 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6717 instances, 6568 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 758122, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065174s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.9%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758326, Over = 0
+PHY-3001 : End incremental legalization; 0.386854s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.0%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 4 cells processed and 600 slack improved
+OPT-1001 : End bottleneck based optimization; 3.695645s wall, 3.843750s user + 0.000000s system = 3.843750s CPU (104.0%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 736, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15892/17872.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929840, over cnt = 194(0%), over = 247, worst = 7
+PHY-1002 : len = 930184, over cnt = 98(0%), over = 103, worst = 2
+PHY-1002 : len = 930672, over cnt = 51(0%), over = 52, worst = 2
+PHY-1002 : len = 931312, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 931568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.901345s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.08, top10 = 45.95, top15 = 44.01.
+OPT-1001 : End congestion update; 1.216622s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (106.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17694 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.741054s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.1%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6629 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6717 instances, 6568 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 758084, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061950s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.9%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 7, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 758416, Over = 0
+PHY-3001 : End incremental legalization; 0.385178s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.4%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 2350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.476257s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (104.1%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 736, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17694 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.714238s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16262/17872.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 931536, over cnt = 61(0%), over = 67, worst = 3
+PHY-1002 : len = 931480, over cnt = 39(0%), over = 40, worst = 2
+PHY-1002 : len = 931672, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 931736, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 931872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.771044s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.3%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 49.28, top10 = 46.04, top15 = 44.05.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17694 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.712151s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.000000
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 20.435015s wall, 21.734375s user + 0.234375s system = 21.968750s CPU (107.5%)
+
+RUN-1003 : finish command "place" in 64.279428s wall, 93.421875s user + 5.500000s system = 98.921875s CPU (153.9%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 640 MB, peak memory is 743 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.680412s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (172.9%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 640 MB, peak memory is 743 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6719 instances
+RUN-1001 : 3285 mslices, 3283 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17872 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9979 nets have 2 pins
+RUN-1001 : 6465 nets have [3 - 5] pins
+RUN-1001 : 777 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 305 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71939, tnet num: 17694, tinst num: 6717, tnode num: 94231, tedge num: 119632.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.575135s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.2%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 658 MB, peak memory is 743 MB
+PHY-1001 : 3285 mslices, 3283 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17694 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 864640, over cnt = 2703(7%), over = 4350, worst = 8
+PHY-1002 : len = 879984, over cnt = 1742(4%), over = 2535, worst = 7
+PHY-1002 : len = 898640, over cnt = 788(2%), over = 1130, worst = 7
+PHY-1002 : len = 915592, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 915776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.004320s wall, 3.906250s user + 0.031250s system = 3.937500s CPU (131.1%)
+
+PHY-1001 : Congestion index: top1 = 55.11, top5 = 49.16, top10 = 45.83, top15 = 43.77.
+PHY-1001 : End global routing; 3.320956s wall, 4.218750s user + 0.031250s system = 4.250000s CPU (128.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 712, peak = 743.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 982, peak = 982.
+PHY-1001 : End build detailed router design. 3.928132s wall, 3.859375s user + 0.046875s system = 3.906250s CPU (99.4%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271160, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.175527s wall, 5.125000s user + 0.046875s system = 5.171875s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271216, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.427907s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.2%)
+
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1018, peak = 1017.
+PHY-1001 : End phase 1; 5.615085s wall, 5.562500s user + 0.046875s system = 5.609375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.29238e+06, over cnt = 1483(0%), over = 1492, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1034, reserve = 1033, peak = 1034.
+PHY-1001 : End initial routed; 29.422716s wall, 60.203125s user + 0.187500s system = 60.390625s CPU (205.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16795(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.197287s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1046, peak = 1045.
+PHY-1001 : End phase 2; 32.620069s wall, 63.406250s user + 0.187500s system = 63.593750s CPU (195.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.155761s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.3%)
+
+PHY-1022 : len = 2.29238e+06, over cnt = 1483(0%), over = 1492, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.407423s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26926e+06, over cnt = 477(0%), over = 478, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.073799s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (189.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.26772e+06, over cnt = 79(0%), over = 79, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.563922s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (149.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.26842e+06, over cnt = 14(0%), over = 14, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.303554s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (108.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.26863e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.200310s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (109.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.26869e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.200752s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (101.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.26865e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.249971s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.26866e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 7; 0.354443s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16795(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.212278s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 455 feed throughs used by 363 nets
+PHY-1001 : End commit to database; 2.184319s wall, 2.156250s user + 0.031250s system = 2.187500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1145, reserve = 1150, peak = 1145.
+PHY-1001 : End phase 3; 9.154224s wall, 10.390625s user + 0.046875s system = 10.437500s CPU (114.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.128846s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.0%)
+
+PHY-1022 : len = 2.26866e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.357781s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (96.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16795(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.144793s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 455 feed throughs used by 363 nets
+PHY-1001 : End commit to database; 2.273196s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1158, peak = 1154.
+PHY-1001 : End phase 4; 5.801650s wall, 5.796875s user + 0.000000s system = 5.796875s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.26866e+06
+PHY-1001 : Current memory(MB): used = 1155, reserve = 1160, peak = 1155.
+PHY-1001 : End export database. 0.059605s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.9%)
+
+PHY-1001 : End detail routing; 57.562032s wall, 89.468750s user + 0.328125s system = 89.796875s CPU (156.0%)
+
+RUN-1003 : finish command "route" in 63.505285s wall, 96.328125s user + 0.359375s system = 96.687500s CPU (152.3%)
+
+RUN-1004 : used memory is 1082 MB, reserved memory is 1083 MB, peak memory is 1155 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10214 out of 19600 52.11%
+#reg 9422 out of 19600 48.07%
+#le 12257
+ #lut only 2835 out of 12257 23.13%
+ #reg only 2043 out of 12257 16.67%
+ #lut® 7379 out of 12257 60.20%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 16
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1769
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1366
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1277
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 965
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 138
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg2_syn_239.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg63_syn_213.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P35 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P66 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P163 LVCMOS33 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE NONE
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P162 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P8 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P16 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12257 |9187 |1027 |9451 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |548 |453 |23 |459 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |115 |105 |4 |97 |4 |0 |
+| U_ecc_gen |ecc_gen |10 |10 |0 |7 |0 |0 |
+| U_crc16_24b |crc16_24b |22 |22 |0 |18 |0 |0 |
+| exdev_ctl_a |exdev_ctl |754 |371 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |188 |112 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |256 |139 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |373 |96 |567 |0 |0 |
+| u_ADconfig |AD_config |173 |127 |25 |125 |0 |0 |
+| u_gen_sp |gen_sp |254 |162 |71 |120 |0 |0 |
+| sampling_fe_a |sampling_fe |2855 |2310 |306 |2055 |25 |0 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |173 |109 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_sort |sort |2647 |2185 |289 |1876 |25 |0 |
+| rddpram_ctl |rddpram_ctl |3 |1 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2239 |1855 |253 |1531 |22 |0 |
+| channelPart |channel_part_8478 |146 |140 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |57 |48 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1737 |1432 |197 |1132 |0 |0 |
+| adc_addr_gen |adc_addr_gen |200 |172 |27 |118 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |6 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |958 |681 |170 |668 |0 |0 |
+| ram_switch_state |ram_switch_state |579 |579 |0 |346 |0 |0 |
+| read_ram_i |read_ram |271 |213 |44 |189 |0 |0 |
+| read_ram_addr |read_ram_addr |217 |177 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |45 |27 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |9 |9 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |334 |271 |36 |278 |3 |0 |
+| u0_soft_n |cdc_sync |14 |14 |0 |14 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3206 |2590 |349 |2069 |25 |1 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |174 |94 |17 |146 |0 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_sort |sort_rev |2999 |2477 |332 |1890 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2573 |2163 |290 |1535 |22 |1 |
+| channelPart |channel_part_8478 |144 |132 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1992 |1700 |197 |1120 |0 |0 |
+| adc_addr_gen |adc_addr_gen |206 |179 |27 |101 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| insert |insert |984 |719 |170 |664 |0 |0 |
+| ram_switch_state |ram_switch_state |802 |802 |0 |355 |0 |0 |
+| read_ram_i |read_ram_rev |349 |253 |81 |202 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |292 |207 |73 |161 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |46 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9917
+ #2 2 4259
+ #3 3 1681
+ #4 4 522
+ #5 5-10 827
+ #6 11-50 557
+ #7 51-100 13
+ #8 >500 1
+ Average 2.74
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.035187s wall, 3.515625s user + 0.031250s system = 3.546875s CPU (174.3%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1084 MB, peak memory is 1155 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71939, tnet num: 17694, tinst num: 6717, tnode num: 94231, tedge num: 119632.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.574057s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.3%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1089 MB, peak memory is 1155 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17694 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.439401s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (101.0%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1091 MB, peak memory is 1155 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6717
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17872, pip num: 168839
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 455
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3229 valid insts, and 470428 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.558172s wall, 64.984375s user + 0.203125s system = 65.187500s CPU (682.0%)
+
+RUN-1004 : used memory is 1182 MB, reserved memory is 1188 MB, peak memory is 1359 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_154943.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_163145.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_163145.log
new file mode 100644
index 0000000..9936c0d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_163145.log
@@ -0,0 +1,2037 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 16:31:45 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.322449s wall, 2.234375s user + 0.078125s system = 2.312500s CPU (99.6%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 316 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17986 instances
+RUN-0007 : 7661 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20564 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13082 nets have 2 pins
+RUN-1001 : 6444 nets have [3 - 5] pins
+RUN-1001 : 620 nets have [6 - 10] pins
+RUN-1001 : 181 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17984 instances, 7661 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.239410s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (97.1%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 514 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.080481s wall, 2.015625s user + 0.031250s system = 2.046875s CPU (98.4%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11825e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17984.
+PHY-3001 : Level 1 #clusters 2051.
+PHY-3001 : End clustering; 0.142429s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (153.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32681e+06, overlap = 447.375
+PHY-3002 : Step(2): len = 1.21277e+06, overlap = 492.031
+PHY-3002 : Step(3): len = 854256, overlap = 571.531
+PHY-3002 : Step(4): len = 796625, overlap = 595.094
+PHY-3002 : Step(5): len = 625051, overlap = 763.906
+PHY-3002 : Step(6): len = 553878, overlap = 846.75
+PHY-3002 : Step(7): len = 475465, overlap = 919.25
+PHY-3002 : Step(8): len = 435213, overlap = 966.5
+PHY-3002 : Step(9): len = 396311, overlap = 1029.19
+PHY-3002 : Step(10): len = 370878, overlap = 1031.53
+PHY-3002 : Step(11): len = 325662, overlap = 1075.22
+PHY-3002 : Step(12): len = 307603, overlap = 1115.06
+PHY-3002 : Step(13): len = 270358, overlap = 1170.19
+PHY-3002 : Step(14): len = 253854, overlap = 1221.72
+PHY-3002 : Step(15): len = 229490, overlap = 1275.16
+PHY-3002 : Step(16): len = 213861, overlap = 1309.06
+PHY-3002 : Step(17): len = 190508, overlap = 1330.88
+PHY-3002 : Step(18): len = 179455, overlap = 1361.78
+PHY-3002 : Step(19): len = 165284, overlap = 1392.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.31406e-06
+PHY-3002 : Step(20): len = 165466, overlap = 1346.91
+PHY-3002 : Step(21): len = 202919, overlap = 1205.69
+PHY-3002 : Step(22): len = 211139, overlap = 1153.94
+PHY-3002 : Step(23): len = 217503, overlap = 1084.84
+PHY-3002 : Step(24): len = 217194, overlap = 1057.38
+PHY-3002 : Step(25): len = 213766, overlap = 1039.53
+PHY-3002 : Step(26): len = 209686, overlap = 1019.31
+PHY-3002 : Step(27): len = 205682, overlap = 1025.91
+PHY-3002 : Step(28): len = 202366, overlap = 1025.41
+PHY-3002 : Step(29): len = 198815, overlap = 1041.31
+PHY-3002 : Step(30): len = 196891, overlap = 1048.53
+PHY-3002 : Step(31): len = 192947, overlap = 1032.38
+PHY-3002 : Step(32): len = 190652, overlap = 1028.38
+PHY-3002 : Step(33): len = 188982, overlap = 1047.53
+PHY-3002 : Step(34): len = 188856, overlap = 1050.19
+PHY-3002 : Step(35): len = 187822, overlap = 1046.66
+PHY-3002 : Step(36): len = 187691, overlap = 1043.84
+PHY-3002 : Step(37): len = 186699, overlap = 1045.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.62811e-06
+PHY-3002 : Step(38): len = 190190, overlap = 1023.97
+PHY-3002 : Step(39): len = 200878, overlap = 998
+PHY-3002 : Step(40): len = 204969, overlap = 973.031
+PHY-3002 : Step(41): len = 210699, overlap = 962.406
+PHY-3002 : Step(42): len = 213685, overlap = 962.031
+PHY-3002 : Step(43): len = 214913, overlap = 971.312
+PHY-3002 : Step(44): len = 214129, overlap = 962.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.25623e-06
+PHY-3002 : Step(45): len = 222317, overlap = 945.719
+PHY-3002 : Step(46): len = 241846, overlap = 887.062
+PHY-3002 : Step(47): len = 250733, overlap = 810.094
+PHY-3002 : Step(48): len = 259458, overlap = 764.75
+PHY-3002 : Step(49): len = 264898, overlap = 729.594
+PHY-3002 : Step(50): len = 268782, overlap = 717.594
+PHY-3002 : Step(51): len = 268659, overlap = 693.25
+PHY-3002 : Step(52): len = 267038, overlap = 699.969
+PHY-3002 : Step(53): len = 265608, overlap = 708.531
+PHY-3002 : Step(54): len = 263857, overlap = 714.938
+PHY-3002 : Step(55): len = 262442, overlap = 716.219
+PHY-3002 : Step(56): len = 261697, overlap = 712.75
+PHY-3002 : Step(57): len = 261651, overlap = 701.625
+PHY-3002 : Step(58): len = 261227, overlap = 706.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.05125e-05
+PHY-3002 : Step(59): len = 276346, overlap = 609.156
+PHY-3002 : Step(60): len = 291797, overlap = 571.688
+PHY-3002 : Step(61): len = 297779, overlap = 568.531
+PHY-3002 : Step(62): len = 301292, overlap = 564.406
+PHY-3002 : Step(63): len = 299531, overlap = 563.281
+PHY-3002 : Step(64): len = 300587, overlap = 555.219
+PHY-3002 : Step(65): len = 301742, overlap = 556.719
+PHY-3002 : Step(66): len = 303460, overlap = 538.031
+PHY-3002 : Step(67): len = 301977, overlap = 542.531
+PHY-3002 : Step(68): len = 300507, overlap = 528.469
+PHY-3002 : Step(69): len = 299876, overlap = 522.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.10249e-05
+PHY-3002 : Step(70): len = 318230, overlap = 482.656
+PHY-3002 : Step(71): len = 329376, overlap = 452.5
+PHY-3002 : Step(72): len = 333339, overlap = 419.688
+PHY-3002 : Step(73): len = 334752, overlap = 392.281
+PHY-3002 : Step(74): len = 333824, overlap = 357.469
+PHY-3002 : Step(75): len = 335637, overlap = 379.844
+PHY-3002 : Step(76): len = 334442, overlap = 390.5
+PHY-3002 : Step(77): len = 334205, overlap = 407.562
+PHY-3002 : Step(78): len = 334333, overlap = 392.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.20498e-05
+PHY-3002 : Step(79): len = 350059, overlap = 360.938
+PHY-3002 : Step(80): len = 361689, overlap = 339.031
+PHY-3002 : Step(81): len = 364498, overlap = 329.688
+PHY-3002 : Step(82): len = 368120, overlap = 324.688
+PHY-3002 : Step(83): len = 371135, overlap = 305.406
+PHY-3002 : Step(84): len = 373997, overlap = 280.5
+PHY-3002 : Step(85): len = 371594, overlap = 279.188
+PHY-3002 : Step(86): len = 373031, overlap = 280.469
+PHY-3002 : Step(87): len = 374790, overlap = 279.188
+PHY-3002 : Step(88): len = 376019, overlap = 266.062
+PHY-3002 : Step(89): len = 375474, overlap = 260.156
+PHY-3002 : Step(90): len = 377506, overlap = 264.469
+PHY-3002 : Step(91): len = 379997, overlap = 270.062
+PHY-3002 : Step(92): len = 381499, overlap = 250.094
+PHY-3002 : Step(93): len = 378396, overlap = 252.562
+PHY-3002 : Step(94): len = 378137, overlap = 257.031
+PHY-3002 : Step(95): len = 377776, overlap = 258.812
+PHY-3002 : Step(96): len = 378238, overlap = 260.094
+PHY-3002 : Step(97): len = 377541, overlap = 259.375
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.40997e-05
+PHY-3002 : Step(98): len = 393731, overlap = 263.688
+PHY-3002 : Step(99): len = 403714, overlap = 270.438
+PHY-3002 : Step(100): len = 402161, overlap = 260.656
+PHY-3002 : Step(101): len = 403139, overlap = 265.25
+PHY-3002 : Step(102): len = 406115, overlap = 263.562
+PHY-3002 : Step(103): len = 409921, overlap = 261.969
+PHY-3002 : Step(104): len = 409057, overlap = 261.656
+PHY-3002 : Step(105): len = 411247, overlap = 265.344
+PHY-3002 : Step(106): len = 415044, overlap = 267.875
+PHY-3002 : Step(107): len = 417805, overlap = 267
+PHY-3002 : Step(108): len = 414534, overlap = 279.844
+PHY-3002 : Step(109): len = 413890, overlap = 267.531
+PHY-3002 : Step(110): len = 415583, overlap = 257.938
+PHY-3002 : Step(111): len = 417219, overlap = 249.938
+PHY-3002 : Step(112): len = 413916, overlap = 234.875
+PHY-3002 : Step(113): len = 414176, overlap = 247.031
+PHY-3002 : Step(114): len = 415397, overlap = 239.5
+PHY-3002 : Step(115): len = 416638, overlap = 231.375
+PHY-3002 : Step(116): len = 414219, overlap = 227.656
+PHY-3002 : Step(117): len = 414070, overlap = 224.562
+PHY-3002 : Step(118): len = 415000, overlap = 225.969
+PHY-3002 : Step(119): len = 416356, overlap = 230.719
+PHY-3002 : Step(120): len = 414329, overlap = 243.5
+PHY-3002 : Step(121): len = 414525, overlap = 240.781
+PHY-3002 : Step(122): len = 415219, overlap = 251.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168199
+PHY-3002 : Step(123): len = 427793, overlap = 228.094
+PHY-3002 : Step(124): len = 434978, overlap = 211.5
+PHY-3002 : Step(125): len = 434224, overlap = 212.938
+PHY-3002 : Step(126): len = 434893, overlap = 214.719
+PHY-3002 : Step(127): len = 437387, overlap = 214.312
+PHY-3002 : Step(128): len = 440422, overlap = 218.344
+PHY-3002 : Step(129): len = 439475, overlap = 220.5
+PHY-3002 : Step(130): len = 439959, overlap = 218.125
+PHY-3002 : Step(131): len = 442104, overlap = 214.969
+PHY-3002 : Step(132): len = 443728, overlap = 215.188
+PHY-3002 : Step(133): len = 442552, overlap = 226.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000315424
+PHY-3002 : Step(134): len = 449199, overlap = 215
+PHY-3002 : Step(135): len = 456791, overlap = 208.969
+PHY-3002 : Step(136): len = 458741, overlap = 221.25
+PHY-3002 : Step(137): len = 460138, overlap = 210.938
+PHY-3002 : Step(138): len = 461978, overlap = 206.938
+PHY-3002 : Step(139): len = 463732, overlap = 200.469
+PHY-3002 : Step(140): len = 463075, overlap = 203.844
+PHY-3002 : Step(141): len = 464420, overlap = 206.25
+PHY-3002 : Step(142): len = 466826, overlap = 197.656
+PHY-3002 : Step(143): len = 468395, overlap = 196.719
+PHY-3002 : Step(144): len = 468161, overlap = 197.438
+PHY-3002 : Step(145): len = 468919, overlap = 193.844
+PHY-3002 : Step(146): len = 470408, overlap = 190.969
+PHY-3002 : Step(147): len = 471038, overlap = 194.094
+PHY-3002 : Step(148): len = 470098, overlap = 194.125
+PHY-3002 : Step(149): len = 469787, overlap = 192.844
+PHY-3002 : Step(150): len = 470962, overlap = 194.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000597386
+PHY-3002 : Step(151): len = 477356, overlap = 187.469
+PHY-3002 : Step(152): len = 485467, overlap = 177.438
+PHY-3002 : Step(153): len = 487792, overlap = 172.25
+PHY-3002 : Step(154): len = 489820, overlap = 169.969
+PHY-3002 : Step(155): len = 492289, overlap = 166.719
+PHY-3002 : Step(156): len = 494288, overlap = 161.812
+PHY-3002 : Step(157): len = 494621, overlap = 167.094
+PHY-3002 : Step(158): len = 495412, overlap = 158.875
+PHY-3002 : Step(159): len = 497530, overlap = 158.125
+PHY-3002 : Step(160): len = 499660, overlap = 161.844
+PHY-3002 : Step(161): len = 499659, overlap = 155.344
+PHY-3002 : Step(162): len = 500171, overlap = 145.469
+PHY-3002 : Step(163): len = 501354, overlap = 144.875
+PHY-3002 : Step(164): len = 502419, overlap = 141.625
+PHY-3002 : Step(165): len = 502507, overlap = 135.938
+PHY-3002 : Step(166): len = 502911, overlap = 136.219
+PHY-3002 : Step(167): len = 503441, overlap = 133.781
+PHY-3002 : Step(168): len = 503676, overlap = 133.844
+PHY-3002 : Step(169): len = 503613, overlap = 131.625
+PHY-3002 : Step(170): len = 503662, overlap = 133.656
+PHY-3002 : Step(171): len = 503864, overlap = 139.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108125
+PHY-3002 : Step(172): len = 508017, overlap = 138.406
+PHY-3002 : Step(173): len = 515100, overlap = 140.438
+PHY-3002 : Step(174): len = 516366, overlap = 136.719
+PHY-3002 : Step(175): len = 517528, overlap = 132.312
+PHY-3002 : Step(176): len = 519652, overlap = 132.719
+PHY-3002 : Step(177): len = 520672, overlap = 132.875
+PHY-3002 : Step(178): len = 520221, overlap = 132.375
+PHY-3002 : Step(179): len = 520126, overlap = 135.25
+PHY-3002 : Step(180): len = 521307, overlap = 133.188
+PHY-3002 : Step(181): len = 522214, overlap = 132.5
+PHY-3002 : Step(182): len = 521960, overlap = 133.5
+PHY-3002 : Step(183): len = 521951, overlap = 135.812
+PHY-3002 : Step(184): len = 522274, overlap = 134.25
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00187339
+PHY-3002 : Step(185): len = 525598, overlap = 136.688
+PHY-3002 : Step(186): len = 531982, overlap = 134.781
+PHY-3002 : Step(187): len = 533798, overlap = 129.438
+PHY-3002 : Step(188): len = 534889, overlap = 126.938
+PHY-3002 : Step(189): len = 535931, overlap = 126.094
+PHY-3002 : Step(190): len = 536614, overlap = 125.531
+PHY-3002 : Step(191): len = 537630, overlap = 128.594
+PHY-3002 : Step(192): len = 538953, overlap = 129.156
+PHY-3002 : Step(193): len = 539831, overlap = 128.594
+PHY-3002 : Step(194): len = 540970, overlap = 124.75
+PHY-3002 : Step(195): len = 542306, overlap = 125.406
+PHY-3002 : Step(196): len = 542817, overlap = 125.406
+PHY-3002 : Step(197): len = 543125, overlap = 123.969
+PHY-3002 : Step(198): len = 543331, overlap = 123.969
+PHY-3002 : Step(199): len = 543607, overlap = 125.344
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00307474
+PHY-3002 : Step(200): len = 546970, overlap = 124.781
+PHY-3002 : Step(201): len = 555249, overlap = 108.75
+PHY-3002 : Step(202): len = 560298, overlap = 101.938
+PHY-3002 : Step(203): len = 566036, overlap = 104.688
+PHY-3002 : Step(204): len = 569242, overlap = 103.969
+PHY-3002 : Step(205): len = 572082, overlap = 105.062
+PHY-3002 : Step(206): len = 573488, overlap = 100.906
+PHY-3002 : Step(207): len = 574436, overlap = 101.594
+PHY-3002 : Step(208): len = 574997, overlap = 98.375
+PHY-3002 : Step(209): len = 575327, overlap = 96.875
+PHY-3002 : Step(210): len = 575154, overlap = 96.2812
+PHY-3002 : Step(211): len = 574947, overlap = 90.3438
+PHY-3002 : Step(212): len = 574615, overlap = 96.1562
+PHY-3002 : Step(213): len = 574424, overlap = 96.1562
+PHY-3002 : Step(214): len = 574285, overlap = 91.1562
+PHY-3002 : Step(215): len = 574158, overlap = 90.1562
+PHY-3002 : Step(216): len = 573866, overlap = 87.6562
+PHY-3002 : Step(217): len = 573742, overlap = 90.125
+PHY-3002 : Step(218): len = 573607, overlap = 89.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.019382s wall, 0.046875s user + 0.031250s system = 0.078125s CPU (403.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753960, over cnt = 1673(4%), over = 7641, worst = 41
+PHY-1001 : End global iterations; 0.740556s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 63.38, top10 = 53.94, top15 = 48.26.
+PHY-3001 : End congestion estimation; 0.996619s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (130.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.907977s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012894
+PHY-3002 : Step(219): len = 682872, overlap = 60.7812
+PHY-3002 : Step(220): len = 680164, overlap = 61.5
+PHY-3002 : Step(221): len = 671439, overlap = 58.2812
+PHY-3002 : Step(222): len = 665226, overlap = 60.6875
+PHY-3002 : Step(223): len = 663081, overlap = 55.8438
+PHY-3002 : Step(224): len = 662916, overlap = 53.5938
+PHY-3002 : Step(225): len = 660482, overlap = 53.4375
+PHY-3002 : Step(226): len = 656745, overlap = 53.25
+PHY-3002 : Step(227): len = 653517, overlap = 53.7188
+PHY-3002 : Step(228): len = 651915, overlap = 50.4688
+PHY-3002 : Step(229): len = 650566, overlap = 43.9375
+PHY-3002 : Step(230): len = 649789, overlap = 39.6562
+PHY-3002 : Step(231): len = 649010, overlap = 39.6875
+PHY-3002 : Step(232): len = 648983, overlap = 36.4375
+PHY-3002 : Step(233): len = 648835, overlap = 39.7188
+PHY-3002 : Step(234): len = 649183, overlap = 37.0625
+PHY-3002 : Step(235): len = 647443, overlap = 37.6562
+PHY-3002 : Step(236): len = 646551, overlap = 37.75
+PHY-3002 : Step(237): len = 644304, overlap = 38.4688
+PHY-3002 : Step(238): len = 642657, overlap = 46.9062
+PHY-3002 : Step(239): len = 640494, overlap = 55.25
+PHY-3002 : Step(240): len = 638385, overlap = 57.375
+PHY-3002 : Step(241): len = 636246, overlap = 62.2812
+PHY-3002 : Step(242): len = 634318, overlap = 64.0625
+PHY-3002 : Step(243): len = 632554, overlap = 66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025788
+PHY-3002 : Step(244): len = 636935, overlap = 63.2812
+PHY-3002 : Step(245): len = 642468, overlap = 58.875
+PHY-3002 : Step(246): len = 644067, overlap = 55.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479888
+PHY-3002 : Step(247): len = 655065, overlap = 49.3125
+PHY-3002 : Step(248): len = 673391, overlap = 48.2188
+PHY-3002 : Step(249): len = 686922, overlap = 44.4375
+PHY-3002 : Step(250): len = 689884, overlap = 43.6875
+PHY-3002 : Step(251): len = 689070, overlap = 41.375
+PHY-3002 : Step(252): len = 686972, overlap = 40.5625
+PHY-3002 : Step(253): len = 686400, overlap = 38.8438
+PHY-3002 : Step(254): len = 686300, overlap = 37.125
+PHY-3002 : Step(255): len = 687195, overlap = 36.875
+PHY-3002 : Step(256): len = 688672, overlap = 36.3125
+PHY-3002 : Step(257): len = 687776, overlap = 38.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000959777
+PHY-3002 : Step(258): len = 693185, overlap = 37.9375
+PHY-3002 : Step(259): len = 707793, overlap = 42.5625
+PHY-3002 : Step(260): len = 721904, overlap = 45.25
+PHY-3002 : Step(261): len = 720538, overlap = 45.125
+PHY-3002 : Step(262): len = 718584, overlap = 47.0625
+PHY-3002 : Step(263): len = 718363, overlap = 47.125
+PHY-3002 : Step(264): len = 719234, overlap = 46.2812
+PHY-3002 : Step(265): len = 718781, overlap = 48.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00167098
+PHY-3002 : Step(266): len = 722104, overlap = 49.2188
+PHY-3002 : Step(267): len = 730523, overlap = 49.75
+PHY-3002 : Step(268): len = 737525, overlap = 49.1875
+PHY-3002 : Step(269): len = 740778, overlap = 49.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 74/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825680, over cnt = 2877(8%), over = 14308, worst = 47
+PHY-1001 : End global iterations; 1.663656s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 102.03, top5 = 79.19, top10 = 68.21, top15 = 61.55.
+PHY-3001 : End congestion estimation; 1.960735s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (129.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.960951s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124258
+PHY-3002 : Step(270): len = 725463, overlap = 236.562
+PHY-3002 : Step(271): len = 714675, overlap = 193.031
+PHY-3002 : Step(272): len = 701615, overlap = 166.75
+PHY-3002 : Step(273): len = 689587, overlap = 158.375
+PHY-3002 : Step(274): len = 680492, overlap = 144.562
+PHY-3002 : Step(275): len = 672516, overlap = 132.812
+PHY-3002 : Step(276): len = 666832, overlap = 120.75
+PHY-3002 : Step(277): len = 661263, overlap = 110.562
+PHY-3002 : Step(278): len = 655318, overlap = 116.375
+PHY-3002 : Step(279): len = 649278, overlap = 130
+PHY-3002 : Step(280): len = 643735, overlap = 130.25
+PHY-3002 : Step(281): len = 639232, overlap = 127.812
+PHY-3002 : Step(282): len = 634588, overlap = 129.969
+PHY-3002 : Step(283): len = 632464, overlap = 131.406
+PHY-3002 : Step(284): len = 628294, overlap = 126.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000248516
+PHY-3002 : Step(285): len = 629070, overlap = 123.781
+PHY-3002 : Step(286): len = 629965, overlap = 121.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000410701
+PHY-3002 : Step(287): len = 632475, overlap = 120.031
+PHY-3002 : Step(288): len = 642103, overlap = 112.312
+PHY-3002 : Step(289): len = 646065, overlap = 106.562
+PHY-3002 : Step(290): len = 643239, overlap = 108.25
+PHY-3002 : Step(291): len = 641402, overlap = 106.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000710718
+PHY-3002 : Step(292): len = 645464, overlap = 105.312
+PHY-3002 : Step(293): len = 650386, overlap = 94.7812
+PHY-3002 : Step(294): len = 655979, overlap = 89.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00142144
+PHY-3002 : Step(295): len = 657103, overlap = 88.4062
+PHY-3002 : Step(296): len = 661829, overlap = 85.6562
+PHY-3002 : Step(297): len = 669725, overlap = 77.25
+PHY-3002 : Step(298): len = 674047, overlap = 72.9375
+PHY-3002 : Step(299): len = 675876, overlap = 71.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.585437s wall, 1.515625s user + 0.062500s system = 1.578125s CPU (99.5%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 563 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 378.78 peak overflow 2.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 541/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777144, over cnt = 3139(8%), over = 11076, worst = 28
+PHY-1001 : End global iterations; 1.758682s wall, 2.375000s user + 0.062500s system = 2.437500s CPU (138.6%)
+
+PHY-1001 : Congestion index: top1 = 71.70, top5 = 58.36, top10 = 52.43, top15 = 48.72.
+PHY-1001 : End incremental global routing; 2.126086s wall, 2.734375s user + 0.062500s system = 2.796875s CPU (131.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.977597s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.7%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 318 needs to be replaced
+PHY-3001 : design contains 18256 instances, 7754 luts, 9281 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6080 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700079
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17267/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793176, over cnt = 3172(9%), over = 11083, worst = 28
+PHY-1001 : End global iterations; 0.272826s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (126.0%)
+
+PHY-1001 : Congestion index: top1 = 71.14, top5 = 58.22, top10 = 52.62, top15 = 49.03.
+PHY-3001 : End congestion estimation; 0.558362s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (114.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85043, tnet num: 20658, tinst num: 18256, tnode num: 115859, tedge num: 135500.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.554159s wall, 1.500000s user + 0.046875s system = 1.546875s CPU (99.5%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 633 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.580901s wall, 2.484375s user + 0.093750s system = 2.578125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(300): len = 699095, overlap = 0.1875
+PHY-3002 : Step(301): len = 698633, overlap = 0
+PHY-3002 : Step(302): len = 698393, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17369/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790720, over cnt = 3169(9%), over = 11146, worst = 28
+PHY-1001 : End global iterations; 0.223202s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (126.0%)
+
+PHY-1001 : Congestion index: top1 = 71.81, top5 = 58.63, top10 = 52.89, top15 = 49.25.
+PHY-3001 : End congestion estimation; 0.587043s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (111.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.023771s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000436837
+PHY-3002 : Step(303): len = 698158, overlap = 72.9375
+PHY-3002 : Step(304): len = 698336, overlap = 73.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000873674
+PHY-3002 : Step(305): len = 698525, overlap = 73.0625
+PHY-3002 : Step(306): len = 698983, overlap = 73.5625
+PHY-3001 : Final: Len = 698983, Over = 73.5625
+PHY-3001 : End incremental placement; 5.486746s wall, 5.718750s user + 0.296875s system = 6.015625s CPU (109.6%)
+
+OPT-1001 : Total overflow 384.31 peak overflow 2.78
+OPT-1001 : End high-fanout net optimization; 9.160029s wall, 10.078125s user + 0.375000s system = 10.453125s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 710, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17297/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793536, over cnt = 3069(8%), over = 10071, worst = 28
+PHY-1002 : len = 834904, over cnt = 2268(6%), over = 6024, worst = 23
+PHY-1002 : len = 878272, over cnt = 1104(3%), over = 2756, worst = 23
+PHY-1002 : len = 909920, over cnt = 279(0%), over = 702, worst = 13
+PHY-1002 : len = 919472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.988436s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (129.7%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.59, top10 = 48.02, top15 = 45.70.
+OPT-1001 : End congestion update; 2.289310s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (125.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.848347s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 119 cells processed and 18250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 53 cells processed and 6850 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1900 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 850 slack improved
+OPT-1001 : End bottleneck based optimization; 3.573096s wall, 4.140625s user + 0.015625s system = 4.156250s CPU (116.3%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 691, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17333/20842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920464, over cnt = 83(0%), over = 110, worst = 4
+PHY-1002 : len = 920512, over cnt = 40(0%), over = 43, worst = 3
+PHY-1002 : len = 920776, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 921040, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 921072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.783324s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (103.7%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 51.38, top10 = 47.82, top15 = 45.53.
+OPT-1001 : End congestion update; 1.079294s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (101.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.854043s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.057616s wall, 2.078125s user + 0.000000s system = 2.078125s CPU (101.0%)
+
+OPT-1001 : Current memory(MB): used = 707, reserve = 701, peak = 735.
+OPT-1001 : End physical optimization; 16.703205s wall, 18.203125s user + 0.500000s system = 18.703125s CPU (112.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7754 LUT to BLE ...
+SYN-4008 : Packed 7754 LUT and 3134 SEQ to BLE.
+SYN-4003 : Packing 6153 remaining SEQ's ...
+SYN-4005 : Packed 4101 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2052 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9806/13661 primitive instances ...
+PHY-3001 : End packing; 1.792377s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6670 instances
+RUN-1001 : 3261 mslices, 3261 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17832 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6509 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6668 instances, 6522 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3515 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 705686, Over = 204.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7445/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858864, over cnt = 2009(5%), over = 3264, worst = 8
+PHY-1002 : len = 867896, over cnt = 1189(3%), over = 1689, worst = 7
+PHY-1002 : len = 880112, over cnt = 514(1%), over = 700, worst = 6
+PHY-1002 : len = 887272, over cnt = 163(0%), over = 222, worst = 5
+PHY-1002 : len = 890768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.976495s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (143.9%)
+
+PHY-1001 : Congestion index: top1 = 57.39, top5 = 50.20, top10 = 46.73, top15 = 44.49.
+PHY-3001 : End congestion estimation; 2.421177s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (136.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6668, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.760982s wall, 1.750000s user + 0.015625s system = 1.765625s CPU (100.3%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 610 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.674776s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.26697e-05
+PHY-3002 : Step(307): len = 691602, overlap = 206
+PHY-3002 : Step(308): len = 683836, overlap = 205.25
+PHY-3002 : Step(309): len = 677655, overlap = 206.75
+PHY-3002 : Step(310): len = 672841, overlap = 216.25
+PHY-3002 : Step(311): len = 669449, overlap = 225
+PHY-3002 : Step(312): len = 666398, overlap = 225.25
+PHY-3002 : Step(313): len = 664858, overlap = 218.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000125339
+PHY-3002 : Step(314): len = 666869, overlap = 208.75
+PHY-3002 : Step(315): len = 670486, overlap = 203.75
+PHY-3002 : Step(316): len = 671644, overlap = 199.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000250679
+PHY-3002 : Step(317): len = 677534, overlap = 198.25
+PHY-3002 : Step(318): len = 684375, overlap = 186.75
+PHY-3002 : Step(319): len = 684183, overlap = 186.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.424381s wall, 0.312500s user + 0.640625s system = 0.953125s CPU (224.6%)
+
+PHY-3001 : Trial Legalized: Len = 757719
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 975/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872424, over cnt = 2646(7%), over = 4451, worst = 7
+PHY-1002 : len = 892264, over cnt = 1457(4%), over = 2022, worst = 7
+PHY-1002 : len = 912312, over cnt = 398(1%), over = 525, worst = 5
+PHY-1002 : len = 919384, over cnt = 79(0%), over = 100, worst = 5
+PHY-1002 : len = 921248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.716991s wall, 3.968750s user + 0.078125s system = 4.046875s CPU (148.9%)
+
+PHY-1001 : Congestion index: top1 = 56.68, top5 = 50.88, top10 = 47.48, top15 = 45.26.
+PHY-3001 : End congestion estimation; 3.215627s wall, 4.453125s user + 0.093750s system = 4.546875s CPU (141.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.897516s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171654
+PHY-3002 : Step(320): len = 732552, overlap = 37.25
+PHY-3002 : Step(321): len = 717815, overlap = 56.75
+PHY-3002 : Step(322): len = 705260, overlap = 79.75
+PHY-3002 : Step(323): len = 697585, overlap = 105.75
+PHY-3002 : Step(324): len = 692369, overlap = 121
+PHY-3002 : Step(325): len = 690073, overlap = 130.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343309
+PHY-3002 : Step(326): len = 694281, overlap = 126.5
+PHY-3002 : Step(327): len = 698775, overlap = 122.25
+PHY-3002 : Step(328): len = 700530, overlap = 125.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000686617
+PHY-3002 : Step(329): len = 703663, overlap = 123.75
+PHY-3002 : Step(330): len = 708517, overlap = 120.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034961s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.4%)
+
+PHY-3001 : Legalized: Len = 735420, Over = 0
+PHY-3001 : Spreading special nets. 441 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.102520s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (91.4%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 183, deltaY = 345, maxDist = 2.
+PHY-3001 : Final: Len = 744855, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6671, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.018406s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (99.9%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 641 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4683/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874512, over cnt = 2464(7%), over = 3852, worst = 8
+PHY-1002 : len = 886000, over cnt = 1564(4%), over = 2201, worst = 6
+PHY-1002 : len = 906104, over cnt = 411(1%), over = 514, worst = 5
+PHY-1002 : len = 913792, over cnt = 70(0%), over = 85, worst = 5
+PHY-1002 : len = 915416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.352952s wall, 3.250000s user + 0.031250s system = 3.281250s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.95, top10 = 46.69, top15 = 44.63.
+PHY-1001 : End incremental global routing; 2.766610s wall, 3.656250s user + 0.031250s system = 3.687500s CPU (133.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.923106s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.9%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6579 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750654
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16211/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922952, over cnt = 103(0%), over = 140, worst = 8
+PHY-1002 : len = 923128, over cnt = 58(0%), over = 74, worst = 8
+PHY-1002 : len = 923920, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 924112, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 924224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.857271s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (109.4%)
+
+PHY-1001 : Congestion index: top1 = 56.29, top5 = 50.12, top10 = 46.94, top15 = 44.88.
+PHY-3001 : End congestion estimation; 1.197988s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (105.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71542, tnet num: 17675, tinst num: 6692, tnode num: 93911, tedge num: 118783.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.967910s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (100.0%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 660 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.944297s wall, 2.921875s user + 0.031250s system = 2.953125s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(331): len = 748232, overlap = 0
+PHY-3002 : Step(332): len = 747363, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16198/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919288, over cnt = 71(0%), over = 97, worst = 4
+PHY-1002 : len = 919528, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 920032, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 920080, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 920112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.877949s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.97, top10 = 46.77, top15 = 44.70.
+PHY-3001 : End congestion estimation; 1.234682s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (102.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.911387s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000157527
+PHY-3002 : Step(333): len = 747253, overlap = 1
+PHY-3002 : Step(334): len = 747381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005432s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (287.7%)
+
+PHY-3001 : Legalized: Len = 747516, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062437s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 747582, Over = 0
+PHY-3001 : End incremental placement; 6.803832s wall, 7.031250s user + 0.109375s system = 7.140625s CPU (105.0%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.011350s wall, 12.125000s user + 0.156250s system = 12.281250s CPU (111.5%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 734, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16175/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919680, over cnt = 54(0%), over = 70, worst = 4
+PHY-1002 : len = 919672, over cnt = 35(0%), over = 44, worst = 3
+PHY-1002 : len = 920096, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 920168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.657958s wall, 0.656250s user + 0.046875s system = 0.703125s CPU (106.9%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.95, top10 = 46.76, top15 = 44.70.
+OPT-1001 : End congestion update; 0.994383s wall, 0.984375s user + 0.046875s system = 1.031250s CPU (103.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.764583s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.1%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 756770, Over = 0
+PHY-3001 : Spreading special nets. 30 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065105s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.0%)
+
+PHY-3001 : 41 instances has been re-located, deltaX = 12, deltaY = 27, maxDist = 3.
+PHY-3001 : Final: Len = 757514, Over = 0
+PHY-3001 : End incremental legalization; 0.405870s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 60 cells processed and 22074 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758204, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063992s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.7%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 16, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758608, Over = 0
+PHY-3001 : End incremental legalization; 0.441933s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (116.7%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 4156 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758812, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066494s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 7, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 759358, Over = 0
+PHY-3001 : End incremental legalization; 0.416608s wall, 0.531250s user + 0.015625s system = 0.546875s CPU (131.3%)
+
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 18 cells processed and 1161 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759597, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066666s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.8%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 759599, Over = 0
+PHY-3001 : End incremental legalization; 0.409412s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization; 4.106607s wall, 4.265625s user + 0.078125s system = 4.343750s CPU (105.8%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 735, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15721/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930944, over cnt = 193(0%), over = 264, worst = 6
+PHY-1002 : len = 931160, over cnt = 92(0%), over = 103, worst = 3
+PHY-1002 : len = 931928, over cnt = 35(0%), over = 35, worst = 1
+PHY-1002 : len = 932424, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932504, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.932100s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (107.3%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 49.54, top10 = 46.48, top15 = 44.48.
+OPT-1001 : End congestion update; 1.280034s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (105.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.768811s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (101.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759705, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062653s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 759739, Over = 0
+PHY-3001 : End incremental legalization; 0.407496s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (103.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.589283s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (102.6%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 735, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.774464s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16201/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932536, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 932560, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 932624, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 932744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 932808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.853860s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.58, top10 = 46.48, top15 = 44.49.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.771634s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.764081s wall, 24.062500s user + 0.281250s system = 24.343750s CPU (106.9%)
+
+RUN-1003 : finish command "place" in 72.134056s wall, 107.078125s user + 7.906250s system = 114.984375s CPU (159.4%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 598 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.828192s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (170.1%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 599 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6701 instances
+RUN-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17857 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 734 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.681647s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (99.4%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 629 MB, peak memory is 737 MB
+PHY-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862800, over cnt = 2648(7%), over = 4341, worst = 9
+PHY-1002 : len = 880744, over cnt = 1618(4%), over = 2343, worst = 9
+PHY-1002 : len = 903616, over cnt = 451(1%), over = 577, worst = 6
+PHY-1002 : len = 912696, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 913024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.418806s wall, 4.390625s user + 0.031250s system = 4.421875s CPU (129.3%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.00, top10 = 45.84, top15 = 43.81.
+PHY-1001 : End global routing; 3.776772s wall, 4.765625s user + 0.031250s system = 4.796875s CPU (127.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 710, reserve = 712, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 980, reserve = 980, peak = 980.
+PHY-1001 : End build detailed router design. 4.286816s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270736, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.698600s wall, 5.656250s user + 0.015625s system = 5.671875s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270792, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.488633s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (102.3%)
+
+PHY-1001 : Current memory(MB): used = 1016, reserve = 1017, peak = 1016.
+PHY-1001 : End phase 1; 6.198803s wall, 6.156250s user + 0.015625s system = 6.171875s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1032, peak = 1032.
+PHY-1001 : End initial routed; 37.692483s wall, 71.281250s user + 0.375000s system = 71.656250s CPU (190.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.482652s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1043, reserve = 1044, peak = 1043.
+PHY-1001 : End phase 2; 41.175197s wall, 74.750000s user + 0.375000s system = 75.125000s CPU (182.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.137882s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.0%)
+
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.424315s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26109e+06, over cnt = 626(0%), over = 627, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.460389s wall, 2.484375s user + 0.015625s system = 2.500000s CPU (171.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25966e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.714768s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (150.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25927e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.475279s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (105.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25919e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.330914s wall, 0.375000s user + 0.031250s system = 0.406250s CPU (122.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.256207s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (103.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.471838s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.394699s wall, 2.343750s user + 0.046875s system = 2.390625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1144, reserve = 1149, peak = 1144.
+PHY-1001 : End phase 3; 9.947913s wall, 11.359375s user + 0.109375s system = 11.468750s CPU (115.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.144384s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.402129s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.449807s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.485473s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1157, peak = 1152.
+PHY-1001 : End phase 4; 6.362721s wall, 6.343750s user + 0.000000s system = 6.343750s CPU (99.7%)
+
+PHY-1003 : Routed, final wirelength = 2.25928e+06
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1159, peak = 1154.
+PHY-1001 : End export database. 0.156529s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.8%)
+
+PHY-1001 : End detail routing; 68.552313s wall, 103.421875s user + 0.546875s system = 103.968750s CPU (151.7%)
+
+RUN-1003 : finish command "route" in 75.452522s wall, 111.281250s user + 0.609375s system = 111.890625s CPU (148.3%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1082 MB, peak memory is 1155 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10187 out of 19600 51.97%
+#reg 9425 out of 19600 48.09%
+#le 12209
+ #lut only 2784 out of 12209 22.80%
+ #reg only 2022 out of 12209 16.56%
+ #lut® 7403 out of 12209 60.64%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1380
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1287
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 961
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 131
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_307.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P170 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12209 |9160 |1027 |9456 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |457 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |97 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |42 |42 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |759 |371 |96 |575 |0 |0 |
+| u_ADconfig |AD_config |187 |121 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |260 |165 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |384 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |173 |121 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |254 |145 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2935 |2382 |306 |2076 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |170 |93 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort |2735 |2268 |289 |1906 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2326 |1968 |253 |1555 |22 |0 |
+| channelPart |channel_part_8478 |141 |135 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |50 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1807 |1513 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |208 |181 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |961 |694 |170 |656 |0 |0 |
+| ram_switch_state |ram_switch_state |638 |638 |0 |372 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |48 |41 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |235 |36 |273 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3122 |2458 |349 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |115 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2917 |2332 |332 |1914 |25 |1 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2476 |1975 |290 |1550 |22 |1 |
+| channelPart |channel_part_8478 |130 |124 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1909 |1532 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |202 |174 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |1003 |657 |170 |701 |0 |0 |
+| ram_switch_state |ram_switch_state |704 |701 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |352 |251 |81 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |162 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |41 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9896
+ #2 2 4222
+ #3 3 1721
+ #4 4 562
+ #5 5-10 766
+ #6 11-50 583
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.182456s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (171.8%)
+
+RUN-1004 : used memory is 1082 MB, reserved memory is 1083 MB, peak memory is 1155 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.697505s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (99.4%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1088 MB, peak memory is 1155 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.547356s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.0%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1092 MB, peak memory is 1155 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6699
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17857, pip num: 168201
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 529
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3230 valid insts, and 469612 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.082232s wall, 67.500000s user + 0.234375s system = 67.734375s CPU (671.8%)
+
+RUN-1004 : used memory is 1239 MB, reserved memory is 1240 MB, peak memory is 1358 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_163145.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_164220.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_164220.log
new file mode 100644
index 0000000..2578afe
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_164220.log
@@ -0,0 +1,2037 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 16:42:21 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.315226s wall, 2.250000s user + 0.062500s system = 2.312500s CPU (99.9%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 316 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17986 instances
+RUN-0007 : 7661 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20564 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13082 nets have 2 pins
+RUN-1001 : 6444 nets have [3 - 5] pins
+RUN-1001 : 620 nets have [6 - 10] pins
+RUN-1001 : 181 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17984 instances, 7661 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.270990s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (100.8%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 514 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.114177s wall, 2.078125s user + 0.046875s system = 2.125000s CPU (100.5%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11825e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17984.
+PHY-3001 : Level 1 #clusters 2051.
+PHY-3001 : End clustering; 0.266223s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (111.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32681e+06, overlap = 447.375
+PHY-3002 : Step(2): len = 1.21277e+06, overlap = 492.031
+PHY-3002 : Step(3): len = 854256, overlap = 571.531
+PHY-3002 : Step(4): len = 796625, overlap = 595.094
+PHY-3002 : Step(5): len = 625051, overlap = 763.906
+PHY-3002 : Step(6): len = 553878, overlap = 846.75
+PHY-3002 : Step(7): len = 475465, overlap = 919.25
+PHY-3002 : Step(8): len = 435213, overlap = 966.5
+PHY-3002 : Step(9): len = 396311, overlap = 1029.19
+PHY-3002 : Step(10): len = 370878, overlap = 1031.53
+PHY-3002 : Step(11): len = 325662, overlap = 1075.22
+PHY-3002 : Step(12): len = 307603, overlap = 1115.06
+PHY-3002 : Step(13): len = 270358, overlap = 1170.19
+PHY-3002 : Step(14): len = 253854, overlap = 1221.72
+PHY-3002 : Step(15): len = 229490, overlap = 1275.16
+PHY-3002 : Step(16): len = 213861, overlap = 1309.06
+PHY-3002 : Step(17): len = 190508, overlap = 1330.88
+PHY-3002 : Step(18): len = 179455, overlap = 1361.78
+PHY-3002 : Step(19): len = 165284, overlap = 1392.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.31406e-06
+PHY-3002 : Step(20): len = 165466, overlap = 1346.91
+PHY-3002 : Step(21): len = 202919, overlap = 1205.69
+PHY-3002 : Step(22): len = 211139, overlap = 1153.94
+PHY-3002 : Step(23): len = 217503, overlap = 1084.84
+PHY-3002 : Step(24): len = 217194, overlap = 1057.38
+PHY-3002 : Step(25): len = 213766, overlap = 1039.53
+PHY-3002 : Step(26): len = 209686, overlap = 1019.31
+PHY-3002 : Step(27): len = 205682, overlap = 1025.91
+PHY-3002 : Step(28): len = 202366, overlap = 1025.41
+PHY-3002 : Step(29): len = 198815, overlap = 1041.31
+PHY-3002 : Step(30): len = 196891, overlap = 1048.53
+PHY-3002 : Step(31): len = 192947, overlap = 1032.38
+PHY-3002 : Step(32): len = 190652, overlap = 1028.38
+PHY-3002 : Step(33): len = 188982, overlap = 1047.53
+PHY-3002 : Step(34): len = 188856, overlap = 1050.19
+PHY-3002 : Step(35): len = 187822, overlap = 1046.66
+PHY-3002 : Step(36): len = 187691, overlap = 1043.84
+PHY-3002 : Step(37): len = 186699, overlap = 1045.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.62811e-06
+PHY-3002 : Step(38): len = 190190, overlap = 1023.97
+PHY-3002 : Step(39): len = 200878, overlap = 998
+PHY-3002 : Step(40): len = 204969, overlap = 973.031
+PHY-3002 : Step(41): len = 210699, overlap = 962.406
+PHY-3002 : Step(42): len = 213685, overlap = 962.031
+PHY-3002 : Step(43): len = 214913, overlap = 971.312
+PHY-3002 : Step(44): len = 214129, overlap = 962.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.25623e-06
+PHY-3002 : Step(45): len = 222317, overlap = 945.719
+PHY-3002 : Step(46): len = 241846, overlap = 887.062
+PHY-3002 : Step(47): len = 250733, overlap = 810.094
+PHY-3002 : Step(48): len = 259458, overlap = 764.75
+PHY-3002 : Step(49): len = 264898, overlap = 729.594
+PHY-3002 : Step(50): len = 268782, overlap = 717.594
+PHY-3002 : Step(51): len = 268659, overlap = 693.25
+PHY-3002 : Step(52): len = 267038, overlap = 699.969
+PHY-3002 : Step(53): len = 265608, overlap = 708.531
+PHY-3002 : Step(54): len = 263857, overlap = 714.938
+PHY-3002 : Step(55): len = 262442, overlap = 716.219
+PHY-3002 : Step(56): len = 261697, overlap = 712.75
+PHY-3002 : Step(57): len = 261651, overlap = 701.625
+PHY-3002 : Step(58): len = 261227, overlap = 706.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.05125e-05
+PHY-3002 : Step(59): len = 276346, overlap = 609.156
+PHY-3002 : Step(60): len = 291797, overlap = 571.688
+PHY-3002 : Step(61): len = 297779, overlap = 568.531
+PHY-3002 : Step(62): len = 301292, overlap = 564.406
+PHY-3002 : Step(63): len = 299531, overlap = 563.281
+PHY-3002 : Step(64): len = 300587, overlap = 555.219
+PHY-3002 : Step(65): len = 301742, overlap = 556.719
+PHY-3002 : Step(66): len = 303460, overlap = 538.031
+PHY-3002 : Step(67): len = 301977, overlap = 542.531
+PHY-3002 : Step(68): len = 300507, overlap = 528.469
+PHY-3002 : Step(69): len = 299876, overlap = 522.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.10249e-05
+PHY-3002 : Step(70): len = 318230, overlap = 482.656
+PHY-3002 : Step(71): len = 329376, overlap = 452.5
+PHY-3002 : Step(72): len = 333339, overlap = 419.688
+PHY-3002 : Step(73): len = 334752, overlap = 392.281
+PHY-3002 : Step(74): len = 333824, overlap = 357.469
+PHY-3002 : Step(75): len = 335637, overlap = 379.844
+PHY-3002 : Step(76): len = 334442, overlap = 390.5
+PHY-3002 : Step(77): len = 334205, overlap = 407.562
+PHY-3002 : Step(78): len = 334333, overlap = 392.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.20498e-05
+PHY-3002 : Step(79): len = 350059, overlap = 360.938
+PHY-3002 : Step(80): len = 361689, overlap = 339.031
+PHY-3002 : Step(81): len = 364498, overlap = 329.688
+PHY-3002 : Step(82): len = 368120, overlap = 324.688
+PHY-3002 : Step(83): len = 371135, overlap = 305.406
+PHY-3002 : Step(84): len = 373997, overlap = 280.5
+PHY-3002 : Step(85): len = 371594, overlap = 279.188
+PHY-3002 : Step(86): len = 373031, overlap = 280.469
+PHY-3002 : Step(87): len = 374790, overlap = 279.188
+PHY-3002 : Step(88): len = 376019, overlap = 266.062
+PHY-3002 : Step(89): len = 375474, overlap = 260.156
+PHY-3002 : Step(90): len = 377506, overlap = 264.469
+PHY-3002 : Step(91): len = 379997, overlap = 270.062
+PHY-3002 : Step(92): len = 381499, overlap = 250.094
+PHY-3002 : Step(93): len = 378396, overlap = 252.562
+PHY-3002 : Step(94): len = 378137, overlap = 257.031
+PHY-3002 : Step(95): len = 377776, overlap = 258.812
+PHY-3002 : Step(96): len = 378238, overlap = 260.094
+PHY-3002 : Step(97): len = 377541, overlap = 259.375
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.40997e-05
+PHY-3002 : Step(98): len = 393731, overlap = 263.688
+PHY-3002 : Step(99): len = 403714, overlap = 270.438
+PHY-3002 : Step(100): len = 402161, overlap = 260.656
+PHY-3002 : Step(101): len = 403139, overlap = 265.25
+PHY-3002 : Step(102): len = 406115, overlap = 263.562
+PHY-3002 : Step(103): len = 409921, overlap = 261.969
+PHY-3002 : Step(104): len = 409057, overlap = 261.656
+PHY-3002 : Step(105): len = 411247, overlap = 265.344
+PHY-3002 : Step(106): len = 415044, overlap = 267.875
+PHY-3002 : Step(107): len = 417805, overlap = 267
+PHY-3002 : Step(108): len = 414534, overlap = 279.844
+PHY-3002 : Step(109): len = 413890, overlap = 267.531
+PHY-3002 : Step(110): len = 415583, overlap = 257.938
+PHY-3002 : Step(111): len = 417219, overlap = 249.938
+PHY-3002 : Step(112): len = 413916, overlap = 234.875
+PHY-3002 : Step(113): len = 414176, overlap = 247.031
+PHY-3002 : Step(114): len = 415397, overlap = 239.5
+PHY-3002 : Step(115): len = 416638, overlap = 231.375
+PHY-3002 : Step(116): len = 414219, overlap = 227.656
+PHY-3002 : Step(117): len = 414070, overlap = 224.562
+PHY-3002 : Step(118): len = 415000, overlap = 225.969
+PHY-3002 : Step(119): len = 416356, overlap = 230.719
+PHY-3002 : Step(120): len = 414329, overlap = 243.5
+PHY-3002 : Step(121): len = 414525, overlap = 240.781
+PHY-3002 : Step(122): len = 415219, overlap = 251.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168199
+PHY-3002 : Step(123): len = 427793, overlap = 228.094
+PHY-3002 : Step(124): len = 434978, overlap = 211.5
+PHY-3002 : Step(125): len = 434224, overlap = 212.938
+PHY-3002 : Step(126): len = 434893, overlap = 214.719
+PHY-3002 : Step(127): len = 437387, overlap = 214.312
+PHY-3002 : Step(128): len = 440422, overlap = 218.344
+PHY-3002 : Step(129): len = 439475, overlap = 220.5
+PHY-3002 : Step(130): len = 439959, overlap = 218.125
+PHY-3002 : Step(131): len = 442104, overlap = 214.969
+PHY-3002 : Step(132): len = 443728, overlap = 215.188
+PHY-3002 : Step(133): len = 442552, overlap = 226.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000315424
+PHY-3002 : Step(134): len = 449199, overlap = 215
+PHY-3002 : Step(135): len = 456791, overlap = 208.969
+PHY-3002 : Step(136): len = 458741, overlap = 221.25
+PHY-3002 : Step(137): len = 460138, overlap = 210.938
+PHY-3002 : Step(138): len = 461978, overlap = 206.938
+PHY-3002 : Step(139): len = 463732, overlap = 200.469
+PHY-3002 : Step(140): len = 463075, overlap = 203.844
+PHY-3002 : Step(141): len = 464420, overlap = 206.25
+PHY-3002 : Step(142): len = 466826, overlap = 197.656
+PHY-3002 : Step(143): len = 468395, overlap = 196.719
+PHY-3002 : Step(144): len = 468161, overlap = 197.438
+PHY-3002 : Step(145): len = 468919, overlap = 193.844
+PHY-3002 : Step(146): len = 470408, overlap = 190.969
+PHY-3002 : Step(147): len = 471038, overlap = 194.094
+PHY-3002 : Step(148): len = 470098, overlap = 194.125
+PHY-3002 : Step(149): len = 469787, overlap = 192.844
+PHY-3002 : Step(150): len = 470962, overlap = 194.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000597386
+PHY-3002 : Step(151): len = 477356, overlap = 187.469
+PHY-3002 : Step(152): len = 485467, overlap = 177.438
+PHY-3002 : Step(153): len = 487792, overlap = 172.25
+PHY-3002 : Step(154): len = 489820, overlap = 169.969
+PHY-3002 : Step(155): len = 492289, overlap = 166.719
+PHY-3002 : Step(156): len = 494288, overlap = 161.812
+PHY-3002 : Step(157): len = 494621, overlap = 167.094
+PHY-3002 : Step(158): len = 495412, overlap = 158.875
+PHY-3002 : Step(159): len = 497530, overlap = 158.125
+PHY-3002 : Step(160): len = 499660, overlap = 161.844
+PHY-3002 : Step(161): len = 499659, overlap = 155.344
+PHY-3002 : Step(162): len = 500171, overlap = 145.469
+PHY-3002 : Step(163): len = 501354, overlap = 144.875
+PHY-3002 : Step(164): len = 502419, overlap = 141.625
+PHY-3002 : Step(165): len = 502507, overlap = 135.938
+PHY-3002 : Step(166): len = 502911, overlap = 136.219
+PHY-3002 : Step(167): len = 503441, overlap = 133.781
+PHY-3002 : Step(168): len = 503676, overlap = 133.844
+PHY-3002 : Step(169): len = 503613, overlap = 131.625
+PHY-3002 : Step(170): len = 503662, overlap = 133.656
+PHY-3002 : Step(171): len = 503864, overlap = 139.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108125
+PHY-3002 : Step(172): len = 508017, overlap = 138.406
+PHY-3002 : Step(173): len = 515100, overlap = 140.438
+PHY-3002 : Step(174): len = 516366, overlap = 136.719
+PHY-3002 : Step(175): len = 517528, overlap = 132.312
+PHY-3002 : Step(176): len = 519652, overlap = 132.719
+PHY-3002 : Step(177): len = 520672, overlap = 132.875
+PHY-3002 : Step(178): len = 520221, overlap = 132.375
+PHY-3002 : Step(179): len = 520126, overlap = 135.25
+PHY-3002 : Step(180): len = 521307, overlap = 133.188
+PHY-3002 : Step(181): len = 522214, overlap = 132.5
+PHY-3002 : Step(182): len = 521960, overlap = 133.5
+PHY-3002 : Step(183): len = 521951, overlap = 135.812
+PHY-3002 : Step(184): len = 522274, overlap = 134.25
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00187339
+PHY-3002 : Step(185): len = 525598, overlap = 136.688
+PHY-3002 : Step(186): len = 531982, overlap = 134.781
+PHY-3002 : Step(187): len = 533798, overlap = 129.438
+PHY-3002 : Step(188): len = 534889, overlap = 126.938
+PHY-3002 : Step(189): len = 535931, overlap = 126.094
+PHY-3002 : Step(190): len = 536614, overlap = 125.531
+PHY-3002 : Step(191): len = 537630, overlap = 128.594
+PHY-3002 : Step(192): len = 538953, overlap = 129.156
+PHY-3002 : Step(193): len = 539831, overlap = 128.594
+PHY-3002 : Step(194): len = 540970, overlap = 124.75
+PHY-3002 : Step(195): len = 542306, overlap = 125.406
+PHY-3002 : Step(196): len = 542817, overlap = 125.406
+PHY-3002 : Step(197): len = 543125, overlap = 123.969
+PHY-3002 : Step(198): len = 543331, overlap = 123.969
+PHY-3002 : Step(199): len = 543607, overlap = 125.344
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00307474
+PHY-3002 : Step(200): len = 546970, overlap = 124.781
+PHY-3002 : Step(201): len = 555249, overlap = 108.75
+PHY-3002 : Step(202): len = 560298, overlap = 101.938
+PHY-3002 : Step(203): len = 566036, overlap = 104.688
+PHY-3002 : Step(204): len = 569242, overlap = 103.969
+PHY-3002 : Step(205): len = 572082, overlap = 105.062
+PHY-3002 : Step(206): len = 573488, overlap = 100.906
+PHY-3002 : Step(207): len = 574436, overlap = 101.594
+PHY-3002 : Step(208): len = 574997, overlap = 98.375
+PHY-3002 : Step(209): len = 575327, overlap = 96.875
+PHY-3002 : Step(210): len = 575154, overlap = 96.2812
+PHY-3002 : Step(211): len = 574947, overlap = 90.3438
+PHY-3002 : Step(212): len = 574615, overlap = 96.1562
+PHY-3002 : Step(213): len = 574424, overlap = 96.1562
+PHY-3002 : Step(214): len = 574285, overlap = 91.1562
+PHY-3002 : Step(215): len = 574158, overlap = 90.1562
+PHY-3002 : Step(216): len = 573866, overlap = 87.6562
+PHY-3002 : Step(217): len = 573742, overlap = 90.125
+PHY-3002 : Step(218): len = 573607, overlap = 89.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015064s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (103.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753960, over cnt = 1673(4%), over = 7641, worst = 41
+PHY-1001 : End global iterations; 0.758657s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 63.38, top10 = 53.94, top15 = 48.26.
+PHY-3001 : End congestion estimation; 1.019166s wall, 1.312500s user + 0.031250s system = 1.343750s CPU (131.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.121834s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012894
+PHY-3002 : Step(219): len = 682872, overlap = 60.7812
+PHY-3002 : Step(220): len = 680164, overlap = 61.5
+PHY-3002 : Step(221): len = 671439, overlap = 58.2812
+PHY-3002 : Step(222): len = 665226, overlap = 60.6875
+PHY-3002 : Step(223): len = 663081, overlap = 55.8438
+PHY-3002 : Step(224): len = 662916, overlap = 53.5938
+PHY-3002 : Step(225): len = 660482, overlap = 53.4375
+PHY-3002 : Step(226): len = 656745, overlap = 53.25
+PHY-3002 : Step(227): len = 653517, overlap = 53.7188
+PHY-3002 : Step(228): len = 651915, overlap = 50.4688
+PHY-3002 : Step(229): len = 650566, overlap = 43.9375
+PHY-3002 : Step(230): len = 649789, overlap = 39.6562
+PHY-3002 : Step(231): len = 649010, overlap = 39.6875
+PHY-3002 : Step(232): len = 648983, overlap = 36.4375
+PHY-3002 : Step(233): len = 648835, overlap = 39.7188
+PHY-3002 : Step(234): len = 649183, overlap = 37.0625
+PHY-3002 : Step(235): len = 647443, overlap = 37.6562
+PHY-3002 : Step(236): len = 646551, overlap = 37.75
+PHY-3002 : Step(237): len = 644304, overlap = 38.4688
+PHY-3002 : Step(238): len = 642657, overlap = 46.9062
+PHY-3002 : Step(239): len = 640494, overlap = 55.25
+PHY-3002 : Step(240): len = 638385, overlap = 57.375
+PHY-3002 : Step(241): len = 636246, overlap = 62.2812
+PHY-3002 : Step(242): len = 634318, overlap = 64.0625
+PHY-3002 : Step(243): len = 632554, overlap = 66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025788
+PHY-3002 : Step(244): len = 636935, overlap = 63.2812
+PHY-3002 : Step(245): len = 642468, overlap = 58.875
+PHY-3002 : Step(246): len = 644067, overlap = 55.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479888
+PHY-3002 : Step(247): len = 655065, overlap = 49.3125
+PHY-3002 : Step(248): len = 673391, overlap = 48.2188
+PHY-3002 : Step(249): len = 686922, overlap = 44.4375
+PHY-3002 : Step(250): len = 689884, overlap = 43.6875
+PHY-3002 : Step(251): len = 689070, overlap = 41.375
+PHY-3002 : Step(252): len = 686972, overlap = 40.5625
+PHY-3002 : Step(253): len = 686400, overlap = 38.8438
+PHY-3002 : Step(254): len = 686300, overlap = 37.125
+PHY-3002 : Step(255): len = 687195, overlap = 36.875
+PHY-3002 : Step(256): len = 688672, overlap = 36.3125
+PHY-3002 : Step(257): len = 687776, overlap = 38.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000959777
+PHY-3002 : Step(258): len = 693185, overlap = 37.9375
+PHY-3002 : Step(259): len = 707793, overlap = 42.5625
+PHY-3002 : Step(260): len = 721904, overlap = 45.25
+PHY-3002 : Step(261): len = 720538, overlap = 45.125
+PHY-3002 : Step(262): len = 718584, overlap = 47.0625
+PHY-3002 : Step(263): len = 718363, overlap = 47.125
+PHY-3002 : Step(264): len = 719234, overlap = 46.2812
+PHY-3002 : Step(265): len = 718781, overlap = 48.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00167098
+PHY-3002 : Step(266): len = 722104, overlap = 49.2188
+PHY-3002 : Step(267): len = 730523, overlap = 49.75
+PHY-3002 : Step(268): len = 737525, overlap = 49.1875
+PHY-3002 : Step(269): len = 740778, overlap = 49.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 74/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825680, over cnt = 2877(8%), over = 14308, worst = 47
+PHY-1001 : End global iterations; 1.628796s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 102.03, top5 = 79.19, top10 = 68.21, top15 = 61.55.
+PHY-3001 : End congestion estimation; 1.929089s wall, 2.515625s user + 0.031250s system = 2.546875s CPU (132.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.947241s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124258
+PHY-3002 : Step(270): len = 725463, overlap = 236.562
+PHY-3002 : Step(271): len = 714675, overlap = 193.031
+PHY-3002 : Step(272): len = 701615, overlap = 166.75
+PHY-3002 : Step(273): len = 689587, overlap = 158.375
+PHY-3002 : Step(274): len = 680492, overlap = 144.562
+PHY-3002 : Step(275): len = 672516, overlap = 132.812
+PHY-3002 : Step(276): len = 666832, overlap = 120.75
+PHY-3002 : Step(277): len = 661263, overlap = 110.562
+PHY-3002 : Step(278): len = 655318, overlap = 116.375
+PHY-3002 : Step(279): len = 649278, overlap = 130
+PHY-3002 : Step(280): len = 643735, overlap = 130.25
+PHY-3002 : Step(281): len = 639232, overlap = 127.812
+PHY-3002 : Step(282): len = 634588, overlap = 129.969
+PHY-3002 : Step(283): len = 632464, overlap = 131.406
+PHY-3002 : Step(284): len = 628294, overlap = 126.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000248516
+PHY-3002 : Step(285): len = 629070, overlap = 123.781
+PHY-3002 : Step(286): len = 629965, overlap = 121.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000410701
+PHY-3002 : Step(287): len = 632475, overlap = 120.031
+PHY-3002 : Step(288): len = 642103, overlap = 112.312
+PHY-3002 : Step(289): len = 646065, overlap = 106.562
+PHY-3002 : Step(290): len = 643239, overlap = 108.25
+PHY-3002 : Step(291): len = 641402, overlap = 106.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000710718
+PHY-3002 : Step(292): len = 645464, overlap = 105.312
+PHY-3002 : Step(293): len = 650386, overlap = 94.7812
+PHY-3002 : Step(294): len = 655979, overlap = 89.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00142144
+PHY-3002 : Step(295): len = 657103, overlap = 88.4062
+PHY-3002 : Step(296): len = 661829, overlap = 85.6562
+PHY-3002 : Step(297): len = 669725, overlap = 77.25
+PHY-3002 : Step(298): len = 674047, overlap = 72.9375
+PHY-3002 : Step(299): len = 675876, overlap = 71.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.586547s wall, 1.546875s user + 0.031250s system = 1.578125s CPU (99.5%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 563 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 378.78 peak overflow 2.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 541/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777144, over cnt = 3139(8%), over = 11076, worst = 28
+PHY-1001 : End global iterations; 1.769782s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 71.70, top5 = 58.36, top10 = 52.43, top15 = 48.72.
+PHY-1001 : End incremental global routing; 2.163925s wall, 2.968750s user + 0.000000s system = 2.968750s CPU (137.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.984958s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (99.9%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 318 needs to be replaced
+PHY-3001 : design contains 18256 instances, 7754 luts, 9281 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6080 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700079
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17267/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793176, over cnt = 3172(9%), over = 11083, worst = 28
+PHY-1001 : End global iterations; 0.377593s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (115.9%)
+
+PHY-1001 : Congestion index: top1 = 71.14, top5 = 58.22, top10 = 52.62, top15 = 49.03.
+PHY-3001 : End congestion estimation; 0.692981s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (110.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85043, tnet num: 20658, tinst num: 18256, tnode num: 115859, tedge num: 135500.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.652343s wall, 1.625000s user + 0.031250s system = 1.656250s CPU (100.2%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 612 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.687228s wall, 2.625000s user + 0.062500s system = 2.687500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(300): len = 699095, overlap = 0.1875
+PHY-3002 : Step(301): len = 698633, overlap = 0
+PHY-3002 : Step(302): len = 698393, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17369/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790720, over cnt = 3169(9%), over = 11146, worst = 28
+PHY-1001 : End global iterations; 0.232181s wall, 0.265625s user + 0.031250s system = 0.296875s CPU (127.9%)
+
+PHY-1001 : Congestion index: top1 = 71.81, top5 = 58.63, top10 = 52.89, top15 = 49.25.
+PHY-3001 : End congestion estimation; 0.523760s wall, 0.546875s user + 0.031250s system = 0.578125s CPU (110.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.036180s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000436837
+PHY-3002 : Step(303): len = 698158, overlap = 72.9375
+PHY-3002 : Step(304): len = 698336, overlap = 73.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000873674
+PHY-3002 : Step(305): len = 698525, overlap = 73.0625
+PHY-3002 : Step(306): len = 698983, overlap = 73.5625
+PHY-3001 : Final: Len = 698983, Over = 73.5625
+PHY-3001 : End incremental placement; 5.657753s wall, 5.765625s user + 0.203125s system = 5.968750s CPU (105.5%)
+
+OPT-1001 : Total overflow 384.31 peak overflow 2.78
+OPT-1001 : End high-fanout net optimization; 9.561759s wall, 10.531250s user + 0.234375s system = 10.765625s CPU (112.6%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 711, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17297/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793536, over cnt = 3069(8%), over = 10071, worst = 28
+PHY-1002 : len = 834904, over cnt = 2268(6%), over = 6024, worst = 23
+PHY-1002 : len = 878272, over cnt = 1104(3%), over = 2756, worst = 23
+PHY-1002 : len = 909920, over cnt = 279(0%), over = 702, worst = 13
+PHY-1002 : len = 919472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.062113s wall, 2.765625s user + 0.046875s system = 2.812500s CPU (136.4%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.59, top10 = 48.02, top15 = 45.70.
+OPT-1001 : End congestion update; 2.360730s wall, 3.046875s user + 0.062500s system = 3.109375s CPU (131.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.870510s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 119 cells processed and 18250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 53 cells processed and 6850 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1900 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 850 slack improved
+OPT-1001 : End bottleneck based optimization; 3.679496s wall, 4.375000s user + 0.062500s system = 4.437500s CPU (120.6%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 705, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17333/20842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920464, over cnt = 83(0%), over = 110, worst = 4
+PHY-1002 : len = 920512, over cnt = 40(0%), over = 43, worst = 3
+PHY-1002 : len = 920776, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 921040, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 921072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.812515s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (101.9%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 51.38, top10 = 47.82, top15 = 45.53.
+OPT-1001 : End congestion update; 1.117393s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.862882s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.107782s wall, 2.109375s user + 0.000000s system = 2.109375s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 705, peak = 734.
+OPT-1001 : End physical optimization; 17.266275s wall, 19.000000s user + 0.328125s system = 19.328125s CPU (111.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7754 LUT to BLE ...
+SYN-4008 : Packed 7754 LUT and 3134 SEQ to BLE.
+SYN-4003 : Packing 6153 remaining SEQ's ...
+SYN-4005 : Packed 4101 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2052 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9806/13661 primitive instances ...
+PHY-3001 : End packing; 1.744883s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6670 instances
+RUN-1001 : 3261 mslices, 3261 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17832 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6509 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6668 instances, 6522 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3515 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 705686, Over = 204.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7445/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858864, over cnt = 2009(5%), over = 3264, worst = 8
+PHY-1002 : len = 867896, over cnt = 1189(3%), over = 1689, worst = 7
+PHY-1002 : len = 880112, over cnt = 514(1%), over = 700, worst = 6
+PHY-1002 : len = 887272, over cnt = 163(0%), over = 222, worst = 5
+PHY-1002 : len = 890768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.948563s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 57.39, top5 = 50.20, top10 = 46.73, top15 = 44.49.
+PHY-3001 : End congestion estimation; 2.404407s wall, 3.171875s user + 0.015625s system = 3.187500s CPU (132.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6668, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.791875s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (99.4%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 620 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.737809s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.26697e-05
+PHY-3002 : Step(307): len = 691602, overlap = 206
+PHY-3002 : Step(308): len = 683836, overlap = 205.25
+PHY-3002 : Step(309): len = 677655, overlap = 206.75
+PHY-3002 : Step(310): len = 672841, overlap = 216.25
+PHY-3002 : Step(311): len = 669449, overlap = 225
+PHY-3002 : Step(312): len = 666398, overlap = 225.25
+PHY-3002 : Step(313): len = 664858, overlap = 218.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000125339
+PHY-3002 : Step(314): len = 666869, overlap = 208.75
+PHY-3002 : Step(315): len = 670486, overlap = 203.75
+PHY-3002 : Step(316): len = 671644, overlap = 199.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000250679
+PHY-3002 : Step(317): len = 677534, overlap = 198.25
+PHY-3002 : Step(318): len = 684375, overlap = 186.75
+PHY-3002 : Step(319): len = 684183, overlap = 186.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.434820s wall, 0.359375s user + 0.671875s system = 1.031250s CPU (237.2%)
+
+PHY-3001 : Trial Legalized: Len = 757719
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 975/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872424, over cnt = 2646(7%), over = 4451, worst = 7
+PHY-1002 : len = 892264, over cnt = 1457(4%), over = 2022, worst = 7
+PHY-1002 : len = 912312, over cnt = 398(1%), over = 525, worst = 5
+PHY-1002 : len = 919384, over cnt = 79(0%), over = 100, worst = 5
+PHY-1002 : len = 921248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.856766s wall, 4.093750s user + 0.031250s system = 4.125000s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 56.68, top5 = 50.88, top10 = 47.48, top15 = 45.26.
+PHY-3001 : End congestion estimation; 3.376083s wall, 4.609375s user + 0.046875s system = 4.656250s CPU (137.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.916736s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171654
+PHY-3002 : Step(320): len = 732552, overlap = 37.25
+PHY-3002 : Step(321): len = 717815, overlap = 56.75
+PHY-3002 : Step(322): len = 705260, overlap = 79.75
+PHY-3002 : Step(323): len = 697585, overlap = 105.75
+PHY-3002 : Step(324): len = 692369, overlap = 121
+PHY-3002 : Step(325): len = 690073, overlap = 130.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343309
+PHY-3002 : Step(326): len = 694281, overlap = 126.5
+PHY-3002 : Step(327): len = 698775, overlap = 122.25
+PHY-3002 : Step(328): len = 700530, overlap = 125.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000686617
+PHY-3002 : Step(329): len = 703663, overlap = 123.75
+PHY-3002 : Step(330): len = 708517, overlap = 120.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037588s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (83.1%)
+
+PHY-3001 : Legalized: Len = 735420, Over = 0
+PHY-3001 : Spreading special nets. 441 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.105161s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (104.0%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 183, deltaY = 345, maxDist = 2.
+PHY-3001 : Final: Len = 744855, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6671, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.021320s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (99.7%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 652 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4683/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874512, over cnt = 2464(7%), over = 3852, worst = 8
+PHY-1002 : len = 886000, over cnt = 1564(4%), over = 2201, worst = 6
+PHY-1002 : len = 906104, over cnt = 411(1%), over = 514, worst = 5
+PHY-1002 : len = 913792, over cnt = 70(0%), over = 85, worst = 5
+PHY-1002 : len = 915416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.337616s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.95, top10 = 46.69, top15 = 44.63.
+PHY-1001 : End incremental global routing; 2.758168s wall, 3.796875s user + 0.015625s system = 3.812500s CPU (138.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.947473s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.6%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6579 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750654
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16211/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922952, over cnt = 103(0%), over = 140, worst = 8
+PHY-1002 : len = 923128, over cnt = 58(0%), over = 74, worst = 8
+PHY-1002 : len = 923920, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 924112, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 924224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.846980s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (108.8%)
+
+PHY-1001 : Congestion index: top1 = 56.29, top5 = 50.12, top10 = 46.94, top15 = 44.88.
+PHY-3001 : End congestion estimation; 1.197537s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (107.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71542, tnet num: 17675, tinst num: 6692, tnode num: 93911, tedge num: 118783.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.975534s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (98.9%)
+
+RUN-1004 : used memory is 686 MB, reserved memory is 688 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.927095s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(331): len = 748232, overlap = 0
+PHY-3002 : Step(332): len = 747363, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16198/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919288, over cnt = 71(0%), over = 97, worst = 4
+PHY-1002 : len = 919528, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 920032, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 920080, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 920112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.901059s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.97, top10 = 46.77, top15 = 44.70.
+PHY-3001 : End congestion estimation; 1.254341s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (104.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.921337s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000157527
+PHY-3002 : Step(333): len = 747253, overlap = 1
+PHY-3002 : Step(334): len = 747381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005371s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 747516, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062940s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.3%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 747582, Over = 0
+PHY-3001 : End incremental placement; 6.811308s wall, 6.968750s user + 0.140625s system = 7.109375s CPU (104.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.043383s wall, 12.234375s user + 0.156250s system = 12.390625s CPU (112.2%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 730, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16175/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919680, over cnt = 54(0%), over = 70, worst = 4
+PHY-1002 : len = 919672, over cnt = 35(0%), over = 44, worst = 3
+PHY-1002 : len = 920096, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 920168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.650627s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (108.1%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.95, top10 = 46.76, top15 = 44.70.
+OPT-1001 : End congestion update; 0.996788s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (105.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.778812s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.3%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 756770, Over = 0
+PHY-3001 : Spreading special nets. 30 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067210s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (116.2%)
+
+PHY-3001 : 41 instances has been re-located, deltaX = 12, deltaY = 27, maxDist = 3.
+PHY-3001 : Final: Len = 757514, Over = 0
+PHY-3001 : End incremental legalization; 0.423264s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (125.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 60 cells processed and 22074 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758204, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067704s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.3%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 16, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758608, Over = 0
+PHY-3001 : End incremental legalization; 0.417434s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (101.1%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 4156 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758812, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065604s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.3%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 7, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 759358, Over = 0
+PHY-3001 : End incremental legalization; 0.422296s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (114.7%)
+
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 18 cells processed and 1161 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759597, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063585s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.3%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 759599, Over = 0
+PHY-3001 : End incremental legalization; 0.413811s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (124.6%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization; 4.070278s wall, 4.546875s user + 0.031250s system = 4.578125s CPU (112.5%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 732, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15721/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930944, over cnt = 193(0%), over = 264, worst = 6
+PHY-1002 : len = 931160, over cnt = 92(0%), over = 103, worst = 3
+PHY-1002 : len = 931928, over cnt = 35(0%), over = 35, worst = 1
+PHY-1002 : len = 932424, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932504, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.921465s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (103.4%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 49.54, top10 = 46.48, top15 = 44.48.
+OPT-1001 : End congestion update; 1.273229s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (101.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.782231s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759705, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063929s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.8%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 759739, Over = 0
+PHY-3001 : End incremental legalization; 0.466535s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (117.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.657758s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (104.6%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 732, peak = 741.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.776351s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16201/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932536, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 932560, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 932624, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 932744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 932808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.850277s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (102.9%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.58, top10 = 46.48, top15 = 44.49.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.790510s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.834768s wall, 24.609375s user + 0.203125s system = 24.812500s CPU (108.7%)
+
+RUN-1003 : finish command "place" in 76.151069s wall, 116.953125s user + 7.343750s system = 124.296875s CPU (163.2%)
+
+RUN-1004 : used memory is 684 MB, reserved memory is 680 MB, peak memory is 741 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.793901s wall, 3.125000s user + 0.031250s system = 3.156250s CPU (175.9%)
+
+RUN-1004 : used memory is 684 MB, reserved memory is 681 MB, peak memory is 741 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6701 instances
+RUN-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17857 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 734 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.805160s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (91.8%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 659 MB, peak memory is 741 MB
+PHY-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862800, over cnt = 2648(7%), over = 4341, worst = 9
+PHY-1002 : len = 880744, over cnt = 1618(4%), over = 2343, worst = 9
+PHY-1002 : len = 903616, over cnt = 451(1%), over = 577, worst = 6
+PHY-1002 : len = 912696, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 913024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.602172s wall, 4.796875s user + 0.015625s system = 4.812500s CPU (133.6%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.00, top10 = 45.84, top15 = 43.81.
+PHY-1001 : End global routing; 3.981886s wall, 5.171875s user + 0.015625s system = 5.187500s CPU (130.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 711, reserve = 705, peak = 741.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 981, reserve = 979, peak = 981.
+PHY-1001 : End build detailed router design. 4.377989s wall, 4.328125s user + 0.046875s system = 4.375000s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270736, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.893864s wall, 5.890625s user + 0.000000s system = 5.890625s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270792, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.556775s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (101.0%)
+
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1017, peak = 1017.
+PHY-1001 : End phase 1; 6.462136s wall, 6.468750s user + 0.000000s system = 6.468750s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1032, peak = 1032.
+PHY-1001 : End initial routed; 40.111511s wall, 74.703125s user + 0.265625s system = 74.968750s CPU (186.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.507793s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1046, peak = 1046.
+PHY-1001 : End phase 2; 43.619377s wall, 78.203125s user + 0.265625s system = 78.468750s CPU (179.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.143219s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.2%)
+
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.437857s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26109e+06, over cnt = 626(0%), over = 627, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.560604s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (167.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25966e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.735892s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (146.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25927e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.510538s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (110.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25919e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.340457s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (105.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.270927s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (98.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.531149s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.395097s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1150, peak = 1146.
+PHY-1001 : End phase 3; 10.220836s wall, 11.625000s user + 0.015625s system = 11.640625s CPU (113.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.143759s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.7%)
+
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.411768s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.504031s wall, 3.468750s user + 0.031250s system = 3.500000s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.537833s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (99.1%)
+
+PHY-1001 : Current memory(MB): used = 1155, reserve = 1159, peak = 1155.
+PHY-1001 : End phase 4; 6.481584s wall, 6.421875s user + 0.031250s system = 6.453125s CPU (99.6%)
+
+PHY-1003 : Routed, final wirelength = 2.25928e+06
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1161, peak = 1157.
+PHY-1001 : End export database. 0.066579s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.3%)
+
+PHY-1001 : End detail routing; 71.660155s wall, 107.562500s user + 0.359375s system = 107.921875s CPU (150.6%)
+
+RUN-1003 : finish command "route" in 78.591609s wall, 115.515625s user + 0.406250s system = 115.921875s CPU (147.5%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1084 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10187 out of 19600 51.97%
+#reg 9425 out of 19600 48.09%
+#le 12209
+ #lut only 2784 out of 12209 22.80%
+ #reg only 2022 out of 12209 16.56%
+ #lut® 7403 out of 12209 60.64%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1380
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1287
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 961
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 131
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_307.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P170 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12209 |9160 |1027 |9456 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |457 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |97 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |42 |42 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |759 |371 |96 |575 |0 |0 |
+| u_ADconfig |AD_config |187 |121 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |260 |165 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |384 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |173 |121 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |254 |145 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2935 |2382 |306 |2076 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |170 |93 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort |2735 |2268 |289 |1906 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2326 |1968 |253 |1555 |22 |0 |
+| channelPart |channel_part_8478 |141 |135 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |50 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1807 |1513 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |208 |181 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |961 |694 |170 |656 |0 |0 |
+| ram_switch_state |ram_switch_state |638 |638 |0 |372 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |48 |41 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |235 |36 |273 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3122 |2458 |349 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |115 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2917 |2332 |332 |1914 |25 |1 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2476 |1975 |290 |1550 |22 |1 |
+| channelPart |channel_part_8478 |130 |124 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1909 |1532 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |202 |174 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |1003 |657 |170 |701 |0 |0 |
+| ram_switch_state |ram_switch_state |704 |701 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |352 |251 |81 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |162 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |41 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9896
+ #2 2 4222
+ #3 3 1721
+ #4 4 562
+ #5 5-10 766
+ #6 11-50 583
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.157205s wall, 3.718750s user + 0.015625s system = 3.734375s CPU (173.1%)
+
+RUN-1004 : used memory is 1082 MB, reserved memory is 1086 MB, peak memory is 1157 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.702675s wall, 1.687500s user + 0.015625s system = 1.703125s CPU (100.0%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1091 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.576003s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.1%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1093 MB, peak memory is 1157 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6699
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17857, pip num: 168201
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 529
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3230 valid insts, and 469612 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.642237s wall, 62.718750s user + 0.218750s system = 62.937500s CPU (652.7%)
+
+RUN-1004 : used memory is 1246 MB, reserved memory is 1246 MB, peak memory is 1362 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_164220.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_164910.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_164910.log
new file mode 100644
index 0000000..6e2bb66
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_164910.log
@@ -0,0 +1,2037 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 16:49:10 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.314977s wall, 2.109375s user + 0.187500s system = 2.296875s CPU (99.2%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 315 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17986 instances
+RUN-0007 : 7661 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20564 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13082 nets have 2 pins
+RUN-1001 : 6444 nets have [3 - 5] pins
+RUN-1001 : 620 nets have [6 - 10] pins
+RUN-1001 : 181 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17984 instances, 7661 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.257273s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (99.4%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 514 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.092682s wall, 2.062500s user + 0.031250s system = 2.093750s CPU (100.1%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11825e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17984.
+PHY-3001 : Level 1 #clusters 2051.
+PHY-3001 : End clustering; 0.137343s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32681e+06, overlap = 447.375
+PHY-3002 : Step(2): len = 1.21277e+06, overlap = 492.031
+PHY-3002 : Step(3): len = 854256, overlap = 571.531
+PHY-3002 : Step(4): len = 796625, overlap = 595.094
+PHY-3002 : Step(5): len = 625051, overlap = 763.906
+PHY-3002 : Step(6): len = 553878, overlap = 846.75
+PHY-3002 : Step(7): len = 475465, overlap = 919.25
+PHY-3002 : Step(8): len = 435213, overlap = 966.5
+PHY-3002 : Step(9): len = 396311, overlap = 1029.19
+PHY-3002 : Step(10): len = 370878, overlap = 1031.53
+PHY-3002 : Step(11): len = 325662, overlap = 1075.22
+PHY-3002 : Step(12): len = 307603, overlap = 1115.06
+PHY-3002 : Step(13): len = 270358, overlap = 1170.19
+PHY-3002 : Step(14): len = 253854, overlap = 1221.72
+PHY-3002 : Step(15): len = 229490, overlap = 1275.16
+PHY-3002 : Step(16): len = 213861, overlap = 1309.06
+PHY-3002 : Step(17): len = 190508, overlap = 1330.88
+PHY-3002 : Step(18): len = 179455, overlap = 1361.78
+PHY-3002 : Step(19): len = 165284, overlap = 1392.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.31406e-06
+PHY-3002 : Step(20): len = 165466, overlap = 1346.91
+PHY-3002 : Step(21): len = 202919, overlap = 1205.69
+PHY-3002 : Step(22): len = 211139, overlap = 1153.94
+PHY-3002 : Step(23): len = 217503, overlap = 1084.84
+PHY-3002 : Step(24): len = 217194, overlap = 1057.38
+PHY-3002 : Step(25): len = 213766, overlap = 1039.53
+PHY-3002 : Step(26): len = 209686, overlap = 1019.31
+PHY-3002 : Step(27): len = 205682, overlap = 1025.91
+PHY-3002 : Step(28): len = 202366, overlap = 1025.41
+PHY-3002 : Step(29): len = 198815, overlap = 1041.31
+PHY-3002 : Step(30): len = 196891, overlap = 1048.53
+PHY-3002 : Step(31): len = 192947, overlap = 1032.38
+PHY-3002 : Step(32): len = 190652, overlap = 1028.38
+PHY-3002 : Step(33): len = 188982, overlap = 1047.53
+PHY-3002 : Step(34): len = 188856, overlap = 1050.19
+PHY-3002 : Step(35): len = 187822, overlap = 1046.66
+PHY-3002 : Step(36): len = 187691, overlap = 1043.84
+PHY-3002 : Step(37): len = 186699, overlap = 1045.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.62811e-06
+PHY-3002 : Step(38): len = 190190, overlap = 1023.97
+PHY-3002 : Step(39): len = 200878, overlap = 998
+PHY-3002 : Step(40): len = 204969, overlap = 973.031
+PHY-3002 : Step(41): len = 210699, overlap = 962.406
+PHY-3002 : Step(42): len = 213685, overlap = 962.031
+PHY-3002 : Step(43): len = 214913, overlap = 971.312
+PHY-3002 : Step(44): len = 214129, overlap = 962.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.25623e-06
+PHY-3002 : Step(45): len = 222317, overlap = 945.719
+PHY-3002 : Step(46): len = 241846, overlap = 887.062
+PHY-3002 : Step(47): len = 250733, overlap = 810.094
+PHY-3002 : Step(48): len = 259458, overlap = 764.75
+PHY-3002 : Step(49): len = 264898, overlap = 729.594
+PHY-3002 : Step(50): len = 268782, overlap = 717.594
+PHY-3002 : Step(51): len = 268659, overlap = 693.25
+PHY-3002 : Step(52): len = 267038, overlap = 699.969
+PHY-3002 : Step(53): len = 265608, overlap = 708.531
+PHY-3002 : Step(54): len = 263857, overlap = 714.938
+PHY-3002 : Step(55): len = 262442, overlap = 716.219
+PHY-3002 : Step(56): len = 261697, overlap = 712.75
+PHY-3002 : Step(57): len = 261651, overlap = 701.625
+PHY-3002 : Step(58): len = 261227, overlap = 706.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.05125e-05
+PHY-3002 : Step(59): len = 276346, overlap = 609.156
+PHY-3002 : Step(60): len = 291797, overlap = 571.688
+PHY-3002 : Step(61): len = 297779, overlap = 568.531
+PHY-3002 : Step(62): len = 301292, overlap = 564.406
+PHY-3002 : Step(63): len = 299531, overlap = 563.281
+PHY-3002 : Step(64): len = 300587, overlap = 555.219
+PHY-3002 : Step(65): len = 301742, overlap = 556.719
+PHY-3002 : Step(66): len = 303460, overlap = 538.031
+PHY-3002 : Step(67): len = 301977, overlap = 542.531
+PHY-3002 : Step(68): len = 300507, overlap = 528.469
+PHY-3002 : Step(69): len = 299876, overlap = 522.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.10249e-05
+PHY-3002 : Step(70): len = 318230, overlap = 482.656
+PHY-3002 : Step(71): len = 329376, overlap = 452.5
+PHY-3002 : Step(72): len = 333339, overlap = 419.688
+PHY-3002 : Step(73): len = 334752, overlap = 392.281
+PHY-3002 : Step(74): len = 333824, overlap = 357.469
+PHY-3002 : Step(75): len = 335637, overlap = 379.844
+PHY-3002 : Step(76): len = 334442, overlap = 390.5
+PHY-3002 : Step(77): len = 334205, overlap = 407.562
+PHY-3002 : Step(78): len = 334333, overlap = 392.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.20498e-05
+PHY-3002 : Step(79): len = 350059, overlap = 360.938
+PHY-3002 : Step(80): len = 361689, overlap = 339.031
+PHY-3002 : Step(81): len = 364498, overlap = 329.688
+PHY-3002 : Step(82): len = 368120, overlap = 324.688
+PHY-3002 : Step(83): len = 371135, overlap = 305.406
+PHY-3002 : Step(84): len = 373997, overlap = 280.5
+PHY-3002 : Step(85): len = 371594, overlap = 279.188
+PHY-3002 : Step(86): len = 373031, overlap = 280.469
+PHY-3002 : Step(87): len = 374790, overlap = 279.188
+PHY-3002 : Step(88): len = 376019, overlap = 266.062
+PHY-3002 : Step(89): len = 375474, overlap = 260.156
+PHY-3002 : Step(90): len = 377506, overlap = 264.469
+PHY-3002 : Step(91): len = 379997, overlap = 270.062
+PHY-3002 : Step(92): len = 381499, overlap = 250.094
+PHY-3002 : Step(93): len = 378396, overlap = 252.562
+PHY-3002 : Step(94): len = 378137, overlap = 257.031
+PHY-3002 : Step(95): len = 377776, overlap = 258.812
+PHY-3002 : Step(96): len = 378238, overlap = 260.094
+PHY-3002 : Step(97): len = 377541, overlap = 259.375
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.40997e-05
+PHY-3002 : Step(98): len = 393731, overlap = 263.688
+PHY-3002 : Step(99): len = 403714, overlap = 270.438
+PHY-3002 : Step(100): len = 402161, overlap = 260.656
+PHY-3002 : Step(101): len = 403139, overlap = 265.25
+PHY-3002 : Step(102): len = 406115, overlap = 263.562
+PHY-3002 : Step(103): len = 409921, overlap = 261.969
+PHY-3002 : Step(104): len = 409057, overlap = 261.656
+PHY-3002 : Step(105): len = 411247, overlap = 265.344
+PHY-3002 : Step(106): len = 415044, overlap = 267.875
+PHY-3002 : Step(107): len = 417805, overlap = 267
+PHY-3002 : Step(108): len = 414534, overlap = 279.844
+PHY-3002 : Step(109): len = 413890, overlap = 267.531
+PHY-3002 : Step(110): len = 415583, overlap = 257.938
+PHY-3002 : Step(111): len = 417219, overlap = 249.938
+PHY-3002 : Step(112): len = 413916, overlap = 234.875
+PHY-3002 : Step(113): len = 414176, overlap = 247.031
+PHY-3002 : Step(114): len = 415397, overlap = 239.5
+PHY-3002 : Step(115): len = 416638, overlap = 231.375
+PHY-3002 : Step(116): len = 414219, overlap = 227.656
+PHY-3002 : Step(117): len = 414070, overlap = 224.562
+PHY-3002 : Step(118): len = 415000, overlap = 225.969
+PHY-3002 : Step(119): len = 416356, overlap = 230.719
+PHY-3002 : Step(120): len = 414329, overlap = 243.5
+PHY-3002 : Step(121): len = 414525, overlap = 240.781
+PHY-3002 : Step(122): len = 415219, overlap = 251.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168199
+PHY-3002 : Step(123): len = 427793, overlap = 228.094
+PHY-3002 : Step(124): len = 434978, overlap = 211.5
+PHY-3002 : Step(125): len = 434224, overlap = 212.938
+PHY-3002 : Step(126): len = 434893, overlap = 214.719
+PHY-3002 : Step(127): len = 437387, overlap = 214.312
+PHY-3002 : Step(128): len = 440422, overlap = 218.344
+PHY-3002 : Step(129): len = 439475, overlap = 220.5
+PHY-3002 : Step(130): len = 439959, overlap = 218.125
+PHY-3002 : Step(131): len = 442104, overlap = 214.969
+PHY-3002 : Step(132): len = 443728, overlap = 215.188
+PHY-3002 : Step(133): len = 442552, overlap = 226.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000315424
+PHY-3002 : Step(134): len = 449199, overlap = 215
+PHY-3002 : Step(135): len = 456791, overlap = 208.969
+PHY-3002 : Step(136): len = 458741, overlap = 221.25
+PHY-3002 : Step(137): len = 460138, overlap = 210.938
+PHY-3002 : Step(138): len = 461978, overlap = 206.938
+PHY-3002 : Step(139): len = 463732, overlap = 200.469
+PHY-3002 : Step(140): len = 463075, overlap = 203.844
+PHY-3002 : Step(141): len = 464420, overlap = 206.25
+PHY-3002 : Step(142): len = 466826, overlap = 197.656
+PHY-3002 : Step(143): len = 468395, overlap = 196.719
+PHY-3002 : Step(144): len = 468161, overlap = 197.438
+PHY-3002 : Step(145): len = 468919, overlap = 193.844
+PHY-3002 : Step(146): len = 470408, overlap = 190.969
+PHY-3002 : Step(147): len = 471038, overlap = 194.094
+PHY-3002 : Step(148): len = 470098, overlap = 194.125
+PHY-3002 : Step(149): len = 469787, overlap = 192.844
+PHY-3002 : Step(150): len = 470962, overlap = 194.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000597386
+PHY-3002 : Step(151): len = 477356, overlap = 187.469
+PHY-3002 : Step(152): len = 485467, overlap = 177.438
+PHY-3002 : Step(153): len = 487792, overlap = 172.25
+PHY-3002 : Step(154): len = 489820, overlap = 169.969
+PHY-3002 : Step(155): len = 492289, overlap = 166.719
+PHY-3002 : Step(156): len = 494288, overlap = 161.812
+PHY-3002 : Step(157): len = 494621, overlap = 167.094
+PHY-3002 : Step(158): len = 495412, overlap = 158.875
+PHY-3002 : Step(159): len = 497530, overlap = 158.125
+PHY-3002 : Step(160): len = 499660, overlap = 161.844
+PHY-3002 : Step(161): len = 499659, overlap = 155.344
+PHY-3002 : Step(162): len = 500171, overlap = 145.469
+PHY-3002 : Step(163): len = 501354, overlap = 144.875
+PHY-3002 : Step(164): len = 502419, overlap = 141.625
+PHY-3002 : Step(165): len = 502507, overlap = 135.938
+PHY-3002 : Step(166): len = 502911, overlap = 136.219
+PHY-3002 : Step(167): len = 503441, overlap = 133.781
+PHY-3002 : Step(168): len = 503676, overlap = 133.844
+PHY-3002 : Step(169): len = 503613, overlap = 131.625
+PHY-3002 : Step(170): len = 503662, overlap = 133.656
+PHY-3002 : Step(171): len = 503864, overlap = 139.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108125
+PHY-3002 : Step(172): len = 508017, overlap = 138.406
+PHY-3002 : Step(173): len = 515100, overlap = 140.438
+PHY-3002 : Step(174): len = 516366, overlap = 136.719
+PHY-3002 : Step(175): len = 517528, overlap = 132.312
+PHY-3002 : Step(176): len = 519652, overlap = 132.719
+PHY-3002 : Step(177): len = 520672, overlap = 132.875
+PHY-3002 : Step(178): len = 520221, overlap = 132.375
+PHY-3002 : Step(179): len = 520126, overlap = 135.25
+PHY-3002 : Step(180): len = 521307, overlap = 133.188
+PHY-3002 : Step(181): len = 522214, overlap = 132.5
+PHY-3002 : Step(182): len = 521960, overlap = 133.5
+PHY-3002 : Step(183): len = 521951, overlap = 135.812
+PHY-3002 : Step(184): len = 522274, overlap = 134.25
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00187339
+PHY-3002 : Step(185): len = 525598, overlap = 136.688
+PHY-3002 : Step(186): len = 531982, overlap = 134.781
+PHY-3002 : Step(187): len = 533798, overlap = 129.438
+PHY-3002 : Step(188): len = 534889, overlap = 126.938
+PHY-3002 : Step(189): len = 535931, overlap = 126.094
+PHY-3002 : Step(190): len = 536614, overlap = 125.531
+PHY-3002 : Step(191): len = 537630, overlap = 128.594
+PHY-3002 : Step(192): len = 538953, overlap = 129.156
+PHY-3002 : Step(193): len = 539831, overlap = 128.594
+PHY-3002 : Step(194): len = 540970, overlap = 124.75
+PHY-3002 : Step(195): len = 542306, overlap = 125.406
+PHY-3002 : Step(196): len = 542817, overlap = 125.406
+PHY-3002 : Step(197): len = 543125, overlap = 123.969
+PHY-3002 : Step(198): len = 543331, overlap = 123.969
+PHY-3002 : Step(199): len = 543607, overlap = 125.344
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00307474
+PHY-3002 : Step(200): len = 546970, overlap = 124.781
+PHY-3002 : Step(201): len = 555249, overlap = 108.75
+PHY-3002 : Step(202): len = 560298, overlap = 101.938
+PHY-3002 : Step(203): len = 566036, overlap = 104.688
+PHY-3002 : Step(204): len = 569242, overlap = 103.969
+PHY-3002 : Step(205): len = 572082, overlap = 105.062
+PHY-3002 : Step(206): len = 573488, overlap = 100.906
+PHY-3002 : Step(207): len = 574436, overlap = 101.594
+PHY-3002 : Step(208): len = 574997, overlap = 98.375
+PHY-3002 : Step(209): len = 575327, overlap = 96.875
+PHY-3002 : Step(210): len = 575154, overlap = 96.2812
+PHY-3002 : Step(211): len = 574947, overlap = 90.3438
+PHY-3002 : Step(212): len = 574615, overlap = 96.1562
+PHY-3002 : Step(213): len = 574424, overlap = 96.1562
+PHY-3002 : Step(214): len = 574285, overlap = 91.1562
+PHY-3002 : Step(215): len = 574158, overlap = 90.1562
+PHY-3002 : Step(216): len = 573866, overlap = 87.6562
+PHY-3002 : Step(217): len = 573742, overlap = 90.125
+PHY-3002 : Step(218): len = 573607, overlap = 89.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015034s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (103.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753960, over cnt = 1673(4%), over = 7641, worst = 41
+PHY-1001 : End global iterations; 0.757993s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (144.3%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 63.38, top10 = 53.94, top15 = 48.26.
+PHY-3001 : End congestion estimation; 1.020972s wall, 1.312500s user + 0.031250s system = 1.343750s CPU (131.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.917247s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012894
+PHY-3002 : Step(219): len = 682872, overlap = 60.7812
+PHY-3002 : Step(220): len = 680164, overlap = 61.5
+PHY-3002 : Step(221): len = 671439, overlap = 58.2812
+PHY-3002 : Step(222): len = 665226, overlap = 60.6875
+PHY-3002 : Step(223): len = 663081, overlap = 55.8438
+PHY-3002 : Step(224): len = 662916, overlap = 53.5938
+PHY-3002 : Step(225): len = 660482, overlap = 53.4375
+PHY-3002 : Step(226): len = 656745, overlap = 53.25
+PHY-3002 : Step(227): len = 653517, overlap = 53.7188
+PHY-3002 : Step(228): len = 651915, overlap = 50.4688
+PHY-3002 : Step(229): len = 650566, overlap = 43.9375
+PHY-3002 : Step(230): len = 649789, overlap = 39.6562
+PHY-3002 : Step(231): len = 649010, overlap = 39.6875
+PHY-3002 : Step(232): len = 648983, overlap = 36.4375
+PHY-3002 : Step(233): len = 648835, overlap = 39.7188
+PHY-3002 : Step(234): len = 649183, overlap = 37.0625
+PHY-3002 : Step(235): len = 647443, overlap = 37.6562
+PHY-3002 : Step(236): len = 646551, overlap = 37.75
+PHY-3002 : Step(237): len = 644304, overlap = 38.4688
+PHY-3002 : Step(238): len = 642657, overlap = 46.9062
+PHY-3002 : Step(239): len = 640494, overlap = 55.25
+PHY-3002 : Step(240): len = 638385, overlap = 57.375
+PHY-3002 : Step(241): len = 636246, overlap = 62.2812
+PHY-3002 : Step(242): len = 634318, overlap = 64.0625
+PHY-3002 : Step(243): len = 632554, overlap = 66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025788
+PHY-3002 : Step(244): len = 636935, overlap = 63.2812
+PHY-3002 : Step(245): len = 642468, overlap = 58.875
+PHY-3002 : Step(246): len = 644067, overlap = 55.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479888
+PHY-3002 : Step(247): len = 655065, overlap = 49.3125
+PHY-3002 : Step(248): len = 673391, overlap = 48.2188
+PHY-3002 : Step(249): len = 686922, overlap = 44.4375
+PHY-3002 : Step(250): len = 689884, overlap = 43.6875
+PHY-3002 : Step(251): len = 689070, overlap = 41.375
+PHY-3002 : Step(252): len = 686972, overlap = 40.5625
+PHY-3002 : Step(253): len = 686400, overlap = 38.8438
+PHY-3002 : Step(254): len = 686300, overlap = 37.125
+PHY-3002 : Step(255): len = 687195, overlap = 36.875
+PHY-3002 : Step(256): len = 688672, overlap = 36.3125
+PHY-3002 : Step(257): len = 687776, overlap = 38.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000959777
+PHY-3002 : Step(258): len = 693185, overlap = 37.9375
+PHY-3002 : Step(259): len = 707793, overlap = 42.5625
+PHY-3002 : Step(260): len = 721904, overlap = 45.25
+PHY-3002 : Step(261): len = 720538, overlap = 45.125
+PHY-3002 : Step(262): len = 718584, overlap = 47.0625
+PHY-3002 : Step(263): len = 718363, overlap = 47.125
+PHY-3002 : Step(264): len = 719234, overlap = 46.2812
+PHY-3002 : Step(265): len = 718781, overlap = 48.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00167098
+PHY-3002 : Step(266): len = 722104, overlap = 49.2188
+PHY-3002 : Step(267): len = 730523, overlap = 49.75
+PHY-3002 : Step(268): len = 737525, overlap = 49.1875
+PHY-3002 : Step(269): len = 740778, overlap = 49.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 74/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825680, over cnt = 2877(8%), over = 14308, worst = 47
+PHY-1001 : End global iterations; 1.714198s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (138.5%)
+
+PHY-1001 : Congestion index: top1 = 102.03, top5 = 79.19, top10 = 68.21, top15 = 61.55.
+PHY-3001 : End congestion estimation; 2.008742s wall, 2.640625s user + 0.046875s system = 2.687500s CPU (133.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.154057s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (97.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124258
+PHY-3002 : Step(270): len = 725463, overlap = 236.562
+PHY-3002 : Step(271): len = 714675, overlap = 193.031
+PHY-3002 : Step(272): len = 701615, overlap = 166.75
+PHY-3002 : Step(273): len = 689587, overlap = 158.375
+PHY-3002 : Step(274): len = 680492, overlap = 144.562
+PHY-3002 : Step(275): len = 672516, overlap = 132.812
+PHY-3002 : Step(276): len = 666832, overlap = 120.75
+PHY-3002 : Step(277): len = 661263, overlap = 110.562
+PHY-3002 : Step(278): len = 655318, overlap = 116.375
+PHY-3002 : Step(279): len = 649278, overlap = 130
+PHY-3002 : Step(280): len = 643735, overlap = 130.25
+PHY-3002 : Step(281): len = 639232, overlap = 127.812
+PHY-3002 : Step(282): len = 634588, overlap = 129.969
+PHY-3002 : Step(283): len = 632464, overlap = 131.406
+PHY-3002 : Step(284): len = 628294, overlap = 126.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000248516
+PHY-3002 : Step(285): len = 629070, overlap = 123.781
+PHY-3002 : Step(286): len = 629965, overlap = 121.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000410701
+PHY-3002 : Step(287): len = 632475, overlap = 120.031
+PHY-3002 : Step(288): len = 642103, overlap = 112.312
+PHY-3002 : Step(289): len = 646065, overlap = 106.562
+PHY-3002 : Step(290): len = 643239, overlap = 108.25
+PHY-3002 : Step(291): len = 641402, overlap = 106.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000710718
+PHY-3002 : Step(292): len = 645464, overlap = 105.312
+PHY-3002 : Step(293): len = 650386, overlap = 94.7812
+PHY-3002 : Step(294): len = 655979, overlap = 89.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00142144
+PHY-3002 : Step(295): len = 657103, overlap = 88.4062
+PHY-3002 : Step(296): len = 661829, overlap = 85.6562
+PHY-3002 : Step(297): len = 669725, overlap = 77.25
+PHY-3002 : Step(298): len = 674047, overlap = 72.9375
+PHY-3002 : Step(299): len = 675876, overlap = 71.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.540328s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (99.4%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 564 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 378.78 peak overflow 2.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 541/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777144, over cnt = 3139(8%), over = 11076, worst = 28
+PHY-1001 : End global iterations; 1.733346s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (140.6%)
+
+PHY-1001 : Congestion index: top1 = 71.70, top5 = 58.36, top10 = 52.43, top15 = 48.72.
+PHY-1001 : End incremental global routing; 2.118959s wall, 2.812500s user + 0.015625s system = 2.828125s CPU (133.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.981562s wall, 0.937500s user + 0.046875s system = 0.984375s CPU (100.3%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 318 needs to be replaced
+PHY-3001 : design contains 18256 instances, 7754 luts, 9281 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6080 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700079
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17267/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793176, over cnt = 3172(9%), over = 11083, worst = 28
+PHY-1001 : End global iterations; 0.268498s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (133.8%)
+
+PHY-1001 : Congestion index: top1 = 71.14, top5 = 58.22, top10 = 52.62, top15 = 49.03.
+PHY-3001 : End congestion estimation; 0.538951s wall, 0.609375s user + 0.031250s system = 0.640625s CPU (118.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85043, tnet num: 20658, tinst num: 18256, tnode num: 115859, tedge num: 135500.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.559236s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (99.2%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 613 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.579696s wall, 2.531250s user + 0.046875s system = 2.578125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(300): len = 699095, overlap = 0.1875
+PHY-3002 : Step(301): len = 698633, overlap = 0
+PHY-3002 : Step(302): len = 698393, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17369/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790720, over cnt = 3169(9%), over = 11146, worst = 28
+PHY-1001 : End global iterations; 0.221770s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (105.7%)
+
+PHY-1001 : Congestion index: top1 = 71.81, top5 = 58.63, top10 = 52.89, top15 = 49.25.
+PHY-3001 : End congestion estimation; 0.508107s wall, 0.515625s user + 0.015625s system = 0.531250s CPU (104.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.996594s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000436837
+PHY-3002 : Step(303): len = 698158, overlap = 72.9375
+PHY-3002 : Step(304): len = 698336, overlap = 73.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000873674
+PHY-3002 : Step(305): len = 698525, overlap = 73.0625
+PHY-3002 : Step(306): len = 698983, overlap = 73.5625
+PHY-3001 : Final: Len = 698983, Over = 73.5625
+PHY-3001 : End incremental placement; 5.280698s wall, 5.328125s user + 0.203125s system = 5.531250s CPU (104.7%)
+
+OPT-1001 : Total overflow 384.31 peak overflow 2.78
+OPT-1001 : End high-fanout net optimization; 8.951487s wall, 9.656250s user + 0.265625s system = 9.921875s CPU (110.8%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 710, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17297/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793536, over cnt = 3069(8%), over = 10071, worst = 28
+PHY-1002 : len = 834904, over cnt = 2268(6%), over = 6024, worst = 23
+PHY-1002 : len = 878272, over cnt = 1104(3%), over = 2756, worst = 23
+PHY-1002 : len = 909920, over cnt = 279(0%), over = 702, worst = 13
+PHY-1002 : len = 919472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.001124s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (124.1%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.59, top10 = 48.02, top15 = 45.70.
+OPT-1001 : End congestion update; 2.299291s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (121.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.897887s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 119 cells processed and 18250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 53 cells processed and 6850 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1900 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 850 slack improved
+OPT-1001 : End bottleneck based optimization; 3.640050s wall, 4.125000s user + 0.000000s system = 4.125000s CPU (113.3%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 696, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17333/20842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920464, over cnt = 83(0%), over = 110, worst = 4
+PHY-1002 : len = 920512, over cnt = 40(0%), over = 43, worst = 3
+PHY-1002 : len = 920776, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 921040, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 921072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.883636s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 51.38, top10 = 47.82, top15 = 45.53.
+OPT-1001 : End congestion update; 1.191454s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (104.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.857614s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.2%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.171802s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (102.9%)
+
+OPT-1001 : Current memory(MB): used = 710, reserve = 705, peak = 734.
+OPT-1001 : End physical optimization; 16.629925s wall, 17.921875s user + 0.312500s system = 18.234375s CPU (109.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7754 LUT to BLE ...
+SYN-4008 : Packed 7754 LUT and 3134 SEQ to BLE.
+SYN-4003 : Packing 6153 remaining SEQ's ...
+SYN-4005 : Packed 4101 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2052 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9806/13661 primitive instances ...
+PHY-3001 : End packing; 1.786918s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6670 instances
+RUN-1001 : 3261 mslices, 3261 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17832 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6509 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6668 instances, 6522 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3515 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 705686, Over = 204.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7445/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858864, over cnt = 2009(5%), over = 3264, worst = 8
+PHY-1002 : len = 867896, over cnt = 1189(3%), over = 1689, worst = 7
+PHY-1002 : len = 880112, over cnt = 514(1%), over = 700, worst = 6
+PHY-1002 : len = 887272, over cnt = 163(0%), over = 222, worst = 5
+PHY-1002 : len = 890768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.938228s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (141.9%)
+
+PHY-1001 : Congestion index: top1 = 57.39, top5 = 50.20, top10 = 46.73, top15 = 44.49.
+PHY-3001 : End congestion estimation; 2.384950s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (134.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6668, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.717768s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (100.1%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 613 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.690229s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.26697e-05
+PHY-3002 : Step(307): len = 691602, overlap = 206
+PHY-3002 : Step(308): len = 683836, overlap = 205.25
+PHY-3002 : Step(309): len = 677655, overlap = 206.75
+PHY-3002 : Step(310): len = 672841, overlap = 216.25
+PHY-3002 : Step(311): len = 669449, overlap = 225
+PHY-3002 : Step(312): len = 666398, overlap = 225.25
+PHY-3002 : Step(313): len = 664858, overlap = 218.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000125339
+PHY-3002 : Step(314): len = 666869, overlap = 208.75
+PHY-3002 : Step(315): len = 670486, overlap = 203.75
+PHY-3002 : Step(316): len = 671644, overlap = 199.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000250679
+PHY-3002 : Step(317): len = 677534, overlap = 198.25
+PHY-3002 : Step(318): len = 684375, overlap = 186.75
+PHY-3002 : Step(319): len = 684183, overlap = 186.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.423291s wall, 0.406250s user + 0.718750s system = 1.125000s CPU (265.8%)
+
+PHY-3001 : Trial Legalized: Len = 757719
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 975/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872424, over cnt = 2646(7%), over = 4451, worst = 7
+PHY-1002 : len = 892264, over cnt = 1457(4%), over = 2022, worst = 7
+PHY-1002 : len = 912312, over cnt = 398(1%), over = 525, worst = 5
+PHY-1002 : len = 919384, over cnt = 79(0%), over = 100, worst = 5
+PHY-1002 : len = 921248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.657200s wall, 3.875000s user + 0.000000s system = 3.875000s CPU (145.8%)
+
+PHY-1001 : Congestion index: top1 = 56.68, top5 = 50.88, top10 = 47.48, top15 = 45.26.
+PHY-3001 : End congestion estimation; 3.155158s wall, 4.375000s user + 0.000000s system = 4.375000s CPU (138.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.912373s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171654
+PHY-3002 : Step(320): len = 732552, overlap = 37.25
+PHY-3002 : Step(321): len = 717815, overlap = 56.75
+PHY-3002 : Step(322): len = 705260, overlap = 79.75
+PHY-3002 : Step(323): len = 697585, overlap = 105.75
+PHY-3002 : Step(324): len = 692369, overlap = 121
+PHY-3002 : Step(325): len = 690073, overlap = 130.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343309
+PHY-3002 : Step(326): len = 694281, overlap = 126.5
+PHY-3002 : Step(327): len = 698775, overlap = 122.25
+PHY-3002 : Step(328): len = 700530, overlap = 125.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000686617
+PHY-3002 : Step(329): len = 703663, overlap = 123.75
+PHY-3002 : Step(330): len = 708517, overlap = 120.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033991s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (91.9%)
+
+PHY-3001 : Legalized: Len = 735420, Over = 0
+PHY-3001 : Spreading special nets. 441 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.103177s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (106.0%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 183, deltaY = 345, maxDist = 2.
+PHY-3001 : Final: Len = 744855, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6671, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.956004s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (99.9%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 637 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4683/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874512, over cnt = 2464(7%), over = 3852, worst = 8
+PHY-1002 : len = 886000, over cnt = 1564(4%), over = 2201, worst = 6
+PHY-1002 : len = 906104, over cnt = 411(1%), over = 514, worst = 5
+PHY-1002 : len = 913792, over cnt = 70(0%), over = 85, worst = 5
+PHY-1002 : len = 915416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.332616s wall, 3.171875s user + 0.015625s system = 3.187500s CPU (136.6%)
+
+PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.95, top10 = 46.69, top15 = 44.63.
+PHY-1001 : End incremental global routing; 2.728749s wall, 3.562500s user + 0.015625s system = 3.578125s CPU (131.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.918846s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (98.6%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6579 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750654
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16211/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922952, over cnt = 103(0%), over = 140, worst = 8
+PHY-1002 : len = 923128, over cnt = 58(0%), over = 74, worst = 8
+PHY-1002 : len = 923920, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 924112, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 924224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.829093s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (105.5%)
+
+PHY-1001 : Congestion index: top1 = 56.29, top5 = 50.12, top10 = 46.94, top15 = 44.88.
+PHY-3001 : End congestion estimation; 1.165132s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (103.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71542, tnet num: 17675, tinst num: 6692, tnode num: 93911, tedge num: 118783.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.949568s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (100.2%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 653 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.890538s wall, 2.859375s user + 0.015625s system = 2.875000s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(331): len = 748232, overlap = 0
+PHY-3002 : Step(332): len = 747363, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16198/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919288, over cnt = 71(0%), over = 97, worst = 4
+PHY-1002 : len = 919528, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 920032, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 920080, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 920112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.834924s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (104.8%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.97, top10 = 46.77, top15 = 44.70.
+PHY-3001 : End congestion estimation; 1.169631s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (102.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.917282s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000157527
+PHY-3002 : Step(333): len = 747253, overlap = 1
+PHY-3002 : Step(334): len = 747381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005421s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (288.2%)
+
+PHY-3001 : Legalized: Len = 747516, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062215s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 747582, Over = 0
+PHY-3001 : End incremental placement; 6.651930s wall, 6.734375s user + 0.093750s system = 6.828125s CPU (102.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.818753s wall, 11.812500s user + 0.109375s system = 11.921875s CPU (110.2%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16175/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919680, over cnt = 54(0%), over = 70, worst = 4
+PHY-1002 : len = 919672, over cnt = 35(0%), over = 44, worst = 3
+PHY-1002 : len = 920096, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 920168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.664007s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (105.9%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.95, top10 = 46.76, top15 = 44.70.
+OPT-1001 : End congestion update; 1.012860s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (103.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.770414s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 756770, Over = 0
+PHY-3001 : Spreading special nets. 30 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065757s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.0%)
+
+PHY-3001 : 41 instances has been re-located, deltaX = 12, deltaY = 27, maxDist = 3.
+PHY-3001 : Final: Len = 757514, Over = 0
+PHY-3001 : End incremental legalization; 0.419970s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 60 cells processed and 22074 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758204, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062768s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.6%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 16, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758608, Over = 0
+PHY-3001 : End incremental legalization; 0.411177s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.8%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 4156 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758812, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064584s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.8%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 7, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 759358, Over = 0
+PHY-3001 : End incremental legalization; 0.406475s wall, 0.671875s user + 0.015625s system = 0.687500s CPU (169.1%)
+
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 18 cells processed and 1161 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759597, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063090s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.1%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 759599, Over = 0
+PHY-3001 : End incremental legalization; 0.404166s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.5%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization; 4.016584s wall, 4.375000s user + 0.015625s system = 4.390625s CPU (109.3%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15721/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930944, over cnt = 193(0%), over = 264, worst = 6
+PHY-1002 : len = 931160, over cnt = 92(0%), over = 103, worst = 3
+PHY-1002 : len = 931928, over cnt = 35(0%), over = 35, worst = 1
+PHY-1002 : len = 932424, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932504, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.889419s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (110.7%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 49.54, top10 = 46.48, top15 = 44.48.
+OPT-1001 : End congestion update; 1.230582s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (107.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.761460s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.5%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759705, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070624s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (88.5%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 759739, Over = 0
+PHY-3001 : End incremental legalization; 0.445982s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.6%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.573443s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (106.9%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 730, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.762052s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16201/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932536, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 932560, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 932624, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 932744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 932808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.793367s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.4%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.58, top10 = 46.48, top15 = 44.49.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.754844s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.297664s wall, 23.921875s user + 0.156250s system = 24.078125s CPU (108.0%)
+
+RUN-1003 : finish command "place" in 74.045455s wall, 113.859375s user + 7.687500s system = 121.546875s CPU (164.2%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 645 MB, peak memory is 735 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.794029s wall, 3.156250s user + 0.015625s system = 3.171875s CPU (176.8%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 646 MB, peak memory is 735 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6701 instances
+RUN-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17857 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 734 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.678610s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.5%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 619 MB, peak memory is 735 MB
+PHY-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862800, over cnt = 2648(7%), over = 4341, worst = 9
+PHY-1002 : len = 880744, over cnt = 1618(4%), over = 2343, worst = 9
+PHY-1002 : len = 903616, over cnt = 451(1%), over = 577, worst = 6
+PHY-1002 : len = 912696, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 913024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.341306s wall, 4.531250s user + 0.015625s system = 4.546875s CPU (136.1%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.00, top10 = 45.84, top15 = 43.81.
+PHY-1001 : End global routing; 3.699889s wall, 4.859375s user + 0.015625s system = 4.875000s CPU (131.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 706, reserve = 708, peak = 735.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 981, reserve = 985, peak = 981.
+PHY-1001 : End build detailed router design. 4.343880s wall, 4.281250s user + 0.031250s system = 4.312500s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270736, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.581931s wall, 5.562500s user + 0.000000s system = 5.562500s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270792, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.492883s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.4%)
+
+PHY-1001 : Current memory(MB): used = 1016, reserve = 1020, peak = 1016.
+PHY-1001 : End phase 1; 6.086319s wall, 6.062500s user + 0.000000s system = 6.062500s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1033, peak = 1032.
+PHY-1001 : End initial routed; 38.927874s wall, 72.156250s user + 0.421875s system = 72.578125s CPU (186.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.556802s wall, 3.515625s user + 0.015625s system = 3.531250s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1046, peak = 1045.
+PHY-1001 : End phase 2; 42.484740s wall, 75.671875s user + 0.437500s system = 76.109375s CPU (179.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.156527s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.8%)
+
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.489608s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26109e+06, over cnt = 626(0%), over = 627, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.578824s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (168.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25966e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.787826s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (140.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25927e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.508818s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (104.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25919e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.345665s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (104.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.270692s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (98.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.560123s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.384824s wall, 2.343750s user + 0.046875s system = 2.390625s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1157, peak = 1152.
+PHY-1001 : End phase 3; 10.369323s wall, 11.750000s user + 0.046875s system = 11.796875s CPU (113.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.153379s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (91.7%)
+
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.426902s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.455711s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.482549s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1165, peak = 1159.
+PHY-1001 : End phase 4; 6.396582s wall, 6.375000s user + 0.000000s system = 6.375000s CPU (99.7%)
+
+PHY-1003 : Routed, final wirelength = 2.25928e+06
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1169, peak = 1164.
+PHY-1001 : End export database. 0.066319s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.2%)
+
+PHY-1001 : End detail routing; 70.162277s wall, 104.609375s user + 0.531250s system = 105.140625s CPU (149.9%)
+
+RUN-1003 : finish command "route" in 76.686602s wall, 112.296875s user + 0.546875s system = 112.843750s CPU (147.1%)
+
+RUN-1004 : used memory is 1069 MB, reserved memory is 1093 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10187 out of 19600 51.97%
+#reg 9425 out of 19600 48.09%
+#le 12209
+ #lut only 2784 out of 12209 22.80%
+ #reg only 2022 out of 12209 16.56%
+ #lut® 7403 out of 12209 60.64%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1380
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1287
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 961
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 131
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_307.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P170 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12209 |9160 |1027 |9456 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |457 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |97 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |42 |42 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |759 |371 |96 |575 |0 |0 |
+| u_ADconfig |AD_config |187 |121 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |260 |165 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |384 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |173 |121 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |254 |145 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2935 |2382 |306 |2076 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |170 |93 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort |2735 |2268 |289 |1906 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2326 |1968 |253 |1555 |22 |0 |
+| channelPart |channel_part_8478 |141 |135 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |50 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1807 |1513 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |208 |181 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |961 |694 |170 |656 |0 |0 |
+| ram_switch_state |ram_switch_state |638 |638 |0 |372 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |48 |41 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |235 |36 |273 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3122 |2458 |349 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |115 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2917 |2332 |332 |1914 |25 |1 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2476 |1975 |290 |1550 |22 |1 |
+| channelPart |channel_part_8478 |130 |124 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1909 |1532 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |202 |174 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |1003 |657 |170 |701 |0 |0 |
+| ram_switch_state |ram_switch_state |704 |701 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |352 |251 |81 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |162 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |41 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9896
+ #2 2 4222
+ #3 3 1721
+ #4 4 562
+ #5 5-10 766
+ #6 11-50 583
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.162562s wall, 3.750000s user + 0.015625s system = 3.765625s CPU (174.1%)
+
+RUN-1004 : used memory is 1070 MB, reserved memory is 1094 MB, peak memory is 1164 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.733423s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (100.1%)
+
+RUN-1004 : used memory is 1073 MB, reserved memory is 1097 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.576623s wall, 1.546875s user + 0.015625s system = 1.562500s CPU (99.1%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1115 MB, peak memory is 1164 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6699
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17857, pip num: 168201
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 529
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3230 valid insts, and 469612 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.754404s wall, 62.890625s user + 0.296875s system = 63.187500s CPU (647.8%)
+
+RUN-1004 : used memory is 1245 MB, reserved memory is 1244 MB, peak memory is 1360 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_164910.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_170016.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_170016.log
new file mode 100644
index 0000000..2576f97
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_170016.log
@@ -0,0 +1,3578 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 17:00:16 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.331396s wall, 2.203125s user + 0.125000s system = 2.328125s CPU (99.9%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 322 MB, peak memory is 351 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 1.5000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -multiply_by 1.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 19021 instances
+RUN-0007 : 8696 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21599 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14249 nets have 2 pins
+RUN-1001 : 5919 nets have [3 - 5] pins
+RUN-1001 : 856 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 178 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 19019 instances, 8696 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5958 pins
+PHY-0007 : Cell area utilization is 55%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91022, tnet num: 21421, tinst num: 19019, tnode num: 121280, tedge num: 145932.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.290430s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.3%)
+
+RUN-1004 : used memory is 550 MB, reserved memory is 533 MB, peak memory is 550 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.201970s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (99.3%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.28277e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 19019.
+PHY-3001 : Level 1 #clusters 2574.
+PHY-3001 : End clustering; 0.179165s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.4485e+06, overlap = 566.656
+PHY-3002 : Step(2): len = 1.12189e+06, overlap = 637.219
+PHY-3002 : Step(3): len = 881628, overlap = 734.469
+PHY-3002 : Step(4): len = 735949, overlap = 810.094
+PHY-3002 : Step(5): len = 568407, overlap = 919.781
+PHY-3002 : Step(6): len = 487470, overlap = 1003.03
+PHY-3002 : Step(7): len = 415227, overlap = 1076.34
+PHY-3002 : Step(8): len = 363495, overlap = 1160.97
+PHY-3002 : Step(9): len = 323796, overlap = 1200.09
+PHY-3002 : Step(10): len = 288381, overlap = 1261.81
+PHY-3002 : Step(11): len = 264025, overlap = 1349.38
+PHY-3002 : Step(12): len = 241741, overlap = 1394.84
+PHY-3002 : Step(13): len = 224367, overlap = 1425.56
+PHY-3002 : Step(14): len = 212975, overlap = 1469.81
+PHY-3002 : Step(15): len = 199377, overlap = 1498.16
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.26386e-07
+PHY-3002 : Step(16): len = 200806, overlap = 1453.78
+PHY-3002 : Step(17): len = 233214, overlap = 1355.97
+PHY-3002 : Step(18): len = 234017, overlap = 1288.47
+PHY-3002 : Step(19): len = 234417, overlap = 1223.22
+PHY-3002 : Step(20): len = 229368, overlap = 1182.78
+PHY-3002 : Step(21): len = 226416, overlap = 1194.44
+PHY-3002 : Step(22): len = 221279, overlap = 1162.38
+PHY-3002 : Step(23): len = 217002, overlap = 1154.84
+PHY-3002 : Step(24): len = 212535, overlap = 1142.22
+PHY-3002 : Step(25): len = 209512, overlap = 1143.56
+PHY-3002 : Step(26): len = 206685, overlap = 1131.41
+PHY-3002 : Step(27): len = 204126, overlap = 1142.53
+PHY-3002 : Step(28): len = 201794, overlap = 1145.16
+PHY-3002 : Step(29): len = 199662, overlap = 1145.84
+PHY-3002 : Step(30): len = 198210, overlap = 1145.91
+PHY-3002 : Step(31): len = 195796, overlap = 1140.91
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.85277e-06
+PHY-3002 : Step(32): len = 202732, overlap = 1101.44
+PHY-3002 : Step(33): len = 221192, overlap = 1078.56
+PHY-3002 : Step(34): len = 228961, overlap = 1050.59
+PHY-3002 : Step(35): len = 234282, overlap = 1029.03
+PHY-3002 : Step(36): len = 233958, overlap = 1013.75
+PHY-3002 : Step(37): len = 233561, overlap = 1011.06
+PHY-3002 : Step(38): len = 232011, overlap = 1001.03
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.70555e-06
+PHY-3002 : Step(39): len = 244543, overlap = 946
+PHY-3002 : Step(40): len = 264478, overlap = 895.5
+PHY-3002 : Step(41): len = 273695, overlap = 829.75
+PHY-3002 : Step(42): len = 276570, overlap = 791.156
+PHY-3002 : Step(43): len = 275409, overlap = 787.156
+PHY-3002 : Step(44): len = 275607, overlap = 782.75
+PHY-3002 : Step(45): len = 275279, overlap = 774.469
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.41109e-06
+PHY-3002 : Step(46): len = 294898, overlap = 710.125
+PHY-3002 : Step(47): len = 313067, overlap = 645.531
+PHY-3002 : Step(48): len = 321823, overlap = 613.781
+PHY-3002 : Step(49): len = 324869, overlap = 607.438
+PHY-3002 : Step(50): len = 321931, overlap = 607.25
+PHY-3002 : Step(51): len = 321510, overlap = 599.438
+PHY-3002 : Step(52): len = 320611, overlap = 600.719
+PHY-3002 : Step(53): len = 321270, overlap = 598.281
+PHY-3002 : Step(54): len = 321324, overlap = 594.75
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.48222e-05
+PHY-3002 : Step(55): len = 342878, overlap = 553.344
+PHY-3002 : Step(56): len = 360431, overlap = 513.188
+PHY-3002 : Step(57): len = 364608, overlap = 488.562
+PHY-3002 : Step(58): len = 366130, overlap = 468.312
+PHY-3002 : Step(59): len = 364739, overlap = 439.312
+PHY-3002 : Step(60): len = 365096, overlap = 422.062
+PHY-3002 : Step(61): len = 364851, overlap = 398.438
+PHY-3002 : Step(62): len = 365825, overlap = 378.281
+PHY-3002 : Step(63): len = 365862, overlap = 377.531
+PHY-3002 : Step(64): len = 366606, overlap = 384.281
+PHY-3002 : Step(65): len = 367423, overlap = 386.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.96444e-05
+PHY-3002 : Step(66): len = 386450, overlap = 356.406
+PHY-3002 : Step(67): len = 401634, overlap = 354.594
+PHY-3002 : Step(68): len = 403929, overlap = 372.812
+PHY-3002 : Step(69): len = 403600, overlap = 371.094
+PHY-3002 : Step(70): len = 403186, overlap = 368.75
+PHY-3002 : Step(71): len = 404602, overlap = 365.812
+PHY-3002 : Step(72): len = 403847, overlap = 347.562
+PHY-3002 : Step(73): len = 403892, overlap = 337
+PHY-3002 : Step(74): len = 404983, overlap = 332.969
+PHY-3002 : Step(75): len = 405111, overlap = 341.875
+PHY-3002 : Step(76): len = 404115, overlap = 346.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.92887e-05
+PHY-3002 : Step(77): len = 419164, overlap = 336.625
+PHY-3002 : Step(78): len = 429733, overlap = 322.531
+PHY-3002 : Step(79): len = 431600, overlap = 300.75
+PHY-3002 : Step(80): len = 433230, overlap = 289.5
+PHY-3002 : Step(81): len = 433688, overlap = 307.219
+PHY-3002 : Step(82): len = 434828, overlap = 290.906
+PHY-3002 : Step(83): len = 433055, overlap = 286.281
+PHY-3002 : Step(84): len = 433097, overlap = 292.219
+PHY-3002 : Step(85): len = 432909, overlap = 296.75
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000118577
+PHY-3002 : Step(86): len = 445151, overlap = 268.75
+PHY-3002 : Step(87): len = 454531, overlap = 263.188
+PHY-3002 : Step(88): len = 457666, overlap = 247.188
+PHY-3002 : Step(89): len = 460552, overlap = 247.031
+PHY-3002 : Step(90): len = 463689, overlap = 246.375
+PHY-3002 : Step(91): len = 467944, overlap = 247.188
+PHY-3002 : Step(92): len = 468379, overlap = 237.938
+PHY-3002 : Step(93): len = 468780, overlap = 230.469
+PHY-3002 : Step(94): len = 468313, overlap = 219.219
+PHY-3002 : Step(95): len = 468253, overlap = 220.562
+PHY-3002 : Step(96): len = 467017, overlap = 220.719
+PHY-3002 : Step(97): len = 466894, overlap = 217.031
+PHY-3002 : Step(98): len = 466935, overlap = 222.438
+PHY-3002 : Step(99): len = 468213, overlap = 214.406
+PHY-3002 : Step(100): len = 467751, overlap = 210.281
+PHY-3002 : Step(101): len = 468455, overlap = 208.562
+PHY-3002 : Step(102): len = 468313, overlap = 206.656
+PHY-3002 : Step(103): len = 469379, overlap = 204.188
+PHY-3002 : Step(104): len = 468591, overlap = 204.188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000237155
+PHY-3002 : Step(105): len = 474992, overlap = 204.812
+PHY-3002 : Step(106): len = 481119, overlap = 194.438
+PHY-3002 : Step(107): len = 482541, overlap = 173.875
+PHY-3002 : Step(108): len = 484191, overlap = 168.375
+PHY-3002 : Step(109): len = 486123, overlap = 169.094
+PHY-3002 : Step(110): len = 487818, overlap = 172.906
+PHY-3002 : Step(111): len = 486866, overlap = 185.438
+PHY-3002 : Step(112): len = 487105, overlap = 176.531
+PHY-3002 : Step(113): len = 488300, overlap = 176.469
+PHY-3002 : Step(114): len = 489011, overlap = 174.594
+PHY-3002 : Step(115): len = 487439, overlap = 176.75
+PHY-3002 : Step(116): len = 487373, overlap = 177.469
+PHY-3002 : Step(117): len = 487819, overlap = 180.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000454185
+PHY-3002 : Step(118): len = 493432, overlap = 182.406
+PHY-3002 : Step(119): len = 499972, overlap = 180.219
+PHY-3002 : Step(120): len = 500998, overlap = 180.531
+PHY-3002 : Step(121): len = 501872, overlap = 185.188
+PHY-3002 : Step(122): len = 502932, overlap = 183.031
+PHY-3002 : Step(123): len = 503617, overlap = 176.781
+PHY-3002 : Step(124): len = 503151, overlap = 179.375
+PHY-3002 : Step(125): len = 503283, overlap = 178.656
+PHY-3002 : Step(126): len = 503909, overlap = 169.062
+PHY-3002 : Step(127): len = 504586, overlap = 167.188
+PHY-3002 : Step(128): len = 504156, overlap = 175.031
+PHY-3002 : Step(129): len = 503993, overlap = 180.312
+PHY-3002 : Step(130): len = 504636, overlap = 171.406
+PHY-3002 : Step(131): len = 505361, overlap = 163.812
+PHY-3002 : Step(132): len = 505026, overlap = 173.156
+PHY-3002 : Step(133): len = 504774, overlap = 171.906
+PHY-3002 : Step(134): len = 504901, overlap = 162.938
+PHY-3002 : Step(135): len = 505520, overlap = 166.938
+PHY-3002 : Step(136): len = 504832, overlap = 173.844
+PHY-3002 : Step(137): len = 504602, overlap = 175.094
+PHY-3002 : Step(138): len = 504315, overlap = 174.281
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00081836
+PHY-3002 : Step(139): len = 507144, overlap = 176.469
+PHY-3002 : Step(140): len = 510585, overlap = 178.781
+PHY-3002 : Step(141): len = 511411, overlap = 180.438
+PHY-3002 : Step(142): len = 512072, overlap = 177.75
+PHY-3002 : Step(143): len = 513293, overlap = 168.281
+PHY-3002 : Step(144): len = 514847, overlap = 163.469
+PHY-3002 : Step(145): len = 515310, overlap = 156.531
+PHY-3002 : Step(146): len = 515518, overlap = 156.281
+PHY-3002 : Step(147): len = 515769, overlap = 157.594
+PHY-3002 : Step(148): len = 515843, overlap = 156.125
+PHY-3002 : Step(149): len = 515700, overlap = 151.094
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00132411
+PHY-3002 : Step(150): len = 516885, overlap = 151.312
+PHY-3002 : Step(151): len = 518926, overlap = 149.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015203s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (102.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 689160, over cnt = 1476(4%), over = 6572, worst = 27
+PHY-1001 : End global iterations; 0.909826s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (130.5%)
+
+PHY-1001 : Congestion index: top1 = 72.33, top5 = 57.50, top10 = 50.06, top15 = 45.11.
+PHY-3001 : End congestion estimation; 1.190372s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (124.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.006609s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.96552e-05
+PHY-3002 : Step(152): len = 620709, overlap = 121.094
+PHY-3002 : Step(153): len = 637860, overlap = 108.281
+PHY-3002 : Step(154): len = 622051, overlap = 108.062
+PHY-3002 : Step(155): len = 616692, overlap = 102.219
+PHY-3002 : Step(156): len = 608397, overlap = 102.844
+PHY-3002 : Step(157): len = 603804, overlap = 100.719
+PHY-3002 : Step(158): len = 602208, overlap = 97.9062
+PHY-3002 : Step(159): len = 595521, overlap = 94.4688
+PHY-3002 : Step(160): len = 595578, overlap = 90.75
+PHY-3002 : Step(161): len = 589958, overlap = 91.5938
+PHY-3002 : Step(162): len = 586887, overlap = 95.125
+PHY-3002 : Step(163): len = 584897, overlap = 93.6875
+PHY-3002 : Step(164): len = 582840, overlap = 92.25
+PHY-3002 : Step(165): len = 580515, overlap = 90.4688
+PHY-3002 : Step(166): len = 580096, overlap = 93.0312
+PHY-3002 : Step(167): len = 576531, overlap = 92.75
+PHY-3002 : Step(168): len = 574415, overlap = 92.9688
+PHY-3002 : Step(169): len = 573180, overlap = 89.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00013931
+PHY-3002 : Step(170): len = 571781, overlap = 89.4688
+PHY-3002 : Step(171): len = 574702, overlap = 87.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000245467
+PHY-3002 : Step(172): len = 579405, overlap = 87.4688
+PHY-3002 : Step(173): len = 585691, overlap = 83.125
+PHY-3002 : Step(174): len = 599644, overlap = 80.0938
+PHY-3002 : Step(175): len = 603214, overlap = 79.7188
+PHY-3002 : Step(176): len = 606815, overlap = 77.8438
+PHY-3002 : Step(177): len = 604766, overlap = 81.3438
+PHY-3002 : Step(178): len = 602782, overlap = 81.5625
+PHY-3002 : Step(179): len = 602723, overlap = 79.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 95/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 702168, over cnt = 2602(7%), over = 11190, worst = 43
+PHY-1001 : End global iterations; 1.722807s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (139.7%)
+
+PHY-1001 : Congestion index: top1 = 83.28, top5 = 64.66, top10 = 56.86, top15 = 51.97.
+PHY-3001 : End congestion estimation; 2.048904s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (133.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.017875s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (98.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.26072e-05
+PHY-3002 : Step(180): len = 600578, overlap = 401.719
+PHY-3002 : Step(181): len = 605210, overlap = 361.562
+PHY-3002 : Step(182): len = 598960, overlap = 351.75
+PHY-3002 : Step(183): len = 597242, overlap = 323.594
+PHY-3002 : Step(184): len = 597123, overlap = 291.938
+PHY-3002 : Step(185): len = 592246, overlap = 276.406
+PHY-3002 : Step(186): len = 589840, overlap = 263
+PHY-3002 : Step(187): len = 588419, overlap = 253.688
+PHY-3002 : Step(188): len = 585154, overlap = 256.375
+PHY-3002 : Step(189): len = 582571, overlap = 258.719
+PHY-3002 : Step(190): len = 580125, overlap = 259.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000145214
+PHY-3002 : Step(191): len = 580080, overlap = 253.094
+PHY-3002 : Step(192): len = 581221, overlap = 251.562
+PHY-3002 : Step(193): len = 584815, overlap = 245.188
+PHY-3002 : Step(194): len = 587956, overlap = 239.688
+PHY-3002 : Step(195): len = 588476, overlap = 232.844
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000290429
+PHY-3002 : Step(196): len = 591395, overlap = 224.219
+PHY-3002 : Step(197): len = 593589, overlap = 220.625
+PHY-3002 : Step(198): len = 597211, overlap = 213.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000521736
+PHY-3002 : Step(199): len = 603673, overlap = 199.281
+PHY-3002 : Step(200): len = 607444, overlap = 192.5
+PHY-3002 : Step(201): len = 612216, overlap = 181.969
+PHY-3002 : Step(202): len = 616195, overlap = 170.812
+PHY-3002 : Step(203): len = 618573, overlap = 164.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00101881
+PHY-3002 : Step(204): len = 620495, overlap = 166.812
+PHY-3002 : Step(205): len = 624208, overlap = 162.719
+PHY-3002 : Step(206): len = 628927, overlap = 158.375
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91022, tnet num: 21421, tinst num: 19019, tnode num: 121280, tedge num: 145932.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.667537s wall, 1.625000s user + 0.015625s system = 1.640625s CPU (98.4%)
+
+RUN-1004 : used memory is 591 MB, reserved memory is 580 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 592.31 peak overflow 4.56
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 736/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751024, over cnt = 3276(9%), over = 12329, worst = 31
+PHY-1001 : End global iterations; 1.434611s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (154.7%)
+
+PHY-1001 : Congestion index: top1 = 73.73, top5 = 61.67, top10 = 55.55, top15 = 51.55.
+PHY-1001 : End incremental global routing; 1.799672s wall, 2.546875s user + 0.031250s system = 2.578125s CPU (143.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.036140s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (101.0%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18890 has valid locations, 372 needs to be replaced
+PHY-3001 : design contains 19347 instances, 8782 luts, 9344 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6091 pins
+PHY-3001 : Found 1257 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 660471
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17435/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 769144, over cnt = 3328(9%), over = 12513, worst = 31
+PHY-1001 : End global iterations; 0.295457s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 73.97, top5 = 61.94, top10 = 55.96, top15 = 52.06.
+PHY-3001 : End congestion estimation; 0.590013s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (105.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92351, tnet num: 21749, tinst num: 19347, tnode num: 123349, tedge num: 147934.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.632004s wall, 1.578125s user + 0.046875s system = 1.625000s CPU (99.6%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 650 MB, peak memory is 745 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.144227s wall, 3.031250s user + 0.093750s system = 3.125000s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(207): len = 658836, overlap = 0.5
+PHY-3002 : Step(208): len = 658996, overlap = 0.4375
+PHY-3002 : Step(209): len = 658487, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17507/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765752, over cnt = 3336(9%), over = 12559, worst = 31
+PHY-1001 : End global iterations; 0.288471s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (108.3%)
+
+PHY-1001 : Congestion index: top1 = 73.86, top5 = 62.35, top10 = 56.25, top15 = 52.21.
+PHY-3001 : End congestion estimation; 0.583759s wall, 0.609375s user + 0.015625s system = 0.625000s CPU (107.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.066335s wall, 1.000000s user + 0.062500s system = 1.062500s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000297372
+PHY-3002 : Step(210): len = 658705, overlap = 161.594
+PHY-3002 : Step(211): len = 659387, overlap = 161.406
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000594743
+PHY-3002 : Step(212): len = 659567, overlap = 161.625
+PHY-3002 : Step(213): len = 660376, overlap = 162
+PHY-3001 : Final: Len = 660376, Over = 162
+PHY-3001 : End incremental placement; 6.115758s wall, 6.312500s user + 0.296875s system = 6.609375s CPU (108.1%)
+
+OPT-1001 : Total overflow 599.34 peak overflow 4.56
+OPT-1001 : End high-fanout net optimization; 9.590714s wall, 10.625000s user + 0.343750s system = 10.968750s CPU (114.4%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 740, peak = 764.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17474/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 771616, over cnt = 3286(9%), over = 11181, worst = 31
+PHY-1002 : len = 826312, over cnt = 2536(7%), over = 6566, worst = 22
+PHY-1002 : len = 876400, over cnt = 1423(4%), over = 3327, worst = 22
+PHY-1002 : len = 906064, over cnt = 716(2%), over = 1698, worst = 22
+PHY-1002 : len = 936280, over cnt = 29(0%), over = 70, worst = 13
+PHY-1001 : End global iterations; 2.828606s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (125.4%)
+
+PHY-1001 : Congestion index: top1 = 62.26, top5 = 55.05, top10 = 51.17, top15 = 48.80.
+OPT-1001 : End congestion update; 3.149013s wall, 3.859375s user + 0.000000s system = 3.859375s CPU (122.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.922358s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (98.3%)
+
+OPT-0007 : Start: WNS -4701 TNS -2426099 NUM_FEPS 1065
+OPT-0007 : Iter 1: improved WNS -4085 TNS -2402519 NUM_FEPS 1065 with 71 cells processed and 3658 slack improved
+OPT-0007 : Iter 2: improved WNS -4085 TNS -2397167 NUM_FEPS 1065 with 66 cells processed and 2432 slack improved
+OPT-0007 : Iter 3: improved WNS -4085 TNS -2395719 NUM_FEPS 1065 with 41 cells processed and 1850 slack improved
+OPT-0007 : Iter 4: improved WNS -4085 TNS -2394519 NUM_FEPS 1065 with 53 cells processed and 1016 slack improved
+OPT-0007 : Iter 5: improved WNS -4085 TNS -2393801 NUM_FEPS 1065 with 19 cells processed and 400 slack improved
+OPT-0007 : Iter 6: improved WNS -4085 TNS -2389079 NUM_FEPS 1065 with 2 cells processed and 268 slack improved
+OPT-1001 : End bottleneck based optimization; 4.924038s wall, 5.593750s user + 0.031250s system = 5.625000s CPU (114.2%)
+
+OPT-1001 : Current memory(MB): used = 720, reserve = 712, peak = 764.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17616/21929.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 936504, over cnt = 342(0%), over = 492, worst = 13
+PHY-1002 : len = 935320, over cnt = 213(0%), over = 244, worst = 4
+PHY-1002 : len = 936232, over cnt = 105(0%), over = 117, worst = 3
+PHY-1002 : len = 937728, over cnt = 27(0%), over = 33, worst = 3
+PHY-1002 : len = 939128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.005579s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (116.5%)
+
+PHY-1001 : Congestion index: top1 = 61.88, top5 = 54.63, top10 = 50.95, top15 = 48.65.
+OPT-1001 : End congestion update; 1.318504s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (112.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21751 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.930895s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.7%)
+
+OPT-0007 : Start: WNS -4085 TNS -2389079 NUM_FEPS 1065
+OPT-0007 : Iter 1: improved WNS -4085 TNS -2387363 NUM_FEPS 1065 with 36 cells processed and 2248 slack improved
+OPT-0007 : Iter 2: improved WNS -4085 TNS -2387363 NUM_FEPS 1065 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.414042s wall, 2.546875s user + 0.046875s system = 2.593750s CPU (107.4%)
+
+OPT-1001 : Current memory(MB): used = 722, reserve = 716, peak = 764.
+OPT-1001 : End physical optimization; 18.955754s wall, 20.750000s user + 0.468750s system = 21.218750s CPU (111.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8782 LUT to BLE ...
+SYN-4008 : Packed 8782 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6211 remaining SEQ's ...
+SYN-4005 : Packed 4456 SEQ with LUT/SLICE
+SYN-4006 : 1483 single LUT's are left
+SYN-4006 : 1755 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10537/14392 primitive instances ...
+PHY-3001 : End packing; 2.031644s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7339 instances
+RUN-1001 : 3595 mslices, 3596 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18923 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10441 nets have 2 pins
+RUN-1001 : 6583 nets have [3 - 5] pins
+RUN-1001 : 943 nets have [6 - 10] pins
+RUN-1001 : 508 nets have [11 - 20] pins
+RUN-1001 : 417 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7337 instances, 7191 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3642 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 670132, Over = 367
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7934/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862104, over cnt = 2360(6%), over = 4005, worst = 10
+PHY-1002 : len = 873848, over cnt = 1492(4%), over = 2145, worst = 10
+PHY-1002 : len = 893312, over cnt = 518(1%), over = 660, worst = 6
+PHY-1002 : len = 898488, over cnt = 303(0%), over = 395, worst = 4
+PHY-1002 : len = 905544, over cnt = 44(0%), over = 47, worst = 2
+PHY-1001 : End global iterations; 2.425423s wall, 3.375000s user + 0.015625s system = 3.390625s CPU (139.8%)
+
+PHY-1001 : Congestion index: top1 = 60.32, top5 = 54.16, top10 = 50.47, top15 = 47.91.
+PHY-3001 : End congestion estimation; 2.898253s wall, 3.859375s user + 0.015625s system = 3.875000s CPU (133.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81628, tnet num: 18745, tinst num: 7337, tnode num: 104650, tedge num: 136867.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.901195s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (98.6%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 644 MB, peak memory is 764 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.925034s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.36756e-05
+PHY-3002 : Step(214): len = 654550, overlap = 365.75
+PHY-3002 : Step(215): len = 645611, overlap = 373.75
+PHY-3002 : Step(216): len = 640490, overlap = 384.25
+PHY-3002 : Step(217): len = 637727, overlap = 401.5
+PHY-3002 : Step(218): len = 635494, overlap = 408.25
+PHY-3002 : Step(219): len = 633661, overlap = 405.75
+PHY-3002 : Step(220): len = 631479, overlap = 401
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.73511e-05
+PHY-3002 : Step(221): len = 635058, overlap = 396.5
+PHY-3002 : Step(222): len = 641000, overlap = 384
+PHY-3002 : Step(223): len = 640929, overlap = 386
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000174702
+PHY-3002 : Step(224): len = 649621, overlap = 366
+PHY-3002 : Step(225): len = 655408, overlap = 359.5
+PHY-3002 : Step(226): len = 655175, overlap = 353
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000344773
+PHY-3002 : Step(227): len = 664072, overlap = 342
+PHY-3002 : Step(228): len = 675612, overlap = 330.25
+PHY-3002 : Step(229): len = 676018, overlap = 321
+PHY-3002 : Step(230): len = 676352, overlap = 315
+PHY-3002 : Step(231): len = 678024, overlap = 313.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000578724
+PHY-3002 : Step(232): len = 682318, overlap = 306.25
+PHY-3002 : Step(233): len = 685042, overlap = 298.75
+PHY-3002 : Step(234): len = 690118, overlap = 291.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00115616
+PHY-3002 : Step(235): len = 692400, overlap = 289.75
+PHY-3002 : Step(236): len = 699535, overlap = 279.25
+PHY-3002 : Step(237): len = 708272, overlap = 270.5
+PHY-3002 : Step(238): len = 709642, overlap = 269.25
+PHY-3002 : Step(239): len = 710674, overlap = 260.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.385557s wall, 0.406250s user + 0.656250s system = 1.062500s CPU (275.6%)
+
+PHY-3001 : Trial Legalized: Len = 797754
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 765/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942360, over cnt = 3304(9%), over = 5508, worst = 8
+PHY-1002 : len = 960464, over cnt = 2210(6%), over = 3329, worst = 8
+PHY-1002 : len = 987424, over cnt = 998(2%), over = 1441, worst = 6
+PHY-1002 : len = 1.00032e+06, over cnt = 488(1%), over = 748, worst = 6
+PHY-1002 : len = 1.01297e+06, over cnt = 18(0%), over = 28, worst = 3
+PHY-1001 : End global iterations; 3.165356s wall, 4.546875s user + 0.093750s system = 4.640625s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 60.95, top5 = 54.84, top10 = 51.48, top15 = 49.31.
+PHY-3001 : End congestion estimation; 3.701352s wall, 5.093750s user + 0.093750s system = 5.187500s CPU (140.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.203865s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000216673
+PHY-3002 : Step(240): len = 751778, overlap = 89.25
+PHY-3002 : Step(241): len = 728443, overlap = 142.25
+PHY-3002 : Step(242): len = 710080, overlap = 200.5
+PHY-3002 : Step(243): len = 698874, overlap = 236.25
+PHY-3002 : Step(244): len = 693056, overlap = 251.5
+PHY-3002 : Step(245): len = 688214, overlap = 268.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000433346
+PHY-3002 : Step(246): len = 691584, overlap = 261.5
+PHY-3002 : Step(247): len = 694145, overlap = 257.25
+PHY-3002 : Step(248): len = 695772, overlap = 250.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00083788
+PHY-3002 : Step(249): len = 698784, overlap = 245
+PHY-3002 : Step(250): len = 704555, overlap = 244
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00156457
+PHY-3002 : Step(251): len = 705975, overlap = 243.25
+PHY-3002 : Step(252): len = 712925, overlap = 240.25
+PHY-3002 : Step(253): len = 717257, overlap = 232.5
+PHY-3002 : Step(254): len = 718373, overlap = 231.5
+PHY-3002 : Step(255): len = 720473, overlap = 228
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037053s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (84.3%)
+
+PHY-3001 : Legalized: Len = 759105, Over = 0
+PHY-3001 : Spreading special nets. 561 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.141677s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.3%)
+
+PHY-3001 : 865 instances has been re-located, deltaX = 320, deltaY = 527, maxDist = 3.
+PHY-3001 : Final: Len = 773592, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81628, tnet num: 18745, tinst num: 7340, tnode num: 104650, tedge num: 136867.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.146413s wall, 2.125000s user + 0.015625s system = 2.140625s CPU (99.7%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 673 MB, peak memory is 769 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4791/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 933560, over cnt = 2984(8%), over = 4773, worst = 7
+PHY-1002 : len = 949832, over cnt = 1841(5%), over = 2634, worst = 7
+PHY-1002 : len = 976648, over cnt = 541(1%), over = 710, worst = 7
+PHY-1002 : len = 985288, over cnt = 97(0%), over = 109, worst = 3
+PHY-1002 : len = 988288, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.527011s wall, 3.687500s user + 0.000000s system = 3.687500s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 60.11, top5 = 54.01, top10 = 50.60, top15 = 48.38.
+PHY-1001 : End incremental global routing; 2.958837s wall, 4.125000s user + 0.000000s system = 4.125000s CPU (139.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.032130s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (98.4%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7248 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 778234
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17164/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994648, over cnt = 94(0%), over = 127, worst = 9
+PHY-1002 : len = 994736, over cnt = 53(0%), over = 64, worst = 4
+PHY-1002 : len = 995120, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 995376, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 995584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.971274s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (112.6%)
+
+PHY-1001 : Congestion index: top1 = 60.34, top5 = 54.31, top10 = 50.87, top15 = 48.62.
+PHY-3001 : End congestion estimation; 1.349946s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (108.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81832, tnet num: 18764, tinst num: 7359, tnode num: 104896, tedge num: 137120.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.151828s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (100.2%)
+
+RUN-1004 : used memory is 729 MB, reserved memory is 733 MB, peak memory is 772 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.201026s wall, 3.156250s user + 0.046875s system = 3.203125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(256): len = 776902, overlap = 0
+PHY-3002 : Step(257): len = 776309, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17148/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992440, over cnt = 83(0%), over = 117, worst = 6
+PHY-1002 : len = 992584, over cnt = 48(0%), over = 58, worst = 4
+PHY-1002 : len = 992872, over cnt = 18(0%), over = 20, worst = 2
+PHY-1002 : len = 993376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.706813s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.7%)
+
+PHY-1001 : Congestion index: top1 = 60.22, top5 = 54.05, top10 = 50.71, top15 = 48.49.
+PHY-3001 : End congestion estimation; 1.076850s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (101.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.117631s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000792542
+PHY-3002 : Step(258): len = 776138, overlap = 2.25
+PHY-3002 : Step(259): len = 776274, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005386s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (290.1%)
+
+PHY-3001 : Legalized: Len = 776293, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068637s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (113.8%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 2, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 776361, Over = 0
+PHY-3001 : End incremental placement; 7.350894s wall, 7.421875s user + 0.156250s system = 7.578125s CPU (103.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.984528s wall, 13.234375s user + 0.171875s system = 13.406250s CPU (111.9%)
+
+OPT-1001 : Current memory(MB): used = 784, reserve = 782, peak = 787.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17110/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992352, over cnt = 108(0%), over = 135, worst = 5
+PHY-1002 : len = 992648, over cnt = 45(0%), over = 47, worst = 2
+PHY-1002 : len = 992832, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 993120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.738067s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (105.9%)
+
+PHY-1001 : Congestion index: top1 = 60.41, top5 = 53.93, top10 = 50.62, top15 = 48.40.
+OPT-1001 : End congestion update; 1.108848s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (104.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.863947s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.5%)
+
+OPT-0007 : Start: WNS -4095 TNS -2245387 NUM_FEPS 981
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 776978, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.076450s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (102.2%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 8, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 777278, Over = 0
+PHY-3001 : End incremental legalization; 0.490332s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (108.3%)
+
+OPT-0007 : Iter 1: improved WNS -4054 TNS -2232610 NUM_FEPS 981 with 48 cells processed and 5601 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777614, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069143s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (113.0%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 7, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 777740, Over = 0
+PHY-3001 : End incremental legalization; 0.494888s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.0%)
+
+OPT-0007 : Iter 2: improved WNS -4054 TNS -2231520 NUM_FEPS 981 with 19 cells processed and 1654 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777796, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069262s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.2%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 777908, Over = 0
+PHY-3001 : End incremental legalization; 0.459511s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.6%)
+
+OPT-0007 : Iter 3: improved WNS -4054 TNS -2230249 NUM_FEPS 981 with 10 cells processed and 1227 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777648, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070247s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (89.0%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 777984, Over = 0
+PHY-3001 : End incremental legalization; 0.460393s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.4%)
+
+OPT-0007 : Iter 4: improved WNS -4054 TNS -2227314 NUM_FEPS 981 with 13 cells processed and 853 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777984, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.073134s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (85.5%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 7, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 777958, Over = 0
+PHY-3001 : End incremental legalization; 0.508882s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (98.3%)
+
+OPT-0007 : Iter 5: improved WNS -4054 TNS -2226157 NUM_FEPS 981 with 7 cells processed and 600 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 778240, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069677s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (89.7%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 778258, Over = 0
+PHY-3001 : End incremental legalization; 0.460382s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.8%)
+
+OPT-0007 : Iter 6: improved WNS -4054 TNS -2224669 NUM_FEPS 981 with 4 cells processed and 600 slack improved
+OPT-1001 : End bottleneck based optimization; 6.133122s wall, 6.515625s user + 0.000000s system = 6.515625s CPU (106.2%)
+
+OPT-1001 : Current memory(MB): used = 784, reserve = 783, peak = 787.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16775/18943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994048, over cnt = 439(1%), over = 545, worst = 4
+PHY-1002 : len = 993736, over cnt = 262(0%), over = 297, worst = 4
+PHY-1002 : len = 995448, over cnt = 95(0%), over = 100, worst = 4
+PHY-1002 : len = 996672, over cnt = 40(0%), over = 40, worst = 1
+PHY-1002 : len = 997968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.092785s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (115.8%)
+
+PHY-1001 : Congestion index: top1 = 60.54, top5 = 54.33, top10 = 50.89, top15 = 48.65.
+OPT-1001 : End congestion update; 1.472499s wall, 1.640625s user + 0.015625s system = 1.656250s CPU (112.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.884956s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (98.9%)
+
+OPT-0007 : Start: WNS -4054 TNS -2228716 NUM_FEPS 981
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 778612, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.074874s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (83.5%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 10, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 779012, Over = 0
+PHY-3001 : End incremental legalization; 0.474973s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (121.7%)
+
+OPT-0007 : Iter 1: improved WNS -4054 TNS -2228898 NUM_FEPS 981 with 37 cells processed and 3041 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 779124, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.072008s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (108.5%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 779138, Over = 0
+PHY-3001 : End incremental legalization; 0.470043s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.7%)
+
+OPT-0007 : Iter 2: improved WNS -4054 TNS -2228471 NUM_FEPS 981 with 9 cells processed and 629 slack improved
+OPT-0007 : Iter 3: improved WNS -4054 TNS -2228471 NUM_FEPS 981 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.674664s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (107.6%)
+
+OPT-1001 : Current memory(MB): used = 784, reserve = 783, peak = 787.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.890362s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16976/18943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 997912, over cnt = 158(0%), over = 193, worst = 5
+PHY-1002 : len = 997656, over cnt = 117(0%), over = 135, worst = 5
+PHY-1002 : len = 998472, over cnt = 51(0%), over = 58, worst = 3
+PHY-1002 : len = 999064, over cnt = 19(0%), over = 22, worst = 2
+PHY-1002 : len = 999576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.987319s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (109.2%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.36, top10 = 50.93, top15 = 48.69.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.915727s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -4054 TNS -2229784 NUM_FEPS 981
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 60.413793
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -4054ps with logic level 5
+RUN-1001 : #2 path slack -3995ps with logic level 5
+RUN-1001 : 0 HFN exist on timing critical paths out of 18943 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18943 nets
+OPT-1001 : End physical optimization; 27.570838s wall, 29.546875s user + 0.218750s system = 29.765625s CPU (108.0%)
+
+RUN-1003 : finish command "place" in 81.305753s wall, 116.109375s user + 5.921875s system = 122.031250s CPU (150.1%)
+
+RUN-1004 : used memory is 686 MB, reserved memory is 678 MB, peak memory is 787 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.878926s wall, 3.265625s user + 0.015625s system = 3.281250s CPU (174.6%)
+
+RUN-1004 : used memory is 687 MB, reserved memory is 680 MB, peak memory is 787 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81872, tnet num: 18765, tinst num: 7363, tnode num: 104951, tedge num: 137171.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.876122s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.1%)
+
+RUN-1004 : used memory is 698 MB, reserved memory is 702 MB, peak memory is 787 MB
+PHY-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909224, over cnt = 3287(9%), over = 5337, worst = 7
+PHY-1002 : len = 930584, over cnt = 1989(5%), over = 2857, worst = 7
+PHY-1002 : len = 954544, over cnt = 840(2%), over = 1188, worst = 7
+PHY-1002 : len = 973984, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 974424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.758339s wall, 4.984375s user + 0.015625s system = 5.000000s CPU (133.0%)
+
+PHY-1001 : Congestion index: top1 = 59.35, top5 = 53.78, top10 = 50.28, top15 = 48.09.
+PHY-1001 : End global routing; 4.177391s wall, 5.390625s user + 0.031250s system = 5.421875s CPU (129.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 759, reserve = 761, peak = 787.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1033, peak = 1031.
+PHY-1001 : End build detailed router design. 4.471794s wall, 4.406250s user + 0.046875s system = 4.453125s CPU (99.6%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273664, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.763269s wall, 5.750000s user + 0.000000s system = 5.750000s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273720, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.593138s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1065, reserve = 1068, peak = 1065.
+PHY-1001 : End phase 1; 6.367982s wall, 6.359375s user + 0.000000s system = 6.359375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 35% nets.
+PHY-1001 : Routed 42% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.58654e+06, over cnt = 2305(0%), over = 2324, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1084, reserve = 1087, peak = 1084.
+PHY-1001 : End initial routed; 34.536806s wall, 68.390625s user + 0.421875s system = 68.812500s CPU (199.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -6.182 | -3395.741 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.965794s wall, 3.968750s user + 0.000000s system = 3.968750s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1097, reserve = 1100, peak = 1097.
+PHY-1001 : End phase 2; 38.502800s wall, 72.359375s user + 0.421875s system = 72.781250s CPU (189.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 63 pins with SWNS -6.050ns STNS -3390.015ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.528410s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.5%)
+
+PHY-1022 : len = 2.58686e+06, over cnt = 2360(0%), over = 2379, worst = 2, crit = 2
+PHY-1001 : End optimize timing; 0.886219s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53891e+06, over cnt = 952(0%), over = 954, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 3.014074s wall, 4.484375s user + 0.000000s system = 4.484375s CPU (148.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53486e+06, over cnt = 272(0%), over = 272, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.829272s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (143.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53452e+06, over cnt = 73(0%), over = 73, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.980898s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (119.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53546e+06, over cnt = 30(0%), over = 30, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.537880s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (113.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.5359e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.895090s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (110.0%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53593e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 1.364144s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.53582e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 2.373871s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.53584e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.230001s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (115.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53583e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.259949s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (108.2%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.308663s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.317758s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.438341s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.217590s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (107.7%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.219442s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (113.9%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.252939s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.264232s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.349856s wall, 0.359375s user + 0.031250s system = 0.390625s CPU (111.7%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.436978s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.231146s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.231632s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (114.7%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.255593s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (97.8%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.265829s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (105.8%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.362004s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.429438s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.110684s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.210079s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.1%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.204345s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.248637s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.269496s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (92.8%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.346715s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.423326s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.353813s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.176680s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.212906s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.4%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.209123s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (89.7%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.252307s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.255806s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (103.8%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.353305s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.420118s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.144979s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.135471s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.163391s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.216963s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.221522s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.248006s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.270252s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.342003s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.407814s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.190617s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.364858s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.221019s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.231139s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.213442s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.2%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.228583s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.7%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.258434s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.272830s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.374415s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.437599s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.220510s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.226546s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.216757s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.414906s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.181677s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.220076s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.211049s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (111.1%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.255285s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.267199s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.372527s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.436765s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.221578s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.184708s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.194385s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.196269s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.219318s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.298124s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (99.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -6.050 | -3394.643 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.819390s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1107, reserve = 1110, peak = 1107.
+PHY-1001 : End phase 3; 55.607142s wall, 58.187500s user + 0.125000s system = 58.312500s CPU (104.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 47 pins with SWNS -5.708ns STNS -3385.794ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.415146s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.9%)
+
+PHY-1022 : len = 2.53595e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.749128s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.708ns, -3385.794ns, 981}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53548e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.221545s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53548e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.280245s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (117.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.347280s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.508838s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.756094s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.203620s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.197171s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.237224s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.248268s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.347614s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (98.9%)
+
+PHY-1001 : ===== DR Iter 11 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.211289s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.218434s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.233765s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.284643s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.400358s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.468256s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 17 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.202817s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.207931s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.2%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.237227s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.246636s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.392272s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (95.6%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.453907s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 1.018619s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (98.2%)
+
+PHY-1001 : ===== DR Iter 24 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.200098s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.190090s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.227777s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.236738s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (105.6%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.327599s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.380889s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 1.181879s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 1.144598s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 32 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.192466s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (113.7%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.188432s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (107.8%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.233236s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.245589s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.322155s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.380103s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.249900s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 1.242453s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.147183s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 41 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.206208s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (106.1%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.225732s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (103.8%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.249400s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.263616s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (94.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.344312s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.415176s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (109.1%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.097472s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.112683s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.105976s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.123522s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 51 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.204427s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.218576s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.264872s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.278270s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (95.5%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.404321s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.473170s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.111064s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.113990s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.119748s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.129235s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.110982s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 62 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.201154s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.196747s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.238096s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.251271s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.355498s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.419875s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.129326s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.249654s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.218012s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.183709s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.114836s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.130901s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (98.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.889769s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1109, reserve = 1112, peak = 1109.
+PHY-1001 : End phase 4; 44.041844s wall, 43.984375s user + 0.093750s system = 44.078125s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.53539e+06
+PHY-1001 : 916 feed throughs used by 648 nets
+PHY-1001 : Current memory(MB): used = 1219, reserve = 1227, peak = 1219.
+PHY-1001 : End export database. 2.804391s wall, 2.765625s user + 0.031250s system = 2.796875s CPU (99.7%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 13 2) is for feedthrough
+PHY-3001 : eco cells: (1 26 1) is for feedthrough
+PHY-3001 : eco cells: (1 30 3) is for feedthrough
+PHY-3001 : eco cells: (1 33 3) is for feedthrough
+PHY-3001 : eco cells: (2 2 0) is for feedthrough
+PHY-3001 : eco cells: (2 4 3) is for feedthrough
+PHY-3001 : eco cells: (2 6 0) is for feedthrough
+PHY-3001 : eco cells: (2 6 3) is for feedthrough
+PHY-3001 : eco cells: (2 12 1) is for feedthrough
+PHY-3001 : eco cells: (2 16 0) is for feedthrough
+PHY-3001 : eco cells: (2 24 3) is for feedthrough
+PHY-3001 : eco cells: (2 28 3) is for feedthrough
+PHY-3001 : eco cells: (2 32 0) is for feedthrough
+PHY-3001 : eco cells: (2 34 3) is for feedthrough
+PHY-3001 : eco cells: (2 39 3) is for feedthrough
+PHY-3001 : eco cells: (2 54 2) is for feedthrough
+PHY-3001 : eco cells: (2 68 1) is for feedthrough
+PHY-3001 : eco cells: (3 8 1) is for feedthrough
+PHY-3001 : eco cells: (3 8 3) is for feedthrough
+PHY-3001 : eco cells: (3 15 1) is for feedthrough
+PHY-3001 : eco cells: (3 16 1) is for feedthrough
+PHY-3001 : eco cells: (3 19 0) is for feedthrough
+PHY-3001 : eco cells: (3 22 3) is for feedthrough
+PHY-3001 : eco cells: (3 25 3) is for feedthrough
+PHY-3001 : eco cells: (3 28 3) is for feedthrough
+PHY-3001 : eco cells: (3 34 0) is for feedthrough
+PHY-3001 : eco cells: (3 34 1) is for feedthrough
+PHY-3001 : eco cells: (3 35 3) is for feedthrough
+PHY-3001 : eco cells: (4 8 1) is for feedthrough
+PHY-3001 : eco cells: (4 12 0) is for feedthrough
+PHY-3001 : eco cells: (4 12 2) is for feedthrough
+PHY-3001 : eco cells: (4 13 2) is for feedthrough
+PHY-3001 : eco cells: (4 14 0) is for feedthrough
+PHY-3001 : eco cells: (4 26 3) is for feedthrough
+PHY-3001 : eco cells: (4 30 1) is for feedthrough
+PHY-3001 : eco cells: (4 31 1) is for feedthrough
+PHY-3001 : eco cells: (4 31 2) is for feedthrough
+PHY-3001 : eco cells: (4 35 0) is for feedthrough
+PHY-3001 : eco cells: (4 45 0) is for feedthrough
+PHY-3001 : eco cells: (4 49 2) is for feedthrough
+PHY-3001 : eco cells: (4 53 2) is for feedthrough
+PHY-3001 : eco cells: (4 58 1) is for feedthrough
+PHY-3001 : eco cells: (4 59 0) is for feedthrough
+PHY-3001 : eco cells: (5 3 1) is for feedthrough
+PHY-3001 : eco cells: (5 4 0) is for feedthrough
+PHY-3001 : eco cells: (5 5 2) is for feedthrough
+PHY-3001 : eco cells: (5 5 3) is for feedthrough
+PHY-3001 : eco cells: (5 6 3) is for feedthrough
+PHY-3001 : eco cells: (5 9 0) is for feedthrough
+PHY-3001 : eco cells: (5 10 0) is for feedthrough
+PHY-3001 : eco cells: (5 12 3) is for feedthrough
+PHY-3001 : eco cells: (5 14 2) is for feedthrough
+PHY-3001 : eco cells: (5 15 2) is for feedthrough
+PHY-3001 : eco cells: (5 17 1) is for feedthrough
+PHY-3001 : eco cells: (5 18 0) is for feedthrough
+PHY-3001 : eco cells: (5 19 2) is for feedthrough
+PHY-3001 : eco cells: (5 20 2) is for feedthrough
+PHY-3001 : eco cells: (5 21 0) is for feedthrough
+PHY-3001 : eco cells: (5 29 1) is for feedthrough
+PHY-3001 : eco cells: (5 29 2) is for feedthrough
+PHY-3001 : eco cells: (5 31 0) is for feedthrough
+PHY-3001 : eco cells: (5 33 3) is for feedthrough
+PHY-3001 : eco cells: (5 35 2) is for feedthrough
+PHY-3001 : eco cells: (5 36 1) is for feedthrough
+PHY-3001 : eco cells: (5 36 2) is for feedthrough
+PHY-3001 : eco cells: (5 38 1) is for feedthrough
+PHY-3001 : eco cells: (5 51 3) is for feedthrough
+PHY-3001 : eco cells: (5 59 3) is for feedthrough
+PHY-3001 : eco cells: (5 63 0) is for feedthrough
+PHY-3001 : eco cells: (5 63 3) is for feedthrough
+PHY-3001 : eco cells: (5 66 2) is for feedthrough
+PHY-3001 : eco cells: (6 7 3) is for feedthrough
+PHY-3001 : eco cells: (6 11 3) is for feedthrough
+PHY-3001 : eco cells: (6 12 2) is for feedthrough
+PHY-3001 : eco cells: (6 13 2) is for feedthrough
+PHY-3001 : eco cells: (6 19 2) is for feedthrough
+PHY-3001 : eco cells: (6 20 2) is for feedthrough
+PHY-3001 : eco cells: (6 20 3) is for feedthrough
+PHY-3001 : eco cells: (6 29 0) is for feedthrough
+PHY-3001 : eco cells: (6 29 2) is for feedthrough
+PHY-3001 : eco cells: (6 33 2) is for feedthrough
+PHY-3001 : eco cells: (6 35 0) is for feedthrough
+PHY-3001 : eco cells: (6 36 3) is for feedthrough
+PHY-3001 : eco cells: (6 40 0) is for feedthrough
+PHY-3001 : eco cells: (6 44 3) is for feedthrough
+PHY-3001 : eco cells: (6 53 0) is for feedthrough
+PHY-3001 : eco cells: (6 55 3) is for feedthrough
+PHY-3001 : eco cells: (6 67 2) is for feedthrough
+PHY-3001 : eco cells: (6 68 3) is for feedthrough
+PHY-3001 : eco cells: (7 8 0) is for feedthrough
+PHY-3001 : eco cells: (7 9 0) is for feedthrough
+PHY-3001 : eco cells: (7 10 3) is for feedthrough
+PHY-3001 : eco cells: (7 11 0) is for feedthrough
+PHY-3001 : eco cells: (7 21 3) is for feedthrough
+PHY-3001 : eco cells: (7 28 2) is for feedthrough
+PHY-3001 : eco cells: (7 30 0) is for feedthrough
+PHY-3001 : eco cells: (7 31 0) is for feedthrough
+PHY-3001 : eco cells: (9 9 3) is for feedthrough
+PHY-3001 : eco cells: (9 10 0) is for feedthrough
+PHY-3001 : eco cells: (9 11 0) is for feedthrough
+PHY-3001 : eco cells: (9 11 1) is for feedthrough
+PHY-3001 : eco cells: (9 12 0) is for feedthrough
+PHY-3001 : eco cells: (9 13 2) is for feedthrough
+PHY-3001 : eco cells: (9 14 2) is for feedthrough
+PHY-3001 : eco cells: (9 17 0) is for feedthrough
+PHY-3001 : eco cells: (9 18 1) is for feedthrough
+PHY-3001 : eco cells: (9 22 1) is for feedthrough
+PHY-3001 : eco cells: (9 25 2) is for feedthrough
+PHY-3001 : eco cells: (9 26 1) is for feedthrough
+PHY-3001 : eco cells: (9 29 0) is for feedthrough
+PHY-3001 : eco cells: (9 29 2) is for feedthrough
+PHY-3001 : eco cells: (9 65 0) is for feedthrough
+PHY-3001 : eco cells: (9 69 2) is for feedthrough
+PHY-3001 : eco cells: (10 8 0) is for feedthrough
+PHY-3001 : eco cells: (10 11 1) is for feedthrough
+PHY-3001 : eco cells: (10 12 1) is for feedthrough
+PHY-3001 : eco cells: (10 13 1) is for feedthrough
+PHY-3001 : eco cells: (10 14 2) is for feedthrough
+PHY-3001 : eco cells: (10 16 1) is for feedthrough
+PHY-3001 : eco cells: (10 19 0) is for feedthrough
+PHY-3001 : eco cells: (10 22 1) is for feedthrough
+PHY-3001 : eco cells: (10 22 2) is for feedthrough
+PHY-3001 : eco cells: (10 24 3) is for feedthrough
+PHY-3001 : eco cells: (10 25 0) is for feedthrough
+PHY-3001 : eco cells: (10 27 0) is for feedthrough
+PHY-3001 : eco cells: (10 27 2) is for feedthrough
+PHY-3001 : eco cells: (10 36 3) is for feedthrough
+PHY-3001 : eco cells: (10 42 2) is for feedthrough
+PHY-3001 : eco cells: (10 58 3) is for feedthrough
+PHY-3001 : eco cells: (10 59 0) is for feedthrough
+PHY-3001 : eco cells: (10 63 2) is for feedthrough
+PHY-3001 : eco cells: (10 67 0) is for feedthrough
+PHY-3001 : eco cells: (11 7 0) is for feedthrough
+PHY-3001 : eco cells: (11 8 2) is for feedthrough
+PHY-3001 : eco cells: (11 9 0) is for feedthrough
+PHY-3001 : eco cells: (11 10 1) is for feedthrough
+PHY-3001 : eco cells: (11 11 0) is for feedthrough
+PHY-3001 : eco cells: (11 11 2) is for feedthrough
+PHY-3001 : eco cells: (11 12 0) is for feedthrough
+PHY-3001 : eco cells: (11 12 3) is for feedthrough
+PHY-3001 : eco cells: (11 13 3) is for feedthrough
+PHY-3001 : eco cells: (11 14 3) is for feedthrough
+PHY-3001 : eco cells: (11 15 0) is for feedthrough
+PHY-3001 : eco cells: (11 18 1) is for feedthrough
+PHY-3001 : eco cells: (11 21 2) is for feedthrough
+PHY-3001 : eco cells: (11 23 1) is for feedthrough
+PHY-3001 : eco cells: (11 24 0) is for feedthrough
+PHY-3001 : eco cells: (11 25 0) is for feedthrough
+PHY-3001 : eco cells: (11 25 2) is for feedthrough
+PHY-3001 : eco cells: (11 27 1) is for feedthrough
+PHY-3001 : eco cells: (11 30 1) is for feedthrough
+PHY-3001 : eco cells: (11 33 0) is for feedthrough
+PHY-3001 : eco cells: (11 40 2) is for feedthrough
+PHY-3001 : eco cells: (11 41 2) is for feedthrough
+PHY-3001 : eco cells: (11 49 2) is for feedthrough
+PHY-3001 : eco cells: (11 50 2) is for feedthrough
+PHY-3001 : eco cells: (11 53 2) is for feedthrough
+PHY-3001 : eco cells: (11 61 0) is for feedthrough
+PHY-3001 : eco cells: (11 65 2) is for feedthrough
+PHY-3001 : eco cells: (11 66 3) is for feedthrough
+PHY-3001 : eco cells: (12 7 2) is for feedthrough
+PHY-3001 : eco cells: (12 8 0) is for feedthrough
+PHY-3001 : eco cells: (12 10 1) is for feedthrough
+PHY-3001 : eco cells: (12 13 0) is for feedthrough
+PHY-3001 : eco cells: (12 13 2) is for feedthrough
+PHY-3001 : eco cells: (12 14 0) is for feedthrough
+PHY-3001 : eco cells: (12 15 3) is for feedthrough
+PHY-3001 : eco cells: (12 16 0) is for feedthrough
+PHY-3001 : eco cells: (12 16 1) is for feedthrough
+PHY-3001 : eco cells: (12 28 2) is for feedthrough
+PHY-3001 : eco cells: (12 30 0) is for feedthrough
+PHY-3001 : eco cells: (12 35 3) is for feedthrough
+PHY-3001 : eco cells: (12 38 1) is for feedthrough
+PHY-3001 : eco cells: (12 45 1) is for feedthrough
+PHY-3001 : eco cells: (12 49 2) is for feedthrough
+PHY-3001 : eco cells: (12 56 1) is for feedthrough
+PHY-3001 : eco cells: (12 63 2) is for feedthrough
+PHY-3001 : eco cells: (12 66 0) is for feedthrough
+PHY-3001 : eco cells: (13 10 0) is for feedthrough
+PHY-3001 : eco cells: (13 10 2) is for feedthrough
+PHY-3001 : eco cells: (13 12 0) is for feedthrough
+PHY-3001 : eco cells: (13 12 1) is for feedthrough
+PHY-3001 : eco cells: (13 16 0) is for feedthrough
+PHY-3001 : eco cells: (13 22 0) is for feedthrough
+PHY-3001 : eco cells: (13 27 3) is for feedthrough
+PHY-3001 : eco cells: (13 29 1) is for feedthrough
+PHY-3001 : eco cells: (13 31 2) is for feedthrough
+PHY-3001 : eco cells: (13 33 1) is for feedthrough
+PHY-3001 : eco cells: (13 34 2) is for feedthrough
+PHY-3001 : eco cells: (13 35 3) is for feedthrough
+PHY-3001 : eco cells: (13 43 2) is for feedthrough
+PHY-3001 : eco cells: (13 47 2) is for feedthrough
+PHY-3001 : eco cells: (13 50 2) is for feedthrough
+PHY-3001 : eco cells: (13 51 0) is for feedthrough
+PHY-3001 : eco cells: (13 54 2) is for feedthrough
+PHY-3001 : eco cells: (13 54 3) is for feedthrough
+PHY-3001 : eco cells: (13 57 0) is for feedthrough
+PHY-3001 : eco cells: (13 58 2) is for feedthrough
+PHY-3001 : eco cells: (13 62 0) is for feedthrough
+PHY-3001 : eco cells: (13 63 3) is for feedthrough
+PHY-3001 : eco cells: (13 64 0) is for feedthrough
+PHY-3001 : eco cells: (13 64 1) is for feedthrough
+PHY-3001 : eco cells: (13 67 3) is for feedthrough
+PHY-3001 : eco cells: (14 4 3) is for feedthrough
+PHY-3001 : eco cells: (14 11 1) is for feedthrough
+PHY-3001 : eco cells: (14 11 2) is for feedthrough
+PHY-3001 : eco cells: (14 12 2) is for feedthrough
+PHY-3001 : eco cells: (14 14 0) is for feedthrough
+PHY-3001 : eco cells: (14 14 1) is for feedthrough
+PHY-3001 : eco cells: (14 18 3) is for feedthrough
+PHY-3001 : eco cells: (14 20 2) is for feedthrough
+PHY-3001 : eco cells: (14 20 3) is for feedthrough
+PHY-3001 : eco cells: (14 21 0) is for feedthrough
+PHY-3001 : eco cells: (14 21 2) is for feedthrough
+PHY-3001 : eco cells: (14 22 1) is for feedthrough
+PHY-3001 : eco cells: (14 25 1) is for feedthrough
+PHY-3001 : eco cells: (14 25 2) is for feedthrough
+PHY-3001 : eco cells: (14 26 3) is for feedthrough
+PHY-3001 : eco cells: (14 27 2) is for feedthrough
+PHY-3001 : eco cells: (14 28 2) is for feedthrough
+PHY-3001 : eco cells: (14 35 0) is for feedthrough
+PHY-3001 : eco cells: (14 43 2) is for feedthrough
+PHY-3001 : eco cells: (14 48 1) is for feedthrough
+PHY-3001 : eco cells: (14 49 0) is for feedthrough
+PHY-3001 : eco cells: (14 50 2) is for feedthrough
+PHY-3001 : eco cells: (14 69 3) is for feedthrough
+PHY-3001 : eco cells: (15 10 2) is for feedthrough
+PHY-3001 : eco cells: (15 13 2) is for feedthrough
+PHY-3001 : eco cells: (15 32 1) is for feedthrough
+PHY-3001 : eco cells: (15 33 2) is for feedthrough
+PHY-3001 : eco cells: (15 43 0) is for feedthrough
+PHY-3001 : eco cells: (15 56 2) is for feedthrough
+PHY-3001 : eco cells: (15 61 0) is for feedthrough
+PHY-3001 : eco cells: (15 62 3) is for feedthrough
+PHY-3001 : eco cells: (15 65 3) is for feedthrough
+PHY-3001 : eco cells: (17 6 2) is for feedthrough
+PHY-3001 : eco cells: (17 16 3) is for feedthrough
+PHY-3001 : eco cells: (17 17 2) is for feedthrough
+PHY-3001 : eco cells: (17 18 3) is for feedthrough
+PHY-3001 : eco cells: (17 21 0) is for feedthrough
+PHY-3001 : eco cells: (17 23 3) is for feedthrough
+PHY-3001 : eco cells: (17 24 1) is for feedthrough
+PHY-3001 : eco cells: (17 24 3) is for feedthrough
+PHY-3001 : eco cells: (17 25 2) is for feedthrough
+PHY-3001 : eco cells: (17 26 1) is for feedthrough
+PHY-3001 : eco cells: (17 27 1) is for feedthrough
+PHY-3001 : eco cells: (17 28 1) is for feedthrough
+PHY-3001 : eco cells: (17 30 2) is for feedthrough
+PHY-3001 : eco cells: (17 31 2) is for feedthrough
+PHY-3001 : eco cells: (17 62 3) is for feedthrough
+PHY-3001 : eco cells: (17 66 0) is for feedthrough
+PHY-3001 : eco cells: (18 6 3) is for feedthrough
+PHY-3001 : eco cells: (18 7 1) is for feedthrough
+PHY-3001 : eco cells: (18 8 3) is for feedthrough
+PHY-3001 : eco cells: (18 14 1) is for feedthrough
+PHY-3001 : eco cells: (18 17 2) is for feedthrough
+PHY-3001 : eco cells: (18 21 3) is for feedthrough
+PHY-3001 : eco cells: (18 24 2) is for feedthrough
+PHY-3001 : eco cells: (18 25 3) is for feedthrough
+PHY-3001 : eco cells: (18 27 0) is for feedthrough
+PHY-3001 : eco cells: (18 28 1) is for feedthrough
+PHY-3001 : eco cells: (18 30 1) is for feedthrough
+PHY-3001 : eco cells: (18 32 0) is for feedthrough
+PHY-3001 : eco cells: (18 34 1) is for feedthrough
+PHY-3001 : eco cells: (18 35 0) is for feedthrough
+PHY-3001 : eco cells: (18 36 3) is for feedthrough
+PHY-3001 : eco cells: (18 44 0) is for feedthrough
+PHY-3001 : eco cells: (18 46 1) is for feedthrough
+PHY-3001 : eco cells: (18 62 3) is for feedthrough
+PHY-3001 : eco cells: (19 3 0) is for feedthrough
+PHY-3001 : eco cells: (19 3 1) is for feedthrough
+PHY-3001 : eco cells: (19 5 1) is for feedthrough
+PHY-3001 : eco cells: (19 7 0) is for feedthrough
+PHY-3001 : eco cells: (19 8 0) is for feedthrough
+PHY-3001 : eco cells: (19 13 3) is for feedthrough
+PHY-3001 : eco cells: (19 16 1) is for feedthrough
+PHY-3001 : eco cells: (19 18 0) is for feedthrough
+PHY-3001 : eco cells: (19 18 1) is for feedthrough
+PHY-3001 : eco cells: (19 23 0) is for feedthrough
+PHY-3001 : eco cells: (19 23 3) is for feedthrough
+PHY-3001 : eco cells: (19 25 2) is for feedthrough
+PHY-3001 : eco cells: (19 27 0) is for feedthrough
+PHY-3001 : eco cells: (19 28 1) is for feedthrough
+PHY-3001 : eco cells: (19 29 0) is for feedthrough
+PHY-3001 : eco cells: (19 30 1) is for feedthrough
+PHY-3001 : eco cells: (19 31 1) is for feedthrough
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+PHY-3001 : eco cells: (36 19 1) is for feedthrough
+PHY-3001 : eco cells: (36 20 0) is for feedthrough
+PHY-3001 : eco cells: (36 20 1) is for feedthrough
+PHY-3001 : eco cells: (36 21 2) is for feedthrough
+PHY-3001 : eco cells: (36 24 3) is for feedthrough
+PHY-3001 : eco cells: (36 25 1) is for feedthrough
+PHY-3001 : eco cells: (36 27 0) is for feedthrough
+PHY-3001 : eco cells: (36 27 1) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 1) is for feedthrough
+PHY-3001 : eco cells: (36 29 0) is for feedthrough
+PHY-3001 : eco cells: (36 29 2) is for feedthrough
+PHY-3001 : eco cells: (36 32 2) is for feedthrough
+PHY-3001 : eco cells: (36 33 1) is for feedthrough
+PHY-3001 : eco cells: (36 34 0) is for feedthrough
+PHY-3001 : eco cells: (36 42 0) is for feedthrough
+PHY-3001 : eco cells: (36 50 2) is for feedthrough
+PHY-3001 : eco cells: (36 51 3) is for feedthrough
+PHY-3001 : eco cells: (36 66 3) is for feedthrough
+PHY-3001 : eco cells: (37 4 0) is for feedthrough
+PHY-3001 : eco cells: (37 16 1) is for feedthrough
+PHY-3001 : eco cells: (37 18 1) is for feedthrough
+PHY-3001 : eco cells: (37 18 3) is for feedthrough
+PHY-3001 : eco cells: (37 19 2) is for feedthrough
+PHY-3001 : eco cells: (37 20 0) is for feedthrough
+PHY-3001 : eco cells: (37 21 2) is for feedthrough
+PHY-3001 : eco cells: (37 21 3) is for feedthrough
+PHY-3001 : eco cells: (37 22 1) is for feedthrough
+PHY-3001 : eco cells: (37 24 1) is for feedthrough
+PHY-3001 : eco cells: (37 25 2) is for feedthrough
+PHY-3001 : eco cells: (37 26 2) is for feedthrough
+PHY-3001 : eco cells: (37 27 1) is for feedthrough
+PHY-3001 : eco cells: (37 27 2) is for feedthrough
+PHY-3001 : eco cells: (37 28 2) is for feedthrough
+PHY-3001 : eco cells: (37 28 3) is for feedthrough
+PHY-3001 : eco cells: (37 29 2) is for feedthrough
+PHY-3001 : eco cells: (37 31 0) is for feedthrough
+PHY-3001 : eco cells: (37 31 1) is for feedthrough
+PHY-3001 : eco cells: (37 53 3) is for feedthrough
+PHY-3001 : eco cells: (37 64 2) is for feedthrough
+PHY-3001 : eco cells: (37 65 2) is for feedthrough
+PHY-3001 : eco cells: (38 9 1) is for feedthrough
+PHY-3001 : eco cells: (38 10 0) is for feedthrough
+PHY-3001 : eco cells: (38 19 3) is for feedthrough
+PHY-3001 : eco cells: (38 21 2) is for feedthrough
+PHY-3001 : eco cells: (38 22 1) is for feedthrough
+PHY-3001 : eco cells: (38 23 1) is for feedthrough
+PHY-3001 : eco cells: (38 27 1) is for feedthrough
+PHY-3001 : eco cells: (38 30 2) is for feedthrough
+PHY-3001 : eco cells: (38 32 1) is for feedthrough
+PHY-3001 : eco cells: (38 32 3) is for feedthrough
+PHY-3001 : eco cells: (38 40 1) is for feedthrough
+PHY-3001 : eco cells: (38 67 3) is for feedthrough
+PHY-3001 : eco cells: (39 12 1) is for feedthrough
+PHY-3001 : eco cells: (39 13 3) is for feedthrough
+PHY-3001 : eco cells: (39 19 3) is for feedthrough
+PHY-3001 : eco cells: (39 27 1) is for feedthrough
+PHY-3001 : eco cells: (39 29 2) is for feedthrough
+PHY-3001 : eco cells: (39 29 3) is for feedthrough
+PHY-3001 : eco cells: (39 30 3) is for feedthrough
+PHY-3001 : eco cells: (39 33 3) is for feedthrough
+PHY-3001 : eco cells: (39 39 1) is for feedthrough
+PHY-3001 : eco cells: (39 41 2) is for feedthrough
+PHY-3001 : eco cells: (39 41 3) is for feedthrough
+PHY-3001 : eco cells: (39 42 2) is for feedthrough
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.933178s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (98.8%)
+
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.472312s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (100.8%)
+
+RUN-1004 : used memory is 1215 MB, reserved memory is 1223 MB, peak memory is 1219 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1216, reserve = 1223, peak = 1219.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1239, reserve = 1246, peak = 1239.
+PHY-1001 : End build detailed router design. 2.206824s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.022747s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (137.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.034757s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.033912s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (138.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.032539s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (96.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.033029s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (141.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.033206s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (94.1%)
+
+PHY-1001 : Current memory(MB): used = 1239, reserve = 1246, peak = 1239.
+PHY-1001 : End phase 1; 0.228179s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1239, reserve = 1246, peak = 1239.
+PHY-1001 : End initial routed; 0.172765s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.861004s wall, 3.859375s user + 0.000000s system = 3.859375s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1240, reserve = 1247, peak = 1240.
+PHY-1001 : End phase 2; 4.033829s wall, 4.031250s user + 0.000000s system = 4.031250s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 11 pins with SWNS -5.791ns STNS -3388.165ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.153952s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.5%)
+
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.445154s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.155902s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.156748s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.155985s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.155186s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.157678s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.159536s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.9%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.161131s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (116.4%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.154424s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.156953s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.156044s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.154796s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.161648s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.157389s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (109.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.154704s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (111.1%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.180976s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (120.9%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.219977s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.154744s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.162482s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.157135s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.155233s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.154807s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.158713s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.157390s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.158403s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.159645s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (107.7%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.157262s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.183721s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.157503s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.156153s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.157510s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.157291s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.154819s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.161148s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.154810s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (121.1%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.157628s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (138.8%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.156909s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.155410s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (90.5%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.157581s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (109.1%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.157337s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.154876s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.159499s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.0%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.162049s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.155911s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (110.2%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.152493s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.153553s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.155973s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.154481s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.157567s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.162764s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.162096s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.162921s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.9%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.167332s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.162013s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (115.7%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.157969s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.156549s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.154857s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.157035s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.152314s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.3%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.155667s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (120.4%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.157184s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (109.3%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.153552s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (91.6%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.154855s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.160771s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.9%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.151529s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.156497s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.151345s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.9%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.156655s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.157685s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.157272s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.155459s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.156673s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.156253s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (120.0%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.154237s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (111.4%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.155823s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.811419s wall, 3.812500s user + 0.000000s system = 3.812500s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1240, reserve = 1247, peak = 1240.
+PHY-1001 : End phase 3; 16.113205s wall, 16.250000s user + 0.140625s system = 16.390625s CPU (101.7%)
+
+PHY-1001 : 916 feed throughs used by 648 nets
+PHY-1001 : Current memory(MB): used = 1240, reserve = 1247, peak = 1240.
+PHY-1001 : End export database. 2.857283s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (99.5%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x25y22_w2beg5), nets: u_bus_top/lv_cnt_a_sync1d[17] u_bus_top/u_local_bus_slve_cis/slv_mcu_din[31]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 27.278613s wall, 26.906250s user + 0.140625s system = 27.046875s CPU (99.2%)
+
+RUN-1004 : used memory is 1225 MB, reserved memory is 1233 MB, peak memory is 1240 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x25y22_w2beg5), nets: u_bus_top/lv_cnt_a_sync1d[17] u_bus_top/u_local_bus_slve_cis/slv_mcu_din[31]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 188.031594s wall, 225.109375s user + 0.937500s system = 226.046875s CPU (120.2%)
+
+RUN-1004 : used memory is 1225 MB, reserved memory is 1233 MB, peak memory is 1240 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_170016.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_170937.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_170937.log
new file mode 100644
index 0000000..624e33a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_170937.log
@@ -0,0 +1,3583 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 17:09:37 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.298723s wall, 2.156250s user + 0.093750s system = 2.250000s CPU (97.9%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 322 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 1.5000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -multiply_by 1.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 19021 instances
+RUN-0007 : 8696 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21599 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14249 nets have 2 pins
+RUN-1001 : 5919 nets have [3 - 5] pins
+RUN-1001 : 856 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 178 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 19019 instances, 8696 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5958 pins
+PHY-0007 : Cell area utilization is 55%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91022, tnet num: 21421, tinst num: 19019, tnode num: 121280, tedge num: 145932.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.188404s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.9%)
+
+RUN-1004 : used memory is 550 MB, reserved memory is 533 MB, peak memory is 550 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.021591s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (99.7%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.28277e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 19019.
+PHY-3001 : Level 1 #clusters 2574.
+PHY-3001 : End clustering; 0.143567s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (141.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.4485e+06, overlap = 566.656
+PHY-3002 : Step(2): len = 1.12189e+06, overlap = 637.219
+PHY-3002 : Step(3): len = 881628, overlap = 734.469
+PHY-3002 : Step(4): len = 735949, overlap = 810.094
+PHY-3002 : Step(5): len = 568407, overlap = 919.781
+PHY-3002 : Step(6): len = 487470, overlap = 1003.03
+PHY-3002 : Step(7): len = 415227, overlap = 1076.34
+PHY-3002 : Step(8): len = 363495, overlap = 1160.97
+PHY-3002 : Step(9): len = 323796, overlap = 1200.09
+PHY-3002 : Step(10): len = 288381, overlap = 1261.81
+PHY-3002 : Step(11): len = 264025, overlap = 1349.38
+PHY-3002 : Step(12): len = 241741, overlap = 1394.84
+PHY-3002 : Step(13): len = 224367, overlap = 1425.56
+PHY-3002 : Step(14): len = 212975, overlap = 1469.81
+PHY-3002 : Step(15): len = 199377, overlap = 1498.16
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.26386e-07
+PHY-3002 : Step(16): len = 200806, overlap = 1453.78
+PHY-3002 : Step(17): len = 233214, overlap = 1355.97
+PHY-3002 : Step(18): len = 234017, overlap = 1288.47
+PHY-3002 : Step(19): len = 234417, overlap = 1223.22
+PHY-3002 : Step(20): len = 229368, overlap = 1182.78
+PHY-3002 : Step(21): len = 226416, overlap = 1194.44
+PHY-3002 : Step(22): len = 221279, overlap = 1162.38
+PHY-3002 : Step(23): len = 217002, overlap = 1154.84
+PHY-3002 : Step(24): len = 212535, overlap = 1142.22
+PHY-3002 : Step(25): len = 209512, overlap = 1143.56
+PHY-3002 : Step(26): len = 206685, overlap = 1131.41
+PHY-3002 : Step(27): len = 204126, overlap = 1142.53
+PHY-3002 : Step(28): len = 201794, overlap = 1145.16
+PHY-3002 : Step(29): len = 199662, overlap = 1145.84
+PHY-3002 : Step(30): len = 198210, overlap = 1145.91
+PHY-3002 : Step(31): len = 195796, overlap = 1140.91
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.85277e-06
+PHY-3002 : Step(32): len = 202732, overlap = 1101.44
+PHY-3002 : Step(33): len = 221192, overlap = 1078.56
+PHY-3002 : Step(34): len = 228961, overlap = 1050.59
+PHY-3002 : Step(35): len = 234282, overlap = 1029.03
+PHY-3002 : Step(36): len = 233958, overlap = 1013.75
+PHY-3002 : Step(37): len = 233561, overlap = 1011.06
+PHY-3002 : Step(38): len = 232011, overlap = 1001.03
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.70555e-06
+PHY-3002 : Step(39): len = 244543, overlap = 946
+PHY-3002 : Step(40): len = 264478, overlap = 895.5
+PHY-3002 : Step(41): len = 273695, overlap = 829.75
+PHY-3002 : Step(42): len = 276570, overlap = 791.156
+PHY-3002 : Step(43): len = 275409, overlap = 787.156
+PHY-3002 : Step(44): len = 275607, overlap = 782.75
+PHY-3002 : Step(45): len = 275279, overlap = 774.469
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.41109e-06
+PHY-3002 : Step(46): len = 294898, overlap = 710.125
+PHY-3002 : Step(47): len = 313067, overlap = 645.531
+PHY-3002 : Step(48): len = 321823, overlap = 613.781
+PHY-3002 : Step(49): len = 324869, overlap = 607.438
+PHY-3002 : Step(50): len = 321931, overlap = 607.25
+PHY-3002 : Step(51): len = 321510, overlap = 599.438
+PHY-3002 : Step(52): len = 320611, overlap = 600.719
+PHY-3002 : Step(53): len = 321270, overlap = 598.281
+PHY-3002 : Step(54): len = 321324, overlap = 594.75
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.48222e-05
+PHY-3002 : Step(55): len = 342878, overlap = 553.344
+PHY-3002 : Step(56): len = 360431, overlap = 513.188
+PHY-3002 : Step(57): len = 364608, overlap = 488.562
+PHY-3002 : Step(58): len = 366130, overlap = 468.312
+PHY-3002 : Step(59): len = 364739, overlap = 439.312
+PHY-3002 : Step(60): len = 365096, overlap = 422.062
+PHY-3002 : Step(61): len = 364851, overlap = 398.438
+PHY-3002 : Step(62): len = 365825, overlap = 378.281
+PHY-3002 : Step(63): len = 365862, overlap = 377.531
+PHY-3002 : Step(64): len = 366606, overlap = 384.281
+PHY-3002 : Step(65): len = 367423, overlap = 386.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.96444e-05
+PHY-3002 : Step(66): len = 386450, overlap = 356.406
+PHY-3002 : Step(67): len = 401634, overlap = 354.594
+PHY-3002 : Step(68): len = 403929, overlap = 372.812
+PHY-3002 : Step(69): len = 403600, overlap = 371.094
+PHY-3002 : Step(70): len = 403186, overlap = 368.75
+PHY-3002 : Step(71): len = 404602, overlap = 365.812
+PHY-3002 : Step(72): len = 403847, overlap = 347.562
+PHY-3002 : Step(73): len = 403892, overlap = 337
+PHY-3002 : Step(74): len = 404983, overlap = 332.969
+PHY-3002 : Step(75): len = 405111, overlap = 341.875
+PHY-3002 : Step(76): len = 404115, overlap = 346.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.92887e-05
+PHY-3002 : Step(77): len = 419164, overlap = 336.625
+PHY-3002 : Step(78): len = 429733, overlap = 322.531
+PHY-3002 : Step(79): len = 431600, overlap = 300.75
+PHY-3002 : Step(80): len = 433230, overlap = 289.5
+PHY-3002 : Step(81): len = 433688, overlap = 307.219
+PHY-3002 : Step(82): len = 434828, overlap = 290.906
+PHY-3002 : Step(83): len = 433055, overlap = 286.281
+PHY-3002 : Step(84): len = 433097, overlap = 292.219
+PHY-3002 : Step(85): len = 432909, overlap = 296.75
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000118577
+PHY-3002 : Step(86): len = 445151, overlap = 268.75
+PHY-3002 : Step(87): len = 454531, overlap = 263.188
+PHY-3002 : Step(88): len = 457666, overlap = 247.188
+PHY-3002 : Step(89): len = 460552, overlap = 247.031
+PHY-3002 : Step(90): len = 463689, overlap = 246.375
+PHY-3002 : Step(91): len = 467944, overlap = 247.188
+PHY-3002 : Step(92): len = 468379, overlap = 237.938
+PHY-3002 : Step(93): len = 468780, overlap = 230.469
+PHY-3002 : Step(94): len = 468313, overlap = 219.219
+PHY-3002 : Step(95): len = 468253, overlap = 220.562
+PHY-3002 : Step(96): len = 467017, overlap = 220.719
+PHY-3002 : Step(97): len = 466894, overlap = 217.031
+PHY-3002 : Step(98): len = 466935, overlap = 222.438
+PHY-3002 : Step(99): len = 468213, overlap = 214.406
+PHY-3002 : Step(100): len = 467751, overlap = 210.281
+PHY-3002 : Step(101): len = 468455, overlap = 208.562
+PHY-3002 : Step(102): len = 468313, overlap = 206.656
+PHY-3002 : Step(103): len = 469379, overlap = 204.188
+PHY-3002 : Step(104): len = 468591, overlap = 204.188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000237155
+PHY-3002 : Step(105): len = 474992, overlap = 204.812
+PHY-3002 : Step(106): len = 481119, overlap = 194.438
+PHY-3002 : Step(107): len = 482541, overlap = 173.875
+PHY-3002 : Step(108): len = 484191, overlap = 168.375
+PHY-3002 : Step(109): len = 486123, overlap = 169.094
+PHY-3002 : Step(110): len = 487818, overlap = 172.906
+PHY-3002 : Step(111): len = 486866, overlap = 185.438
+PHY-3002 : Step(112): len = 487105, overlap = 176.531
+PHY-3002 : Step(113): len = 488300, overlap = 176.469
+PHY-3002 : Step(114): len = 489011, overlap = 174.594
+PHY-3002 : Step(115): len = 487439, overlap = 176.75
+PHY-3002 : Step(116): len = 487373, overlap = 177.469
+PHY-3002 : Step(117): len = 487819, overlap = 180.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000454185
+PHY-3002 : Step(118): len = 493432, overlap = 182.406
+PHY-3002 : Step(119): len = 499972, overlap = 180.219
+PHY-3002 : Step(120): len = 500998, overlap = 180.531
+PHY-3002 : Step(121): len = 501872, overlap = 185.188
+PHY-3002 : Step(122): len = 502932, overlap = 183.031
+PHY-3002 : Step(123): len = 503617, overlap = 176.781
+PHY-3002 : Step(124): len = 503151, overlap = 179.375
+PHY-3002 : Step(125): len = 503283, overlap = 178.656
+PHY-3002 : Step(126): len = 503909, overlap = 169.062
+PHY-3002 : Step(127): len = 504586, overlap = 167.188
+PHY-3002 : Step(128): len = 504156, overlap = 175.031
+PHY-3002 : Step(129): len = 503993, overlap = 180.312
+PHY-3002 : Step(130): len = 504636, overlap = 171.406
+PHY-3002 : Step(131): len = 505361, overlap = 163.812
+PHY-3002 : Step(132): len = 505026, overlap = 173.156
+PHY-3002 : Step(133): len = 504774, overlap = 171.906
+PHY-3002 : Step(134): len = 504901, overlap = 162.938
+PHY-3002 : Step(135): len = 505520, overlap = 166.938
+PHY-3002 : Step(136): len = 504832, overlap = 173.844
+PHY-3002 : Step(137): len = 504602, overlap = 175.094
+PHY-3002 : Step(138): len = 504315, overlap = 174.281
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00081836
+PHY-3002 : Step(139): len = 507144, overlap = 176.469
+PHY-3002 : Step(140): len = 510585, overlap = 178.781
+PHY-3002 : Step(141): len = 511411, overlap = 180.438
+PHY-3002 : Step(142): len = 512072, overlap = 177.75
+PHY-3002 : Step(143): len = 513293, overlap = 168.281
+PHY-3002 : Step(144): len = 514847, overlap = 163.469
+PHY-3002 : Step(145): len = 515310, overlap = 156.531
+PHY-3002 : Step(146): len = 515518, overlap = 156.281
+PHY-3002 : Step(147): len = 515769, overlap = 157.594
+PHY-3002 : Step(148): len = 515843, overlap = 156.125
+PHY-3002 : Step(149): len = 515700, overlap = 151.094
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00132411
+PHY-3002 : Step(150): len = 516885, overlap = 151.312
+PHY-3002 : Step(151): len = 518926, overlap = 149.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012363s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (379.1%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 689160, over cnt = 1476(4%), over = 6572, worst = 27
+PHY-1001 : End global iterations; 0.815087s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (151.4%)
+
+PHY-1001 : Congestion index: top1 = 72.33, top5 = 57.50, top10 = 50.06, top15 = 45.11.
+PHY-3001 : End congestion estimation; 1.041674s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (139.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.933224s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.96552e-05
+PHY-3002 : Step(152): len = 620709, overlap = 121.094
+PHY-3002 : Step(153): len = 637860, overlap = 108.281
+PHY-3002 : Step(154): len = 622051, overlap = 108.062
+PHY-3002 : Step(155): len = 616692, overlap = 102.219
+PHY-3002 : Step(156): len = 608397, overlap = 102.844
+PHY-3002 : Step(157): len = 603804, overlap = 100.719
+PHY-3002 : Step(158): len = 602208, overlap = 97.9062
+PHY-3002 : Step(159): len = 595521, overlap = 94.4688
+PHY-3002 : Step(160): len = 595578, overlap = 90.75
+PHY-3002 : Step(161): len = 589958, overlap = 91.5938
+PHY-3002 : Step(162): len = 586887, overlap = 95.125
+PHY-3002 : Step(163): len = 584897, overlap = 93.6875
+PHY-3002 : Step(164): len = 582840, overlap = 92.25
+PHY-3002 : Step(165): len = 580515, overlap = 90.4688
+PHY-3002 : Step(166): len = 580096, overlap = 93.0312
+PHY-3002 : Step(167): len = 576531, overlap = 92.75
+PHY-3002 : Step(168): len = 574415, overlap = 92.9688
+PHY-3002 : Step(169): len = 573180, overlap = 89.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00013931
+PHY-3002 : Step(170): len = 571781, overlap = 89.4688
+PHY-3002 : Step(171): len = 574702, overlap = 87.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000245467
+PHY-3002 : Step(172): len = 579405, overlap = 87.4688
+PHY-3002 : Step(173): len = 585691, overlap = 83.125
+PHY-3002 : Step(174): len = 599644, overlap = 80.0938
+PHY-3002 : Step(175): len = 603214, overlap = 79.7188
+PHY-3002 : Step(176): len = 606815, overlap = 77.8438
+PHY-3002 : Step(177): len = 604766, overlap = 81.3438
+PHY-3002 : Step(178): len = 602782, overlap = 81.5625
+PHY-3002 : Step(179): len = 602723, overlap = 79.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 95/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 702168, over cnt = 2602(7%), over = 11190, worst = 43
+PHY-1001 : End global iterations; 1.557687s wall, 2.093750s user + 0.046875s system = 2.140625s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 83.28, top5 = 64.66, top10 = 56.86, top15 = 51.97.
+PHY-3001 : End congestion estimation; 1.852356s wall, 2.390625s user + 0.046875s system = 2.437500s CPU (131.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.365518s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (96.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.26072e-05
+PHY-3002 : Step(180): len = 600578, overlap = 401.719
+PHY-3002 : Step(181): len = 605210, overlap = 361.562
+PHY-3002 : Step(182): len = 598960, overlap = 351.75
+PHY-3002 : Step(183): len = 597242, overlap = 323.594
+PHY-3002 : Step(184): len = 597123, overlap = 291.938
+PHY-3002 : Step(185): len = 592246, overlap = 276.406
+PHY-3002 : Step(186): len = 589840, overlap = 263
+PHY-3002 : Step(187): len = 588419, overlap = 253.688
+PHY-3002 : Step(188): len = 585154, overlap = 256.375
+PHY-3002 : Step(189): len = 582571, overlap = 258.719
+PHY-3002 : Step(190): len = 580125, overlap = 259.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000145214
+PHY-3002 : Step(191): len = 580080, overlap = 253.094
+PHY-3002 : Step(192): len = 581221, overlap = 251.562
+PHY-3002 : Step(193): len = 584815, overlap = 245.188
+PHY-3002 : Step(194): len = 587956, overlap = 239.688
+PHY-3002 : Step(195): len = 588476, overlap = 232.844
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000290429
+PHY-3002 : Step(196): len = 591395, overlap = 224.219
+PHY-3002 : Step(197): len = 593589, overlap = 220.625
+PHY-3002 : Step(198): len = 597211, overlap = 213.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000521736
+PHY-3002 : Step(199): len = 603673, overlap = 199.281
+PHY-3002 : Step(200): len = 607444, overlap = 192.5
+PHY-3002 : Step(201): len = 612216, overlap = 181.969
+PHY-3002 : Step(202): len = 616195, overlap = 170.812
+PHY-3002 : Step(203): len = 618573, overlap = 164.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00101881
+PHY-3002 : Step(204): len = 620495, overlap = 166.812
+PHY-3002 : Step(205): len = 624208, overlap = 162.719
+PHY-3002 : Step(206): len = 628927, overlap = 158.375
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91022, tnet num: 21421, tinst num: 19019, tnode num: 121280, tedge num: 145932.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.704868s wall, 1.609375s user + 0.062500s system = 1.671875s CPU (98.1%)
+
+RUN-1004 : used memory is 592 MB, reserved memory is 581 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 592.31 peak overflow 4.56
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 736/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751024, over cnt = 3276(9%), over = 12329, worst = 31
+PHY-1001 : End global iterations; 1.499657s wall, 2.171875s user + 0.015625s system = 2.187500s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 73.73, top5 = 61.67, top10 = 55.55, top15 = 51.55.
+PHY-1001 : End incremental global routing; 1.870463s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (137.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.324362s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (97.9%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18890 has valid locations, 372 needs to be replaced
+PHY-3001 : design contains 19347 instances, 8782 luts, 9344 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6091 pins
+PHY-3001 : Found 1257 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 660471
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17435/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 769144, over cnt = 3328(9%), over = 12513, worst = 31
+PHY-1001 : End global iterations; 0.303330s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (128.8%)
+
+PHY-1001 : Congestion index: top1 = 73.97, top5 = 61.94, top10 = 55.96, top15 = 52.06.
+PHY-3001 : End congestion estimation; 0.605875s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (116.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92351, tnet num: 21749, tinst num: 19347, tnode num: 123349, tedge num: 147934.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.673688s wall, 1.640625s user + 0.031250s system = 1.671875s CPU (99.9%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 658 MB, peak memory is 744 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.849594s wall, 2.750000s user + 0.078125s system = 2.828125s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(207): len = 658836, overlap = 0.5
+PHY-3002 : Step(208): len = 658996, overlap = 0.4375
+PHY-3002 : Step(209): len = 658487, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17507/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765752, over cnt = 3336(9%), over = 12559, worst = 31
+PHY-1001 : End global iterations; 0.295994s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (116.1%)
+
+PHY-1001 : Congestion index: top1 = 73.86, top5 = 62.35, top10 = 56.25, top15 = 52.21.
+PHY-3001 : End congestion estimation; 0.599750s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (109.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.120013s wall, 1.046875s user + 0.078125s system = 1.125000s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000297372
+PHY-3002 : Step(210): len = 658705, overlap = 161.594
+PHY-3002 : Step(211): len = 659387, overlap = 161.406
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000594743
+PHY-3002 : Step(212): len = 659567, overlap = 161.625
+PHY-3002 : Step(213): len = 660376, overlap = 162
+PHY-3001 : Final: Len = 660376, Over = 162
+PHY-3001 : End incremental placement; 5.990797s wall, 6.187500s user + 0.265625s system = 6.453125s CPU (107.7%)
+
+OPT-1001 : Total overflow 599.34 peak overflow 4.56
+OPT-1001 : End high-fanout net optimization; 9.844902s wall, 10.718750s user + 0.312500s system = 11.031250s CPU (112.1%)
+
+OPT-1001 : Current memory(MB): used = 746, reserve = 740, peak = 766.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17474/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 771616, over cnt = 3286(9%), over = 11181, worst = 31
+PHY-1002 : len = 826312, over cnt = 2536(7%), over = 6566, worst = 22
+PHY-1002 : len = 876400, over cnt = 1423(4%), over = 3327, worst = 22
+PHY-1002 : len = 906064, over cnt = 716(2%), over = 1698, worst = 22
+PHY-1002 : len = 936280, over cnt = 29(0%), over = 70, worst = 13
+PHY-1001 : End global iterations; 2.829632s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (122.0%)
+
+PHY-1001 : Congestion index: top1 = 62.26, top5 = 55.05, top10 = 51.17, top15 = 48.80.
+OPT-1001 : End congestion update; 3.147460s wall, 3.765625s user + 0.000000s system = 3.765625s CPU (119.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.320049s wall, 1.296875s user + 0.031250s system = 1.328125s CPU (100.6%)
+
+OPT-0007 : Start: WNS -4701 TNS -2426099 NUM_FEPS 1065
+OPT-0007 : Iter 1: improved WNS -4085 TNS -2402519 NUM_FEPS 1065 with 71 cells processed and 3658 slack improved
+OPT-0007 : Iter 2: improved WNS -4085 TNS -2397167 NUM_FEPS 1065 with 66 cells processed and 2432 slack improved
+OPT-0007 : Iter 3: improved WNS -4085 TNS -2395719 NUM_FEPS 1065 with 41 cells processed and 1850 slack improved
+OPT-0007 : Iter 4: improved WNS -4085 TNS -2394519 NUM_FEPS 1065 with 53 cells processed and 1016 slack improved
+OPT-0007 : Iter 5: improved WNS -4085 TNS -2393801 NUM_FEPS 1065 with 19 cells processed and 400 slack improved
+OPT-0007 : Iter 6: improved WNS -4085 TNS -2389079 NUM_FEPS 1065 with 2 cells processed and 268 slack improved
+OPT-1001 : End bottleneck based optimization; 5.349575s wall, 5.937500s user + 0.031250s system = 5.968750s CPU (111.6%)
+
+OPT-1001 : Current memory(MB): used = 724, reserve = 721, peak = 766.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17616/21929.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 936504, over cnt = 342(0%), over = 492, worst = 13
+PHY-1002 : len = 935320, over cnt = 213(0%), over = 244, worst = 4
+PHY-1002 : len = 936232, over cnt = 105(0%), over = 117, worst = 3
+PHY-1002 : len = 937728, over cnt = 27(0%), over = 33, worst = 3
+PHY-1002 : len = 939128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.034111s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (108.8%)
+
+PHY-1001 : Congestion index: top1 = 61.88, top5 = 54.63, top10 = 50.95, top15 = 48.65.
+OPT-1001 : End congestion update; 1.351128s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (107.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21751 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.955490s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.8%)
+
+OPT-0007 : Start: WNS -4085 TNS -2389079 NUM_FEPS 1065
+OPT-0007 : Iter 1: improved WNS -4085 TNS -2387363 NUM_FEPS 1065 with 36 cells processed and 2248 slack improved
+OPT-0007 : Iter 2: improved WNS -4085 TNS -2387363 NUM_FEPS 1065 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.473929s wall, 2.546875s user + 0.031250s system = 2.578125s CPU (104.2%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 731, peak = 766.
+OPT-1001 : End physical optimization; 19.750837s wall, 21.265625s user + 0.453125s system = 21.718750s CPU (110.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8782 LUT to BLE ...
+SYN-4008 : Packed 8782 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6211 remaining SEQ's ...
+SYN-4005 : Packed 4456 SEQ with LUT/SLICE
+SYN-4006 : 1483 single LUT's are left
+SYN-4006 : 1755 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10537/14392 primitive instances ...
+PHY-3001 : End packing; 2.047043s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7339 instances
+RUN-1001 : 3595 mslices, 3596 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18923 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10441 nets have 2 pins
+RUN-1001 : 6583 nets have [3 - 5] pins
+RUN-1001 : 943 nets have [6 - 10] pins
+RUN-1001 : 508 nets have [11 - 20] pins
+RUN-1001 : 417 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7337 instances, 7191 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3642 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 670132, Over = 367
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7934/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862104, over cnt = 2360(6%), over = 4005, worst = 10
+PHY-1002 : len = 873848, over cnt = 1492(4%), over = 2145, worst = 10
+PHY-1002 : len = 893312, over cnt = 518(1%), over = 660, worst = 6
+PHY-1002 : len = 898488, over cnt = 303(0%), over = 395, worst = 4
+PHY-1002 : len = 905544, over cnt = 44(0%), over = 47, worst = 2
+PHY-1001 : End global iterations; 2.345784s wall, 3.218750s user + 0.046875s system = 3.265625s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 60.32, top5 = 54.16, top10 = 50.47, top15 = 47.91.
+PHY-3001 : End congestion estimation; 2.872180s wall, 3.718750s user + 0.046875s system = 3.765625s CPU (131.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81628, tnet num: 18745, tinst num: 7337, tnode num: 104650, tedge num: 136867.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.870978s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.2%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 639 MB, peak memory is 766 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.939773s wall, 2.921875s user + 0.015625s system = 2.937500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.36756e-05
+PHY-3002 : Step(214): len = 654550, overlap = 365.75
+PHY-3002 : Step(215): len = 645611, overlap = 373.75
+PHY-3002 : Step(216): len = 640490, overlap = 384.25
+PHY-3002 : Step(217): len = 637727, overlap = 401.5
+PHY-3002 : Step(218): len = 635494, overlap = 408.25
+PHY-3002 : Step(219): len = 633661, overlap = 405.75
+PHY-3002 : Step(220): len = 631479, overlap = 401
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.73511e-05
+PHY-3002 : Step(221): len = 635058, overlap = 396.5
+PHY-3002 : Step(222): len = 641000, overlap = 384
+PHY-3002 : Step(223): len = 640929, overlap = 386
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000174702
+PHY-3002 : Step(224): len = 649621, overlap = 366
+PHY-3002 : Step(225): len = 655408, overlap = 359.5
+PHY-3002 : Step(226): len = 655175, overlap = 353
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000344773
+PHY-3002 : Step(227): len = 664072, overlap = 342
+PHY-3002 : Step(228): len = 675612, overlap = 330.25
+PHY-3002 : Step(229): len = 676018, overlap = 321
+PHY-3002 : Step(230): len = 676352, overlap = 315
+PHY-3002 : Step(231): len = 678024, overlap = 313.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000578724
+PHY-3002 : Step(232): len = 682318, overlap = 306.25
+PHY-3002 : Step(233): len = 685042, overlap = 298.75
+PHY-3002 : Step(234): len = 690118, overlap = 291.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00115616
+PHY-3002 : Step(235): len = 692400, overlap = 289.75
+PHY-3002 : Step(236): len = 699535, overlap = 279.25
+PHY-3002 : Step(237): len = 708272, overlap = 270.5
+PHY-3002 : Step(238): len = 709642, overlap = 269.25
+PHY-3002 : Step(239): len = 710674, overlap = 260.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.386046s wall, 0.375000s user + 0.625000s system = 1.000000s CPU (259.0%)
+
+PHY-3001 : Trial Legalized: Len = 797754
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 765/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942360, over cnt = 3304(9%), over = 5508, worst = 8
+PHY-1002 : len = 960464, over cnt = 2210(6%), over = 3329, worst = 8
+PHY-1002 : len = 987424, over cnt = 998(2%), over = 1441, worst = 6
+PHY-1002 : len = 1.00032e+06, over cnt = 488(1%), over = 748, worst = 6
+PHY-1002 : len = 1.01297e+06, over cnt = 18(0%), over = 28, worst = 3
+PHY-1001 : End global iterations; 3.318464s wall, 4.656250s user + 0.000000s system = 4.656250s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 60.95, top5 = 54.84, top10 = 51.48, top15 = 49.31.
+PHY-3001 : End congestion estimation; 3.869529s wall, 5.203125s user + 0.000000s system = 5.203125s CPU (134.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.065677s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (101.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000216673
+PHY-3002 : Step(240): len = 751778, overlap = 89.25
+PHY-3002 : Step(241): len = 728443, overlap = 142.25
+PHY-3002 : Step(242): len = 710080, overlap = 200.5
+PHY-3002 : Step(243): len = 698874, overlap = 236.25
+PHY-3002 : Step(244): len = 693056, overlap = 251.5
+PHY-3002 : Step(245): len = 688214, overlap = 268.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000433346
+PHY-3002 : Step(246): len = 691584, overlap = 261.5
+PHY-3002 : Step(247): len = 694145, overlap = 257.25
+PHY-3002 : Step(248): len = 695772, overlap = 250.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00083788
+PHY-3002 : Step(249): len = 698784, overlap = 245
+PHY-3002 : Step(250): len = 704555, overlap = 244
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00156457
+PHY-3002 : Step(251): len = 705975, overlap = 243.25
+PHY-3002 : Step(252): len = 712925, overlap = 240.25
+PHY-3002 : Step(253): len = 717257, overlap = 232.5
+PHY-3002 : Step(254): len = 718373, overlap = 231.5
+PHY-3002 : Step(255): len = 720473, overlap = 228
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.036690s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (127.8%)
+
+PHY-3001 : Legalized: Len = 759105, Over = 0
+PHY-3001 : Spreading special nets. 561 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.142764s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-3001 : 865 instances has been re-located, deltaX = 320, deltaY = 527, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 773592, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81628, tnet num: 18745, tinst num: 7340, tnode num: 104650, tedge num: 136867.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.175692s wall, 2.140625s user + 0.031250s system = 2.171875s CPU (99.8%)
+
+RUN-1004 : used memory is 663 MB, reserved memory is 686 MB, peak memory is 766 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4791/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 933560, over cnt = 2984(8%), over = 4773, worst = 7
+PHY-1002 : len = 949832, over cnt = 1841(5%), over = 2634, worst = 7
+PHY-1002 : len = 976648, over cnt = 541(1%), over = 710, worst = 7
+PHY-1002 : len = 985288, over cnt = 97(0%), over = 109, worst = 3
+PHY-1002 : len = 988288, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.656564s wall, 3.875000s user + 0.031250s system = 3.906250s CPU (147.0%)
+
+PHY-1001 : Congestion index: top1 = 60.11, top5 = 54.01, top10 = 50.60, top15 = 48.38.
+PHY-1001 : End incremental global routing; 3.108982s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (140.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.106157s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (100.3%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7248 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 778234
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17164/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994648, over cnt = 94(0%), over = 127, worst = 9
+PHY-1002 : len = 994736, over cnt = 53(0%), over = 64, worst = 4
+PHY-1002 : len = 995120, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 995376, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 995584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.008069s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.2%)
+
+PHY-1001 : Congestion index: top1 = 60.34, top5 = 54.31, top10 = 50.87, top15 = 48.62.
+PHY-3001 : End congestion estimation; 1.395597s wall, 1.375000s user + 0.015625s system = 1.390625s CPU (99.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81832, tnet num: 18764, tinst num: 7359, tnode num: 104896, tedge num: 137120.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.225847s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (100.4%)
+
+RUN-1004 : used memory is 694 MB, reserved memory is 696 MB, peak memory is 772 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.661853s wall, 3.656250s user + 0.015625s system = 3.671875s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(256): len = 776902, overlap = 0
+PHY-3002 : Step(257): len = 776309, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17148/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992440, over cnt = 83(0%), over = 117, worst = 6
+PHY-1002 : len = 992584, over cnt = 48(0%), over = 58, worst = 4
+PHY-1002 : len = 992872, over cnt = 18(0%), over = 20, worst = 2
+PHY-1002 : len = 993376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.820222s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (104.8%)
+
+PHY-1001 : Congestion index: top1 = 60.22, top5 = 54.05, top10 = 50.71, top15 = 48.49.
+PHY-3001 : End congestion estimation; 1.217049s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (102.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.062517s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000792542
+PHY-3002 : Step(258): len = 776138, overlap = 2.25
+PHY-3002 : Step(259): len = 776274, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005357s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (291.7%)
+
+PHY-3001 : Legalized: Len = 776293, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.072474s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (107.8%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 2, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 776361, Over = 0
+PHY-3001 : End incremental placement; 7.948580s wall, 8.046875s user + 0.093750s system = 8.140625s CPU (102.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 12.843728s wall, 14.171875s user + 0.140625s system = 14.312500s CPU (111.4%)
+
+OPT-1001 : Current memory(MB): used = 782, reserve = 786, peak = 788.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17110/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992352, over cnt = 108(0%), over = 135, worst = 5
+PHY-1002 : len = 992648, over cnt = 45(0%), over = 47, worst = 2
+PHY-1002 : len = 992832, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 993120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.772122s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 60.41, top5 = 53.93, top10 = 50.62, top15 = 48.40.
+OPT-1001 : End congestion update; 1.158307s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (101.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.934908s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (98.6%)
+
+OPT-0007 : Start: WNS -4095 TNS -2245387 NUM_FEPS 981
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 776978, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.077577s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (100.7%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 8, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 777278, Over = 0
+PHY-3001 : End incremental legalization; 0.490520s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.9%)
+
+OPT-0007 : Iter 1: improved WNS -4054 TNS -2232610 NUM_FEPS 981 with 48 cells processed and 5601 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777614, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.074195s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (84.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 7, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 777740, Over = 0
+PHY-3001 : End incremental legalization; 0.513386s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (118.7%)
+
+OPT-0007 : Iter 2: improved WNS -4054 TNS -2231520 NUM_FEPS 981 with 19 cells processed and 1654 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777796, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.078395s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (99.7%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 777908, Over = 0
+PHY-3001 : End incremental legalization; 0.741363s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (75.9%)
+
+OPT-0007 : Iter 3: improved WNS -4054 TNS -2230249 NUM_FEPS 981 with 10 cells processed and 1227 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777648, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.073320s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (85.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 777984, Over = 0
+PHY-3001 : End incremental legalization; 0.574801s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (100.6%)
+
+OPT-0007 : Iter 4: improved WNS -4054 TNS -2227314 NUM_FEPS 981 with 13 cells processed and 853 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777984, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.071349s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (87.6%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 7, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 777958, Over = 0
+PHY-3001 : End incremental legalization; 0.539776s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (104.2%)
+
+OPT-0007 : Iter 5: improved WNS -4054 TNS -2226157 NUM_FEPS 981 with 7 cells processed and 600 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 778240, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.081013s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (115.7%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 778258, Over = 0
+PHY-3001 : End incremental legalization; 0.521567s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (101.9%)
+
+OPT-0007 : Iter 6: improved WNS -4054 TNS -2224669 NUM_FEPS 981 with 4 cells processed and 600 slack improved
+OPT-1001 : End bottleneck based optimization; 7.003844s wall, 7.187500s user + 0.031250s system = 7.218750s CPU (103.1%)
+
+OPT-1001 : Current memory(MB): used = 781, reserve = 785, peak = 788.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16775/18943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994048, over cnt = 439(1%), over = 545, worst = 4
+PHY-1002 : len = 993736, over cnt = 262(0%), over = 297, worst = 4
+PHY-1002 : len = 995448, over cnt = 95(0%), over = 100, worst = 4
+PHY-1002 : len = 996672, over cnt = 40(0%), over = 40, worst = 1
+PHY-1002 : len = 997968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.179675s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (108.6%)
+
+PHY-1001 : Congestion index: top1 = 60.54, top5 = 54.33, top10 = 50.89, top15 = 48.65.
+OPT-1001 : End congestion update; 1.569017s wall, 1.671875s user + 0.015625s system = 1.687500s CPU (107.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.900368s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.9%)
+
+OPT-0007 : Start: WNS -4054 TNS -2228716 NUM_FEPS 981
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 778612, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.074373s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (84.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 10, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 779012, Over = 0
+PHY-3001 : End incremental legalization; 0.493773s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.1%)
+
+OPT-0007 : Iter 1: improved WNS -4054 TNS -2228898 NUM_FEPS 981 with 37 cells processed and 3041 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 779124, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.076267s wall, 0.062500s user + 0.015625s system = 0.078125s CPU (102.4%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 779138, Over = 0
+PHY-3001 : End incremental legalization; 0.488802s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (118.3%)
+
+OPT-0007 : Iter 2: improved WNS -4054 TNS -2228471 NUM_FEPS 981 with 9 cells processed and 629 slack improved
+OPT-0007 : Iter 3: improved WNS -4054 TNS -2228471 NUM_FEPS 981 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.826056s wall, 4.109375s user + 0.031250s system = 4.140625s CPU (108.2%)
+
+OPT-1001 : Current memory(MB): used = 781, reserve = 785, peak = 788.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.959953s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (97.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16976/18943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 997912, over cnt = 158(0%), over = 193, worst = 5
+PHY-1002 : len = 997656, over cnt = 117(0%), over = 135, worst = 5
+PHY-1002 : len = 998472, over cnt = 51(0%), over = 58, worst = 3
+PHY-1002 : len = 999064, over cnt = 19(0%), over = 22, worst = 2
+PHY-1002 : len = 999576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.026471s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (108.1%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.36, top10 = 50.93, top15 = 48.69.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.928387s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -4054 TNS -2229784 NUM_FEPS 981
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 60.413793
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -4054ps with logic level 5
+RUN-1001 : #2 path slack -3995ps with logic level 5
+RUN-1001 : 0 HFN exist on timing critical paths out of 18943 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18943 nets
+OPT-1001 : End physical optimization; 29.656280s wall, 31.531250s user + 0.250000s system = 31.781250s CPU (107.2%)
+
+RUN-1003 : finish command "place" in 82.808480s wall, 115.453125s user + 5.640625s system = 121.093750s CPU (146.2%)
+
+RUN-1004 : used memory is 686 MB, reserved memory is 700 MB, peak memory is 788 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.912128s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (170.8%)
+
+RUN-1004 : used memory is 686 MB, reserved memory is 700 MB, peak memory is 788 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81872, tnet num: 18765, tinst num: 7363, tnode num: 104951, tedge num: 137171.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.866025s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.5%)
+
+RUN-1004 : used memory is 666 MB, reserved memory is 676 MB, peak memory is 788 MB
+PHY-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909224, over cnt = 3287(9%), over = 5337, worst = 7
+PHY-1002 : len = 930584, over cnt = 1989(5%), over = 2857, worst = 7
+PHY-1002 : len = 954544, over cnt = 840(2%), over = 1188, worst = 7
+PHY-1002 : len = 973984, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 974424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 4.078611s wall, 5.562500s user + 0.015625s system = 5.578125s CPU (136.8%)
+
+PHY-1001 : Congestion index: top1 = 59.35, top5 = 53.78, top10 = 50.28, top15 = 48.09.
+PHY-1001 : End global routing; 4.495404s wall, 5.984375s user + 0.015625s system = 6.000000s CPU (133.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 757, reserve = 764, peak = 788.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1029, reserve = 1036, peak = 1029.
+PHY-1001 : End build detailed router design. 4.417544s wall, 4.359375s user + 0.062500s system = 4.421875s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273664, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.583316s wall, 6.515625s user + 0.000000s system = 6.515625s CPU (99.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273720, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.591641s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1064, reserve = 1071, peak = 1064.
+PHY-1001 : End phase 1; 7.189008s wall, 7.125000s user + 0.000000s system = 7.125000s CPU (99.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 35% nets.
+PHY-1001 : Routed 42% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.58654e+06, over cnt = 2305(0%), over = 2324, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1083, reserve = 1085, peak = 1083.
+PHY-1001 : End initial routed; 37.693590s wall, 74.234375s user + 0.296875s system = 74.531250s CPU (197.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -6.182 | -3395.741 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.801503s wall, 3.750000s user + 0.000000s system = 3.750000s CPU (98.6%)
+
+PHY-1001 : Current memory(MB): used = 1093, reserve = 1097, peak = 1093.
+PHY-1001 : End phase 2; 41.495161s wall, 77.984375s user + 0.296875s system = 78.281250s CPU (188.7%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 63 pins with SWNS -6.050ns STNS -3390.015ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.431873s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.3%)
+
+PHY-1022 : len = 2.58686e+06, over cnt = 2360(0%), over = 2379, worst = 2, crit = 2
+PHY-1001 : End optimize timing; 0.722748s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53891e+06, over cnt = 952(0%), over = 954, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.807314s wall, 4.062500s user + 0.000000s system = 4.062500s CPU (144.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53486e+06, over cnt = 272(0%), over = 272, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.737227s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (137.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53452e+06, over cnt = 73(0%), over = 73, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.898289s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (118.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53546e+06, over cnt = 30(0%), over = 30, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.492546s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (120.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.5359e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.747763s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (108.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53593e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 1.097844s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.53582e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 1.781327s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.53584e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.203239s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (107.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53583e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.221798s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.274299s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.275190s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.392299s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.195419s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.197170s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.217498s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.229221s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.4%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.314043s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.373108s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (96.3%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.190584s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (106.6%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.207526s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.229989s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.256978s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.389022s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.405067s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.013658s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.188553s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (124.3%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.181958s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.5%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.214880s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.229796s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.324210s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.380126s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.994894s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.018220s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (101.3%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.197772s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.8%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.183909s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.5%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.215858s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (108.6%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.238903s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.331869s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.405982s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.987307s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.990436s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.079509s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (98.4%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.204902s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.217390s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.242406s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.254653s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (104.3%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.311997s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.384034s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.996082s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.076076s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.056893s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.062677s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.196726s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (127.1%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.203968s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.228644s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.238256s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.324143s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.451379s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.280919s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.294313s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.366068s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.248199s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.255516s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.206177s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (106.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.228486s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.269973s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.264825s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.363718s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.440180s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.288380s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.231347s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.289488s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.397535s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.204145s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.218725s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -6.050 | -3394.643 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.929437s wall, 3.906250s user + 0.000000s system = 3.906250s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1103, reserve = 1108, peak = 1103.
+PHY-1001 : End phase 3; 51.726126s wall, 53.906250s user + 0.078125s system = 53.984375s CPU (104.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 47 pins with SWNS -5.708ns STNS -3385.794ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.423977s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.5%)
+
+PHY-1022 : len = 2.53595e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.737284s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.708ns, -3385.794ns, 981}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53548e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.225215s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (111.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53548e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.273591s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (131.4%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.346048s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.554476s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.899085s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.226852s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.205616s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.251364s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.263827s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (94.8%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.369200s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 11 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.216896s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.231806s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.253065s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (105.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.262577s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.391397s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.459547s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 17 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.228038s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (130.2%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.238270s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.258158s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.264311s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.374210s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.436359s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 1.340008s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 24 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.220101s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.227774s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.261452s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.277067s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.364012s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.442556s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 1.262975s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 1.396574s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 32 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.210888s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.210037s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.1%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.249074s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.257169s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (91.1%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.376197s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.455831s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.246884s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 1.241277s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.291955s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 41 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.214383s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.234685s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.284508s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.264500s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (94.5%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.388498s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.445277s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (105.3%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.258138s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.461680s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.314430s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.284352s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 51 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.213783s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.264716s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (88.5%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.252008s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (111.6%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.264573s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (94.5%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.381410s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.443846s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.281871s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.238216s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.276476s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.450102s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.362829s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 62 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.211482s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (103.4%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.209349s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.299281s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (83.5%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.298960s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.381345s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.450769s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.339417s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.216167s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.021877s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.087832s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.167063s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.178342s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.624458s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (98.7%)
+
+PHY-1001 : Current memory(MB): used = 1105, reserve = 1111, peak = 1105.
+PHY-1001 : End phase 4; 47.510053s wall, 47.328125s user + 0.062500s system = 47.390625s CPU (99.7%)
+
+PHY-1003 : Routed, final wirelength = 2.53539e+06
+PHY-1001 : 916 feed throughs used by 648 nets
+PHY-1001 : Current memory(MB): used = 1213, reserve = 1221, peak = 1213.
+PHY-1001 : End export database. 2.567912s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (99.8%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 13 2) is for feedthrough
+PHY-3001 : eco cells: (1 26 1) is for feedthrough
+PHY-3001 : eco cells: (1 30 3) is for feedthrough
+PHY-3001 : eco cells: (1 33 3) is for feedthrough
+PHY-3001 : eco cells: (2 2 0) is for feedthrough
+PHY-3001 : eco cells: (2 4 3) is for feedthrough
+PHY-3001 : eco cells: (2 6 0) is for feedthrough
+PHY-3001 : eco cells: (2 6 3) is for feedthrough
+PHY-3001 : eco cells: (2 12 1) is for feedthrough
+PHY-3001 : eco cells: (2 16 0) is for feedthrough
+PHY-3001 : eco cells: (2 24 3) is for feedthrough
+PHY-3001 : eco cells: (2 28 3) is for feedthrough
+PHY-3001 : eco cells: (2 32 0) is for feedthrough
+PHY-3001 : eco cells: (2 34 3) is for feedthrough
+PHY-3001 : eco cells: (2 39 3) is for feedthrough
+PHY-3001 : eco cells: (2 54 2) is for feedthrough
+PHY-3001 : eco cells: (2 68 1) is for feedthrough
+PHY-3001 : eco cells: (3 8 1) is for feedthrough
+PHY-3001 : eco cells: (3 8 3) is for feedthrough
+PHY-3001 : eco cells: (3 15 1) is for feedthrough
+PHY-3001 : eco cells: (3 16 1) is for feedthrough
+PHY-3001 : eco cells: (3 19 0) is for feedthrough
+PHY-3001 : eco cells: (3 22 3) is for feedthrough
+PHY-3001 : eco cells: (3 25 3) is for feedthrough
+PHY-3001 : eco cells: (3 28 3) is for feedthrough
+PHY-3001 : eco cells: (3 34 0) is for feedthrough
+PHY-3001 : eco cells: (3 34 1) is for feedthrough
+PHY-3001 : eco cells: (3 35 3) is for feedthrough
+PHY-3001 : eco cells: (4 8 1) is for feedthrough
+PHY-3001 : eco cells: (4 12 0) is for feedthrough
+PHY-3001 : eco cells: (4 12 2) is for feedthrough
+PHY-3001 : eco cells: (4 13 2) is for feedthrough
+PHY-3001 : eco cells: (4 14 0) is for feedthrough
+PHY-3001 : eco cells: (4 26 3) is for feedthrough
+PHY-3001 : eco cells: (4 30 1) is for feedthrough
+PHY-3001 : eco cells: (4 31 1) is for feedthrough
+PHY-3001 : eco cells: (4 31 2) is for feedthrough
+PHY-3001 : eco cells: (4 35 0) is for feedthrough
+PHY-3001 : eco cells: (4 45 0) is for feedthrough
+PHY-3001 : eco cells: (4 49 2) is for feedthrough
+PHY-3001 : eco cells: (4 53 2) is for feedthrough
+PHY-3001 : eco cells: (4 58 1) is for feedthrough
+PHY-3001 : eco cells: (4 59 0) is for feedthrough
+PHY-3001 : eco cells: (5 3 1) is for feedthrough
+PHY-3001 : eco cells: (5 4 0) is for feedthrough
+PHY-3001 : eco cells: (5 5 2) is for feedthrough
+PHY-3001 : eco cells: (5 5 3) is for feedthrough
+PHY-3001 : eco cells: (5 6 3) is for feedthrough
+PHY-3001 : eco cells: (5 9 0) is for feedthrough
+PHY-3001 : eco cells: (5 10 0) is for feedthrough
+PHY-3001 : eco cells: (5 12 3) is for feedthrough
+PHY-3001 : eco cells: (5 14 2) is for feedthrough
+PHY-3001 : eco cells: (5 15 2) is for feedthrough
+PHY-3001 : eco cells: (5 17 1) is for feedthrough
+PHY-3001 : eco cells: (5 18 0) is for feedthrough
+PHY-3001 : eco cells: (5 19 2) is for feedthrough
+PHY-3001 : eco cells: (5 20 2) is for feedthrough
+PHY-3001 : eco cells: (5 21 0) is for feedthrough
+PHY-3001 : eco cells: (5 29 1) is for feedthrough
+PHY-3001 : eco cells: (5 29 2) is for feedthrough
+PHY-3001 : eco cells: (5 31 0) is for feedthrough
+PHY-3001 : eco cells: (5 33 3) is for feedthrough
+PHY-3001 : eco cells: (5 35 2) is for feedthrough
+PHY-3001 : eco cells: (5 36 1) is for feedthrough
+PHY-3001 : eco cells: (5 36 2) is for feedthrough
+PHY-3001 : eco cells: (5 38 1) is for feedthrough
+PHY-3001 : eco cells: (5 51 3) is for feedthrough
+PHY-3001 : eco cells: (5 59 3) is for feedthrough
+PHY-3001 : eco cells: (5 63 0) is for feedthrough
+PHY-3001 : eco cells: (5 63 3) is for feedthrough
+PHY-3001 : eco cells: (5 66 2) is for feedthrough
+PHY-3001 : eco cells: (6 7 3) is for feedthrough
+PHY-3001 : eco cells: (6 11 3) is for feedthrough
+PHY-3001 : eco cells: (6 12 2) is for feedthrough
+PHY-3001 : eco cells: (6 13 2) is for feedthrough
+PHY-3001 : eco cells: (6 19 2) is for feedthrough
+PHY-3001 : eco cells: (6 20 2) is for feedthrough
+PHY-3001 : eco cells: (6 20 3) is for feedthrough
+PHY-3001 : eco cells: (6 29 0) is for feedthrough
+PHY-3001 : eco cells: (6 29 2) is for feedthrough
+PHY-3001 : eco cells: (6 33 2) is for feedthrough
+PHY-3001 : eco cells: (6 35 0) is for feedthrough
+PHY-3001 : eco cells: (6 36 3) is for feedthrough
+PHY-3001 : eco cells: (6 40 0) is for feedthrough
+PHY-3001 : eco cells: (6 44 3) is for feedthrough
+PHY-3001 : eco cells: (6 53 0) is for feedthrough
+PHY-3001 : eco cells: (6 55 3) is for feedthrough
+PHY-3001 : eco cells: (6 67 2) is for feedthrough
+PHY-3001 : eco cells: (6 68 3) is for feedthrough
+PHY-3001 : eco cells: (7 8 0) is for feedthrough
+PHY-3001 : eco cells: (7 9 0) is for feedthrough
+PHY-3001 : eco cells: (7 10 3) is for feedthrough
+PHY-3001 : eco cells: (7 11 0) is for feedthrough
+PHY-3001 : eco cells: (7 21 3) is for feedthrough
+PHY-3001 : eco cells: (7 28 2) is for feedthrough
+PHY-3001 : eco cells: (7 30 0) is for feedthrough
+PHY-3001 : eco cells: (7 31 0) is for feedthrough
+PHY-3001 : eco cells: (9 9 3) is for feedthrough
+PHY-3001 : eco cells: (9 10 0) is for feedthrough
+PHY-3001 : eco cells: (9 11 0) is for feedthrough
+PHY-3001 : eco cells: (9 11 1) is for feedthrough
+PHY-3001 : eco cells: (9 12 0) is for feedthrough
+PHY-3001 : eco cells: (9 13 2) is for feedthrough
+PHY-3001 : eco cells: (9 14 2) is for feedthrough
+PHY-3001 : eco cells: (9 17 0) is for feedthrough
+PHY-3001 : eco cells: (9 18 1) is for feedthrough
+PHY-3001 : eco cells: (9 22 1) is for feedthrough
+PHY-3001 : eco cells: (9 25 2) is for feedthrough
+PHY-3001 : eco cells: (9 26 1) is for feedthrough
+PHY-3001 : eco cells: (9 29 0) is for feedthrough
+PHY-3001 : eco cells: (9 29 2) is for feedthrough
+PHY-3001 : eco cells: (9 65 0) is for feedthrough
+PHY-3001 : eco cells: (9 69 2) is for feedthrough
+PHY-3001 : eco cells: (10 8 0) is for feedthrough
+PHY-3001 : eco cells: (10 11 1) is for feedthrough
+PHY-3001 : eco cells: (10 12 1) is for feedthrough
+PHY-3001 : eco cells: (10 13 1) is for feedthrough
+PHY-3001 : eco cells: (10 14 2) is for feedthrough
+PHY-3001 : eco cells: (10 16 1) is for feedthrough
+PHY-3001 : eco cells: (10 19 0) is for feedthrough
+PHY-3001 : eco cells: (10 22 1) is for feedthrough
+PHY-3001 : eco cells: (10 22 2) is for feedthrough
+PHY-3001 : eco cells: (10 24 3) is for feedthrough
+PHY-3001 : eco cells: (10 25 0) is for feedthrough
+PHY-3001 : eco cells: (10 27 0) is for feedthrough
+PHY-3001 : eco cells: (10 27 2) is for feedthrough
+PHY-3001 : eco cells: (10 36 3) is for feedthrough
+PHY-3001 : eco cells: (10 42 2) is for feedthrough
+PHY-3001 : eco cells: (10 58 3) is for feedthrough
+PHY-3001 : eco cells: (10 59 0) is for feedthrough
+PHY-3001 : eco cells: (10 63 2) is for feedthrough
+PHY-3001 : eco cells: (10 67 0) is for feedthrough
+PHY-3001 : eco cells: (11 7 0) is for feedthrough
+PHY-3001 : eco cells: (11 8 2) is for feedthrough
+PHY-3001 : eco cells: (11 9 0) is for feedthrough
+PHY-3001 : eco cells: (11 10 1) is for feedthrough
+PHY-3001 : eco cells: (11 11 0) is for feedthrough
+PHY-3001 : eco cells: (11 11 2) is for feedthrough
+PHY-3001 : eco cells: (11 12 0) is for feedthrough
+PHY-3001 : eco cells: (11 12 3) is for feedthrough
+PHY-3001 : eco cells: (11 13 3) is for feedthrough
+PHY-3001 : eco cells: (11 14 3) is for feedthrough
+PHY-3001 : eco cells: (11 15 0) is for feedthrough
+PHY-3001 : eco cells: (11 18 1) is for feedthrough
+PHY-3001 : eco cells: (11 21 2) is for feedthrough
+PHY-3001 : eco cells: (11 23 1) is for feedthrough
+PHY-3001 : eco cells: (11 24 0) is for feedthrough
+PHY-3001 : eco cells: (11 25 0) is for feedthrough
+PHY-3001 : eco cells: (11 25 2) is for feedthrough
+PHY-3001 : eco cells: (11 27 1) is for feedthrough
+PHY-3001 : eco cells: (11 30 1) is for feedthrough
+PHY-3001 : eco cells: (11 33 0) is for feedthrough
+PHY-3001 : eco cells: (11 40 2) is for feedthrough
+PHY-3001 : eco cells: (11 41 2) is for feedthrough
+PHY-3001 : eco cells: (11 49 2) is for feedthrough
+PHY-3001 : eco cells: (11 50 2) is for feedthrough
+PHY-3001 : eco cells: (11 53 2) is for feedthrough
+PHY-3001 : eco cells: (11 61 0) is for feedthrough
+PHY-3001 : eco cells: (11 65 2) is for feedthrough
+PHY-3001 : eco cells: (11 66 3) is for feedthrough
+PHY-3001 : eco cells: (12 7 2) is for feedthrough
+PHY-3001 : eco cells: (12 8 0) is for feedthrough
+PHY-3001 : eco cells: (12 10 1) is for feedthrough
+PHY-3001 : eco cells: (12 13 0) is for feedthrough
+PHY-3001 : eco cells: (12 13 2) is for feedthrough
+PHY-3001 : eco cells: (12 14 0) is for feedthrough
+PHY-3001 : eco cells: (12 15 3) is for feedthrough
+PHY-3001 : eco cells: (12 16 0) is for feedthrough
+PHY-3001 : eco cells: (12 16 1) is for feedthrough
+PHY-3001 : eco cells: (12 28 2) is for feedthrough
+PHY-3001 : eco cells: (12 30 0) is for feedthrough
+PHY-3001 : eco cells: (12 35 3) is for feedthrough
+PHY-3001 : eco cells: (12 38 1) is for feedthrough
+PHY-3001 : eco cells: (12 45 1) is for feedthrough
+PHY-3001 : eco cells: (12 49 2) is for feedthrough
+PHY-3001 : eco cells: (12 56 1) is for feedthrough
+PHY-3001 : eco cells: (12 63 2) is for feedthrough
+PHY-3001 : eco cells: (12 66 0) is for feedthrough
+PHY-3001 : eco cells: (13 10 0) is for feedthrough
+PHY-3001 : eco cells: (13 10 2) is for feedthrough
+PHY-3001 : eco cells: (13 12 0) is for feedthrough
+PHY-3001 : eco cells: (13 12 1) is for feedthrough
+PHY-3001 : eco cells: (13 16 0) is for feedthrough
+PHY-3001 : eco cells: (13 22 0) is for feedthrough
+PHY-3001 : eco cells: (13 27 3) is for feedthrough
+PHY-3001 : eco cells: (13 29 1) is for feedthrough
+PHY-3001 : eco cells: (13 31 2) is for feedthrough
+PHY-3001 : eco cells: (13 33 1) is for feedthrough
+PHY-3001 : eco cells: (13 34 2) is for feedthrough
+PHY-3001 : eco cells: (13 35 3) is for feedthrough
+PHY-3001 : eco cells: (13 43 2) is for feedthrough
+PHY-3001 : eco cells: (13 47 2) is for feedthrough
+PHY-3001 : eco cells: (13 50 2) is for feedthrough
+PHY-3001 : eco cells: (13 51 0) is for feedthrough
+PHY-3001 : eco cells: (13 54 2) is for feedthrough
+PHY-3001 : eco cells: (13 54 3) is for feedthrough
+PHY-3001 : eco cells: (13 57 0) is for feedthrough
+PHY-3001 : eco cells: (13 58 2) is for feedthrough
+PHY-3001 : eco cells: (13 62 0) is for feedthrough
+PHY-3001 : eco cells: (13 63 3) is for feedthrough
+PHY-3001 : eco cells: (13 64 0) is for feedthrough
+PHY-3001 : eco cells: (13 64 1) is for feedthrough
+PHY-3001 : eco cells: (13 67 3) is for feedthrough
+PHY-3001 : eco cells: (14 4 3) is for feedthrough
+PHY-3001 : eco cells: (14 11 1) is for feedthrough
+PHY-3001 : eco cells: (14 11 2) is for feedthrough
+PHY-3001 : eco cells: (14 12 2) is for feedthrough
+PHY-3001 : eco cells: (14 14 0) is for feedthrough
+PHY-3001 : eco cells: (14 14 1) is for feedthrough
+PHY-3001 : eco cells: (14 18 3) is for feedthrough
+PHY-3001 : eco cells: (14 20 2) is for feedthrough
+PHY-3001 : eco cells: (14 20 3) is for feedthrough
+PHY-3001 : eco cells: (14 21 0) is for feedthrough
+PHY-3001 : eco cells: (14 21 2) is for feedthrough
+PHY-3001 : eco cells: (14 22 1) is for feedthrough
+PHY-3001 : eco cells: (14 25 1) is for feedthrough
+PHY-3001 : eco cells: (14 25 2) is for feedthrough
+PHY-3001 : eco cells: (14 26 3) is for feedthrough
+PHY-3001 : eco cells: (14 27 2) is for feedthrough
+PHY-3001 : eco cells: (14 28 2) is for feedthrough
+PHY-3001 : eco cells: (14 35 0) is for feedthrough
+PHY-3001 : eco cells: (14 43 2) is for feedthrough
+PHY-3001 : eco cells: (14 48 1) is for feedthrough
+PHY-3001 : eco cells: (14 49 0) is for feedthrough
+PHY-3001 : eco cells: (14 50 2) is for feedthrough
+PHY-3001 : eco cells: (14 69 3) is for feedthrough
+PHY-3001 : eco cells: (15 10 2) is for feedthrough
+PHY-3001 : eco cells: (15 13 2) is for feedthrough
+PHY-3001 : eco cells: (15 32 1) is for feedthrough
+PHY-3001 : eco cells: (15 33 2) is for feedthrough
+PHY-3001 : eco cells: (15 43 0) is for feedthrough
+PHY-3001 : eco cells: (15 56 2) is for feedthrough
+PHY-3001 : eco cells: (15 61 0) is for feedthrough
+PHY-3001 : eco cells: (15 62 3) is for feedthrough
+PHY-3001 : eco cells: (15 65 3) is for feedthrough
+PHY-3001 : eco cells: (17 6 2) is for feedthrough
+PHY-3001 : eco cells: (17 16 3) is for feedthrough
+PHY-3001 : eco cells: (17 17 2) is for feedthrough
+PHY-3001 : eco cells: (17 18 3) is for feedthrough
+PHY-3001 : eco cells: (17 21 0) is for feedthrough
+PHY-3001 : eco cells: (17 23 3) is for feedthrough
+PHY-3001 : eco cells: (17 24 1) is for feedthrough
+PHY-3001 : eco cells: (17 24 3) is for feedthrough
+PHY-3001 : eco cells: (17 25 2) is for feedthrough
+PHY-3001 : eco cells: (17 26 1) is for feedthrough
+PHY-3001 : eco cells: (17 27 1) is for feedthrough
+PHY-3001 : eco cells: (17 28 1) is for feedthrough
+PHY-3001 : eco cells: (17 30 2) is for feedthrough
+PHY-3001 : eco cells: (17 31 2) is for feedthrough
+PHY-3001 : eco cells: (17 62 3) is for feedthrough
+PHY-3001 : eco cells: (17 66 0) is for feedthrough
+PHY-3001 : eco cells: (18 6 3) is for feedthrough
+PHY-3001 : eco cells: (18 7 1) is for feedthrough
+PHY-3001 : eco cells: (18 8 3) is for feedthrough
+PHY-3001 : eco cells: (18 14 1) is for feedthrough
+PHY-3001 : eco cells: (18 17 2) is for feedthrough
+PHY-3001 : eco cells: (18 21 3) is for feedthrough
+PHY-3001 : eco cells: (18 24 2) is for feedthrough
+PHY-3001 : eco cells: (18 25 3) is for feedthrough
+PHY-3001 : eco cells: (18 27 0) is for feedthrough
+PHY-3001 : eco cells: (18 28 1) is for feedthrough
+PHY-3001 : eco cells: (18 30 1) is for feedthrough
+PHY-3001 : eco cells: (18 32 0) is for feedthrough
+PHY-3001 : eco cells: (18 34 1) is for feedthrough
+PHY-3001 : eco cells: (18 35 0) is for feedthrough
+PHY-3001 : eco cells: (18 36 3) is for feedthrough
+PHY-3001 : eco cells: (18 44 0) is for feedthrough
+PHY-3001 : eco cells: (18 46 1) is for feedthrough
+PHY-3001 : eco cells: (18 62 3) is for feedthrough
+PHY-3001 : eco cells: (19 3 0) is for feedthrough
+PHY-3001 : eco cells: (19 3 1) is for feedthrough
+PHY-3001 : eco cells: (19 5 1) is for feedthrough
+PHY-3001 : eco cells: (19 7 0) is for feedthrough
+PHY-3001 : eco cells: (19 8 0) is for feedthrough
+PHY-3001 : eco cells: (19 13 3) is for feedthrough
+PHY-3001 : eco cells: (19 16 1) is for feedthrough
+PHY-3001 : eco cells: (19 18 0) is for feedthrough
+PHY-3001 : eco cells: (19 18 1) is for feedthrough
+PHY-3001 : eco cells: (19 23 0) is for feedthrough
+PHY-3001 : eco cells: (19 23 3) is for feedthrough
+PHY-3001 : eco cells: (19 25 2) is for feedthrough
+PHY-3001 : eco cells: (19 27 0) is for feedthrough
+PHY-3001 : eco cells: (19 28 1) is for feedthrough
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+PHY-3001 : eco cells: (36 16 0) is for feedthrough
+PHY-3001 : eco cells: (36 16 2) is for feedthrough
+PHY-3001 : eco cells: (36 18 0) is for feedthrough
+PHY-3001 : eco cells: (36 19 1) is for feedthrough
+PHY-3001 : eco cells: (36 20 0) is for feedthrough
+PHY-3001 : eco cells: (36 20 1) is for feedthrough
+PHY-3001 : eco cells: (36 21 2) is for feedthrough
+PHY-3001 : eco cells: (36 24 3) is for feedthrough
+PHY-3001 : eco cells: (36 25 1) is for feedthrough
+PHY-3001 : eco cells: (36 27 0) is for feedthrough
+PHY-3001 : eco cells: (36 27 1) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 1) is for feedthrough
+PHY-3001 : eco cells: (36 29 0) is for feedthrough
+PHY-3001 : eco cells: (36 29 2) is for feedthrough
+PHY-3001 : eco cells: (36 32 2) is for feedthrough
+PHY-3001 : eco cells: (36 33 1) is for feedthrough
+PHY-3001 : eco cells: (36 34 0) is for feedthrough
+PHY-3001 : eco cells: (36 42 0) is for feedthrough
+PHY-3001 : eco cells: (36 50 2) is for feedthrough
+PHY-3001 : eco cells: (36 51 3) is for feedthrough
+PHY-3001 : eco cells: (36 66 3) is for feedthrough
+PHY-3001 : eco cells: (37 4 0) is for feedthrough
+PHY-3001 : eco cells: (37 16 1) is for feedthrough
+PHY-3001 : eco cells: (37 18 1) is for feedthrough
+PHY-3001 : eco cells: (37 18 3) is for feedthrough
+PHY-3001 : eco cells: (37 19 2) is for feedthrough
+PHY-3001 : eco cells: (37 20 0) is for feedthrough
+PHY-3001 : eco cells: (37 21 2) is for feedthrough
+PHY-3001 : eco cells: (37 21 3) is for feedthrough
+PHY-3001 : eco cells: (37 22 1) is for feedthrough
+PHY-3001 : eco cells: (37 24 1) is for feedthrough
+PHY-3001 : eco cells: (37 25 2) is for feedthrough
+PHY-3001 : eco cells: (37 26 2) is for feedthrough
+PHY-3001 : eco cells: (37 27 1) is for feedthrough
+PHY-3001 : eco cells: (37 27 2) is for feedthrough
+PHY-3001 : eco cells: (37 28 2) is for feedthrough
+PHY-3001 : eco cells: (37 28 3) is for feedthrough
+PHY-3001 : eco cells: (37 29 2) is for feedthrough
+PHY-3001 : eco cells: (37 31 0) is for feedthrough
+PHY-3001 : eco cells: (37 31 1) is for feedthrough
+PHY-3001 : eco cells: (37 53 3) is for feedthrough
+PHY-3001 : eco cells: (37 64 2) is for feedthrough
+PHY-3001 : eco cells: (37 65 2) is for feedthrough
+PHY-3001 : eco cells: (38 9 1) is for feedthrough
+PHY-3001 : eco cells: (38 10 0) is for feedthrough
+PHY-3001 : eco cells: (38 19 3) is for feedthrough
+PHY-3001 : eco cells: (38 21 2) is for feedthrough
+PHY-3001 : eco cells: (38 22 1) is for feedthrough
+PHY-3001 : eco cells: (38 23 1) is for feedthrough
+PHY-3001 : eco cells: (38 27 1) is for feedthrough
+PHY-3001 : eco cells: (38 30 2) is for feedthrough
+PHY-3001 : eco cells: (38 32 1) is for feedthrough
+PHY-3001 : eco cells: (38 32 3) is for feedthrough
+PHY-3001 : eco cells: (38 40 1) is for feedthrough
+PHY-3001 : eco cells: (38 67 3) is for feedthrough
+PHY-3001 : eco cells: (39 12 1) is for feedthrough
+PHY-3001 : eco cells: (39 13 3) is for feedthrough
+PHY-3001 : eco cells: (39 19 3) is for feedthrough
+PHY-3001 : eco cells: (39 27 1) is for feedthrough
+PHY-3001 : eco cells: (39 29 2) is for feedthrough
+PHY-3001 : eco cells: (39 29 3) is for feedthrough
+PHY-3001 : eco cells: (39 30 3) is for feedthrough
+PHY-3001 : eco cells: (39 33 3) is for feedthrough
+PHY-3001 : eco cells: (39 39 1) is for feedthrough
+PHY-3001 : eco cells: (39 41 2) is for feedthrough
+PHY-3001 : eco cells: (39 41 3) is for feedthrough
+PHY-3001 : eco cells: (39 42 2) is for feedthrough
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.864620s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.4%)
+
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.346966s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (99.8%)
+
+RUN-1004 : used memory is 1209 MB, reserved memory is 1218 MB, peak memory is 1213 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1209, reserve = 1218, peak = 1213.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1231, reserve = 1240, peak = 1231.
+PHY-1001 : End build detailed router design. 2.052409s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.022315s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (70.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.029542s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (105.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.030925s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.030051s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (104.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.030847s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (101.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.032509s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (96.1%)
+
+PHY-1001 : Current memory(MB): used = 1231, reserve = 1240, peak = 1231.
+PHY-1001 : End phase 1; 0.212300s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (103.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1231, reserve = 1240, peak = 1231.
+PHY-1001 : End initial routed; 0.157489s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.468177s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1231, reserve = 1240, peak = 1231.
+PHY-1001 : End phase 2; 3.625727s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 11 pins with SWNS -5.791ns STNS -3388.165ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.139400s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.9%)
+
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.392531s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.143534s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.145470s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.145416s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.144492s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.145812s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.4%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.146305s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.179422s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.143972s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.144210s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.142097s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (121.0%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.144366s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.2%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.148448s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.7%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.144469s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.144311s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.167977s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.142802s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.143123s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.3%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.148332s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (115.9%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.145103s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.143486s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (119.8%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.142706s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.145559s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.149622s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.150037s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.7%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.153763s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.176658s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (115.0%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.149787s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.9%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.147316s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.5%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.145249s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.144322s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.143050s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.144424s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.2%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.147204s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.5%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.144277s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (119.1%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.170807s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.144656s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.145131s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.143522s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.144526s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.1%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.143124s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.143540s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.0%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.154643s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.169713s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.169282s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.144399s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.147636s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.8%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.185745s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (92.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.145946s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.1%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.144218s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.144768s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.144305s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.149606s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.144959s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (172.5%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.143523s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.143499s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.145817s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.144643s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.0%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.168396s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.8%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.149239s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.145026s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.144218s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.3%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.145984s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.3%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.149519s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.144161s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.144926s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.144847s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.9%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.146357s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.144431s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.145136s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.145589s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.3%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.143654s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.144597s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.145862s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.1%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.146004s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.585754s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1240, peak = 1232.
+PHY-1001 : End phase 3; 15.077761s wall, 15.171875s user + 0.062500s system = 15.234375s CPU (101.0%)
+
+PHY-1001 : 916 feed throughs used by 648 nets
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1240, peak = 1232.
+PHY-1001 : End export database. 2.633163s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (100.3%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x25y22_w2beg5), nets: u_bus_top/lv_cnt_a_sync1d[17] u_bus_top/u_local_bus_slve_cis/slv_mcu_din[31]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 24.879080s wall, 24.984375s user + 0.062500s system = 25.046875s CPU (100.7%)
+
+RUN-1004 : used memory is 1217 MB, reserved memory is 1225 MB, peak memory is 1232 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x25y22_w2beg5), nets: u_bus_top/lv_cnt_a_sync1d[17] u_bus_top/u_local_bus_slve_cis/slv_mcu_din[31]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 188.978083s wall, 228.859375s user + 0.640625s system = 229.500000s CPU (121.4%)
+
+RUN-1004 : used memory is 1217 MB, reserved memory is 1225 MB, peak memory is 1232 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_170937.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_171606.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_171606.log
new file mode 100644
index 0000000..ed5cb42
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_171606.log
@@ -0,0 +1,2093 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 17:16:06 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.261602s wall, 2.171875s user + 0.078125s system = 2.250000s CPU (99.5%)
+
+RUN-1004 : used memory is 348 MB, reserved memory is 324 MB, peak memory is 352 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 3.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -multiply_by 3.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 19228 instances
+RUN-0007 : 8903 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21806 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14137 nets have 2 pins
+RUN-1001 : 6220 nets have [3 - 5] pins
+RUN-1001 : 875 nets have [6 - 10] pins
+RUN-1001 : 312 nets have [11 - 20] pins
+RUN-1001 : 188 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 19226 instances, 8903 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5958 pins
+PHY-0007 : Cell area utilization is 56%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92309, tnet num: 21628, tinst num: 19226, tnode num: 122567, tedge num: 148092.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.207989s wall, 1.156250s user + 0.046875s system = 1.203125s CPU (99.6%)
+
+RUN-1004 : used memory is 554 MB, reserved memory is 537 MB, peak memory is 554 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.044510s wall, 2.000000s user + 0.046875s system = 2.046875s CPU (100.1%)
+
+PHY-3001 : Found 1252 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.32081e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 19226.
+PHY-3001 : Level 1 #clusters 2530.
+PHY-3001 : End clustering; 0.158232s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (108.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.447e+06, overlap = 554.469
+PHY-3002 : Step(2): len = 1.09904e+06, overlap = 670.469
+PHY-3002 : Step(3): len = 885777, overlap = 767.344
+PHY-3002 : Step(4): len = 729070, overlap = 859.844
+PHY-3002 : Step(5): len = 550760, overlap = 1013.56
+PHY-3002 : Step(6): len = 474804, overlap = 1081.53
+PHY-3002 : Step(7): len = 400655, overlap = 1155.12
+PHY-3002 : Step(8): len = 346475, overlap = 1190.53
+PHY-3002 : Step(9): len = 307022, overlap = 1239.91
+PHY-3002 : Step(10): len = 279609, overlap = 1287.97
+PHY-3002 : Step(11): len = 248763, overlap = 1361.81
+PHY-3002 : Step(12): len = 231176, overlap = 1410.78
+PHY-3002 : Step(13): len = 212574, overlap = 1453.69
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.02238e-06
+PHY-3002 : Step(14): len = 209797, overlap = 1396.66
+PHY-3002 : Step(15): len = 236693, overlap = 1357.38
+PHY-3002 : Step(16): len = 241330, overlap = 1283.28
+PHY-3002 : Step(17): len = 240256, overlap = 1248.5
+PHY-3002 : Step(18): len = 234200, overlap = 1249.38
+PHY-3002 : Step(19): len = 232144, overlap = 1220.38
+PHY-3002 : Step(20): len = 226234, overlap = 1198.44
+PHY-3002 : Step(21): len = 224046, overlap = 1184.03
+PHY-3002 : Step(22): len = 219522, overlap = 1168.16
+PHY-3002 : Step(23): len = 217776, overlap = 1165.66
+PHY-3002 : Step(24): len = 214314, overlap = 1156.5
+PHY-3002 : Step(25): len = 213737, overlap = 1151.81
+PHY-3002 : Step(26): len = 211764, overlap = 1142.47
+PHY-3002 : Step(27): len = 210795, overlap = 1139.41
+PHY-3002 : Step(28): len = 209255, overlap = 1146.53
+PHY-3002 : Step(29): len = 208958, overlap = 1140
+PHY-3002 : Step(30): len = 208125, overlap = 1133.53
+PHY-3002 : Step(31): len = 207230, overlap = 1118.97
+PHY-3002 : Step(32): len = 206793, overlap = 1101.06
+PHY-3002 : Step(33): len = 206418, overlap = 1099.03
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.04476e-06
+PHY-3002 : Step(34): len = 212958, overlap = 1077.06
+PHY-3002 : Step(35): len = 226143, overlap = 1035.09
+PHY-3002 : Step(36): len = 231421, overlap = 1004.09
+PHY-3002 : Step(37): len = 235728, overlap = 986.312
+PHY-3002 : Step(38): len = 236293, overlap = 954.125
+PHY-3002 : Step(39): len = 236940, overlap = 941.438
+PHY-3002 : Step(40): len = 236304, overlap = 946.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.08953e-06
+PHY-3002 : Step(41): len = 253396, overlap = 906.375
+PHY-3002 : Step(42): len = 276402, overlap = 851.438
+PHY-3002 : Step(43): len = 284262, overlap = 838.375
+PHY-3002 : Step(44): len = 286875, overlap = 802.375
+PHY-3002 : Step(45): len = 284263, overlap = 792.688
+PHY-3002 : Step(46): len = 281570, overlap = 768.25
+PHY-3002 : Step(47): len = 281564, overlap = 773.719
+PHY-3002 : Step(48): len = 282435, overlap = 761.094
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.17905e-06
+PHY-3002 : Step(49): len = 303416, overlap = 716.469
+PHY-3002 : Step(50): len = 322417, overlap = 658.719
+PHY-3002 : Step(51): len = 328115, overlap = 584.5
+PHY-3002 : Step(52): len = 329340, overlap = 569.312
+PHY-3002 : Step(53): len = 325273, overlap = 597.656
+PHY-3002 : Step(54): len = 324670, overlap = 606.688
+PHY-3002 : Step(55): len = 324908, overlap = 610.469
+PHY-3002 : Step(56): len = 326359, overlap = 598.281
+PHY-3002 : Step(57): len = 325780, overlap = 590.812
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.63581e-05
+PHY-3002 : Step(58): len = 350165, overlap = 530.219
+PHY-3002 : Step(59): len = 365967, overlap = 483.25
+PHY-3002 : Step(60): len = 368365, overlap = 448.031
+PHY-3002 : Step(61): len = 370246, overlap = 445.125
+PHY-3002 : Step(62): len = 371528, overlap = 450.875
+PHY-3002 : Step(63): len = 374534, overlap = 454.406
+PHY-3002 : Step(64): len = 374929, overlap = 448.188
+PHY-3002 : Step(65): len = 376337, overlap = 436.094
+PHY-3002 : Step(66): len = 376264, overlap = 419.906
+PHY-3002 : Step(67): len = 375930, overlap = 415.688
+PHY-3002 : Step(68): len = 376181, overlap = 439.719
+PHY-3002 : Step(69): len = 377536, overlap = 443.562
+PHY-3002 : Step(70): len = 378431, overlap = 446.312
+PHY-3002 : Step(71): len = 378137, overlap = 436.094
+PHY-3002 : Step(72): len = 378524, overlap = 444.594
+PHY-3002 : Step(73): len = 377616, overlap = 445.531
+PHY-3002 : Step(74): len = 377961, overlap = 430.844
+PHY-3002 : Step(75): len = 375667, overlap = 434.531
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.27162e-05
+PHY-3002 : Step(76): len = 394983, overlap = 419.75
+PHY-3002 : Step(77): len = 407030, overlap = 395.594
+PHY-3002 : Step(78): len = 407894, overlap = 376.75
+PHY-3002 : Step(79): len = 408615, overlap = 375.75
+PHY-3002 : Step(80): len = 409689, overlap = 358.688
+PHY-3002 : Step(81): len = 412213, overlap = 352.844
+PHY-3002 : Step(82): len = 411500, overlap = 344.344
+PHY-3002 : Step(83): len = 412558, overlap = 344.156
+PHY-3002 : Step(84): len = 412796, overlap = 341.438
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.54324e-05
+PHY-3002 : Step(85): len = 430570, overlap = 333.594
+PHY-3002 : Step(86): len = 442795, overlap = 324.938
+PHY-3002 : Step(87): len = 442635, overlap = 308.75
+PHY-3002 : Step(88): len = 443794, overlap = 305.344
+PHY-3002 : Step(89): len = 445630, overlap = 284.406
+PHY-3002 : Step(90): len = 449284, overlap = 281.188
+PHY-3002 : Step(91): len = 450914, overlap = 291.5
+PHY-3002 : Step(92): len = 450621, overlap = 277.594
+PHY-3002 : Step(93): len = 451446, overlap = 276.344
+PHY-3002 : Step(94): len = 452744, overlap = 271.188
+PHY-3002 : Step(95): len = 452584, overlap = 256.375
+PHY-3002 : Step(96): len = 451269, overlap = 250.719
+PHY-3002 : Step(97): len = 451478, overlap = 243.875
+PHY-3002 : Step(98): len = 450464, overlap = 259.188
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000130865
+PHY-3002 : Step(99): len = 462527, overlap = 231.531
+PHY-3002 : Step(100): len = 470513, overlap = 230.25
+PHY-3002 : Step(101): len = 471547, overlap = 229.688
+PHY-3002 : Step(102): len = 472002, overlap = 231.625
+PHY-3002 : Step(103): len = 473791, overlap = 229.031
+PHY-3002 : Step(104): len = 476008, overlap = 228.469
+PHY-3002 : Step(105): len = 476100, overlap = 233.438
+PHY-3002 : Step(106): len = 476997, overlap = 226.812
+PHY-3002 : Step(107): len = 476946, overlap = 226.094
+PHY-3002 : Step(108): len = 477845, overlap = 212.469
+PHY-3002 : Step(109): len = 476939, overlap = 209.094
+PHY-3002 : Step(110): len = 477703, overlap = 210.062
+PHY-3002 : Step(111): len = 477928, overlap = 213.844
+PHY-3002 : Step(112): len = 478583, overlap = 214.844
+PHY-3002 : Step(113): len = 478153, overlap = 213.688
+PHY-3002 : Step(114): len = 478430, overlap = 221.656
+PHY-3002 : Step(115): len = 478343, overlap = 224.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000257561
+PHY-3002 : Step(116): len = 486793, overlap = 214.594
+PHY-3002 : Step(117): len = 494662, overlap = 206.5
+PHY-3002 : Step(118): len = 497044, overlap = 200.156
+PHY-3002 : Step(119): len = 498754, overlap = 203.719
+PHY-3002 : Step(120): len = 500233, overlap = 210
+PHY-3002 : Step(121): len = 501721, overlap = 216.438
+PHY-3002 : Step(122): len = 501907, overlap = 203.719
+PHY-3002 : Step(123): len = 502646, overlap = 198.875
+PHY-3002 : Step(124): len = 502975, overlap = 196.688
+PHY-3002 : Step(125): len = 503448, overlap = 199.562
+PHY-3002 : Step(126): len = 502447, overlap = 200.188
+PHY-3002 : Step(127): len = 502380, overlap = 197.562
+PHY-3002 : Step(128): len = 502641, overlap = 197
+PHY-3002 : Step(129): len = 502877, overlap = 195.75
+PHY-3002 : Step(130): len = 502368, overlap = 192.719
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000464942
+PHY-3002 : Step(131): len = 506654, overlap = 191.844
+PHY-3002 : Step(132): len = 511644, overlap = 181.906
+PHY-3002 : Step(133): len = 513577, overlap = 181.781
+PHY-3002 : Step(134): len = 514614, overlap = 177.75
+PHY-3002 : Step(135): len = 514830, overlap = 177.844
+PHY-3002 : Step(136): len = 514955, overlap = 168.719
+PHY-3002 : Step(137): len = 514612, overlap = 171.562
+PHY-3002 : Step(138): len = 514778, overlap = 174.656
+PHY-3002 : Step(139): len = 515819, overlap = 170.25
+PHY-3002 : Step(140): len = 516623, overlap = 164.531
+PHY-3002 : Step(141): len = 516222, overlap = 163.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000765613
+PHY-3002 : Step(142): len = 518542, overlap = 162.969
+PHY-3002 : Step(143): len = 521770, overlap = 160.5
+PHY-3002 : Step(144): len = 523612, overlap = 154.969
+PHY-3002 : Step(145): len = 525289, overlap = 156.906
+PHY-3002 : Step(146): len = 527410, overlap = 159.875
+PHY-3002 : Step(147): len = 530245, overlap = 153.156
+PHY-3002 : Step(148): len = 530428, overlap = 151.75
+PHY-3002 : Step(149): len = 530641, overlap = 146.5
+PHY-3002 : Step(150): len = 531185, overlap = 150.312
+PHY-3002 : Step(151): len = 531435, overlap = 147.938
+PHY-3002 : Step(152): len = 530781, overlap = 149.844
+PHY-3002 : Step(153): len = 530579, overlap = 147.938
+PHY-3002 : Step(154): len = 530935, overlap = 146.281
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00131086
+PHY-3002 : Step(155): len = 532384, overlap = 152.281
+PHY-3002 : Step(156): len = 534432, overlap = 152.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012836s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21806.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708296, over cnt = 1510(4%), over = 6604, worst = 43
+PHY-1001 : End global iterations; 0.798667s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (138.9%)
+
+PHY-1001 : Congestion index: top1 = 75.04, top5 = 58.36, top10 = 50.45, top15 = 45.30.
+PHY-3001 : End congestion estimation; 1.038310s wall, 1.312500s user + 0.031250s system = 1.343750s CPU (129.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.946617s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.77562e-05
+PHY-3002 : Step(157): len = 642713, overlap = 103.031
+PHY-3002 : Step(158): len = 660220, overlap = 94.375
+PHY-3002 : Step(159): len = 646120, overlap = 94.2812
+PHY-3002 : Step(160): len = 643567, overlap = 91.0938
+PHY-3002 : Step(161): len = 634484, overlap = 91
+PHY-3002 : Step(162): len = 632189, overlap = 89.9375
+PHY-3002 : Step(163): len = 627347, overlap = 86.875
+PHY-3002 : Step(164): len = 624625, overlap = 83.9688
+PHY-3002 : Step(165): len = 622340, overlap = 80.5
+PHY-3002 : Step(166): len = 616067, overlap = 79.2188
+PHY-3002 : Step(167): len = 613779, overlap = 77.7188
+PHY-3002 : Step(168): len = 614219, overlap = 79.3438
+PHY-3002 : Step(169): len = 612165, overlap = 78.7812
+PHY-3002 : Step(170): len = 609958, overlap = 82
+PHY-3002 : Step(171): len = 609959, overlap = 80.4688
+PHY-3002 : Step(172): len = 605933, overlap = 80.0938
+PHY-3002 : Step(173): len = 605165, overlap = 76.9062
+PHY-3002 : Step(174): len = 604460, overlap = 76.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000135512
+PHY-3002 : Step(175): len = 602744, overlap = 76.1562
+PHY-3002 : Step(176): len = 606300, overlap = 75.5312
+PHY-3002 : Step(177): len = 609781, overlap = 73.0625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000271025
+PHY-3002 : Step(178): len = 618534, overlap = 76.3125
+PHY-3002 : Step(179): len = 628406, overlap = 82.4062
+PHY-3002 : Step(180): len = 637165, overlap = 83.4375
+PHY-3002 : Step(181): len = 645241, overlap = 76.75
+PHY-3002 : Step(182): len = 645868, overlap = 74
+PHY-3002 : Step(183): len = 646278, overlap = 72.9375
+PHY-3002 : Step(184): len = 642724, overlap = 71.6562
+PHY-3002 : Step(185): len = 641014, overlap = 75.5938
+PHY-3002 : Step(186): len = 641527, overlap = 76.7812
+PHY-3002 : Step(187): len = 639188, overlap = 77.9688
+PHY-3002 : Step(188): len = 636580, overlap = 77.3438
+PHY-3002 : Step(189): len = 636302, overlap = 74.5625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00054205
+PHY-3002 : Step(190): len = 637503, overlap = 76.1875
+PHY-3002 : Step(191): len = 642840, overlap = 75.1875
+PHY-3002 : Step(192): len = 649577, overlap = 74.0938
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.0010841
+PHY-3002 : Step(193): len = 653163, overlap = 71.2188
+PHY-3002 : Step(194): len = 669952, overlap = 67.3438
+PHY-3002 : Step(195): len = 681341, overlap = 71.2812
+PHY-3002 : Step(196): len = 683348, overlap = 72.25
+PHY-3002 : Step(197): len = 683208, overlap = 78.7188
+PHY-3002 : Step(198): len = 684364, overlap = 76.9375
+PHY-3002 : Step(199): len = 681273, overlap = 76.0938
+PHY-3002 : Step(200): len = 681069, overlap = 75.375
+PHY-3002 : Step(201): len = 681709, overlap = 73.5938
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00181204
+PHY-3002 : Step(202): len = 681993, overlap = 73.875
+PHY-3002 : Step(203): len = 684941, overlap = 76.8438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 126/21806.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 783064, over cnt = 2869(8%), over = 13796, worst = 52
+PHY-1001 : End global iterations; 1.599583s wall, 2.109375s user + 0.000000s system = 2.109375s CPU (131.9%)
+
+PHY-1001 : Congestion index: top1 = 90.65, top5 = 72.43, top10 = 63.87, top15 = 58.28.
+PHY-3001 : End congestion estimation; 1.908298s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (126.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.977271s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (97.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.20827e-05
+PHY-3002 : Step(204): len = 675858, overlap = 365.719
+PHY-3002 : Step(205): len = 676077, overlap = 304.812
+PHY-3002 : Step(206): len = 656194, overlap = 279.438
+PHY-3002 : Step(207): len = 649188, overlap = 280.906
+PHY-3002 : Step(208): len = 638581, overlap = 274.906
+PHY-3002 : Step(209): len = 635451, overlap = 264.062
+PHY-3002 : Step(210): len = 627473, overlap = 268.406
+PHY-3002 : Step(211): len = 621827, overlap = 263.375
+PHY-3002 : Step(212): len = 618968, overlap = 262.531
+PHY-3002 : Step(213): len = 614280, overlap = 262.125
+PHY-3002 : Step(214): len = 610790, overlap = 248.938
+PHY-3002 : Step(215): len = 605956, overlap = 254.312
+PHY-3002 : Step(216): len = 604551, overlap = 253.688
+PHY-3002 : Step(217): len = 599810, overlap = 255.469
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000164165
+PHY-3002 : Step(218): len = 599473, overlap = 252
+PHY-3002 : Step(219): len = 601819, overlap = 250.438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000315492
+PHY-3002 : Step(220): len = 608618, overlap = 243.281
+PHY-3002 : Step(221): len = 616131, overlap = 242.188
+PHY-3002 : Step(222): len = 624898, overlap = 230.656
+PHY-3002 : Step(223): len = 622092, overlap = 229.75
+PHY-3002 : Step(224): len = 621811, overlap = 228.375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000626815
+PHY-3002 : Step(225): len = 627038, overlap = 218.25
+PHY-3002 : Step(226): len = 638356, overlap = 200.469
+PHY-3002 : Step(227): len = 645995, overlap = 184.594
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00125363
+PHY-3002 : Step(228): len = 644784, overlap = 179.594
+PHY-3002 : Step(229): len = 648267, overlap = 171.812
+PHY-3002 : Step(230): len = 657560, overlap = 154.656
+PHY-3002 : Step(231): len = 661594, overlap = 143.688
+PHY-3002 : Step(232): len = 663303, overlap = 135.219
+PHY-3002 : Step(233): len = 664522, overlap = 131.188
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00236125
+PHY-3002 : Step(234): len = 666257, overlap = 127.938
+PHY-3002 : Step(235): len = 669983, overlap = 124.688
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92309, tnet num: 21628, tinst num: 19226, tnode num: 122567, tedge num: 148092.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.653204s wall, 1.546875s user + 0.046875s system = 1.593750s CPU (96.4%)
+
+RUN-1004 : used memory is 596 MB, reserved memory is 585 MB, peak memory is 746 MB
+OPT-1001 : Total overflow 538.03 peak overflow 3.91
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 524/21806.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 794568, over cnt = 3486(9%), over = 13170, worst = 26
+PHY-1001 : End global iterations; 1.706520s wall, 2.281250s user + 0.015625s system = 2.296875s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 73.49, top5 = 59.91, top10 = 54.20, top15 = 50.96.
+PHY-1001 : End incremental global routing; 2.142864s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (126.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.752726s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.7%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 19097 has valid locations, 368 needs to be replaced
+PHY-3001 : design contains 19550 instances, 8973 luts, 9356 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6083 pins
+PHY-3001 : Found 1259 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 701039
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 18117/22130.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 811456, over cnt = 3537(10%), over = 13249, worst = 26
+PHY-1001 : End global iterations; 0.294929s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (121.9%)
+
+PHY-1001 : Congestion index: top1 = 73.25, top5 = 60.17, top10 = 54.52, top15 = 51.25.
+PHY-3001 : End congestion estimation; 0.628609s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (106.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 93611, tnet num: 21952, tinst num: 19550, tnode num: 124633, tedge num: 150048.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.666697s wall, 1.640625s user + 0.031250s system = 1.671875s CPU (100.3%)
+
+RUN-1004 : used memory is 648 MB, reserved memory is 650 MB, peak memory is 751 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21952 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.839319s wall, 2.750000s user + 0.062500s system = 2.812500s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(236): len = 699625, overlap = 0.3125
+PHY-3002 : Step(237): len = 700198, overlap = 0.3125
+PHY-3002 : Step(238): len = 700248, overlap = 0.3125
+PHY-3002 : Step(239): len = 700015, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 18156/22130.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808168, over cnt = 3545(10%), over = 13366, worst = 26
+PHY-1001 : End global iterations; 0.292965s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (128.0%)
+
+PHY-1001 : Congestion index: top1 = 74.27, top5 = 60.67, top10 = 54.90, top15 = 51.60.
+PHY-3001 : End congestion estimation; 0.627233s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (114.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21952 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.354362s wall, 1.312500s user + 0.031250s system = 1.343750s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000184804
+PHY-3002 : Step(240): len = 700283, overlap = 128.531
+PHY-3002 : Step(241): len = 700993, overlap = 127.688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000369608
+PHY-3002 : Step(242): len = 701059, overlap = 127.625
+PHY-3002 : Step(243): len = 701382, overlap = 127.969
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000709634
+PHY-3002 : Step(244): len = 701801, overlap = 127.812
+PHY-3002 : Step(245): len = 702249, overlap = 128.312
+PHY-3001 : Final: Len = 702249, Over = 128.312
+PHY-3001 : End incremental placement; 6.470652s wall, 6.734375s user + 0.343750s system = 7.078125s CPU (109.4%)
+
+OPT-1001 : Total overflow 546.22 peak overflow 3.91
+OPT-1001 : End high-fanout net optimization; 11.042323s wall, 11.921875s user + 0.375000s system = 12.296875s CPU (111.4%)
+
+OPT-1001 : Current memory(MB): used = 755, reserve = 749, peak = 773.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 18154/22130.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 814104, over cnt = 3518(9%), over = 11909, worst = 26
+PHY-1002 : len = 871264, over cnt = 2716(7%), over = 6946, worst = 19
+PHY-1002 : len = 939232, over cnt = 1103(3%), over = 2349, worst = 19
+PHY-1002 : len = 964504, over cnt = 449(1%), over = 910, worst = 19
+PHY-1002 : len = 983144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.713493s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (130.1%)
+
+PHY-1001 : Congestion index: top1 = 58.41, top5 = 53.01, top10 = 49.98, top15 = 48.05.
+OPT-1001 : End congestion update; 3.040479s wall, 3.859375s user + 0.000000s system = 3.859375s CPU (126.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21952 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.965098s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (98.8%)
+
+OPT-0007 : Start: WNS -4184 TNS -2446216 NUM_FEPS 1074
+OPT-0007 : Iter 1: improved WNS -3984 TNS -2431428 NUM_FEPS 1074 with 66 cells processed and 3698 slack improved
+OPT-0007 : Iter 2: improved WNS -3984 TNS -2428326 NUM_FEPS 1074 with 52 cells processed and 2548 slack improved
+OPT-0007 : Iter 3: improved WNS -3984 TNS -2427358 NUM_FEPS 1074 with 17 cells processed and 1000 slack improved
+OPT-0007 : Iter 4: improved WNS -3984 TNS -2427358 NUM_FEPS 1074 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 5: improved WNS -3984 TNS -2420808 NUM_FEPS 1074 with 2 cells processed and 400 slack improved
+OPT-1001 : End bottleneck based optimization; 4.670231s wall, 5.453125s user + 0.031250s system = 5.484375s CPU (117.4%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 722, peak = 773.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 18375/22132.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 983400, over cnt = 177(0%), over = 221, worst = 3
+PHY-1002 : len = 982864, over cnt = 126(0%), over = 144, worst = 3
+PHY-1002 : len = 983368, over cnt = 50(0%), over = 53, worst = 2
+PHY-1002 : len = 984064, over cnt = 11(0%), over = 12, worst = 2
+PHY-1002 : len = 984416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.945740s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (115.7%)
+
+PHY-1001 : Congestion index: top1 = 58.28, top5 = 52.90, top10 = 49.92, top15 = 48.03.
+OPT-1001 : End congestion update; 1.295368s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (109.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21954 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.989282s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.5%)
+
+OPT-0007 : Start: WNS -3984 TNS -2420808 NUM_FEPS 1074
+OPT-0007 : Iter 1: improved WNS -3934 TNS -2418348 NUM_FEPS 1074 with 31 cells processed and 1882 slack improved
+OPT-0007 : Iter 2: improved WNS -3934 TNS -2418348 NUM_FEPS 1074 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.450191s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (105.2%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 730, peak = 773.
+OPT-1001 : End physical optimization; 20.216578s wall, 21.953125s user + 0.484375s system = 22.437500s CPU (111.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8973 LUT to BLE ...
+SYN-4008 : Packed 8973 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6223 remaining SEQ's ...
+SYN-4005 : Packed 4619 SEQ with LUT/SLICE
+SYN-4006 : 1518 single LUT's are left
+SYN-4006 : 1604 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10577/14432 primitive instances ...
+PHY-3001 : End packing; 2.179007s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (97.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7372 instances
+RUN-1001 : 3612 mslices, 3612 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 19082 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10118 nets have 2 pins
+RUN-1001 : 7040 nets have [3 - 5] pins
+RUN-1001 : 968 nets have [6 - 10] pins
+RUN-1001 : 491 nets have [11 - 20] pins
+RUN-1001 : 433 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7370 instances, 7224 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3619 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 709476, Over = 332.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 8065/19082.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899928, over cnt = 2439(6%), over = 4131, worst = 9
+PHY-1002 : len = 910952, over cnt = 1603(4%), over = 2322, worst = 6
+PHY-1002 : len = 931160, over cnt = 501(1%), over = 680, worst = 6
+PHY-1002 : len = 940384, over cnt = 139(0%), over = 176, worst = 5
+PHY-1002 : len = 945496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.249354s wall, 3.171875s user + 0.015625s system = 3.187500s CPU (141.7%)
+
+PHY-1001 : Congestion index: top1 = 59.68, top5 = 53.13, top10 = 49.69, top15 = 47.35.
+PHY-3001 : End congestion estimation; 2.740733s wall, 3.656250s user + 0.015625s system = 3.671875s CPU (134.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83259, tnet num: 18904, tinst num: 7370, tnode num: 106310, tedge num: 139503.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.018377s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (98.3%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 653 MB, peak memory is 773 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18904 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.155171s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.23438e-05
+PHY-3002 : Step(246): len = 693495, overlap = 337.75
+PHY-3002 : Step(247): len = 682964, overlap = 369.25
+PHY-3002 : Step(248): len = 675906, overlap = 412.75
+PHY-3002 : Step(249): len = 670292, overlap = 425.5
+PHY-3002 : Step(250): len = 665634, overlap = 430.75
+PHY-3002 : Step(251): len = 662657, overlap = 422.5
+PHY-3002 : Step(252): len = 659184, overlap = 420.25
+PHY-3002 : Step(253): len = 656602, overlap = 418.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.46876e-05
+PHY-3002 : Step(254): len = 661652, overlap = 409.25
+PHY-3002 : Step(255): len = 667606, overlap = 399
+PHY-3002 : Step(256): len = 669318, overlap = 404
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000169375
+PHY-3002 : Step(257): len = 676769, overlap = 393.5
+PHY-3002 : Step(258): len = 688610, overlap = 375.5
+PHY-3002 : Step(259): len = 690657, overlap = 368.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00033875
+PHY-3002 : Step(260): len = 697277, overlap = 353
+PHY-3002 : Step(261): len = 709936, overlap = 339.5
+PHY-3002 : Step(262): len = 712255, overlap = 330.75
+PHY-3002 : Step(263): len = 712060, overlap = 327.5
+PHY-3002 : Step(264): len = 712161, overlap = 321.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000605577
+PHY-3002 : Step(265): len = 718330, overlap = 312
+PHY-3002 : Step(266): len = 723795, overlap = 305
+PHY-3002 : Step(267): len = 729108, overlap = 300
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.0011383
+PHY-3002 : Step(268): len = 732614, overlap = 296.25
+PHY-3002 : Step(269): len = 739706, overlap = 281.75
+PHY-3002 : Step(270): len = 751969, overlap = 262.25
+PHY-3002 : Step(271): len = 751380, overlap = 263.75
+PHY-3002 : Step(272): len = 749679, overlap = 263.5
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 0.0018847
+PHY-3002 : Step(273): len = 751666, overlap = 260
+PHY-3002 : Step(274): len = 754497, overlap = 257
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.430825s wall, 0.328125s user + 0.718750s system = 1.046875s CPU (243.0%)
+
+PHY-3001 : Trial Legalized: Len = 838208
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 642/19082.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 987480, over cnt = 3425(9%), over = 5781, worst = 7
+PHY-1002 : len = 1.00632e+06, over cnt = 2349(6%), over = 3560, worst = 7
+PHY-1002 : len = 1.03781e+06, over cnt = 937(2%), over = 1338, worst = 6
+PHY-1002 : len = 1.04953e+06, over cnt = 435(1%), over = 622, worst = 6
+PHY-1002 : len = 1.06222e+06, over cnt = 34(0%), over = 42, worst = 4
+PHY-1001 : End global iterations; 3.462836s wall, 4.718750s user + 0.078125s system = 4.796875s CPU (138.5%)
+
+PHY-1001 : Congestion index: top1 = 59.46, top5 = 54.02, top10 = 51.32, top15 = 49.48.
+PHY-3001 : End congestion estimation; 4.096192s wall, 5.312500s user + 0.078125s system = 5.390625s CPU (131.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18904 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.136648s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (97.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000218969
+PHY-3002 : Step(275): len = 788750, overlap = 93
+PHY-3002 : Step(276): len = 763500, overlap = 156
+PHY-3002 : Step(277): len = 742826, overlap = 220.5
+PHY-3002 : Step(278): len = 731770, overlap = 258.5
+PHY-3002 : Step(279): len = 726063, overlap = 272
+PHY-3002 : Step(280): len = 721420, overlap = 293.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000437939
+PHY-3002 : Step(281): len = 726850, overlap = 286.75
+PHY-3002 : Step(282): len = 731588, overlap = 278.5
+PHY-3002 : Step(283): len = 733328, overlap = 267.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000875878
+PHY-3002 : Step(284): len = 736456, overlap = 262.5
+PHY-3002 : Step(285): len = 742494, overlap = 252.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00147291
+PHY-3002 : Step(286): len = 743837, overlap = 250.5
+PHY-3002 : Step(287): len = 752031, overlap = 237.25
+PHY-3002 : Step(288): len = 756250, overlap = 231.5
+PHY-3002 : Step(289): len = 758187, overlap = 231.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00262892
+PHY-3002 : Step(290): len = 759132, overlap = 228.75
+PHY-3002 : Step(291): len = 763442, overlap = 224.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.038202s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (81.8%)
+
+PHY-3001 : Legalized: Len = 796020, Over = 0
+PHY-3001 : Spreading special nets. 568 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.147544s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.9%)
+
+PHY-3001 : 865 instances has been re-located, deltaX = 309, deltaY = 517, maxDist = 5.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 809727, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83259, tnet num: 18904, tinst num: 7373, tnode num: 106310, tedge num: 139503.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.232053s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (100.1%)
+
+RUN-1004 : used memory is 670 MB, reserved memory is 684 MB, peak memory is 773 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4801/19082.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 975472, over cnt = 3218(9%), over = 5124, worst = 8
+PHY-1002 : len = 991408, over cnt = 2049(5%), over = 2955, worst = 7
+PHY-1002 : len = 1.02046e+06, over cnt = 667(1%), over = 891, worst = 7
+PHY-1002 : len = 1.0325e+06, over cnt = 124(0%), over = 156, worst = 6
+PHY-1002 : len = 1.03536e+06, over cnt = 25(0%), over = 32, worst = 3
+PHY-1001 : End global iterations; 2.786190s wall, 4.000000s user + 0.062500s system = 4.062500s CPU (145.8%)
+
+PHY-1001 : Congestion index: top1 = 58.43, top5 = 53.33, top10 = 50.55, top15 = 48.60.
+PHY-1001 : End incremental global routing; 3.250678s wall, 4.453125s user + 0.062500s system = 4.515625s CPU (138.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18904 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.122591s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (97.4%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7279 has valid locations, 33 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 813510
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17340/19112.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04039e+06, over cnt = 133(0%), over = 160, worst = 5
+PHY-1002 : len = 1.04072e+06, over cnt = 77(0%), over = 87, worst = 4
+PHY-1002 : len = 1.0411e+06, over cnt = 36(0%), over = 38, worst = 2
+PHY-1002 : len = 1.04133e+06, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 1.04189e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.084574s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (108.0%)
+
+PHY-1001 : Congestion index: top1 = 59.20, top5 = 53.67, top10 = 50.86, top15 = 48.91.
+PHY-3001 : End congestion estimation; 1.504454s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (105.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83485, tnet num: 18934, tinst num: 7400, tnode num: 106587, tedge num: 139795.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.043116s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (98.7%)
+
+RUN-1004 : used memory is 703 MB, reserved memory is 706 MB, peak memory is 777 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18934 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.042283s wall, 2.984375s user + 0.031250s system = 3.015625s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(292): len = 812630, overlap = 0
+PHY-3002 : Step(293): len = 812101, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17328/19112.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03921e+06, over cnt = 83(0%), over = 108, worst = 7
+PHY-1002 : len = 1.03911e+06, over cnt = 58(0%), over = 59, worst = 2
+PHY-1002 : len = 1.03957e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.03962e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.03969e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.005315s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (104.1%)
+
+PHY-1001 : Congestion index: top1 = 58.88, top5 = 53.52, top10 = 50.76, top15 = 48.79.
+PHY-3001 : End congestion estimation; 1.363188s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (102.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18934 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.978974s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000204557
+PHY-3002 : Step(294): len = 812143, overlap = 2.75
+PHY-3002 : Step(295): len = 812008, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005291s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 811980, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066327s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.2%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 1.
+PHY-3001 : Final: Len = 812230, Over = 0
+PHY-3001 : End incremental placement; 7.484147s wall, 7.765625s user + 0.171875s system = 7.937500s CPU (106.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 12.719947s wall, 14.140625s user + 0.250000s system = 14.390625s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 786, reserve = 789, peak = 793.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17284/19112.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03935e+06, over cnt = 99(0%), over = 126, worst = 6
+PHY-1002 : len = 1.0396e+06, over cnt = 49(0%), over = 52, worst = 2
+PHY-1002 : len = 1.04011e+06, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 1.04019e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.721121s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (110.5%)
+
+PHY-1001 : Congestion index: top1 = 58.34, top5 = 53.34, top10 = 50.55, top15 = 48.66.
+OPT-1001 : End congestion update; 1.092934s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18934 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.814113s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (101.7%)
+
+OPT-0007 : Start: WNS -4156 TNS -2266574 NUM_FEPS 992
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 812357, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067846s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.1%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 13, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 813049, Over = 0
+PHY-3001 : End incremental legalization; 0.441258s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.7%)
+
+OPT-0007 : Iter 1: improved WNS -3806 TNS -2248219 NUM_FEPS 992 with 54 cells processed and 6497 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813141, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064872s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.3%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 4, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 813231, Over = 0
+PHY-3001 : End incremental legalization; 0.428565s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.1%)
+
+OPT-0007 : Iter 2: improved WNS -3766 TNS -2243223 NUM_FEPS 992 with 22 cells processed and 2296 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813085, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066175s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.4%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 1, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 813271, Over = 0
+PHY-3001 : End incremental legalization; 0.430070s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (98.1%)
+
+OPT-0007 : Iter 3: improved WNS -3753 TNS -2243587 NUM_FEPS 992 with 21 cells processed and 2150 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813211, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067908s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.0%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 813231, Over = 0
+PHY-3001 : End incremental legalization; 0.436092s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (100.3%)
+
+OPT-0007 : Iter 4: improved WNS -3753 TNS -2242602 NUM_FEPS 992 with 14 cells processed and 868 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7318 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7406 instances, 7257 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813803, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066586s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.9%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 813843, Over = 0
+PHY-3001 : End incremental legalization; 0.436502s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (107.4%)
+
+OPT-0007 : Iter 5: improved WNS -3753 TNS -2240778 NUM_FEPS 992 with 6 cells processed and 608 slack improved
+OPT-1001 : End bottleneck based optimization; 5.008910s wall, 5.281250s user + 0.046875s system = 5.328125s CPU (106.4%)
+
+OPT-1001 : Current memory(MB): used = 786, reserve = 789, peak = 793.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16914/19113.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04082e+06, over cnt = 474(1%), over = 597, worst = 5
+PHY-1002 : len = 1.04093e+06, over cnt = 256(0%), over = 289, worst = 5
+PHY-1002 : len = 1.04261e+06, over cnt = 107(0%), over = 122, worst = 5
+PHY-1002 : len = 1.04409e+06, over cnt = 36(0%), over = 36, worst = 1
+PHY-1002 : len = 1.04518e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.005426s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (116.6%)
+
+PHY-1001 : Congestion index: top1 = 59.20, top5 = 53.44, top10 = 50.62, top15 = 48.81.
+OPT-1001 : End congestion update; 1.371537s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (112.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.856784s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (96.7%)
+
+OPT-0007 : Start: WNS -3753 TNS -2242765 NUM_FEPS 992
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7318 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7406 instances, 7257 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 814251, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064850s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.4%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 6, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 814377, Over = 0
+PHY-3001 : End incremental legalization; 0.427653s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (98.6%)
+
+OPT-0007 : Iter 1: improved WNS -3753 TNS -2251081 NUM_FEPS 992 with 32 cells processed and 2298 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7318 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7406 instances, 7257 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 814977, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069357s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (112.6%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 814989, Over = 0
+PHY-3001 : End incremental legalization; 0.460721s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.7%)
+
+OPT-0007 : Iter 2: improved WNS -3753 TNS -2250970 NUM_FEPS 992 with 15 cells processed and 874 slack improved
+OPT-0007 : Iter 3: improved WNS -3753 TNS -2250970 NUM_FEPS 992 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.443258s wall, 3.546875s user + 0.046875s system = 3.593750s CPU (104.4%)
+
+OPT-1001 : Current memory(MB): used = 786, reserve = 789, peak = 793.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.824670s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17131/19113.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04545e+06, over cnt = 167(0%), over = 200, worst = 4
+PHY-1002 : len = 1.04557e+06, over cnt = 118(0%), over = 131, worst = 4
+PHY-1002 : len = 1.04638e+06, over cnt = 58(0%), over = 58, worst = 1
+PHY-1002 : len = 1.04706e+06, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 1.0477e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.977783s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (99.1%)
+
+PHY-1001 : Congestion index: top1 = 59.12, top5 = 53.53, top10 = 50.70, top15 = 48.88.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.836889s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -3753 TNS -2252041 NUM_FEPS 992
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 58.724138
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -3753ps with logic level 5
+RUN-1001 : #2 path slack -3753ps with logic level 5
+RUN-1001 : #3 path slack -3716ps with logic level 5
+RUN-1001 : #4 path slack -3716ps with logic level 5
+RUN-1001 : #5 path slack -3663ps with logic level 5
+RUN-1001 : #6 path slack -3656ps with logic level 5
+RUN-1001 : #7 path slack -3656ps with logic level 5
+RUN-1001 : 0 HFN exist on timing critical paths out of 19113 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 19113 nets
+OPT-1001 : End physical optimization; 26.901083s wall, 28.656250s user + 0.390625s system = 29.046875s CPU (108.0%)
+
+RUN-1003 : finish command "place" in 84.466831s wall, 126.515625s user + 6.734375s system = 133.250000s CPU (157.8%)
+
+RUN-1004 : used memory is 688 MB, reserved memory is 702 MB, peak memory is 793 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.793632s wall, 3.093750s user + 0.000000s system = 3.093750s CPU (172.5%)
+
+RUN-1004 : used memory is 688 MB, reserved memory is 703 MB, peak memory is 793 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7408 instances
+RUN-1001 : 3630 mslices, 3627 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 19113 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10116 nets have 2 pins
+RUN-1001 : 7045 nets have [3 - 5] pins
+RUN-1001 : 972 nets have [6 - 10] pins
+RUN-1001 : 502 nets have [11 - 20] pins
+RUN-1001 : 449 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83563, tnet num: 18935, tinst num: 7406, tnode num: 106684, tedge num: 139888.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.735617s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.9%)
+
+RUN-1004 : used memory is 670 MB, reserved memory is 674 MB, peak memory is 793 MB
+PHY-1001 : 3630 mslices, 3627 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 950792, over cnt = 3409(9%), over = 5669, worst = 7
+PHY-1002 : len = 974488, over cnt = 2139(6%), over = 3048, worst = 6
+PHY-1002 : len = 998936, over cnt = 935(2%), over = 1246, worst = 6
+PHY-1002 : len = 1.0214e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.02206e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.421879s wall, 4.671875s user + 0.046875s system = 4.718750s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 58.43, top5 = 53.18, top10 = 50.42, top15 = 48.51.
+PHY-1001 : End global routing; 3.800056s wall, 5.046875s user + 0.046875s system = 5.093750s CPU (134.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 759, reserve = 765, peak = 793.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1039, reserve = 1045, peak = 1039.
+PHY-1001 : End build detailed router design. 4.073774s wall, 3.953125s user + 0.093750s system = 4.046875s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 275624, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.271368s wall, 5.250000s user + 0.000000s system = 5.250000s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 275680, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.453556s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1075, reserve = 1082, peak = 1075.
+PHY-1001 : End phase 1; 5.736924s wall, 5.718750s user + 0.000000s system = 5.718750s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 35% nets.
+PHY-1001 : Routed 41% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.71183e+06, over cnt = 2676(0%), over = 2694, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1096, reserve = 1100, peak = 1096.
+PHY-1001 : End initial routed; 33.247680s wall, 64.656250s user + 0.406250s system = 65.062500s CPU (195.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2866/18035(15%) critical/total net(s).
+RUN-1001 : -----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : -----------------------------------------
+RUN-1001 : Setup | -5.978 | -3462.099 | 1005
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : -----------------------------------------
+PHY-1001 : End update timing; 3.639568s wall, 3.640625s user + 0.000000s system = 3.640625s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1109, reserve = 1114, peak = 1109.
+PHY-1001 : End phase 2; 36.887316s wall, 68.296875s user + 0.406250s system = 68.703125s CPU (186.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 89 pins with SWNS -5.823ns STNS -3448.352ns FEP 1005.
+PHY-1001 : End OPT Iter 1; 0.562604s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (94.4%)
+
+PHY-1022 : len = 2.71238e+06, over cnt = 2734(0%), over = 2752, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.875755s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (96.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.65791e+06, over cnt = 1044(0%), over = 1048, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 3.108382s wall, 5.578125s user + 0.000000s system = 5.578125s CPU (179.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.64962e+06, over cnt = 289(0%), over = 289, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.587986s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (131.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.65068e+06, over cnt = 43(0%), over = 43, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.759226s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (111.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.6512e+06, over cnt = 15(0%), over = 15, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.421279s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (107.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.6515e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.475084s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.65155e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.509448s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (95.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.65154e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.812405s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.65157e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.207837s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.65156e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.215657s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (94.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2866/18035(15%) critical/total net(s).
+RUN-1001 : -----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : -----------------------------------------
+RUN-1001 : Setup | -5.921 | -3455.020 | 1005
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : -----------------------------------------
+PHY-1001 : End update timing; 3.744562s wall, 3.703125s user + 0.000000s system = 3.703125s CPU (98.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 929 feed throughs used by 671 nets
+PHY-1001 : End commit to database; 2.761244s wall, 2.640625s user + 0.046875s system = 2.687500s CPU (97.3%)
+
+PHY-1001 : Current memory(MB): used = 1224, reserve = 1233, peak = 1224.
+PHY-1001 : End phase 3; 15.929500s wall, 18.796875s user + 0.062500s system = 18.859375s CPU (118.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 32 pins with SWNS -5.783ns STNS -3450.347ns FEP 1005.
+PHY-1001 : End OPT Iter 1; 0.353407s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (92.8%)
+
+PHY-1022 : len = 2.65158e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.689959s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (95.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.783ns, -3450.347ns, 1005}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.65153e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.219398s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.65156e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.222953s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2866/18035(15%) critical/total net(s).
+RUN-1001 : -----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : -----------------------------------------
+RUN-1001 : Setup | -5.783 | -3454.874 | 1005
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : -----------------------------------------
+PHY-1001 : End update timing; 4.073171s wall, 4.031250s user + 0.000000s system = 4.031250s CPU (99.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 929 feed throughs used by 671 nets
+PHY-1001 : End commit to database; 2.906555s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (97.8%)
+
+PHY-1001 : Current memory(MB): used = 1234, reserve = 1244, peak = 1234.
+PHY-1001 : End phase 4; 8.185444s wall, 8.062500s user + 0.000000s system = 8.062500s CPU (98.5%)
+
+PHY-1003 : Routed, final wirelength = 2.65156e+06
+PHY-1001 : Current memory(MB): used = 1238, reserve = 1248, peak = 1238.
+PHY-1001 : End export database. 0.075370s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (103.7%)
+
+PHY-1001 : End detail routing; 71.347655s wall, 105.375000s user + 0.562500s system = 105.937500s CPU (148.5%)
+
+RUN-1003 : finish command "route" in 78.124959s wall, 113.375000s user + 0.625000s system = 114.000000s CPU (145.9%)
+
+RUN-1004 : used memory is 1152 MB, reserved memory is 1168 MB, peak memory is 1238 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 12131 out of 19600 61.89%
+#reg 9496 out of 19600 48.45%
+#le 13687
+ #lut only 4191 out of 13687 30.62%
+ #reg only 1556 out of 13687 11.37%
+ #lut® 7940 out of 13687 58.01%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1808
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1479
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1448
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 988
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 135
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 23
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/u_ADconfig/reg1_syn_159.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/reg2_syn_207.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P35 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P66 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P162 LVCMOS33 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P19 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P11 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P10 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |13687 |11104 |1027 |9527 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |533 |488 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |107 |96 |4 |95 |4 |0 |
+| U_crc16_24b |crc16_24b |28 |28 |0 |18 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |10 |0 |0 |
+| exdev_ctl_a |exdev_ctl |746 |436 |96 |566 |0 |0 |
+| u_ADconfig |AD_config |180 |110 |25 |138 |0 |0 |
+| u_gen_sp |gen_sp |257 |154 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |717 |460 |96 |534 |0 |0 |
+| u_ADconfig |AD_config |172 |137 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |251 |148 |71 |114 |0 |0 |
+| sampling_fe_a |sampling_fe |3467 |2922 |306 |2187 |25 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |180 |135 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_sort |sort |3251 |2763 |289 |2007 |25 |0 |
+| rddpram_ctl |rddpram_ctl |7 |4 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |4 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2804 |2386 |253 |1667 |22 |0 |
+| channelPart |channel_part_8478 |182 |171 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |68 |59 |9 |43 |0 |0 |
+| ram_switch |ram_switch |2245 |1907 |197 |1253 |0 |0 |
+| adc_addr_gen |adc_addr_gen |240 |212 |27 |122 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |28 |25 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |29 |26 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |11 |0 |0 |
+| insert |insert |1002 |704 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |1003 |991 |0 |452 |0 |0 |
+| read_ram_i |read_ram |259 |207 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |210 |170 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |46 |34 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |308 |253 |36 |247 |3 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |4073 |3455 |349 |2108 |25 |1 |
+| u0_soft_n |cdc_sync |8 |2 |0 |8 |0 |0 |
+| u_ad_sampling |ad_sampling |175 |138 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_sort |sort_rev |3865 |3298 |332 |1934 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |3470 |2966 |290 |1594 |22 |1 |
+| channelPart |channel_part_8478 |279 |271 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |2745 |2359 |197 |1170 |0 |0 |
+| adc_addr_gen |adc_addr_gen |252 |223 |27 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |8 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |30 |27 |3 |14 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |11 |0 |0 |
+| insert |insert |999 |643 |170 |678 |0 |0 |
+| ram_switch_state |ram_switch_state |1494 |1493 |0 |377 |0 |0 |
+| read_ram_i |read_ram_rev |342 |249 |81 |199 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |210 |73 |158 |0 |0 |
+| read_ram_data |read_ram_data_rev |56 |39 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10054
+ #2 2 4922
+ #3 3 1396
+ #4 4 724
+ #5 5-10 1088
+ #6 11-50 798
+ #7 51-100 34
+ #8 >500 1
+ Average 3.09
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.346559s wall, 4.046875s user + 0.031250s system = 4.078125s CPU (173.8%)
+
+RUN-1004 : used memory is 1154 MB, reserved memory is 1168 MB, peak memory is 1238 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83563, tnet num: 18935, tinst num: 7406, tnode num: 106684, tedge num: 139888.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.888978s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.1%)
+
+RUN-1004 : used memory is 1160 MB, reserved memory is 1174 MB, peak memory is 1238 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.792782s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.2%)
+
+RUN-1004 : used memory is 1163 MB, reserved memory is 1177 MB, peak memory is 1238 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7406
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 19113, pip num: 198421
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 929
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3264 valid insts, and 549065 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.802405s wall, 70.859375s user + 0.187500s system = 71.046875s CPU (657.7%)
+
+RUN-1004 : used memory is 1345 MB, reserved memory is 1348 MB, peak memory is 1461 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_171606.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_171944.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_171944.log
new file mode 100644
index 0000000..4d529e2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_171944.log
@@ -0,0 +1,2093 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 17:19:44 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.295567s wall, 2.265625s user + 0.031250s system = 2.296875s CPU (100.1%)
+
+RUN-1004 : used memory is 348 MB, reserved memory is 324 MB, peak memory is 352 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 3.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -multiply_by 3.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 19228 instances
+RUN-0007 : 8903 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21806 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14137 nets have 2 pins
+RUN-1001 : 6220 nets have [3 - 5] pins
+RUN-1001 : 875 nets have [6 - 10] pins
+RUN-1001 : 312 nets have [11 - 20] pins
+RUN-1001 : 188 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 19226 instances, 8903 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5958 pins
+PHY-0007 : Cell area utilization is 56%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92309, tnet num: 21628, tinst num: 19226, tnode num: 122567, tedge num: 148092.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.251611s wall, 1.171875s user + 0.062500s system = 1.234375s CPU (98.6%)
+
+RUN-1004 : used memory is 554 MB, reserved memory is 537 MB, peak memory is 554 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.121605s wall, 2.000000s user + 0.093750s system = 2.093750s CPU (98.7%)
+
+PHY-3001 : Found 1252 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.32081e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 19226.
+PHY-3001 : Level 1 #clusters 2530.
+PHY-3001 : End clustering; 0.167449s wall, 0.187500s user + 0.046875s system = 0.234375s CPU (140.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.447e+06, overlap = 554.469
+PHY-3002 : Step(2): len = 1.09904e+06, overlap = 670.469
+PHY-3002 : Step(3): len = 885777, overlap = 767.344
+PHY-3002 : Step(4): len = 729070, overlap = 859.844
+PHY-3002 : Step(5): len = 550760, overlap = 1013.56
+PHY-3002 : Step(6): len = 474804, overlap = 1081.53
+PHY-3002 : Step(7): len = 400655, overlap = 1155.12
+PHY-3002 : Step(8): len = 346475, overlap = 1190.53
+PHY-3002 : Step(9): len = 307022, overlap = 1239.91
+PHY-3002 : Step(10): len = 279609, overlap = 1287.97
+PHY-3002 : Step(11): len = 248763, overlap = 1361.81
+PHY-3002 : Step(12): len = 231176, overlap = 1410.78
+PHY-3002 : Step(13): len = 212574, overlap = 1453.69
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.02238e-06
+PHY-3002 : Step(14): len = 209797, overlap = 1396.66
+PHY-3002 : Step(15): len = 236693, overlap = 1357.38
+PHY-3002 : Step(16): len = 241330, overlap = 1283.28
+PHY-3002 : Step(17): len = 240256, overlap = 1248.5
+PHY-3002 : Step(18): len = 234200, overlap = 1249.38
+PHY-3002 : Step(19): len = 232144, overlap = 1220.38
+PHY-3002 : Step(20): len = 226234, overlap = 1198.44
+PHY-3002 : Step(21): len = 224046, overlap = 1184.03
+PHY-3002 : Step(22): len = 219522, overlap = 1168.16
+PHY-3002 : Step(23): len = 217776, overlap = 1165.66
+PHY-3002 : Step(24): len = 214314, overlap = 1156.5
+PHY-3002 : Step(25): len = 213737, overlap = 1151.81
+PHY-3002 : Step(26): len = 211764, overlap = 1142.47
+PHY-3002 : Step(27): len = 210795, overlap = 1139.41
+PHY-3002 : Step(28): len = 209255, overlap = 1146.53
+PHY-3002 : Step(29): len = 208958, overlap = 1140
+PHY-3002 : Step(30): len = 208125, overlap = 1133.53
+PHY-3002 : Step(31): len = 207230, overlap = 1118.97
+PHY-3002 : Step(32): len = 206793, overlap = 1101.06
+PHY-3002 : Step(33): len = 206418, overlap = 1099.03
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.04476e-06
+PHY-3002 : Step(34): len = 212958, overlap = 1077.06
+PHY-3002 : Step(35): len = 226143, overlap = 1035.09
+PHY-3002 : Step(36): len = 231421, overlap = 1004.09
+PHY-3002 : Step(37): len = 235728, overlap = 986.312
+PHY-3002 : Step(38): len = 236293, overlap = 954.125
+PHY-3002 : Step(39): len = 236940, overlap = 941.438
+PHY-3002 : Step(40): len = 236304, overlap = 946.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.08953e-06
+PHY-3002 : Step(41): len = 253396, overlap = 906.375
+PHY-3002 : Step(42): len = 276402, overlap = 851.438
+PHY-3002 : Step(43): len = 284262, overlap = 838.375
+PHY-3002 : Step(44): len = 286875, overlap = 802.375
+PHY-3002 : Step(45): len = 284263, overlap = 792.688
+PHY-3002 : Step(46): len = 281570, overlap = 768.25
+PHY-3002 : Step(47): len = 281564, overlap = 773.719
+PHY-3002 : Step(48): len = 282435, overlap = 761.094
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.17905e-06
+PHY-3002 : Step(49): len = 303416, overlap = 716.469
+PHY-3002 : Step(50): len = 322417, overlap = 658.719
+PHY-3002 : Step(51): len = 328115, overlap = 584.5
+PHY-3002 : Step(52): len = 329340, overlap = 569.312
+PHY-3002 : Step(53): len = 325273, overlap = 597.656
+PHY-3002 : Step(54): len = 324670, overlap = 606.688
+PHY-3002 : Step(55): len = 324908, overlap = 610.469
+PHY-3002 : Step(56): len = 326359, overlap = 598.281
+PHY-3002 : Step(57): len = 325780, overlap = 590.812
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.63581e-05
+PHY-3002 : Step(58): len = 350165, overlap = 530.219
+PHY-3002 : Step(59): len = 365967, overlap = 483.25
+PHY-3002 : Step(60): len = 368365, overlap = 448.031
+PHY-3002 : Step(61): len = 370246, overlap = 445.125
+PHY-3002 : Step(62): len = 371528, overlap = 450.875
+PHY-3002 : Step(63): len = 374534, overlap = 454.406
+PHY-3002 : Step(64): len = 374929, overlap = 448.188
+PHY-3002 : Step(65): len = 376337, overlap = 436.094
+PHY-3002 : Step(66): len = 376264, overlap = 419.906
+PHY-3002 : Step(67): len = 375930, overlap = 415.688
+PHY-3002 : Step(68): len = 376181, overlap = 439.719
+PHY-3002 : Step(69): len = 377536, overlap = 443.562
+PHY-3002 : Step(70): len = 378431, overlap = 446.312
+PHY-3002 : Step(71): len = 378137, overlap = 436.094
+PHY-3002 : Step(72): len = 378524, overlap = 444.594
+PHY-3002 : Step(73): len = 377616, overlap = 445.531
+PHY-3002 : Step(74): len = 377961, overlap = 430.844
+PHY-3002 : Step(75): len = 375667, overlap = 434.531
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.27162e-05
+PHY-3002 : Step(76): len = 394983, overlap = 419.75
+PHY-3002 : Step(77): len = 407030, overlap = 395.594
+PHY-3002 : Step(78): len = 407894, overlap = 376.75
+PHY-3002 : Step(79): len = 408615, overlap = 375.75
+PHY-3002 : Step(80): len = 409689, overlap = 358.688
+PHY-3002 : Step(81): len = 412213, overlap = 352.844
+PHY-3002 : Step(82): len = 411500, overlap = 344.344
+PHY-3002 : Step(83): len = 412558, overlap = 344.156
+PHY-3002 : Step(84): len = 412796, overlap = 341.438
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.54324e-05
+PHY-3002 : Step(85): len = 430570, overlap = 333.594
+PHY-3002 : Step(86): len = 442795, overlap = 324.938
+PHY-3002 : Step(87): len = 442635, overlap = 308.75
+PHY-3002 : Step(88): len = 443794, overlap = 305.344
+PHY-3002 : Step(89): len = 445630, overlap = 284.406
+PHY-3002 : Step(90): len = 449284, overlap = 281.188
+PHY-3002 : Step(91): len = 450914, overlap = 291.5
+PHY-3002 : Step(92): len = 450621, overlap = 277.594
+PHY-3002 : Step(93): len = 451446, overlap = 276.344
+PHY-3002 : Step(94): len = 452744, overlap = 271.188
+PHY-3002 : Step(95): len = 452584, overlap = 256.375
+PHY-3002 : Step(96): len = 451269, overlap = 250.719
+PHY-3002 : Step(97): len = 451478, overlap = 243.875
+PHY-3002 : Step(98): len = 450464, overlap = 259.188
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000130865
+PHY-3002 : Step(99): len = 462527, overlap = 231.531
+PHY-3002 : Step(100): len = 470513, overlap = 230.25
+PHY-3002 : Step(101): len = 471547, overlap = 229.688
+PHY-3002 : Step(102): len = 472002, overlap = 231.625
+PHY-3002 : Step(103): len = 473791, overlap = 229.031
+PHY-3002 : Step(104): len = 476008, overlap = 228.469
+PHY-3002 : Step(105): len = 476100, overlap = 233.438
+PHY-3002 : Step(106): len = 476997, overlap = 226.812
+PHY-3002 : Step(107): len = 476946, overlap = 226.094
+PHY-3002 : Step(108): len = 477845, overlap = 212.469
+PHY-3002 : Step(109): len = 476939, overlap = 209.094
+PHY-3002 : Step(110): len = 477703, overlap = 210.062
+PHY-3002 : Step(111): len = 477928, overlap = 213.844
+PHY-3002 : Step(112): len = 478583, overlap = 214.844
+PHY-3002 : Step(113): len = 478153, overlap = 213.688
+PHY-3002 : Step(114): len = 478430, overlap = 221.656
+PHY-3002 : Step(115): len = 478343, overlap = 224.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000257561
+PHY-3002 : Step(116): len = 486793, overlap = 214.594
+PHY-3002 : Step(117): len = 494662, overlap = 206.5
+PHY-3002 : Step(118): len = 497044, overlap = 200.156
+PHY-3002 : Step(119): len = 498754, overlap = 203.719
+PHY-3002 : Step(120): len = 500233, overlap = 210
+PHY-3002 : Step(121): len = 501721, overlap = 216.438
+PHY-3002 : Step(122): len = 501907, overlap = 203.719
+PHY-3002 : Step(123): len = 502646, overlap = 198.875
+PHY-3002 : Step(124): len = 502975, overlap = 196.688
+PHY-3002 : Step(125): len = 503448, overlap = 199.562
+PHY-3002 : Step(126): len = 502447, overlap = 200.188
+PHY-3002 : Step(127): len = 502380, overlap = 197.562
+PHY-3002 : Step(128): len = 502641, overlap = 197
+PHY-3002 : Step(129): len = 502877, overlap = 195.75
+PHY-3002 : Step(130): len = 502368, overlap = 192.719
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000464942
+PHY-3002 : Step(131): len = 506654, overlap = 191.844
+PHY-3002 : Step(132): len = 511644, overlap = 181.906
+PHY-3002 : Step(133): len = 513577, overlap = 181.781
+PHY-3002 : Step(134): len = 514614, overlap = 177.75
+PHY-3002 : Step(135): len = 514830, overlap = 177.844
+PHY-3002 : Step(136): len = 514955, overlap = 168.719
+PHY-3002 : Step(137): len = 514612, overlap = 171.562
+PHY-3002 : Step(138): len = 514778, overlap = 174.656
+PHY-3002 : Step(139): len = 515819, overlap = 170.25
+PHY-3002 : Step(140): len = 516623, overlap = 164.531
+PHY-3002 : Step(141): len = 516222, overlap = 163.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000765613
+PHY-3002 : Step(142): len = 518542, overlap = 162.969
+PHY-3002 : Step(143): len = 521770, overlap = 160.5
+PHY-3002 : Step(144): len = 523612, overlap = 154.969
+PHY-3002 : Step(145): len = 525289, overlap = 156.906
+PHY-3002 : Step(146): len = 527410, overlap = 159.875
+PHY-3002 : Step(147): len = 530245, overlap = 153.156
+PHY-3002 : Step(148): len = 530428, overlap = 151.75
+PHY-3002 : Step(149): len = 530641, overlap = 146.5
+PHY-3002 : Step(150): len = 531185, overlap = 150.312
+PHY-3002 : Step(151): len = 531435, overlap = 147.938
+PHY-3002 : Step(152): len = 530781, overlap = 149.844
+PHY-3002 : Step(153): len = 530579, overlap = 147.938
+PHY-3002 : Step(154): len = 530935, overlap = 146.281
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00131086
+PHY-3002 : Step(155): len = 532384, overlap = 152.281
+PHY-3002 : Step(156): len = 534432, overlap = 152.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.011999s wall, 0.000000s user + 0.031250s system = 0.031250s CPU (260.4%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21806.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708296, over cnt = 1510(4%), over = 6604, worst = 43
+PHY-1001 : End global iterations; 0.768981s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (132.1%)
+
+PHY-1001 : Congestion index: top1 = 75.04, top5 = 58.36, top10 = 50.45, top15 = 45.30.
+PHY-3001 : End congestion estimation; 1.007642s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (125.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.917313s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.77562e-05
+PHY-3002 : Step(157): len = 642713, overlap = 103.031
+PHY-3002 : Step(158): len = 660220, overlap = 94.375
+PHY-3002 : Step(159): len = 646120, overlap = 94.2812
+PHY-3002 : Step(160): len = 643567, overlap = 91.0938
+PHY-3002 : Step(161): len = 634484, overlap = 91
+PHY-3002 : Step(162): len = 632189, overlap = 89.9375
+PHY-3002 : Step(163): len = 627347, overlap = 86.875
+PHY-3002 : Step(164): len = 624625, overlap = 83.9688
+PHY-3002 : Step(165): len = 622340, overlap = 80.5
+PHY-3002 : Step(166): len = 616067, overlap = 79.2188
+PHY-3002 : Step(167): len = 613779, overlap = 77.7188
+PHY-3002 : Step(168): len = 614219, overlap = 79.3438
+PHY-3002 : Step(169): len = 612165, overlap = 78.7812
+PHY-3002 : Step(170): len = 609958, overlap = 82
+PHY-3002 : Step(171): len = 609959, overlap = 80.4688
+PHY-3002 : Step(172): len = 605933, overlap = 80.0938
+PHY-3002 : Step(173): len = 605165, overlap = 76.9062
+PHY-3002 : Step(174): len = 604460, overlap = 76.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000135512
+PHY-3002 : Step(175): len = 602744, overlap = 76.1562
+PHY-3002 : Step(176): len = 606300, overlap = 75.5312
+PHY-3002 : Step(177): len = 609781, overlap = 73.0625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000271025
+PHY-3002 : Step(178): len = 618534, overlap = 76.3125
+PHY-3002 : Step(179): len = 628406, overlap = 82.4062
+PHY-3002 : Step(180): len = 637165, overlap = 83.4375
+PHY-3002 : Step(181): len = 645241, overlap = 76.75
+PHY-3002 : Step(182): len = 645868, overlap = 74
+PHY-3002 : Step(183): len = 646278, overlap = 72.9375
+PHY-3002 : Step(184): len = 642724, overlap = 71.6562
+PHY-3002 : Step(185): len = 641014, overlap = 75.5938
+PHY-3002 : Step(186): len = 641527, overlap = 76.7812
+PHY-3002 : Step(187): len = 639188, overlap = 77.9688
+PHY-3002 : Step(188): len = 636580, overlap = 77.3438
+PHY-3002 : Step(189): len = 636302, overlap = 74.5625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00054205
+PHY-3002 : Step(190): len = 637503, overlap = 76.1875
+PHY-3002 : Step(191): len = 642840, overlap = 75.1875
+PHY-3002 : Step(192): len = 649577, overlap = 74.0938
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.0010841
+PHY-3002 : Step(193): len = 653163, overlap = 71.2188
+PHY-3002 : Step(194): len = 669952, overlap = 67.3438
+PHY-3002 : Step(195): len = 681341, overlap = 71.2812
+PHY-3002 : Step(196): len = 683348, overlap = 72.25
+PHY-3002 : Step(197): len = 683208, overlap = 78.7188
+PHY-3002 : Step(198): len = 684364, overlap = 76.9375
+PHY-3002 : Step(199): len = 681273, overlap = 76.0938
+PHY-3002 : Step(200): len = 681069, overlap = 75.375
+PHY-3002 : Step(201): len = 681709, overlap = 73.5938
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00181204
+PHY-3002 : Step(202): len = 681993, overlap = 73.875
+PHY-3002 : Step(203): len = 684941, overlap = 76.8438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 126/21806.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 783064, over cnt = 2869(8%), over = 13796, worst = 52
+PHY-1001 : End global iterations; 1.581105s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 90.65, top5 = 72.43, top10 = 63.87, top15 = 58.28.
+PHY-3001 : End congestion estimation; 1.885867s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (130.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.398074s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.20827e-05
+PHY-3002 : Step(204): len = 675858, overlap = 365.719
+PHY-3002 : Step(205): len = 676077, overlap = 304.812
+PHY-3002 : Step(206): len = 656194, overlap = 279.438
+PHY-3002 : Step(207): len = 649188, overlap = 280.906
+PHY-3002 : Step(208): len = 638581, overlap = 274.906
+PHY-3002 : Step(209): len = 635451, overlap = 264.062
+PHY-3002 : Step(210): len = 627473, overlap = 268.406
+PHY-3002 : Step(211): len = 621827, overlap = 263.375
+PHY-3002 : Step(212): len = 618968, overlap = 262.531
+PHY-3002 : Step(213): len = 614280, overlap = 262.125
+PHY-3002 : Step(214): len = 610790, overlap = 248.938
+PHY-3002 : Step(215): len = 605956, overlap = 254.312
+PHY-3002 : Step(216): len = 604551, overlap = 253.688
+PHY-3002 : Step(217): len = 599810, overlap = 255.469
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000164165
+PHY-3002 : Step(218): len = 599473, overlap = 252
+PHY-3002 : Step(219): len = 601819, overlap = 250.438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000315492
+PHY-3002 : Step(220): len = 608618, overlap = 243.281
+PHY-3002 : Step(221): len = 616131, overlap = 242.188
+PHY-3002 : Step(222): len = 624898, overlap = 230.656
+PHY-3002 : Step(223): len = 622092, overlap = 229.75
+PHY-3002 : Step(224): len = 621811, overlap = 228.375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000626815
+PHY-3002 : Step(225): len = 627038, overlap = 218.25
+PHY-3002 : Step(226): len = 638356, overlap = 200.469
+PHY-3002 : Step(227): len = 645995, overlap = 184.594
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00125363
+PHY-3002 : Step(228): len = 644784, overlap = 179.594
+PHY-3002 : Step(229): len = 648267, overlap = 171.812
+PHY-3002 : Step(230): len = 657560, overlap = 154.656
+PHY-3002 : Step(231): len = 661594, overlap = 143.688
+PHY-3002 : Step(232): len = 663303, overlap = 135.219
+PHY-3002 : Step(233): len = 664522, overlap = 131.188
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00236125
+PHY-3002 : Step(234): len = 666257, overlap = 127.938
+PHY-3002 : Step(235): len = 669983, overlap = 124.688
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92309, tnet num: 21628, tinst num: 19226, tnode num: 122567, tedge num: 148092.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.500809s wall, 1.484375s user + 0.015625s system = 1.500000s CPU (99.9%)
+
+RUN-1004 : used memory is 598 MB, reserved memory is 587 MB, peak memory is 746 MB
+OPT-1001 : Total overflow 538.03 peak overflow 3.91
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 524/21806.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 794568, over cnt = 3486(9%), over = 13170, worst = 26
+PHY-1001 : End global iterations; 1.488514s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 73.49, top5 = 59.91, top10 = 54.20, top15 = 50.96.
+PHY-1001 : End incremental global routing; 1.826407s wall, 2.453125s user + 0.015625s system = 2.468750s CPU (135.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21628 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.011594s wall, 0.953125s user + 0.046875s system = 1.000000s CPU (98.9%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 19097 has valid locations, 368 needs to be replaced
+PHY-3001 : design contains 19550 instances, 8973 luts, 9356 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6083 pins
+PHY-3001 : Found 1259 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 701039
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 18117/22130.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 811456, over cnt = 3537(10%), over = 13249, worst = 26
+PHY-1001 : End global iterations; 0.374948s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (120.9%)
+
+PHY-1001 : Congestion index: top1 = 73.25, top5 = 60.17, top10 = 54.52, top15 = 51.25.
+PHY-3001 : End congestion estimation; 0.652072s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (112.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 93611, tnet num: 21952, tinst num: 19550, tnode num: 124633, tedge num: 150048.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.535353s wall, 1.484375s user + 0.046875s system = 1.531250s CPU (99.7%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 650 MB, peak memory is 751 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21952 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.968880s wall, 2.921875s user + 0.046875s system = 2.968750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(236): len = 699625, overlap = 0.3125
+PHY-3002 : Step(237): len = 700198, overlap = 0.3125
+PHY-3002 : Step(238): len = 700248, overlap = 0.3125
+PHY-3002 : Step(239): len = 700015, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 18156/22130.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808168, over cnt = 3545(10%), over = 13366, worst = 26
+PHY-1001 : End global iterations; 0.251310s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (149.2%)
+
+PHY-1001 : Congestion index: top1 = 74.27, top5 = 60.67, top10 = 54.90, top15 = 51.60.
+PHY-3001 : End congestion estimation; 0.523199s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (125.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21952 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.128502s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (98.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000184804
+PHY-3002 : Step(240): len = 700283, overlap = 128.531
+PHY-3002 : Step(241): len = 700993, overlap = 127.688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000369608
+PHY-3002 : Step(242): len = 701059, overlap = 127.625
+PHY-3002 : Step(243): len = 701382, overlap = 127.969
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000709634
+PHY-3002 : Step(244): len = 701801, overlap = 127.812
+PHY-3002 : Step(245): len = 702249, overlap = 128.312
+PHY-3001 : Final: Len = 702249, Over = 128.312
+PHY-3001 : End incremental placement; 6.074575s wall, 6.453125s user + 0.218750s system = 6.671875s CPU (109.8%)
+
+OPT-1001 : Total overflow 546.22 peak overflow 3.91
+OPT-1001 : End high-fanout net optimization; 9.516961s wall, 10.562500s user + 0.281250s system = 10.843750s CPU (113.9%)
+
+OPT-1001 : Current memory(MB): used = 755, reserve = 749, peak = 773.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 18154/22130.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 814104, over cnt = 3518(9%), over = 11909, worst = 26
+PHY-1002 : len = 871264, over cnt = 2716(7%), over = 6946, worst = 19
+PHY-1002 : len = 939232, over cnt = 1103(3%), over = 2349, worst = 19
+PHY-1002 : len = 964504, over cnt = 449(1%), over = 910, worst = 19
+PHY-1002 : len = 983144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.410000s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (133.6%)
+
+PHY-1001 : Congestion index: top1 = 58.41, top5 = 53.01, top10 = 49.98, top15 = 48.05.
+OPT-1001 : End congestion update; 2.697109s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (130.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21952 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.908237s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.1%)
+
+OPT-0007 : Start: WNS -4184 TNS -2446216 NUM_FEPS 1074
+OPT-0007 : Iter 1: improved WNS -3984 TNS -2431428 NUM_FEPS 1074 with 66 cells processed and 3698 slack improved
+OPT-0007 : Iter 2: improved WNS -3984 TNS -2428326 NUM_FEPS 1074 with 52 cells processed and 2548 slack improved
+OPT-0007 : Iter 3: improved WNS -3984 TNS -2427358 NUM_FEPS 1074 with 17 cells processed and 1000 slack improved
+OPT-0007 : Iter 4: improved WNS -3984 TNS -2427358 NUM_FEPS 1074 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 5: improved WNS -3984 TNS -2420808 NUM_FEPS 1074 with 2 cells processed and 400 slack improved
+OPT-1001 : End bottleneck based optimization; 4.199892s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (119.1%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 724, peak = 773.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 18375/22132.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 983400, over cnt = 177(0%), over = 221, worst = 3
+PHY-1002 : len = 982864, over cnt = 126(0%), over = 144, worst = 3
+PHY-1002 : len = 983368, over cnt = 50(0%), over = 53, worst = 2
+PHY-1002 : len = 984064, over cnt = 11(0%), over = 12, worst = 2
+PHY-1002 : len = 984416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.804431s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (104.9%)
+
+PHY-1001 : Congestion index: top1 = 58.28, top5 = 52.90, top10 = 49.92, top15 = 48.03.
+OPT-1001 : End congestion update; 1.093102s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (104.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21954 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.894274s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (96.1%)
+
+OPT-0007 : Start: WNS -3984 TNS -2420808 NUM_FEPS 1074
+OPT-0007 : Iter 1: improved WNS -3934 TNS -2418348 NUM_FEPS 1074 with 31 cells processed and 1882 slack improved
+OPT-0007 : Iter 2: improved WNS -3934 TNS -2418348 NUM_FEPS 1074 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.136501s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (100.9%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 735, peak = 773.
+OPT-1001 : End physical optimization; 17.677424s wall, 19.625000s user + 0.296875s system = 19.921875s CPU (112.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8973 LUT to BLE ...
+SYN-4008 : Packed 8973 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6223 remaining SEQ's ...
+SYN-4005 : Packed 4619 SEQ with LUT/SLICE
+SYN-4006 : 1518 single LUT's are left
+SYN-4006 : 1604 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10577/14432 primitive instances ...
+PHY-3001 : End packing; 1.804649s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7372 instances
+RUN-1001 : 3612 mslices, 3612 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 19082 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10118 nets have 2 pins
+RUN-1001 : 7040 nets have [3 - 5] pins
+RUN-1001 : 968 nets have [6 - 10] pins
+RUN-1001 : 491 nets have [11 - 20] pins
+RUN-1001 : 433 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7370 instances, 7224 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3619 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 709476, Over = 332.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 8065/19082.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899928, over cnt = 2439(6%), over = 4131, worst = 9
+PHY-1002 : len = 910952, over cnt = 1603(4%), over = 2322, worst = 6
+PHY-1002 : len = 931160, over cnt = 501(1%), over = 680, worst = 6
+PHY-1002 : len = 940384, over cnt = 139(0%), over = 176, worst = 5
+PHY-1002 : len = 945496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.926759s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (147.6%)
+
+PHY-1001 : Congestion index: top1 = 59.68, top5 = 53.13, top10 = 49.69, top15 = 47.35.
+PHY-3001 : End congestion estimation; 2.348313s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (139.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83259, tnet num: 18904, tinst num: 7370, tnode num: 106310, tedge num: 139503.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.813113s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.1%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 655 MB, peak memory is 773 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18904 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.813952s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.23438e-05
+PHY-3002 : Step(246): len = 693495, overlap = 337.75
+PHY-3002 : Step(247): len = 682964, overlap = 369.25
+PHY-3002 : Step(248): len = 675906, overlap = 412.75
+PHY-3002 : Step(249): len = 670292, overlap = 425.5
+PHY-3002 : Step(250): len = 665634, overlap = 430.75
+PHY-3002 : Step(251): len = 662657, overlap = 422.5
+PHY-3002 : Step(252): len = 659184, overlap = 420.25
+PHY-3002 : Step(253): len = 656602, overlap = 418.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.46876e-05
+PHY-3002 : Step(254): len = 661652, overlap = 409.25
+PHY-3002 : Step(255): len = 667606, overlap = 399
+PHY-3002 : Step(256): len = 669318, overlap = 404
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000169375
+PHY-3002 : Step(257): len = 676769, overlap = 393.5
+PHY-3002 : Step(258): len = 688610, overlap = 375.5
+PHY-3002 : Step(259): len = 690657, overlap = 368.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00033875
+PHY-3002 : Step(260): len = 697277, overlap = 353
+PHY-3002 : Step(261): len = 709936, overlap = 339.5
+PHY-3002 : Step(262): len = 712255, overlap = 330.75
+PHY-3002 : Step(263): len = 712060, overlap = 327.5
+PHY-3002 : Step(264): len = 712161, overlap = 321.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000605577
+PHY-3002 : Step(265): len = 718330, overlap = 312
+PHY-3002 : Step(266): len = 723795, overlap = 305
+PHY-3002 : Step(267): len = 729108, overlap = 300
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.0011383
+PHY-3002 : Step(268): len = 732614, overlap = 296.25
+PHY-3002 : Step(269): len = 739706, overlap = 281.75
+PHY-3002 : Step(270): len = 751969, overlap = 262.25
+PHY-3002 : Step(271): len = 751380, overlap = 263.75
+PHY-3002 : Step(272): len = 749679, overlap = 263.5
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 0.0018847
+PHY-3002 : Step(273): len = 751666, overlap = 260
+PHY-3002 : Step(274): len = 754497, overlap = 257
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.346679s wall, 0.281250s user + 0.609375s system = 0.890625s CPU (256.9%)
+
+PHY-3001 : Trial Legalized: Len = 838208
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 642/19082.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 987480, over cnt = 3425(9%), over = 5781, worst = 7
+PHY-1002 : len = 1.00632e+06, over cnt = 2349(6%), over = 3560, worst = 7
+PHY-1002 : len = 1.03781e+06, over cnt = 937(2%), over = 1338, worst = 6
+PHY-1002 : len = 1.04953e+06, over cnt = 435(1%), over = 622, worst = 6
+PHY-1002 : len = 1.06222e+06, over cnt = 34(0%), over = 42, worst = 4
+PHY-1001 : End global iterations; 3.005871s wall, 4.171875s user + 0.031250s system = 4.203125s CPU (139.8%)
+
+PHY-1001 : Congestion index: top1 = 59.46, top5 = 54.02, top10 = 51.32, top15 = 49.48.
+PHY-3001 : End congestion estimation; 3.529405s wall, 4.656250s user + 0.031250s system = 4.687500s CPU (132.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18904 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.339190s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (95.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000218969
+PHY-3002 : Step(275): len = 788750, overlap = 93
+PHY-3002 : Step(276): len = 763500, overlap = 156
+PHY-3002 : Step(277): len = 742826, overlap = 220.5
+PHY-3002 : Step(278): len = 731770, overlap = 258.5
+PHY-3002 : Step(279): len = 726063, overlap = 272
+PHY-3002 : Step(280): len = 721420, overlap = 293.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000437939
+PHY-3002 : Step(281): len = 726850, overlap = 286.75
+PHY-3002 : Step(282): len = 731588, overlap = 278.5
+PHY-3002 : Step(283): len = 733328, overlap = 267.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000875878
+PHY-3002 : Step(284): len = 736456, overlap = 262.5
+PHY-3002 : Step(285): len = 742494, overlap = 252.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00147291
+PHY-3002 : Step(286): len = 743837, overlap = 250.5
+PHY-3002 : Step(287): len = 752031, overlap = 237.25
+PHY-3002 : Step(288): len = 756250, overlap = 231.5
+PHY-3002 : Step(289): len = 758187, overlap = 231.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00262892
+PHY-3002 : Step(290): len = 759132, overlap = 228.75
+PHY-3002 : Step(291): len = 763442, overlap = 224.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034491s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (135.9%)
+
+PHY-3001 : Legalized: Len = 796020, Over = 0
+PHY-3001 : Spreading special nets. 568 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.125439s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (112.1%)
+
+PHY-3001 : 865 instances has been re-located, deltaX = 309, deltaY = 517, maxDist = 5.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 809727, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83259, tnet num: 18904, tinst num: 7373, tnode num: 106310, tedge num: 139503.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.088084s wall, 2.078125s user + 0.000000s system = 2.078125s CPU (99.5%)
+
+RUN-1004 : used memory is 670 MB, reserved memory is 687 MB, peak memory is 776 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4801/19082.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 975472, over cnt = 3218(9%), over = 5124, worst = 8
+PHY-1002 : len = 991408, over cnt = 2049(5%), over = 2955, worst = 7
+PHY-1002 : len = 1.02046e+06, over cnt = 667(1%), over = 891, worst = 7
+PHY-1002 : len = 1.0325e+06, over cnt = 124(0%), over = 156, worst = 6
+PHY-1002 : len = 1.03536e+06, over cnt = 25(0%), over = 32, worst = 3
+PHY-1001 : End global iterations; 2.337359s wall, 3.328125s user + 0.031250s system = 3.359375s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 58.43, top5 = 53.33, top10 = 50.55, top15 = 48.60.
+PHY-1001 : End incremental global routing; 2.764918s wall, 3.765625s user + 0.031250s system = 3.796875s CPU (137.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18904 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.972912s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (99.6%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7279 has valid locations, 33 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 813510
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17340/19112.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04039e+06, over cnt = 133(0%), over = 160, worst = 5
+PHY-1002 : len = 1.04072e+06, over cnt = 77(0%), over = 87, worst = 4
+PHY-1002 : len = 1.0411e+06, over cnt = 36(0%), over = 38, worst = 2
+PHY-1002 : len = 1.04133e+06, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 1.04189e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.897927s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 59.20, top5 = 53.67, top10 = 50.86, top15 = 48.91.
+PHY-3001 : End congestion estimation; 1.249452s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (106.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83485, tnet num: 18934, tinst num: 7400, tnode num: 106587, tedge num: 139795.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.015824s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (100.0%)
+
+RUN-1004 : used memory is 706 MB, reserved memory is 713 MB, peak memory is 782 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18934 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.349365s wall, 3.343750s user + 0.015625s system = 3.359375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(292): len = 812630, overlap = 0
+PHY-3002 : Step(293): len = 812101, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17328/19112.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03921e+06, over cnt = 83(0%), over = 108, worst = 7
+PHY-1002 : len = 1.03911e+06, over cnt = 58(0%), over = 59, worst = 2
+PHY-1002 : len = 1.03957e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.03962e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.03969e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.917213s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (103.9%)
+
+PHY-1001 : Congestion index: top1 = 58.88, top5 = 53.52, top10 = 50.76, top15 = 48.79.
+PHY-3001 : End congestion estimation; 1.270202s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (102.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18934 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.987380s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000204557
+PHY-3002 : Step(294): len = 812143, overlap = 2.75
+PHY-3002 : Step(295): len = 812008, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005645s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (276.8%)
+
+PHY-3001 : Legalized: Len = 811980, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067876s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (115.1%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 1.
+PHY-3001 : Final: Len = 812230, Over = 0
+PHY-3001 : End incremental placement; 7.391686s wall, 7.546875s user + 0.046875s system = 7.593750s CPU (102.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.880664s wall, 13.015625s user + 0.093750s system = 13.109375s CPU (110.3%)
+
+OPT-1001 : Current memory(MB): used = 780, reserve = 780, peak = 796.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17284/19112.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03935e+06, over cnt = 99(0%), over = 126, worst = 6
+PHY-1002 : len = 1.0396e+06, over cnt = 49(0%), over = 52, worst = 2
+PHY-1002 : len = 1.04011e+06, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 1.04019e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.725216s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 58.34, top5 = 53.34, top10 = 50.55, top15 = 48.66.
+OPT-1001 : End congestion update; 1.072400s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (103.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18934 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.819434s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.2%)
+
+OPT-0007 : Start: WNS -4156 TNS -2266574 NUM_FEPS 992
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 812357, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066470s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.0%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 13, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 813049, Over = 0
+PHY-3001 : End incremental legalization; 0.436460s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (100.2%)
+
+OPT-0007 : Iter 1: improved WNS -3806 TNS -2248219 NUM_FEPS 992 with 54 cells processed and 6497 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813141, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065069s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.1%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 4, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 813231, Over = 0
+PHY-3001 : End incremental legalization; 0.462439s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.4%)
+
+OPT-0007 : Iter 2: improved WNS -3766 TNS -2243223 NUM_FEPS 992 with 22 cells processed and 2296 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813085, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064079s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.5%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 1, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 813271, Over = 0
+PHY-3001 : End incremental legalization; 0.421306s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.1%)
+
+OPT-0007 : Iter 3: improved WNS -3753 TNS -2243587 NUM_FEPS 992 with 21 cells processed and 2150 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7312 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7400 instances, 7251 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3692 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813211, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063494s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.4%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 813231, Over = 0
+PHY-3001 : End incremental legalization; 0.419292s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (96.9%)
+
+OPT-0007 : Iter 4: improved WNS -3753 TNS -2242602 NUM_FEPS 992 with 14 cells processed and 868 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7318 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7406 instances, 7257 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 813803, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064671s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.6%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 813843, Over = 0
+PHY-3001 : End incremental legalization; 0.465556s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.7%)
+
+OPT-0007 : Iter 5: improved WNS -3753 TNS -2240778 NUM_FEPS 992 with 6 cells processed and 608 slack improved
+OPT-1001 : End bottleneck based optimization; 5.024774s wall, 5.281250s user + 0.031250s system = 5.312500s CPU (105.7%)
+
+OPT-1001 : Current memory(MB): used = 783, reserve = 784, peak = 796.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16914/19113.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04082e+06, over cnt = 474(1%), over = 597, worst = 5
+PHY-1002 : len = 1.04093e+06, over cnt = 256(0%), over = 289, worst = 5
+PHY-1002 : len = 1.04261e+06, over cnt = 107(0%), over = 122, worst = 5
+PHY-1002 : len = 1.04409e+06, over cnt = 36(0%), over = 36, worst = 1
+PHY-1002 : len = 1.04518e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.993358s wall, 1.218750s user + 0.062500s system = 1.281250s CPU (129.0%)
+
+PHY-1001 : Congestion index: top1 = 59.20, top5 = 53.44, top10 = 50.62, top15 = 48.81.
+OPT-1001 : End congestion update; 1.352388s wall, 1.562500s user + 0.062500s system = 1.625000s CPU (120.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.870269s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (97.0%)
+
+OPT-0007 : Start: WNS -3753 TNS -2242765 NUM_FEPS 992
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7318 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7406 instances, 7257 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 814251, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065743s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.1%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 6, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 814377, Over = 0
+PHY-3001 : End incremental legalization; 0.451224s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (124.7%)
+
+OPT-0007 : Iter 1: improved WNS -3753 TNS -2251081 NUM_FEPS 992 with 32 cells processed and 2298 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7318 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7406 instances, 7257 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3694 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 79%
+PHY-3001 : Initial: Len = 814977, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064044s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.6%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 814989, Over = 0
+PHY-3001 : End incremental legalization; 0.418242s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
+
+OPT-0007 : Iter 2: improved WNS -3753 TNS -2250970 NUM_FEPS 992 with 15 cells processed and 874 slack improved
+OPT-0007 : Iter 3: improved WNS -3753 TNS -2250970 NUM_FEPS 992 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.415367s wall, 3.921875s user + 0.062500s system = 3.984375s CPU (116.7%)
+
+OPT-1001 : Current memory(MB): used = 784, reserve = 784, peak = 796.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.814078s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 17131/19113.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04545e+06, over cnt = 167(0%), over = 200, worst = 4
+PHY-1002 : len = 1.04557e+06, over cnt = 118(0%), over = 131, worst = 4
+PHY-1002 : len = 1.04638e+06, over cnt = 58(0%), over = 58, worst = 1
+PHY-1002 : len = 1.04706e+06, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 1.0477e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.929287s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (107.6%)
+
+PHY-1001 : Congestion index: top1 = 59.12, top5 = 53.53, top10 = 50.70, top15 = 48.88.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.813713s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -3753 TNS -2252041 NUM_FEPS 992
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 58.724138
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -3753ps with logic level 5
+RUN-1001 : #2 path slack -3753ps with logic level 5
+RUN-1001 : #3 path slack -3716ps with logic level 5
+RUN-1001 : #4 path slack -3716ps with logic level 5
+RUN-1001 : #5 path slack -3663ps with logic level 5
+RUN-1001 : #6 path slack -3656ps with logic level 5
+RUN-1001 : #7 path slack -3656ps with logic level 5
+RUN-1001 : 0 HFN exist on timing critical paths out of 19113 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 19113 nets
+OPT-1001 : End physical optimization; 25.774732s wall, 27.796875s user + 0.203125s system = 28.000000s CPU (108.6%)
+
+RUN-1003 : finish command "place" in 77.570824s wall, 115.125000s user + 6.453125s system = 121.578125s CPU (156.7%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 639 MB, peak memory is 796 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.818575s wall, 3.046875s user + 0.000000s system = 3.046875s CPU (167.5%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 640 MB, peak memory is 796 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7408 instances
+RUN-1001 : 3630 mslices, 3627 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 19113 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10116 nets have 2 pins
+RUN-1001 : 7045 nets have [3 - 5] pins
+RUN-1001 : 972 nets have [6 - 10] pins
+RUN-1001 : 502 nets have [11 - 20] pins
+RUN-1001 : 449 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83563, tnet num: 18935, tinst num: 7406, tnode num: 106684, tedge num: 139888.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.747127s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.2%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 627 MB, peak memory is 796 MB
+PHY-1001 : 3630 mslices, 3627 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 950792, over cnt = 3409(9%), over = 5669, worst = 7
+PHY-1002 : len = 974488, over cnt = 2139(6%), over = 3048, worst = 6
+PHY-1002 : len = 998936, over cnt = 935(2%), over = 1246, worst = 6
+PHY-1002 : len = 1.0214e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.02206e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.330760s wall, 4.531250s user + 0.000000s system = 4.531250s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 58.43, top5 = 53.18, top10 = 50.42, top15 = 48.51.
+PHY-1001 : End global routing; 3.695665s wall, 4.890625s user + 0.000000s system = 4.890625s CPU (132.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 761, reserve = 772, peak = 796.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1041, peak = 1033.
+PHY-1001 : End build detailed router design. 4.080318s wall, 3.984375s user + 0.078125s system = 4.062500s CPU (99.6%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 275624, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.272596s wall, 6.109375s user + 0.015625s system = 6.125000s CPU (97.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 275680, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.541416s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (98.1%)
+
+PHY-1001 : Current memory(MB): used = 1068, reserve = 1078, peak = 1068.
+PHY-1001 : End phase 1; 6.827475s wall, 6.656250s user + 0.015625s system = 6.671875s CPU (97.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 35% nets.
+PHY-1001 : Routed 41% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.71183e+06, over cnt = 2676(0%), over = 2694, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1093, reserve = 1102, peak = 1093.
+PHY-1001 : End initial routed; 43.091866s wall, 82.796875s user + 0.406250s system = 83.203125s CPU (193.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2866/18035(15%) critical/total net(s).
+RUN-1001 : -----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : -----------------------------------------
+RUN-1001 : Setup | -5.978 | -3462.099 | 1005
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : -----------------------------------------
+PHY-1001 : End update timing; 3.728010s wall, 3.703125s user + 0.000000s system = 3.703125s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1113, reserve = 1122, peak = 1113.
+PHY-1001 : End phase 2; 46.819947s wall, 86.500000s user + 0.406250s system = 86.906250s CPU (185.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 89 pins with SWNS -5.823ns STNS -3448.352ns FEP 1005.
+PHY-1001 : End OPT Iter 1; 0.515185s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (100.1%)
+
+PHY-1022 : len = 2.71238e+06, over cnt = 2734(0%), over = 2752, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.861410s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.65791e+06, over cnt = 1044(0%), over = 1048, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.956011s wall, 5.046875s user + 0.000000s system = 5.046875s CPU (170.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.64962e+06, over cnt = 289(0%), over = 289, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.574175s wall, 2.015625s user + 0.015625s system = 2.031250s CPU (129.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.65068e+06, over cnt = 43(0%), over = 43, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.737618s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (116.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.6512e+06, over cnt = 15(0%), over = 15, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.396322s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.6515e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.524326s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (98.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.65155e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.477972s wall, 0.484375s user + 0.031250s system = 0.515625s CPU (107.9%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.65154e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.809334s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.65157e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.209797s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.3%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.65156e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.229985s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2866/18035(15%) critical/total net(s).
+RUN-1001 : -----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : -----------------------------------------
+RUN-1001 : Setup | -5.921 | -3455.020 | 1005
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : -----------------------------------------
+PHY-1001 : End update timing; 3.641954s wall, 3.609375s user + 0.031250s system = 3.640625s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 929 feed throughs used by 671 nets
+PHY-1001 : End commit to database; 2.566981s wall, 2.531250s user + 0.031250s system = 2.562500s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1211, reserve = 1223, peak = 1211.
+PHY-1001 : End phase 3; 15.419334s wall, 18.015625s user + 0.109375s system = 18.125000s CPU (117.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 32 pins with SWNS -5.783ns STNS -3450.347ns FEP 1005.
+PHY-1001 : End OPT Iter 1; 0.303511s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (97.8%)
+
+PHY-1022 : len = 2.65158e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.586743s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (98.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.783ns, -3450.347ns, 1005}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.65153e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.192624s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.65156e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.219147s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (85.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2866/18035(15%) critical/total net(s).
+RUN-1001 : -----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : -----------------------------------------
+RUN-1001 : Setup | -5.783 | -3454.874 | 1005
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : -----------------------------------------
+PHY-1001 : End update timing; 3.702363s wall, 3.656250s user + 0.015625s system = 3.671875s CPU (99.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 929 feed throughs used by 671 nets
+PHY-1001 : End commit to database; 2.716739s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (98.9%)
+
+PHY-1001 : Current memory(MB): used = 1222, reserve = 1235, peak = 1222.
+PHY-1001 : End phase 4; 7.470859s wall, 7.375000s user + 0.015625s system = 7.390625s CPU (98.9%)
+
+PHY-1003 : Routed, final wirelength = 2.65156e+06
+PHY-1001 : Current memory(MB): used = 1228, reserve = 1241, peak = 1228.
+PHY-1001 : End export database. 0.070381s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.0%)
+
+PHY-1001 : End detail routing; 81.118493s wall, 123.031250s user + 0.625000s system = 123.656250s CPU (152.4%)
+
+RUN-1003 : finish command "route" in 87.782837s wall, 130.843750s user + 0.671875s system = 131.515625s CPU (149.8%)
+
+RUN-1004 : used memory is 1127 MB, reserved memory is 1160 MB, peak memory is 1228 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 12131 out of 19600 61.89%
+#reg 9496 out of 19600 48.45%
+#le 13687
+ #lut only 4191 out of 13687 30.62%
+ #reg only 1556 out of 13687 11.37%
+ #lut® 7940 out of 13687 58.01%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1808
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1479
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1448
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 988
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 135
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 23
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/u_ADconfig/reg1_syn_159.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/reg2_syn_207.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P35 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P66 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P162 LVCMOS33 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P19 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P11 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P10 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |13687 |11104 |1027 |9527 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |533 |488 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |107 |96 |4 |95 |4 |0 |
+| U_crc16_24b |crc16_24b |28 |28 |0 |18 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |10 |0 |0 |
+| exdev_ctl_a |exdev_ctl |746 |436 |96 |566 |0 |0 |
+| u_ADconfig |AD_config |180 |110 |25 |138 |0 |0 |
+| u_gen_sp |gen_sp |257 |154 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |717 |460 |96 |534 |0 |0 |
+| u_ADconfig |AD_config |172 |137 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |251 |148 |71 |114 |0 |0 |
+| sampling_fe_a |sampling_fe |3467 |2922 |306 |2187 |25 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |180 |135 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_sort |sort |3251 |2763 |289 |2007 |25 |0 |
+| rddpram_ctl |rddpram_ctl |7 |4 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |4 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2804 |2386 |253 |1667 |22 |0 |
+| channelPart |channel_part_8478 |182 |171 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |68 |59 |9 |43 |0 |0 |
+| ram_switch |ram_switch |2245 |1907 |197 |1253 |0 |0 |
+| adc_addr_gen |adc_addr_gen |240 |212 |27 |122 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |28 |25 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |29 |26 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |11 |0 |0 |
+| insert |insert |1002 |704 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |1003 |991 |0 |452 |0 |0 |
+| read_ram_i |read_ram |259 |207 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |210 |170 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |46 |34 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |308 |253 |36 |247 |3 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |4073 |3455 |349 |2108 |25 |1 |
+| u0_soft_n |cdc_sync |8 |2 |0 |8 |0 |0 |
+| u_ad_sampling |ad_sampling |175 |138 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_sort |sort_rev |3865 |3298 |332 |1934 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |3470 |2966 |290 |1594 |22 |1 |
+| channelPart |channel_part_8478 |279 |271 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |2745 |2359 |197 |1170 |0 |0 |
+| adc_addr_gen |adc_addr_gen |252 |223 |27 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |8 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |30 |27 |3 |14 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |30 |27 |3 |11 |0 |0 |
+| insert |insert |999 |643 |170 |678 |0 |0 |
+| ram_switch_state |ram_switch_state |1494 |1493 |0 |377 |0 |0 |
+| read_ram_i |read_ram_rev |342 |249 |81 |199 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |210 |73 |158 |0 |0 |
+| read_ram_data |read_ram_data_rev |56 |39 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10054
+ #2 2 4922
+ #3 3 1396
+ #4 4 724
+ #5 5-10 1088
+ #6 11-50 798
+ #7 51-100 34
+ #8 >500 1
+ Average 3.09
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.251420s wall, 3.812500s user + 0.031250s system = 3.843750s CPU (170.7%)
+
+RUN-1004 : used memory is 1128 MB, reserved memory is 1162 MB, peak memory is 1228 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83563, tnet num: 18935, tinst num: 7406, tnode num: 106684, tedge num: 139888.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.758726s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (99.5%)
+
+RUN-1004 : used memory is 1134 MB, reserved memory is 1167 MB, peak memory is 1228 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18935 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.727413s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (98.6%)
+
+RUN-1004 : used memory is 1165 MB, reserved memory is 1191 MB, peak memory is 1228 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7406
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 19113, pip num: 198421
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 929
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3264 valid insts, and 549065 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 11.150752s wall, 71.531250s user + 0.296875s system = 71.828125s CPU (644.2%)
+
+RUN-1004 : used memory is 1276 MB, reserved memory is 1288 MB, peak memory is 1457 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_171944.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_172524.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_172524.log
new file mode 100644
index 0000000..26b15ef
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_172524.log
@@ -0,0 +1,3583 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 17:25:25 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.252092s wall, 2.093750s user + 0.125000s system = 2.218750s CPU (98.5%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 322 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 1.5000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -multiply_by 1.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 19021 instances
+RUN-0007 : 8696 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21599 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14249 nets have 2 pins
+RUN-1001 : 5919 nets have [3 - 5] pins
+RUN-1001 : 856 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 178 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 19019 instances, 8696 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5958 pins
+PHY-0007 : Cell area utilization is 55%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91022, tnet num: 21421, tinst num: 19019, tnode num: 121280, tedge num: 145932.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.180382s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (99.3%)
+
+RUN-1004 : used memory is 550 MB, reserved memory is 533 MB, peak memory is 550 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.069515s wall, 1.984375s user + 0.046875s system = 2.031250s CPU (98.2%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.28277e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 19019.
+PHY-3001 : Level 1 #clusters 2574.
+PHY-3001 : End clustering; 0.158561s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (108.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.4485e+06, overlap = 566.656
+PHY-3002 : Step(2): len = 1.12189e+06, overlap = 637.219
+PHY-3002 : Step(3): len = 881628, overlap = 734.469
+PHY-3002 : Step(4): len = 735949, overlap = 810.094
+PHY-3002 : Step(5): len = 568407, overlap = 919.781
+PHY-3002 : Step(6): len = 487470, overlap = 1003.03
+PHY-3002 : Step(7): len = 415227, overlap = 1076.34
+PHY-3002 : Step(8): len = 363495, overlap = 1160.97
+PHY-3002 : Step(9): len = 323796, overlap = 1200.09
+PHY-3002 : Step(10): len = 288381, overlap = 1261.81
+PHY-3002 : Step(11): len = 264025, overlap = 1349.38
+PHY-3002 : Step(12): len = 241741, overlap = 1394.84
+PHY-3002 : Step(13): len = 224367, overlap = 1425.56
+PHY-3002 : Step(14): len = 212975, overlap = 1469.81
+PHY-3002 : Step(15): len = 199377, overlap = 1498.16
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.26386e-07
+PHY-3002 : Step(16): len = 200806, overlap = 1453.78
+PHY-3002 : Step(17): len = 233214, overlap = 1355.97
+PHY-3002 : Step(18): len = 234017, overlap = 1288.47
+PHY-3002 : Step(19): len = 234417, overlap = 1223.22
+PHY-3002 : Step(20): len = 229368, overlap = 1182.78
+PHY-3002 : Step(21): len = 226416, overlap = 1194.44
+PHY-3002 : Step(22): len = 221279, overlap = 1162.38
+PHY-3002 : Step(23): len = 217002, overlap = 1154.84
+PHY-3002 : Step(24): len = 212535, overlap = 1142.22
+PHY-3002 : Step(25): len = 209512, overlap = 1143.56
+PHY-3002 : Step(26): len = 206685, overlap = 1131.41
+PHY-3002 : Step(27): len = 204126, overlap = 1142.53
+PHY-3002 : Step(28): len = 201794, overlap = 1145.16
+PHY-3002 : Step(29): len = 199662, overlap = 1145.84
+PHY-3002 : Step(30): len = 198210, overlap = 1145.91
+PHY-3002 : Step(31): len = 195796, overlap = 1140.91
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.85277e-06
+PHY-3002 : Step(32): len = 202732, overlap = 1101.44
+PHY-3002 : Step(33): len = 221192, overlap = 1078.56
+PHY-3002 : Step(34): len = 228961, overlap = 1050.59
+PHY-3002 : Step(35): len = 234282, overlap = 1029.03
+PHY-3002 : Step(36): len = 233958, overlap = 1013.75
+PHY-3002 : Step(37): len = 233561, overlap = 1011.06
+PHY-3002 : Step(38): len = 232011, overlap = 1001.03
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.70555e-06
+PHY-3002 : Step(39): len = 244543, overlap = 946
+PHY-3002 : Step(40): len = 264478, overlap = 895.5
+PHY-3002 : Step(41): len = 273695, overlap = 829.75
+PHY-3002 : Step(42): len = 276570, overlap = 791.156
+PHY-3002 : Step(43): len = 275409, overlap = 787.156
+PHY-3002 : Step(44): len = 275607, overlap = 782.75
+PHY-3002 : Step(45): len = 275279, overlap = 774.469
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.41109e-06
+PHY-3002 : Step(46): len = 294898, overlap = 710.125
+PHY-3002 : Step(47): len = 313067, overlap = 645.531
+PHY-3002 : Step(48): len = 321823, overlap = 613.781
+PHY-3002 : Step(49): len = 324869, overlap = 607.438
+PHY-3002 : Step(50): len = 321931, overlap = 607.25
+PHY-3002 : Step(51): len = 321510, overlap = 599.438
+PHY-3002 : Step(52): len = 320611, overlap = 600.719
+PHY-3002 : Step(53): len = 321270, overlap = 598.281
+PHY-3002 : Step(54): len = 321324, overlap = 594.75
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.48222e-05
+PHY-3002 : Step(55): len = 342878, overlap = 553.344
+PHY-3002 : Step(56): len = 360431, overlap = 513.188
+PHY-3002 : Step(57): len = 364608, overlap = 488.562
+PHY-3002 : Step(58): len = 366130, overlap = 468.312
+PHY-3002 : Step(59): len = 364739, overlap = 439.312
+PHY-3002 : Step(60): len = 365096, overlap = 422.062
+PHY-3002 : Step(61): len = 364851, overlap = 398.438
+PHY-3002 : Step(62): len = 365825, overlap = 378.281
+PHY-3002 : Step(63): len = 365862, overlap = 377.531
+PHY-3002 : Step(64): len = 366606, overlap = 384.281
+PHY-3002 : Step(65): len = 367423, overlap = 386.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.96444e-05
+PHY-3002 : Step(66): len = 386450, overlap = 356.406
+PHY-3002 : Step(67): len = 401634, overlap = 354.594
+PHY-3002 : Step(68): len = 403929, overlap = 372.812
+PHY-3002 : Step(69): len = 403600, overlap = 371.094
+PHY-3002 : Step(70): len = 403186, overlap = 368.75
+PHY-3002 : Step(71): len = 404602, overlap = 365.812
+PHY-3002 : Step(72): len = 403847, overlap = 347.562
+PHY-3002 : Step(73): len = 403892, overlap = 337
+PHY-3002 : Step(74): len = 404983, overlap = 332.969
+PHY-3002 : Step(75): len = 405111, overlap = 341.875
+PHY-3002 : Step(76): len = 404115, overlap = 346.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.92887e-05
+PHY-3002 : Step(77): len = 419164, overlap = 336.625
+PHY-3002 : Step(78): len = 429733, overlap = 322.531
+PHY-3002 : Step(79): len = 431600, overlap = 300.75
+PHY-3002 : Step(80): len = 433230, overlap = 289.5
+PHY-3002 : Step(81): len = 433688, overlap = 307.219
+PHY-3002 : Step(82): len = 434828, overlap = 290.906
+PHY-3002 : Step(83): len = 433055, overlap = 286.281
+PHY-3002 : Step(84): len = 433097, overlap = 292.219
+PHY-3002 : Step(85): len = 432909, overlap = 296.75
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000118577
+PHY-3002 : Step(86): len = 445151, overlap = 268.75
+PHY-3002 : Step(87): len = 454531, overlap = 263.188
+PHY-3002 : Step(88): len = 457666, overlap = 247.188
+PHY-3002 : Step(89): len = 460552, overlap = 247.031
+PHY-3002 : Step(90): len = 463689, overlap = 246.375
+PHY-3002 : Step(91): len = 467944, overlap = 247.188
+PHY-3002 : Step(92): len = 468379, overlap = 237.938
+PHY-3002 : Step(93): len = 468780, overlap = 230.469
+PHY-3002 : Step(94): len = 468313, overlap = 219.219
+PHY-3002 : Step(95): len = 468253, overlap = 220.562
+PHY-3002 : Step(96): len = 467017, overlap = 220.719
+PHY-3002 : Step(97): len = 466894, overlap = 217.031
+PHY-3002 : Step(98): len = 466935, overlap = 222.438
+PHY-3002 : Step(99): len = 468213, overlap = 214.406
+PHY-3002 : Step(100): len = 467751, overlap = 210.281
+PHY-3002 : Step(101): len = 468455, overlap = 208.562
+PHY-3002 : Step(102): len = 468313, overlap = 206.656
+PHY-3002 : Step(103): len = 469379, overlap = 204.188
+PHY-3002 : Step(104): len = 468591, overlap = 204.188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000237155
+PHY-3002 : Step(105): len = 474992, overlap = 204.812
+PHY-3002 : Step(106): len = 481119, overlap = 194.438
+PHY-3002 : Step(107): len = 482541, overlap = 173.875
+PHY-3002 : Step(108): len = 484191, overlap = 168.375
+PHY-3002 : Step(109): len = 486123, overlap = 169.094
+PHY-3002 : Step(110): len = 487818, overlap = 172.906
+PHY-3002 : Step(111): len = 486866, overlap = 185.438
+PHY-3002 : Step(112): len = 487105, overlap = 176.531
+PHY-3002 : Step(113): len = 488300, overlap = 176.469
+PHY-3002 : Step(114): len = 489011, overlap = 174.594
+PHY-3002 : Step(115): len = 487439, overlap = 176.75
+PHY-3002 : Step(116): len = 487373, overlap = 177.469
+PHY-3002 : Step(117): len = 487819, overlap = 180.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000454185
+PHY-3002 : Step(118): len = 493432, overlap = 182.406
+PHY-3002 : Step(119): len = 499972, overlap = 180.219
+PHY-3002 : Step(120): len = 500998, overlap = 180.531
+PHY-3002 : Step(121): len = 501872, overlap = 185.188
+PHY-3002 : Step(122): len = 502932, overlap = 183.031
+PHY-3002 : Step(123): len = 503617, overlap = 176.781
+PHY-3002 : Step(124): len = 503151, overlap = 179.375
+PHY-3002 : Step(125): len = 503283, overlap = 178.656
+PHY-3002 : Step(126): len = 503909, overlap = 169.062
+PHY-3002 : Step(127): len = 504586, overlap = 167.188
+PHY-3002 : Step(128): len = 504156, overlap = 175.031
+PHY-3002 : Step(129): len = 503993, overlap = 180.312
+PHY-3002 : Step(130): len = 504636, overlap = 171.406
+PHY-3002 : Step(131): len = 505361, overlap = 163.812
+PHY-3002 : Step(132): len = 505026, overlap = 173.156
+PHY-3002 : Step(133): len = 504774, overlap = 171.906
+PHY-3002 : Step(134): len = 504901, overlap = 162.938
+PHY-3002 : Step(135): len = 505520, overlap = 166.938
+PHY-3002 : Step(136): len = 504832, overlap = 173.844
+PHY-3002 : Step(137): len = 504602, overlap = 175.094
+PHY-3002 : Step(138): len = 504315, overlap = 174.281
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00081836
+PHY-3002 : Step(139): len = 507144, overlap = 176.469
+PHY-3002 : Step(140): len = 510585, overlap = 178.781
+PHY-3002 : Step(141): len = 511411, overlap = 180.438
+PHY-3002 : Step(142): len = 512072, overlap = 177.75
+PHY-3002 : Step(143): len = 513293, overlap = 168.281
+PHY-3002 : Step(144): len = 514847, overlap = 163.469
+PHY-3002 : Step(145): len = 515310, overlap = 156.531
+PHY-3002 : Step(146): len = 515518, overlap = 156.281
+PHY-3002 : Step(147): len = 515769, overlap = 157.594
+PHY-3002 : Step(148): len = 515843, overlap = 156.125
+PHY-3002 : Step(149): len = 515700, overlap = 151.094
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00132411
+PHY-3002 : Step(150): len = 516885, overlap = 151.312
+PHY-3002 : Step(151): len = 518926, overlap = 149.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012026s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (129.9%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 689160, over cnt = 1476(4%), over = 6572, worst = 27
+PHY-1001 : End global iterations; 0.805092s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (122.3%)
+
+PHY-1001 : Congestion index: top1 = 72.33, top5 = 57.50, top10 = 50.06, top15 = 45.11.
+PHY-3001 : End congestion estimation; 1.040335s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (118.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.901842s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.96552e-05
+PHY-3002 : Step(152): len = 620709, overlap = 121.094
+PHY-3002 : Step(153): len = 637860, overlap = 108.281
+PHY-3002 : Step(154): len = 622051, overlap = 108.062
+PHY-3002 : Step(155): len = 616692, overlap = 102.219
+PHY-3002 : Step(156): len = 608397, overlap = 102.844
+PHY-3002 : Step(157): len = 603804, overlap = 100.719
+PHY-3002 : Step(158): len = 602208, overlap = 97.9062
+PHY-3002 : Step(159): len = 595521, overlap = 94.4688
+PHY-3002 : Step(160): len = 595578, overlap = 90.75
+PHY-3002 : Step(161): len = 589958, overlap = 91.5938
+PHY-3002 : Step(162): len = 586887, overlap = 95.125
+PHY-3002 : Step(163): len = 584897, overlap = 93.6875
+PHY-3002 : Step(164): len = 582840, overlap = 92.25
+PHY-3002 : Step(165): len = 580515, overlap = 90.4688
+PHY-3002 : Step(166): len = 580096, overlap = 93.0312
+PHY-3002 : Step(167): len = 576531, overlap = 92.75
+PHY-3002 : Step(168): len = 574415, overlap = 92.9688
+PHY-3002 : Step(169): len = 573180, overlap = 89.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00013931
+PHY-3002 : Step(170): len = 571781, overlap = 89.4688
+PHY-3002 : Step(171): len = 574702, overlap = 87.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000245467
+PHY-3002 : Step(172): len = 579405, overlap = 87.4688
+PHY-3002 : Step(173): len = 585691, overlap = 83.125
+PHY-3002 : Step(174): len = 599644, overlap = 80.0938
+PHY-3002 : Step(175): len = 603214, overlap = 79.7188
+PHY-3002 : Step(176): len = 606815, overlap = 77.8438
+PHY-3002 : Step(177): len = 604766, overlap = 81.3438
+PHY-3002 : Step(178): len = 602782, overlap = 81.5625
+PHY-3002 : Step(179): len = 602723, overlap = 79.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 95/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 702168, over cnt = 2602(7%), over = 11190, worst = 43
+PHY-1001 : End global iterations; 1.544940s wall, 2.125000s user + 0.031250s system = 2.156250s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 83.28, top5 = 64.66, top10 = 56.86, top15 = 51.97.
+PHY-3001 : End congestion estimation; 1.838406s wall, 2.421875s user + 0.031250s system = 2.453125s CPU (133.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.004996s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.26072e-05
+PHY-3002 : Step(180): len = 600578, overlap = 401.719
+PHY-3002 : Step(181): len = 605210, overlap = 361.562
+PHY-3002 : Step(182): len = 598960, overlap = 351.75
+PHY-3002 : Step(183): len = 597242, overlap = 323.594
+PHY-3002 : Step(184): len = 597123, overlap = 291.938
+PHY-3002 : Step(185): len = 592246, overlap = 276.406
+PHY-3002 : Step(186): len = 589840, overlap = 263
+PHY-3002 : Step(187): len = 588419, overlap = 253.688
+PHY-3002 : Step(188): len = 585154, overlap = 256.375
+PHY-3002 : Step(189): len = 582571, overlap = 258.719
+PHY-3002 : Step(190): len = 580125, overlap = 259.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000145214
+PHY-3002 : Step(191): len = 580080, overlap = 253.094
+PHY-3002 : Step(192): len = 581221, overlap = 251.562
+PHY-3002 : Step(193): len = 584815, overlap = 245.188
+PHY-3002 : Step(194): len = 587956, overlap = 239.688
+PHY-3002 : Step(195): len = 588476, overlap = 232.844
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000290429
+PHY-3002 : Step(196): len = 591395, overlap = 224.219
+PHY-3002 : Step(197): len = 593589, overlap = 220.625
+PHY-3002 : Step(198): len = 597211, overlap = 213.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000521736
+PHY-3002 : Step(199): len = 603673, overlap = 199.281
+PHY-3002 : Step(200): len = 607444, overlap = 192.5
+PHY-3002 : Step(201): len = 612216, overlap = 181.969
+PHY-3002 : Step(202): len = 616195, overlap = 170.812
+PHY-3002 : Step(203): len = 618573, overlap = 164.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00101881
+PHY-3002 : Step(204): len = 620495, overlap = 166.812
+PHY-3002 : Step(205): len = 624208, overlap = 162.719
+PHY-3002 : Step(206): len = 628927, overlap = 158.375
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91022, tnet num: 21421, tinst num: 19019, tnode num: 121280, tedge num: 145932.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.491196s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (99.5%)
+
+RUN-1004 : used memory is 592 MB, reserved memory is 580 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 592.31 peak overflow 4.56
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 736/21599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751024, over cnt = 3276(9%), over = 12329, worst = 31
+PHY-1001 : End global iterations; 1.301063s wall, 1.968750s user + 0.078125s system = 2.046875s CPU (157.3%)
+
+PHY-1001 : Congestion index: top1 = 73.73, top5 = 61.67, top10 = 55.55, top15 = 51.55.
+PHY-1001 : End incremental global routing; 1.649373s wall, 2.328125s user + 0.078125s system = 2.406250s CPU (145.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.353106s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (99.3%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18890 has valid locations, 372 needs to be replaced
+PHY-3001 : design contains 19347 instances, 8782 luts, 9344 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6091 pins
+PHY-3001 : Found 1257 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 660471
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17435/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 769144, over cnt = 3328(9%), over = 12513, worst = 31
+PHY-1001 : End global iterations; 0.266189s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (117.4%)
+
+PHY-1001 : Congestion index: top1 = 73.97, top5 = 61.94, top10 = 55.96, top15 = 52.06.
+PHY-3001 : End congestion estimation; 0.527690s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (109.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 92351, tnet num: 21749, tinst num: 19347, tnode num: 123349, tedge num: 147934.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.544365s wall, 1.453125s user + 0.093750s system = 1.546875s CPU (100.2%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 647 MB, peak memory is 744 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.948539s wall, 2.828125s user + 0.125000s system = 2.953125s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(207): len = 658836, overlap = 0.5
+PHY-3002 : Step(208): len = 658996, overlap = 0.4375
+PHY-3002 : Step(209): len = 658487, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17507/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765752, over cnt = 3336(9%), over = 12559, worst = 31
+PHY-1001 : End global iterations; 0.260356s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (132.0%)
+
+PHY-1001 : Congestion index: top1 = 73.86, top5 = 62.35, top10 = 56.25, top15 = 52.21.
+PHY-3001 : End congestion estimation; 0.529001s wall, 0.593750s user + 0.015625s system = 0.609375s CPU (115.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.994219s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000297372
+PHY-3002 : Step(210): len = 658705, overlap = 161.594
+PHY-3002 : Step(211): len = 659387, overlap = 161.406
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000594743
+PHY-3002 : Step(212): len = 659567, overlap = 161.625
+PHY-3002 : Step(213): len = 660376, overlap = 162
+PHY-3001 : Final: Len = 660376, Over = 162
+PHY-3001 : End incremental placement; 5.722688s wall, 5.781250s user + 0.312500s system = 6.093750s CPU (106.5%)
+
+OPT-1001 : Total overflow 599.34 peak overflow 4.56
+OPT-1001 : End high-fanout net optimization; 9.349109s wall, 10.140625s user + 0.406250s system = 10.546875s CPU (112.8%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 741, peak = 765.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17474/21927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 771616, over cnt = 3286(9%), over = 11181, worst = 31
+PHY-1002 : len = 826312, over cnt = 2536(7%), over = 6566, worst = 22
+PHY-1002 : len = 876400, over cnt = 1423(4%), over = 3327, worst = 22
+PHY-1002 : len = 906064, over cnt = 716(2%), over = 1698, worst = 22
+PHY-1002 : len = 936280, over cnt = 29(0%), over = 70, worst = 13
+PHY-1001 : End global iterations; 2.475996s wall, 3.078125s user + 0.000000s system = 3.078125s CPU (124.3%)
+
+PHY-1001 : Congestion index: top1 = 62.26, top5 = 55.05, top10 = 51.17, top15 = 48.80.
+OPT-1001 : End congestion update; 2.767202s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (122.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.857455s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.4%)
+
+OPT-0007 : Start: WNS -4701 TNS -2426099 NUM_FEPS 1065
+OPT-0007 : Iter 1: improved WNS -4085 TNS -2402519 NUM_FEPS 1065 with 71 cells processed and 3658 slack improved
+OPT-0007 : Iter 2: improved WNS -4085 TNS -2397167 NUM_FEPS 1065 with 66 cells processed and 2432 slack improved
+OPT-0007 : Iter 3: improved WNS -4085 TNS -2395719 NUM_FEPS 1065 with 41 cells processed and 1850 slack improved
+OPT-0007 : Iter 4: improved WNS -4085 TNS -2394519 NUM_FEPS 1065 with 53 cells processed and 1016 slack improved
+OPT-0007 : Iter 5: improved WNS -4085 TNS -2393801 NUM_FEPS 1065 with 19 cells processed and 400 slack improved
+OPT-0007 : Iter 6: improved WNS -4085 TNS -2389079 NUM_FEPS 1065 with 2 cells processed and 268 slack improved
+OPT-1001 : End bottleneck based optimization; 4.404657s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (113.5%)
+
+OPT-1001 : Current memory(MB): used = 724, reserve = 724, peak = 765.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17616/21929.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 936504, over cnt = 342(0%), over = 492, worst = 13
+PHY-1002 : len = 935320, over cnt = 213(0%), over = 244, worst = 4
+PHY-1002 : len = 936232, over cnt = 105(0%), over = 117, worst = 3
+PHY-1002 : len = 937728, over cnt = 27(0%), over = 33, worst = 3
+PHY-1002 : len = 939128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.884591s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (109.5%)
+
+PHY-1001 : Congestion index: top1 = 61.88, top5 = 54.63, top10 = 50.95, top15 = 48.65.
+OPT-1001 : End congestion update; 1.177217s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (107.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21751 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.907556s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.9%)
+
+OPT-0007 : Start: WNS -4085 TNS -2389079 NUM_FEPS 1065
+OPT-0007 : Iter 1: improved WNS -4085 TNS -2387363 NUM_FEPS 1065 with 36 cells processed and 2248 slack improved
+OPT-0007 : Iter 2: improved WNS -4085 TNS -2387363 NUM_FEPS 1065 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.233584s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (103.5%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 726, peak = 765.
+OPT-1001 : End physical optimization; 17.801622s wall, 19.296875s user + 0.484375s system = 19.781250s CPU (111.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8782 LUT to BLE ...
+SYN-4008 : Packed 8782 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6211 remaining SEQ's ...
+SYN-4005 : Packed 4456 SEQ with LUT/SLICE
+SYN-4006 : 1483 single LUT's are left
+SYN-4006 : 1755 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10537/14392 primitive instances ...
+PHY-3001 : End packing; 1.827725s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7339 instances
+RUN-1001 : 3595 mslices, 3596 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18923 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10441 nets have 2 pins
+RUN-1001 : 6583 nets have [3 - 5] pins
+RUN-1001 : 943 nets have [6 - 10] pins
+RUN-1001 : 508 nets have [11 - 20] pins
+RUN-1001 : 417 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7337 instances, 7191 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3642 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 670132, Over = 367
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7934/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862104, over cnt = 2360(6%), over = 4005, worst = 10
+PHY-1002 : len = 873848, over cnt = 1492(4%), over = 2145, worst = 10
+PHY-1002 : len = 893312, over cnt = 518(1%), over = 660, worst = 6
+PHY-1002 : len = 898488, over cnt = 303(0%), over = 395, worst = 4
+PHY-1002 : len = 905544, over cnt = 44(0%), over = 47, worst = 2
+PHY-1001 : End global iterations; 2.056881s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 60.32, top5 = 54.16, top10 = 50.47, top15 = 47.91.
+PHY-3001 : End congestion estimation; 2.474069s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (131.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81628, tnet num: 18745, tinst num: 7337, tnode num: 104650, tedge num: 136867.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.747699s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (100.1%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 649 MB, peak memory is 765 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.698478s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.36756e-05
+PHY-3002 : Step(214): len = 654550, overlap = 365.75
+PHY-3002 : Step(215): len = 645611, overlap = 373.75
+PHY-3002 : Step(216): len = 640490, overlap = 384.25
+PHY-3002 : Step(217): len = 637727, overlap = 401.5
+PHY-3002 : Step(218): len = 635494, overlap = 408.25
+PHY-3002 : Step(219): len = 633661, overlap = 405.75
+PHY-3002 : Step(220): len = 631479, overlap = 401
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.73511e-05
+PHY-3002 : Step(221): len = 635058, overlap = 396.5
+PHY-3002 : Step(222): len = 641000, overlap = 384
+PHY-3002 : Step(223): len = 640929, overlap = 386
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000174702
+PHY-3002 : Step(224): len = 649621, overlap = 366
+PHY-3002 : Step(225): len = 655408, overlap = 359.5
+PHY-3002 : Step(226): len = 655175, overlap = 353
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000344773
+PHY-3002 : Step(227): len = 664072, overlap = 342
+PHY-3002 : Step(228): len = 675612, overlap = 330.25
+PHY-3002 : Step(229): len = 676018, overlap = 321
+PHY-3002 : Step(230): len = 676352, overlap = 315
+PHY-3002 : Step(231): len = 678024, overlap = 313.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000578724
+PHY-3002 : Step(232): len = 682318, overlap = 306.25
+PHY-3002 : Step(233): len = 685042, overlap = 298.75
+PHY-3002 : Step(234): len = 690118, overlap = 291.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00115616
+PHY-3002 : Step(235): len = 692400, overlap = 289.75
+PHY-3002 : Step(236): len = 699535, overlap = 279.25
+PHY-3002 : Step(237): len = 708272, overlap = 270.5
+PHY-3002 : Step(238): len = 709642, overlap = 269.25
+PHY-3002 : Step(239): len = 710674, overlap = 260.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.384065s wall, 0.390625s user + 0.531250s system = 0.921875s CPU (240.0%)
+
+PHY-3001 : Trial Legalized: Len = 797754
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 765/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942360, over cnt = 3304(9%), over = 5508, worst = 8
+PHY-1002 : len = 960464, over cnt = 2210(6%), over = 3329, worst = 8
+PHY-1002 : len = 987424, over cnt = 998(2%), over = 1441, worst = 6
+PHY-1002 : len = 1.00032e+06, over cnt = 488(1%), over = 748, worst = 6
+PHY-1002 : len = 1.01297e+06, over cnt = 18(0%), over = 28, worst = 3
+PHY-1001 : End global iterations; 2.800029s wall, 4.062500s user + 0.000000s system = 4.062500s CPU (145.1%)
+
+PHY-1001 : Congestion index: top1 = 60.95, top5 = 54.84, top10 = 51.48, top15 = 49.31.
+PHY-3001 : End congestion estimation; 3.303452s wall, 4.546875s user + 0.015625s system = 4.562500s CPU (138.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.030032s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000216673
+PHY-3002 : Step(240): len = 751778, overlap = 89.25
+PHY-3002 : Step(241): len = 728443, overlap = 142.25
+PHY-3002 : Step(242): len = 710080, overlap = 200.5
+PHY-3002 : Step(243): len = 698874, overlap = 236.25
+PHY-3002 : Step(244): len = 693056, overlap = 251.5
+PHY-3002 : Step(245): len = 688214, overlap = 268.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000433346
+PHY-3002 : Step(246): len = 691584, overlap = 261.5
+PHY-3002 : Step(247): len = 694145, overlap = 257.25
+PHY-3002 : Step(248): len = 695772, overlap = 250.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00083788
+PHY-3002 : Step(249): len = 698784, overlap = 245
+PHY-3002 : Step(250): len = 704555, overlap = 244
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00156457
+PHY-3002 : Step(251): len = 705975, overlap = 243.25
+PHY-3002 : Step(252): len = 712925, overlap = 240.25
+PHY-3002 : Step(253): len = 717257, overlap = 232.5
+PHY-3002 : Step(254): len = 718373, overlap = 231.5
+PHY-3002 : Step(255): len = 720473, overlap = 228
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034052s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (91.8%)
+
+PHY-3001 : Legalized: Len = 759105, Over = 0
+PHY-3001 : Spreading special nets. 561 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.130863s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.5%)
+
+PHY-3001 : 865 instances has been re-located, deltaX = 320, deltaY = 527, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 773592, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81628, tnet num: 18745, tinst num: 7340, tnode num: 104650, tedge num: 136867.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.006078s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (99.7%)
+
+RUN-1004 : used memory is 665 MB, reserved memory is 677 MB, peak memory is 766 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4791/18923.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 933560, over cnt = 2984(8%), over = 4773, worst = 7
+PHY-1002 : len = 949832, over cnt = 1841(5%), over = 2634, worst = 7
+PHY-1002 : len = 976648, over cnt = 541(1%), over = 710, worst = 7
+PHY-1002 : len = 985288, over cnt = 97(0%), over = 109, worst = 3
+PHY-1002 : len = 988288, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.401255s wall, 3.453125s user + 0.031250s system = 3.484375s CPU (145.1%)
+
+PHY-1001 : Congestion index: top1 = 60.11, top5 = 54.01, top10 = 50.60, top15 = 48.38.
+PHY-1001 : End incremental global routing; 2.806498s wall, 3.843750s user + 0.031250s system = 3.875000s CPU (138.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18745 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.992107s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (97.6%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7248 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 778234
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17164/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994648, over cnt = 94(0%), over = 127, worst = 9
+PHY-1002 : len = 994736, over cnt = 53(0%), over = 64, worst = 4
+PHY-1002 : len = 995120, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 995376, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 995584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.890471s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 60.34, top5 = 54.31, top10 = 50.87, top15 = 48.62.
+PHY-3001 : End congestion estimation; 1.237672s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (102.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81832, tnet num: 18764, tinst num: 7359, tnode num: 104896, tedge num: 137120.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.996638s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.2%)
+
+RUN-1004 : used memory is 699 MB, reserved memory is 704 MB, peak memory is 776 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.967186s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(256): len = 776902, overlap = 0
+PHY-3002 : Step(257): len = 776309, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17148/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992440, over cnt = 83(0%), over = 117, worst = 6
+PHY-1002 : len = 992584, over cnt = 48(0%), over = 58, worst = 4
+PHY-1002 : len = 992872, over cnt = 18(0%), over = 20, worst = 2
+PHY-1002 : len = 993376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.655445s wall, 0.687500s user + 0.031250s system = 0.718750s CPU (109.7%)
+
+PHY-1001 : Congestion index: top1 = 60.22, top5 = 54.05, top10 = 50.71, top15 = 48.49.
+PHY-3001 : End congestion estimation; 1.307661s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (82.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.950583s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000792542
+PHY-3002 : Step(258): len = 776138, overlap = 2.25
+PHY-3002 : Step(259): len = 776274, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005372s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 776293, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064295s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 2, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 776361, Over = 0
+PHY-3001 : End incremental placement; 7.032055s wall, 6.734375s user + 0.140625s system = 6.875000s CPU (97.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.382611s wall, 12.078125s user + 0.187500s system = 12.265625s CPU (107.8%)
+
+OPT-1001 : Current memory(MB): used = 784, reserve = 787, peak = 788.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17110/18942.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992352, over cnt = 108(0%), over = 135, worst = 5
+PHY-1002 : len = 992648, over cnt = 45(0%), over = 47, worst = 2
+PHY-1002 : len = 992832, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 993120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.699205s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 60.41, top5 = 53.93, top10 = 50.62, top15 = 48.40.
+OPT-1001 : End congestion update; 1.054685s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18764 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.991916s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.2%)
+
+OPT-0007 : Start: WNS -4095 TNS -2245387 NUM_FEPS 981
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 776978, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066599s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.3%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 8, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 777278, Over = 0
+PHY-3001 : End incremental legalization; 0.429167s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.3%)
+
+OPT-0007 : Iter 1: improved WNS -4054 TNS -2232610 NUM_FEPS 981 with 48 cells processed and 5601 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777614, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069500s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (112.4%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 7, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 777740, Over = 0
+PHY-3001 : End incremental legalization; 0.436379s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (96.7%)
+
+OPT-0007 : Iter 2: improved WNS -4054 TNS -2231520 NUM_FEPS 981 with 19 cells processed and 1654 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777796, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064209s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.3%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 777908, Over = 0
+PHY-3001 : End incremental legalization; 0.424348s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%)
+
+OPT-0007 : Iter 3: improved WNS -4054 TNS -2230249 NUM_FEPS 981 with 10 cells processed and 1227 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777648, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068964s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.6%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 777984, Over = 0
+PHY-3001 : End incremental legalization; 0.485148s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (106.3%)
+
+OPT-0007 : Iter 4: improved WNS -4054 TNS -2227314 NUM_FEPS 981 with 13 cells processed and 853 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7271 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7359 instances, 7210 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3707 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 777984, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064506s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.9%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 7, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 777958, Over = 0
+PHY-3001 : End incremental legalization; 0.461997s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.5%)
+
+OPT-0007 : Iter 5: improved WNS -4054 TNS -2226157 NUM_FEPS 981 with 7 cells processed and 600 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 778240, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067534s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (115.7%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 778258, Over = 0
+PHY-3001 : End incremental legalization; 0.421041s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.2%)
+
+OPT-0007 : Iter 6: improved WNS -4054 TNS -2224669 NUM_FEPS 981 with 4 cells processed and 600 slack improved
+OPT-1001 : End bottleneck based optimization; 5.888708s wall, 6.140625s user + 0.015625s system = 6.156250s CPU (104.5%)
+
+OPT-1001 : Current memory(MB): used = 784, reserve = 787, peak = 788.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16775/18943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994048, over cnt = 439(1%), over = 545, worst = 4
+PHY-1002 : len = 993736, over cnt = 262(0%), over = 297, worst = 4
+PHY-1002 : len = 995448, over cnt = 95(0%), over = 100, worst = 4
+PHY-1002 : len = 996672, over cnt = 40(0%), over = 40, worst = 1
+PHY-1002 : len = 997968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.020685s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (107.2%)
+
+PHY-1001 : Congestion index: top1 = 60.54, top5 = 54.33, top10 = 50.89, top15 = 48.65.
+OPT-1001 : End congestion update; 1.366381s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (106.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.806288s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (98.8%)
+
+OPT-0007 : Start: WNS -4054 TNS -2228716 NUM_FEPS 981
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 778612, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065648s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 10, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 779012, Over = 0
+PHY-3001 : End incremental legalization; 0.423810s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.5%)
+
+OPT-0007 : Iter 1: improved WNS -4054 TNS -2228898 NUM_FEPS 981 with 37 cells processed and 3041 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 779124, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066601s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.8%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 779138, Over = 0
+PHY-3001 : End incremental legalization; 0.422938s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (121.9%)
+
+OPT-0007 : Iter 2: improved WNS -4054 TNS -2228471 NUM_FEPS 981 with 9 cells processed and 629 slack improved
+OPT-0007 : Iter 3: improved WNS -4054 TNS -2228471 NUM_FEPS 981 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.362194s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (105.0%)
+
+OPT-1001 : Current memory(MB): used = 784, reserve = 787, peak = 788.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.843102s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (96.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16976/18943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 997912, over cnt = 158(0%), over = 193, worst = 5
+PHY-1002 : len = 997656, over cnt = 117(0%), over = 135, worst = 5
+PHY-1002 : len = 998472, over cnt = 51(0%), over = 58, worst = 3
+PHY-1002 : len = 999064, over cnt = 19(0%), over = 22, worst = 2
+PHY-1002 : len = 999576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.950155s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (108.5%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.36, top10 = 50.93, top15 = 48.69.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.807197s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -4054 TNS -2229784 NUM_FEPS 981
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 60.413793
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -4054ps with logic level 5
+RUN-1001 : #2 path slack -3995ps with logic level 5
+RUN-1001 : 0 HFN exist on timing critical paths out of 18943 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18943 nets
+OPT-1001 : End physical optimization; 26.012542s wall, 27.281250s user + 0.218750s system = 27.500000s CPU (105.7%)
+
+RUN-1003 : finish command "place" in 74.601883s wall, 105.937500s user + 5.328125s system = 111.265625s CPU (149.1%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 654 MB, peak memory is 788 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.793872s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (173.3%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 655 MB, peak memory is 788 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 81872, tnet num: 18765, tinst num: 7363, tnode num: 104951, tedge num: 137171.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.760909s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (98.5%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 633 MB, peak memory is 788 MB
+PHY-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909224, over cnt = 3287(9%), over = 5337, worst = 7
+PHY-1002 : len = 930584, over cnt = 1989(5%), over = 2857, worst = 7
+PHY-1002 : len = 954544, over cnt = 840(2%), over = 1188, worst = 7
+PHY-1002 : len = 973984, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 974424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.459988s wall, 4.703125s user + 0.015625s system = 4.718750s CPU (136.4%)
+
+PHY-1001 : Congestion index: top1 = 59.35, top5 = 53.78, top10 = 50.28, top15 = 48.09.
+PHY-1001 : End global routing; 3.833864s wall, 5.093750s user + 0.015625s system = 5.109375s CPU (133.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 753, reserve = 762, peak = 788.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1029, reserve = 1036, peak = 1029.
+PHY-1001 : End build detailed router design. 4.110453s wall, 4.031250s user + 0.015625s system = 4.046875s CPU (98.5%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273664, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.155352s wall, 5.109375s user + 0.000000s system = 5.109375s CPU (99.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273720, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.530417s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1064, reserve = 1072, peak = 1064.
+PHY-1001 : End phase 1; 5.698681s wall, 5.640625s user + 0.000000s system = 5.640625s CPU (99.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 35% nets.
+PHY-1001 : Routed 42% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.58654e+06, over cnt = 2305(0%), over = 2324, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1088, reserve = 1093, peak = 1088.
+PHY-1001 : End initial routed; 33.620194s wall, 64.359375s user + 0.281250s system = 64.640625s CPU (192.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -6.182 | -3395.741 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.959569s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1092, reserve = 1096, peak = 1092.
+PHY-1001 : End phase 2; 37.579826s wall, 68.296875s user + 0.296875s system = 68.593750s CPU (182.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 63 pins with SWNS -6.050ns STNS -3390.015ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.504031s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (99.2%)
+
+PHY-1022 : len = 2.58686e+06, over cnt = 2360(0%), over = 2379, worst = 2, crit = 2
+PHY-1001 : End optimize timing; 0.839929s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (98.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53891e+06, over cnt = 952(0%), over = 954, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 4.074010s wall, 5.687500s user + 0.015625s system = 5.703125s CPU (140.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53486e+06, over cnt = 272(0%), over = 272, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.960299s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (141.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53452e+06, over cnt = 73(0%), over = 73, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 1.024042s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (114.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53546e+06, over cnt = 30(0%), over = 30, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.563629s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (116.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.5359e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.915266s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (109.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53593e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 1.315780s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.53582e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 2.401772s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.53584e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.230176s wall, 0.234375s user + 0.046875s system = 0.281250s CPU (122.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53583e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.262425s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.324320s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.317033s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.53588e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.492098s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.216909s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (93.6%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.270025s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (86.8%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.255221s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (110.2%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.258533s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.363144s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.442808s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.3%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.211906s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.222681s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.243432s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.256749s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.357795s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.455661s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.230377s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.204963s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.196553s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.283505s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (77.2%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.284205s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (88.0%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.365853s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.441686s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.400369s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.239247s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (98.3%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.199528s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.195252s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.256573s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.251919s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.358642s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.432209s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.223029s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.181830s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.219836s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.208207s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.221452s wall, 0.250000s user + 0.031250s system = 0.281250s CPU (127.0%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.241629s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.252660s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (92.8%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.386840s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.447126s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.291629s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.290651s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.241014s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.245839s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.214815s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (109.1%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.215221s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.239389s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.259928s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.375076s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.440304s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.260172s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.265901s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.250946s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.402546s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.248428s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (96.4%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.53592e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.205199s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (106.6%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.201584s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.247154s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (94.8%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.253339s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.375487s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.481460s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.248179s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.254307s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.307116s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.264673s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.406551s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.53589e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.250396s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (98.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -6.050 | -3394.643 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.881265s wall, 3.796875s user + 0.031250s system = 3.828125s CPU (98.6%)
+
+PHY-1001 : Current memory(MB): used = 1104, reserve = 1107, peak = 1104.
+PHY-1001 : End phase 3; 58.134394s wall, 60.265625s user + 0.156250s system = 60.421875s CPU (103.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 47 pins with SWNS -5.708ns STNS -3385.794ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.402350s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.0%)
+
+PHY-1022 : len = 2.53595e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.701711s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.708ns, -3385.794ns, 981}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53548e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.220744s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (106.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53548e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.262454s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (125.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.377485s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (91.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.530684s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.770814s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.204559s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (122.2%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.222967s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.254514s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.264043s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (112.4%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.420216s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 11 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.235132s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (113.0%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.311317s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (85.3%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.293173s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.279932s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (106.1%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.418365s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.523667s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (101.4%)
+
+PHY-1001 : ===== DR Iter 17 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.223433s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.267009s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (93.6%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.253766s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.274115s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.388286s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.463201s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 1.347887s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 24 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.230326s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.209676s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.290549s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (107.6%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.279348s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.398762s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.459271s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 1.291083s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 1.343828s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (97.7%)
+
+PHY-1001 : ===== DR Iter 32 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.239278s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.229816s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.322799s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.264778s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (118.0%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.346094s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (103.8%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.404520s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.168598s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 1.076001s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.030450s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 41 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.227059s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (89.5%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.201690s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.226439s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.234834s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (106.5%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.325350s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.367542s wall, 0.375000s user + 0.031250s system = 0.406250s CPU (110.5%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.088194s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.048448s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.077633s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.242589s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.6%)
+
+PHY-1001 : ===== DR Iter 51 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.197359s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.204352s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.233315s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.243679s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.342917s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.384014s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.041440s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.022307s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.183315s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.138088s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.092579s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (97.2%)
+
+PHY-1001 : ===== DR Iter 62 =====
+PHY-1022 : len = 2.53542e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.187958s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.185740s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.223163s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.228987s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.328711s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.389555s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.3%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.230990s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.073592s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.065808s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.030711s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.026555s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.111379s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.601826s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1108, reserve = 1111, peak = 1108.
+PHY-1001 : End phase 4; 44.029847s wall, 43.921875s user + 0.203125s system = 44.125000s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.53539e+06
+PHY-1001 : 916 feed throughs used by 648 nets
+PHY-1001 : Current memory(MB): used = 1216, reserve = 1223, peak = 1216.
+PHY-1001 : End export database. 2.640656s wall, 2.593750s user + 0.015625s system = 2.609375s CPU (98.8%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 13 2) is for feedthrough
+PHY-3001 : eco cells: (1 26 1) is for feedthrough
+PHY-3001 : eco cells: (1 30 3) is for feedthrough
+PHY-3001 : eco cells: (1 33 3) is for feedthrough
+PHY-3001 : eco cells: (2 2 0) is for feedthrough
+PHY-3001 : eco cells: (2 4 3) is for feedthrough
+PHY-3001 : eco cells: (2 6 0) is for feedthrough
+PHY-3001 : eco cells: (2 6 3) is for feedthrough
+PHY-3001 : eco cells: (2 12 1) is for feedthrough
+PHY-3001 : eco cells: (2 16 0) is for feedthrough
+PHY-3001 : eco cells: (2 24 3) is for feedthrough
+PHY-3001 : eco cells: (2 28 3) is for feedthrough
+PHY-3001 : eco cells: (2 32 0) is for feedthrough
+PHY-3001 : eco cells: (2 34 3) is for feedthrough
+PHY-3001 : eco cells: (2 39 3) is for feedthrough
+PHY-3001 : eco cells: (2 54 2) is for feedthrough
+PHY-3001 : eco cells: (2 68 1) is for feedthrough
+PHY-3001 : eco cells: (3 8 1) is for feedthrough
+PHY-3001 : eco cells: (3 8 3) is for feedthrough
+PHY-3001 : eco cells: (3 15 1) is for feedthrough
+PHY-3001 : eco cells: (3 16 1) is for feedthrough
+PHY-3001 : eco cells: (3 19 0) is for feedthrough
+PHY-3001 : eco cells: (3 22 3) is for feedthrough
+PHY-3001 : eco cells: (3 25 3) is for feedthrough
+PHY-3001 : eco cells: (3 28 3) is for feedthrough
+PHY-3001 : eco cells: (3 34 0) is for feedthrough
+PHY-3001 : eco cells: (3 34 1) is for feedthrough
+PHY-3001 : eco cells: (3 35 3) is for feedthrough
+PHY-3001 : eco cells: (4 8 1) is for feedthrough
+PHY-3001 : eco cells: (4 12 0) is for feedthrough
+PHY-3001 : eco cells: (4 12 2) is for feedthrough
+PHY-3001 : eco cells: (4 13 2) is for feedthrough
+PHY-3001 : eco cells: (4 14 0) is for feedthrough
+PHY-3001 : eco cells: (4 26 3) is for feedthrough
+PHY-3001 : eco cells: (4 30 1) is for feedthrough
+PHY-3001 : eco cells: (4 31 1) is for feedthrough
+PHY-3001 : eco cells: (4 31 2) is for feedthrough
+PHY-3001 : eco cells: (4 35 0) is for feedthrough
+PHY-3001 : eco cells: (4 45 0) is for feedthrough
+PHY-3001 : eco cells: (4 49 2) is for feedthrough
+PHY-3001 : eco cells: (4 53 2) is for feedthrough
+PHY-3001 : eco cells: (4 58 1) is for feedthrough
+PHY-3001 : eco cells: (4 59 0) is for feedthrough
+PHY-3001 : eco cells: (5 3 1) is for feedthrough
+PHY-3001 : eco cells: (5 4 0) is for feedthrough
+PHY-3001 : eco cells: (5 5 2) is for feedthrough
+PHY-3001 : eco cells: (5 5 3) is for feedthrough
+PHY-3001 : eco cells: (5 6 3) is for feedthrough
+PHY-3001 : eco cells: (5 9 0) is for feedthrough
+PHY-3001 : eco cells: (5 10 0) is for feedthrough
+PHY-3001 : eco cells: (5 12 3) is for feedthrough
+PHY-3001 : eco cells: (5 14 2) is for feedthrough
+PHY-3001 : eco cells: (5 15 2) is for feedthrough
+PHY-3001 : eco cells: (5 17 1) is for feedthrough
+PHY-3001 : eco cells: (5 18 0) is for feedthrough
+PHY-3001 : eco cells: (5 19 2) is for feedthrough
+PHY-3001 : eco cells: (5 20 2) is for feedthrough
+PHY-3001 : eco cells: (5 21 0) is for feedthrough
+PHY-3001 : eco cells: (5 29 1) is for feedthrough
+PHY-3001 : eco cells: (5 29 2) is for feedthrough
+PHY-3001 : eco cells: (5 31 0) is for feedthrough
+PHY-3001 : eco cells: (5 33 3) is for feedthrough
+PHY-3001 : eco cells: (5 35 2) is for feedthrough
+PHY-3001 : eco cells: (5 36 1) is for feedthrough
+PHY-3001 : eco cells: (5 36 2) is for feedthrough
+PHY-3001 : eco cells: (5 38 1) is for feedthrough
+PHY-3001 : eco cells: (5 51 3) is for feedthrough
+PHY-3001 : eco cells: (5 59 3) is for feedthrough
+PHY-3001 : eco cells: (5 63 0) is for feedthrough
+PHY-3001 : eco cells: (5 63 3) is for feedthrough
+PHY-3001 : eco cells: (5 66 2) is for feedthrough
+PHY-3001 : eco cells: (6 7 3) is for feedthrough
+PHY-3001 : eco cells: (6 11 3) is for feedthrough
+PHY-3001 : eco cells: (6 12 2) is for feedthrough
+PHY-3001 : eco cells: (6 13 2) is for feedthrough
+PHY-3001 : eco cells: (6 19 2) is for feedthrough
+PHY-3001 : eco cells: (6 20 2) is for feedthrough
+PHY-3001 : eco cells: (6 20 3) is for feedthrough
+PHY-3001 : eco cells: (6 29 0) is for feedthrough
+PHY-3001 : eco cells: (6 29 2) is for feedthrough
+PHY-3001 : eco cells: (6 33 2) is for feedthrough
+PHY-3001 : eco cells: (6 35 0) is for feedthrough
+PHY-3001 : eco cells: (6 36 3) is for feedthrough
+PHY-3001 : eco cells: (6 40 0) is for feedthrough
+PHY-3001 : eco cells: (6 44 3) is for feedthrough
+PHY-3001 : eco cells: (6 53 0) is for feedthrough
+PHY-3001 : eco cells: (6 55 3) is for feedthrough
+PHY-3001 : eco cells: (6 67 2) is for feedthrough
+PHY-3001 : eco cells: (6 68 3) is for feedthrough
+PHY-3001 : eco cells: (7 8 0) is for feedthrough
+PHY-3001 : eco cells: (7 9 0) is for feedthrough
+PHY-3001 : eco cells: (7 10 3) is for feedthrough
+PHY-3001 : eco cells: (7 11 0) is for feedthrough
+PHY-3001 : eco cells: (7 21 3) is for feedthrough
+PHY-3001 : eco cells: (7 28 2) is for feedthrough
+PHY-3001 : eco cells: (7 30 0) is for feedthrough
+PHY-3001 : eco cells: (7 31 0) is for feedthrough
+PHY-3001 : eco cells: (9 9 3) is for feedthrough
+PHY-3001 : eco cells: (9 10 0) is for feedthrough
+PHY-3001 : eco cells: (9 11 0) is for feedthrough
+PHY-3001 : eco cells: (9 11 1) is for feedthrough
+PHY-3001 : eco cells: (9 12 0) is for feedthrough
+PHY-3001 : eco cells: (9 13 2) is for feedthrough
+PHY-3001 : eco cells: (9 14 2) is for feedthrough
+PHY-3001 : eco cells: (9 17 0) is for feedthrough
+PHY-3001 : eco cells: (9 18 1) is for feedthrough
+PHY-3001 : eco cells: (9 22 1) is for feedthrough
+PHY-3001 : eco cells: (9 25 2) is for feedthrough
+PHY-3001 : eco cells: (9 26 1) is for feedthrough
+PHY-3001 : eco cells: (9 29 0) is for feedthrough
+PHY-3001 : eco cells: (9 29 2) is for feedthrough
+PHY-3001 : eco cells: (9 65 0) is for feedthrough
+PHY-3001 : eco cells: (9 69 2) is for feedthrough
+PHY-3001 : eco cells: (10 8 0) is for feedthrough
+PHY-3001 : eco cells: (10 11 1) is for feedthrough
+PHY-3001 : eco cells: (10 12 1) is for feedthrough
+PHY-3001 : eco cells: (10 13 1) is for feedthrough
+PHY-3001 : eco cells: (10 14 2) is for feedthrough
+PHY-3001 : eco cells: (10 16 1) is for feedthrough
+PHY-3001 : eco cells: (10 19 0) is for feedthrough
+PHY-3001 : eco cells: (10 22 1) is for feedthrough
+PHY-3001 : eco cells: (10 22 2) is for feedthrough
+PHY-3001 : eco cells: (10 24 3) is for feedthrough
+PHY-3001 : eco cells: (10 25 0) is for feedthrough
+PHY-3001 : eco cells: (10 27 0) is for feedthrough
+PHY-3001 : eco cells: (10 27 2) is for feedthrough
+PHY-3001 : eco cells: (10 36 3) is for feedthrough
+PHY-3001 : eco cells: (10 42 2) is for feedthrough
+PHY-3001 : eco cells: (10 58 3) is for feedthrough
+PHY-3001 : eco cells: (10 59 0) is for feedthrough
+PHY-3001 : eco cells: (10 63 2) is for feedthrough
+PHY-3001 : eco cells: (10 67 0) is for feedthrough
+PHY-3001 : eco cells: (11 7 0) is for feedthrough
+PHY-3001 : eco cells: (11 8 2) is for feedthrough
+PHY-3001 : eco cells: (11 9 0) is for feedthrough
+PHY-3001 : eco cells: (11 10 1) is for feedthrough
+PHY-3001 : eco cells: (11 11 0) is for feedthrough
+PHY-3001 : eco cells: (11 11 2) is for feedthrough
+PHY-3001 : eco cells: (11 12 0) is for feedthrough
+PHY-3001 : eco cells: (11 12 3) is for feedthrough
+PHY-3001 : eco cells: (11 13 3) is for feedthrough
+PHY-3001 : eco cells: (11 14 3) is for feedthrough
+PHY-3001 : eco cells: (11 15 0) is for feedthrough
+PHY-3001 : eco cells: (11 18 1) is for feedthrough
+PHY-3001 : eco cells: (11 21 2) is for feedthrough
+PHY-3001 : eco cells: (11 23 1) is for feedthrough
+PHY-3001 : eco cells: (11 24 0) is for feedthrough
+PHY-3001 : eco cells: (11 25 0) is for feedthrough
+PHY-3001 : eco cells: (11 25 2) is for feedthrough
+PHY-3001 : eco cells: (11 27 1) is for feedthrough
+PHY-3001 : eco cells: (11 30 1) is for feedthrough
+PHY-3001 : eco cells: (11 33 0) is for feedthrough
+PHY-3001 : eco cells: (11 40 2) is for feedthrough
+PHY-3001 : eco cells: (11 41 2) is for feedthrough
+PHY-3001 : eco cells: (11 49 2) is for feedthrough
+PHY-3001 : eco cells: (11 50 2) is for feedthrough
+PHY-3001 : eco cells: (11 53 2) is for feedthrough
+PHY-3001 : eco cells: (11 61 0) is for feedthrough
+PHY-3001 : eco cells: (11 65 2) is for feedthrough
+PHY-3001 : eco cells: (11 66 3) is for feedthrough
+PHY-3001 : eco cells: (12 7 2) is for feedthrough
+PHY-3001 : eco cells: (12 8 0) is for feedthrough
+PHY-3001 : eco cells: (12 10 1) is for feedthrough
+PHY-3001 : eco cells: (12 13 0) is for feedthrough
+PHY-3001 : eco cells: (12 13 2) is for feedthrough
+PHY-3001 : eco cells: (12 14 0) is for feedthrough
+PHY-3001 : eco cells: (12 15 3) is for feedthrough
+PHY-3001 : eco cells: (12 16 0) is for feedthrough
+PHY-3001 : eco cells: (12 16 1) is for feedthrough
+PHY-3001 : eco cells: (12 28 2) is for feedthrough
+PHY-3001 : eco cells: (12 30 0) is for feedthrough
+PHY-3001 : eco cells: (12 35 3) is for feedthrough
+PHY-3001 : eco cells: (12 38 1) is for feedthrough
+PHY-3001 : eco cells: (12 45 1) is for feedthrough
+PHY-3001 : eco cells: (12 49 2) is for feedthrough
+PHY-3001 : eco cells: (12 56 1) is for feedthrough
+PHY-3001 : eco cells: (12 63 2) is for feedthrough
+PHY-3001 : eco cells: (12 66 0) is for feedthrough
+PHY-3001 : eco cells: (13 10 0) is for feedthrough
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+PHY-3001 : eco cells: (30 52 0) is for feedthrough
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+PHY-3001 : eco cells: (30 54 2) is for feedthrough
+PHY-3001 : eco cells: (30 70 1) is for feedthrough
+PHY-3001 : eco cells: (31 7 1) is for feedthrough
+PHY-3001 : eco cells: (31 8 0) is for feedthrough
+PHY-3001 : eco cells: (31 8 1) is for feedthrough
+PHY-3001 : eco cells: (31 9 0) is for feedthrough
+PHY-3001 : eco cells: (31 9 2) is for feedthrough
+PHY-3001 : eco cells: (31 10 1) is for feedthrough
+PHY-3001 : eco cells: (31 11 1) is for feedthrough
+PHY-3001 : eco cells: (31 12 1) is for feedthrough
+PHY-3001 : eco cells: (31 20 0) is for feedthrough
+PHY-3001 : eco cells: (31 23 1) is for feedthrough
+PHY-3001 : eco cells: (31 24 0) is for feedthrough
+PHY-3001 : eco cells: (31 26 1) is for feedthrough
+PHY-3001 : eco cells: (31 31 3) is for feedthrough
+PHY-3001 : eco cells: (31 33 1) is for feedthrough
+PHY-3001 : eco cells: (31 57 3) is for feedthrough
+PHY-3001 : eco cells: (31 66 3) is for feedthrough
+PHY-3001 : eco cells: (31 69 2) is for feedthrough
+PHY-3001 : eco cells: (33 4 2) is for feedthrough
+PHY-3001 : eco cells: (33 8 0) is for feedthrough
+PHY-3001 : eco cells: (33 13 3) is for feedthrough
+PHY-3001 : eco cells: (33 14 0) is for feedthrough
+PHY-3001 : eco cells: (33 17 3) is for feedthrough
+PHY-3001 : eco cells: (33 19 1) is for feedthrough
+PHY-3001 : eco cells: (33 20 3) is for feedthrough
+PHY-3001 : eco cells: (33 21 3) is for feedthrough
+PHY-3001 : eco cells: (33 22 0) is for feedthrough
+PHY-3001 : eco cells: (33 22 2) is for feedthrough
+PHY-3001 : eco cells: (33 23 2) is for feedthrough
+PHY-3001 : eco cells: (33 25 1) is for feedthrough
+PHY-3001 : eco cells: (33 27 0) is for feedthrough
+PHY-3001 : eco cells: (33 27 1) is for feedthrough
+PHY-3001 : eco cells: (33 27 2) is for feedthrough
+PHY-3001 : eco cells: (33 28 1) is for feedthrough
+PHY-3001 : eco cells: (33 28 2) is for feedthrough
+PHY-3001 : eco cells: (33 29 3) is for feedthrough
+PHY-3001 : eco cells: (33 30 3) is for feedthrough
+PHY-3001 : eco cells: (33 33 1) is for feedthrough
+PHY-3001 : eco cells: (33 34 2) is for feedthrough
+PHY-3001 : eco cells: (33 65 0) is for feedthrough
+PHY-3001 : eco cells: (33 65 2) is for feedthrough
+PHY-3001 : eco cells: (34 1 0) is for feedthrough
+PHY-3001 : eco cells: (34 2 2) is for feedthrough
+PHY-3001 : eco cells: (34 13 0) is for feedthrough
+PHY-3001 : eco cells: (34 15 0) is for feedthrough
+PHY-3001 : eco cells: (34 15 3) is for feedthrough
+PHY-3001 : eco cells: (34 16 0) is for feedthrough
+PHY-3001 : eco cells: (34 16 1) is for feedthrough
+PHY-3001 : eco cells: (34 16 3) is for feedthrough
+PHY-3001 : eco cells: (34 17 0) is for feedthrough
+PHY-3001 : eco cells: (34 17 1) is for feedthrough
+PHY-3001 : eco cells: (34 20 2) is for feedthrough
+PHY-3001 : eco cells: (34 21 0) is for feedthrough
+PHY-3001 : eco cells: (34 21 2) is for feedthrough
+PHY-3001 : eco cells: (34 26 3) is for feedthrough
+PHY-3001 : eco cells: (34 28 3) is for feedthrough
+PHY-3001 : eco cells: (34 30 0) is for feedthrough
+PHY-3001 : eco cells: (34 30 2) is for feedthrough
+PHY-3001 : eco cells: (34 31 1) is for feedthrough
+PHY-3001 : eco cells: (34 31 2) is for feedthrough
+PHY-3001 : eco cells: (34 31 3) is for feedthrough
+PHY-3001 : eco cells: (34 32 3) is for feedthrough
+PHY-3001 : eco cells: (34 34 0) is for feedthrough
+PHY-3001 : eco cells: (34 35 2) is for feedthrough
+PHY-3001 : eco cells: (34 48 1) is for feedthrough
+PHY-3001 : eco cells: (34 50 3) is for feedthrough
+PHY-3001 : eco cells: (34 65 2) is for feedthrough
+PHY-3001 : eco cells: (34 66 3) is for feedthrough
+PHY-3001 : eco cells: (34 67 2) is for feedthrough
+PHY-3001 : eco cells: (35 3 3) is for feedthrough
+PHY-3001 : eco cells: (35 6 1) is for feedthrough
+PHY-3001 : eco cells: (35 14 0) is for feedthrough
+PHY-3001 : eco cells: (35 14 3) is for feedthrough
+PHY-3001 : eco cells: (35 15 1) is for feedthrough
+PHY-3001 : eco cells: (35 16 0) is for feedthrough
+PHY-3001 : eco cells: (35 18 0) is for feedthrough
+PHY-3001 : eco cells: (35 19 1) is for feedthrough
+PHY-3001 : eco cells: (35 20 1) is for feedthrough
+PHY-3001 : eco cells: (35 20 2) is for feedthrough
+PHY-3001 : eco cells: (35 21 0) is for feedthrough
+PHY-3001 : eco cells: (35 21 1) is for feedthrough
+PHY-3001 : eco cells: (35 21 3) is for feedthrough
+PHY-3001 : eco cells: (35 22 0) is for feedthrough
+PHY-3001 : eco cells: (35 24 1) is for feedthrough
+PHY-3001 : eco cells: (35 25 1) is for feedthrough
+PHY-3001 : eco cells: (35 26 0) is for feedthrough
+PHY-3001 : eco cells: (35 26 1) is for feedthrough
+PHY-3001 : eco cells: (35 26 3) is for feedthrough
+PHY-3001 : eco cells: (35 28 1) is for feedthrough
+PHY-3001 : eco cells: (35 28 3) is for feedthrough
+PHY-3001 : eco cells: (35 29 1) is for feedthrough
+PHY-3001 : eco cells: (35 30 1) is for feedthrough
+PHY-3001 : eco cells: (35 32 0) is for feedthrough
+PHY-3001 : eco cells: (35 32 2) is for feedthrough
+PHY-3001 : eco cells: (35 32 3) is for feedthrough
+PHY-3001 : eco cells: (35 33 0) is for feedthrough
+PHY-3001 : eco cells: (35 33 2) is for feedthrough
+PHY-3001 : eco cells: (35 46 1) is for feedthrough
+PHY-3001 : eco cells: (35 63 0) is for feedthrough
+PHY-3001 : eco cells: (35 67 2) is for feedthrough
+PHY-3001 : eco cells: (36 3 1) is for feedthrough
+PHY-3001 : eco cells: (36 16 0) is for feedthrough
+PHY-3001 : eco cells: (36 16 2) is for feedthrough
+PHY-3001 : eco cells: (36 18 0) is for feedthrough
+PHY-3001 : eco cells: (36 19 1) is for feedthrough
+PHY-3001 : eco cells: (36 20 0) is for feedthrough
+PHY-3001 : eco cells: (36 20 1) is for feedthrough
+PHY-3001 : eco cells: (36 21 2) is for feedthrough
+PHY-3001 : eco cells: (36 24 3) is for feedthrough
+PHY-3001 : eco cells: (36 25 1) is for feedthrough
+PHY-3001 : eco cells: (36 27 0) is for feedthrough
+PHY-3001 : eco cells: (36 27 1) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 1) is for feedthrough
+PHY-3001 : eco cells: (36 29 0) is for feedthrough
+PHY-3001 : eco cells: (36 29 2) is for feedthrough
+PHY-3001 : eco cells: (36 32 2) is for feedthrough
+PHY-3001 : eco cells: (36 33 1) is for feedthrough
+PHY-3001 : eco cells: (36 34 0) is for feedthrough
+PHY-3001 : eco cells: (36 42 0) is for feedthrough
+PHY-3001 : eco cells: (36 50 2) is for feedthrough
+PHY-3001 : eco cells: (36 51 3) is for feedthrough
+PHY-3001 : eco cells: (36 66 3) is for feedthrough
+PHY-3001 : eco cells: (37 4 0) is for feedthrough
+PHY-3001 : eco cells: (37 16 1) is for feedthrough
+PHY-3001 : eco cells: (37 18 1) is for feedthrough
+PHY-3001 : eco cells: (37 18 3) is for feedthrough
+PHY-3001 : eco cells: (37 19 2) is for feedthrough
+PHY-3001 : eco cells: (37 20 0) is for feedthrough
+PHY-3001 : eco cells: (37 21 2) is for feedthrough
+PHY-3001 : eco cells: (37 21 3) is for feedthrough
+PHY-3001 : eco cells: (37 22 1) is for feedthrough
+PHY-3001 : eco cells: (37 24 1) is for feedthrough
+PHY-3001 : eco cells: (37 25 2) is for feedthrough
+PHY-3001 : eco cells: (37 26 2) is for feedthrough
+PHY-3001 : eco cells: (37 27 1) is for feedthrough
+PHY-3001 : eco cells: (37 27 2) is for feedthrough
+PHY-3001 : eco cells: (37 28 2) is for feedthrough
+PHY-3001 : eco cells: (37 28 3) is for feedthrough
+PHY-3001 : eco cells: (37 29 2) is for feedthrough
+PHY-3001 : eco cells: (37 31 0) is for feedthrough
+PHY-3001 : eco cells: (37 31 1) is for feedthrough
+PHY-3001 : eco cells: (37 53 3) is for feedthrough
+PHY-3001 : eco cells: (37 64 2) is for feedthrough
+PHY-3001 : eco cells: (37 65 2) is for feedthrough
+PHY-3001 : eco cells: (38 9 1) is for feedthrough
+PHY-3001 : eco cells: (38 10 0) is for feedthrough
+PHY-3001 : eco cells: (38 19 3) is for feedthrough
+PHY-3001 : eco cells: (38 21 2) is for feedthrough
+PHY-3001 : eco cells: (38 22 1) is for feedthrough
+PHY-3001 : eco cells: (38 23 1) is for feedthrough
+PHY-3001 : eco cells: (38 27 1) is for feedthrough
+PHY-3001 : eco cells: (38 30 2) is for feedthrough
+PHY-3001 : eco cells: (38 32 1) is for feedthrough
+PHY-3001 : eco cells: (38 32 3) is for feedthrough
+PHY-3001 : eco cells: (38 40 1) is for feedthrough
+PHY-3001 : eco cells: (38 67 3) is for feedthrough
+PHY-3001 : eco cells: (39 12 1) is for feedthrough
+PHY-3001 : eco cells: (39 13 3) is for feedthrough
+PHY-3001 : eco cells: (39 19 3) is for feedthrough
+PHY-3001 : eco cells: (39 27 1) is for feedthrough
+PHY-3001 : eco cells: (39 29 2) is for feedthrough
+PHY-3001 : eco cells: (39 29 3) is for feedthrough
+PHY-3001 : eco cells: (39 30 3) is for feedthrough
+PHY-3001 : eco cells: (39 33 3) is for feedthrough
+PHY-3001 : eco cells: (39 39 1) is for feedthrough
+PHY-3001 : eco cells: (39 41 2) is for feedthrough
+PHY-3001 : eco cells: (39 41 3) is for feedthrough
+PHY-3001 : eco cells: (39 42 2) is for feedthrough
+PHY-3001 : eco cells: 7275 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7363 instances, 7214 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.903079s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (98.6%)
+
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.429373s wall, 1.375000s user + 0.015625s system = 1.390625s CPU (97.3%)
+
+RUN-1004 : used memory is 1212 MB, reserved memory is 1220 MB, peak memory is 1216 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7365 instances
+RUN-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18943 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10437 nets have 2 pins
+RUN-1001 : 6579 nets have [3 - 5] pins
+RUN-1001 : 958 nets have [6 - 10] pins
+RUN-1001 : 514 nets have [11 - 20] pins
+RUN-1001 : 427 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3605 mslices, 3609 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1217, reserve = 1225, peak = 1217.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1239, peak = 1232.
+PHY-1001 : End build detailed router design. 2.122572s wall, 2.109375s user + 0.000000s system = 2.109375s CPU (99.4%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.023960s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (65.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.031040s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.031349s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.030721s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (101.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.030151s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (103.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.030635s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (102.0%)
+
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1239, peak = 1232.
+PHY-1001 : End phase 1; 0.215823s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.4%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1239, peak = 1232.
+PHY-1001 : End initial routed; 0.162051s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.641427s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1239, peak = 1232.
+PHY-1001 : End phase 2; 3.803536s wall, 3.781250s user + 0.000000s system = 3.781250s CPU (99.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 11 pins with SWNS -5.791ns STNS -3388.165ns FEP 981.
+PHY-1001 : End OPT Iter 1; 0.140512s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.1%)
+
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.392132s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (103.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.147330s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.148258s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.4%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.145524s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.148755s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.146078s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.160182s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.150408s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (103.9%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.147475s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.145301s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.145585s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.144618s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (118.8%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.157189s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.149286s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.154620s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (90.9%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.155695s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.153164s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.159368s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (107.8%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.174162s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.148559s wall, 0.171875s user + 0.031250s system = 0.203125s CPU (136.7%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.145807s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.146687s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (85.2%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.213468s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (87.8%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.145881s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.148690s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.1%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.153722s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.147126s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.2%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.147171s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.6%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.145412s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.146030s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.0%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.145110s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.145117s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.146144s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.9%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.150856s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.2%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.148851s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.5%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.145618s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.145676s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (118.0%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.154429s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.147119s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.6%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.144446s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.145168s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.6%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.145900s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.4%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.150151s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.1%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.144899s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.405564s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (34.7%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.145866s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.185388s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (84.3%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.146014s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.0%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.152938s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (91.9%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.152285s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.152460s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.150323s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.9%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.160240s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.194381s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.149499s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.146132s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.9%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.151538s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.8%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.146809s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (117.1%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.147824s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.1%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.148286s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.4%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.145382s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.152453s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.149733s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.9%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.155600s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.154446s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (80.9%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.145467s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (128.9%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.148215s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.145894s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.1%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.146843s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.146861s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.155865s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.151493s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.1%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.147038s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.6%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.147566s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (116.5%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.53539e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.147766s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 2843/17866(15%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : ----------------------------------------
+RUN-1001 : Setup | -5.791 | -3388.165 | 981
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 4.005091s wall, 3.906250s user + 0.000000s system = 3.906250s CPU (97.5%)
+
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1239, peak = 1232.
+PHY-1001 : End phase 3; 15.968831s wall, 15.531250s user + 0.125000s system = 15.656250s CPU (98.0%)
+
+PHY-1001 : 916 feed throughs used by 648 nets
+PHY-1001 : Current memory(MB): used = 1232, reserve = 1239, peak = 1232.
+PHY-1001 : End export database. 2.860500s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (98.9%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x25y22_w2beg5), nets: u_bus_top/lv_cnt_a_sync1d[17] u_bus_top/u_local_bus_slve_cis/slv_mcu_din[31]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 26.251745s wall, 25.734375s user + 0.125000s system = 25.859375s CPU (98.5%)
+
+RUN-1004 : used memory is 1227 MB, reserved memory is 1234 MB, peak memory is 1232 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x25y22_w2beg5), nets: u_bus_top/lv_cnt_a_sync1d[17] u_bus_top/u_local_bus_slve_cis/slv_mcu_din[31]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 187.329495s wall, 220.046875s user + 0.843750s system = 220.890625s CPU (117.9%)
+
+RUN-1004 : used memory is 1227 MB, reserved memory is 1234 MB, peak memory is 1232 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_172524.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_173157.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_173157.log
new file mode 100644
index 0000000..247529b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240314_173157.log
@@ -0,0 +1,2235 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 17:31:57 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.349910s wall, 2.250000s user + 0.078125s system = 2.328125s CPU (99.1%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 317 MB, peak memory is 345 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 1.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18196 instances
+RUN-0007 : 7871 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20774 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13055 nets have 2 pins
+RUN-1001 : 6669 nets have [3 - 5] pins
+RUN-1001 : 620 nets have [6 - 10] pins
+RUN-1001 : 188 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18194 instances, 7871 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 51%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85090, tnet num: 20596, tinst num: 18194, tnode num: 115348, tedge num: 135718.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.266514s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (99.9%)
+
+RUN-1004 : used memory is 535 MB, reserved memory is 518 MB, peak memory is 535 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20596 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.163726s wall, 2.125000s user + 0.031250s system = 2.156250s CPU (99.7%)
+
+PHY-3001 : Found 1253 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.12543e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18194.
+PHY-3001 : Level 1 #clusters 2034.
+PHY-3001 : End clustering; 0.154810s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (121.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.3503e+06, overlap = 480.688
+PHY-3002 : Step(2): len = 1.24272e+06, overlap = 505.156
+PHY-3002 : Step(3): len = 880612, overlap = 595.25
+PHY-3002 : Step(4): len = 773930, overlap = 689.094
+PHY-3002 : Step(5): len = 620754, overlap = 781.969
+PHY-3002 : Step(6): len = 554098, overlap = 841.25
+PHY-3002 : Step(7): len = 464162, overlap = 953.406
+PHY-3002 : Step(8): len = 406361, overlap = 1024.56
+PHY-3002 : Step(9): len = 363070, overlap = 1086
+PHY-3002 : Step(10): len = 327640, overlap = 1121.09
+PHY-3002 : Step(11): len = 293058, overlap = 1168.06
+PHY-3002 : Step(12): len = 268963, overlap = 1236.19
+PHY-3002 : Step(13): len = 243385, overlap = 1310.72
+PHY-3002 : Step(14): len = 222872, overlap = 1342.19
+PHY-3002 : Step(15): len = 199898, overlap = 1374.22
+PHY-3002 : Step(16): len = 182462, overlap = 1423.72
+PHY-3002 : Step(17): len = 169448, overlap = 1442.59
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.38763e-06
+PHY-3002 : Step(18): len = 174653, overlap = 1392.03
+PHY-3002 : Step(19): len = 210463, overlap = 1274.34
+PHY-3002 : Step(20): len = 220068, overlap = 1182.66
+PHY-3002 : Step(21): len = 225681, overlap = 1102.38
+PHY-3002 : Step(22): len = 224448, overlap = 1120.56
+PHY-3002 : Step(23): len = 223779, overlap = 1136.16
+PHY-3002 : Step(24): len = 218472, overlap = 1127.25
+PHY-3002 : Step(25): len = 215897, overlap = 1124.47
+PHY-3002 : Step(26): len = 211762, overlap = 1106.91
+PHY-3002 : Step(27): len = 210773, overlap = 1076.84
+PHY-3002 : Step(28): len = 206042, overlap = 1061.16
+PHY-3002 : Step(29): len = 205125, overlap = 1086.44
+PHY-3002 : Step(30): len = 202460, overlap = 1110.97
+PHY-3002 : Step(31): len = 203335, overlap = 1110.84
+PHY-3002 : Step(32): len = 202982, overlap = 1117.19
+PHY-3002 : Step(33): len = 203224, overlap = 1130.12
+PHY-3002 : Step(34): len = 200044, overlap = 1134.19
+PHY-3002 : Step(35): len = 200213, overlap = 1121.22
+PHY-3002 : Step(36): len = 197075, overlap = 1162.06
+PHY-3002 : Step(37): len = 196257, overlap = 1171.56
+PHY-3002 : Step(38): len = 193802, overlap = 1166.66
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.77527e-06
+PHY-3002 : Step(39): len = 198107, overlap = 1156.38
+PHY-3002 : Step(40): len = 210692, overlap = 1144.25
+PHY-3002 : Step(41): len = 216049, overlap = 1114.19
+PHY-3002 : Step(42): len = 220618, overlap = 1082.72
+PHY-3002 : Step(43): len = 223533, overlap = 1051.91
+PHY-3002 : Step(44): len = 224434, overlap = 1042.88
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.55053e-06
+PHY-3002 : Step(45): len = 234207, overlap = 1020.88
+PHY-3002 : Step(46): len = 263759, overlap = 945.406
+PHY-3002 : Step(47): len = 279929, overlap = 874.719
+PHY-3002 : Step(48): len = 286530, overlap = 833.312
+PHY-3002 : Step(49): len = 288203, overlap = 775.281
+PHY-3002 : Step(50): len = 287904, overlap = 759.781
+PHY-3002 : Step(51): len = 286054, overlap = 756.5
+PHY-3002 : Step(52): len = 284699, overlap = 752.562
+PHY-3002 : Step(53): len = 283946, overlap = 719.969
+PHY-3002 : Step(54): len = 284784, overlap = 713.25
+PHY-3002 : Step(55): len = 284190, overlap = 706.844
+PHY-3002 : Step(56): len = 284134, overlap = 701.844
+PHY-3002 : Step(57): len = 282926, overlap = 711.906
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.11011e-05
+PHY-3002 : Step(58): len = 300009, overlap = 648.156
+PHY-3002 : Step(59): len = 322396, overlap = 519.781
+PHY-3002 : Step(60): len = 330982, overlap = 447.531
+PHY-3002 : Step(61): len = 334867, overlap = 443.812
+PHY-3002 : Step(62): len = 332018, overlap = 456.25
+PHY-3002 : Step(63): len = 330314, overlap = 462.969
+PHY-3002 : Step(64): len = 328609, overlap = 484.438
+PHY-3002 : Step(65): len = 328299, overlap = 498.125
+PHY-3002 : Step(66): len = 327754, overlap = 492.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.22021e-05
+PHY-3002 : Step(67): len = 347259, overlap = 428.562
+PHY-3002 : Step(68): len = 363629, overlap = 380.594
+PHY-3002 : Step(69): len = 371207, overlap = 379.438
+PHY-3002 : Step(70): len = 375416, overlap = 396.906
+PHY-3002 : Step(71): len = 374596, overlap = 396.594
+PHY-3002 : Step(72): len = 374610, overlap = 389.156
+PHY-3002 : Step(73): len = 374953, overlap = 405.25
+PHY-3002 : Step(74): len = 376280, overlap = 392.562
+PHY-3002 : Step(75): len = 376269, overlap = 393.406
+PHY-3002 : Step(76): len = 375907, overlap = 390
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.44043e-05
+PHY-3002 : Step(77): len = 394749, overlap = 369.344
+PHY-3002 : Step(78): len = 407807, overlap = 345.031
+PHY-3002 : Step(79): len = 410204, overlap = 337.375
+PHY-3002 : Step(80): len = 413337, overlap = 335.656
+PHY-3002 : Step(81): len = 415521, overlap = 316
+PHY-3002 : Step(82): len = 418621, overlap = 320.531
+PHY-3002 : Step(83): len = 415939, overlap = 320.219
+PHY-3002 : Step(84): len = 417720, overlap = 315.562
+PHY-3002 : Step(85): len = 419116, overlap = 309.594
+PHY-3002 : Step(86): len = 421127, overlap = 310.25
+PHY-3002 : Step(87): len = 417636, overlap = 314.688
+PHY-3002 : Step(88): len = 417270, overlap = 310.906
+PHY-3002 : Step(89): len = 419094, overlap = 307.25
+PHY-3002 : Step(90): len = 421221, overlap = 296.938
+PHY-3002 : Step(91): len = 419324, overlap = 296.5
+PHY-3002 : Step(92): len = 419873, overlap = 290.281
+PHY-3002 : Step(93): len = 421840, overlap = 299.469
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.88085e-05
+PHY-3002 : Step(94): len = 439103, overlap = 260.688
+PHY-3002 : Step(95): len = 454438, overlap = 260.844
+PHY-3002 : Step(96): len = 456982, overlap = 254.531
+PHY-3002 : Step(97): len = 458542, overlap = 237.062
+PHY-3002 : Step(98): len = 460935, overlap = 241.875
+PHY-3002 : Step(99): len = 462556, overlap = 248.031
+PHY-3002 : Step(100): len = 461395, overlap = 227.406
+PHY-3002 : Step(101): len = 463708, overlap = 212.562
+PHY-3002 : Step(102): len = 464784, overlap = 221.688
+PHY-3002 : Step(103): len = 467771, overlap = 232.094
+PHY-3002 : Step(104): len = 466974, overlap = 232
+PHY-3002 : Step(105): len = 468014, overlap = 232.781
+PHY-3002 : Step(106): len = 468410, overlap = 237.625
+PHY-3002 : Step(107): len = 469172, overlap = 245.75
+PHY-3002 : Step(108): len = 467072, overlap = 250.125
+PHY-3002 : Step(109): len = 467184, overlap = 252.188
+PHY-3002 : Step(110): len = 467826, overlap = 251.969
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000177617
+PHY-3002 : Step(111): len = 482539, overlap = 236.75
+PHY-3002 : Step(112): len = 492559, overlap = 223.375
+PHY-3002 : Step(113): len = 492525, overlap = 216.094
+PHY-3002 : Step(114): len = 492900, overlap = 213
+PHY-3002 : Step(115): len = 495030, overlap = 216.125
+PHY-3002 : Step(116): len = 497090, overlap = 211.969
+PHY-3002 : Step(117): len = 496936, overlap = 212.219
+PHY-3002 : Step(118): len = 498372, overlap = 212.688
+PHY-3002 : Step(119): len = 500244, overlap = 202.406
+PHY-3002 : Step(120): len = 501818, overlap = 205.5
+PHY-3002 : Step(121): len = 501013, overlap = 204.281
+PHY-3002 : Step(122): len = 500965, overlap = 205.344
+PHY-3002 : Step(123): len = 501864, overlap = 205.281
+PHY-3002 : Step(124): len = 502780, overlap = 201.219
+PHY-3002 : Step(125): len = 501992, overlap = 195.156
+PHY-3002 : Step(126): len = 502157, overlap = 195.688
+PHY-3002 : Step(127): len = 502532, overlap = 200.125
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000347391
+PHY-3002 : Step(128): len = 514111, overlap = 192.469
+PHY-3002 : Step(129): len = 521510, overlap = 183.281
+PHY-3002 : Step(130): len = 522203, overlap = 182.625
+PHY-3002 : Step(131): len = 523666, overlap = 173.375
+PHY-3002 : Step(132): len = 525393, overlap = 178.812
+PHY-3002 : Step(133): len = 526548, overlap = 171.25
+PHY-3002 : Step(134): len = 526258, overlap = 164.688
+PHY-3002 : Step(135): len = 527181, overlap = 160.312
+PHY-3002 : Step(136): len = 529398, overlap = 158.969
+PHY-3002 : Step(137): len = 532302, overlap = 156.344
+PHY-3002 : Step(138): len = 532459, overlap = 154.844
+PHY-3002 : Step(139): len = 535214, overlap = 150.438
+PHY-3002 : Step(140): len = 538487, overlap = 151.312
+PHY-3002 : Step(141): len = 540007, overlap = 147.969
+PHY-3002 : Step(142): len = 539337, overlap = 145.469
+PHY-3002 : Step(143): len = 539594, overlap = 147.094
+PHY-3002 : Step(144): len = 540319, overlap = 153.844
+PHY-3002 : Step(145): len = 540614, overlap = 156.031
+PHY-3002 : Step(146): len = 539448, overlap = 153.594
+PHY-3002 : Step(147): len = 539181, overlap = 153.531
+PHY-3002 : Step(148): len = 539412, overlap = 153.75
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000687647
+PHY-3002 : Step(149): len = 545828, overlap = 156.219
+PHY-3002 : Step(150): len = 553298, overlap = 147.688
+PHY-3002 : Step(151): len = 555512, overlap = 152.25
+PHY-3002 : Step(152): len = 556993, overlap = 142.812
+PHY-3002 : Step(153): len = 558307, overlap = 139.062
+PHY-3002 : Step(154): len = 559524, overlap = 140.781
+PHY-3002 : Step(155): len = 559355, overlap = 140.656
+PHY-3002 : Step(156): len = 559660, overlap = 140.625
+PHY-3002 : Step(157): len = 560032, overlap = 146.906
+PHY-3002 : Step(158): len = 560277, overlap = 149
+PHY-3002 : Step(159): len = 560211, overlap = 145
+PHY-3002 : Step(160): len = 560243, overlap = 147.969
+PHY-3002 : Step(161): len = 560390, overlap = 149.031
+PHY-3002 : Step(162): len = 560466, overlap = 146.281
+PHY-3002 : Step(163): len = 559870, overlap = 147.375
+PHY-3002 : Step(164): len = 559517, overlap = 144.625
+PHY-3002 : Step(165): len = 559531, overlap = 145.781
+PHY-3002 : Step(166): len = 559654, overlap = 146.562
+PHY-3002 : Step(167): len = 559279, overlap = 144.719
+PHY-3002 : Step(168): len = 559282, overlap = 145.281
+PHY-3002 : Step(169): len = 559456, overlap = 146.781
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00120974
+PHY-3002 : Step(170): len = 562681, overlap = 146.594
+PHY-3002 : Step(171): len = 567183, overlap = 141.688
+PHY-3002 : Step(172): len = 568255, overlap = 136.719
+PHY-3002 : Step(173): len = 569039, overlap = 134.531
+PHY-3002 : Step(174): len = 570059, overlap = 138.969
+PHY-3002 : Step(175): len = 571297, overlap = 137.25
+PHY-3002 : Step(176): len = 571679, overlap = 135.031
+PHY-3002 : Step(177): len = 572161, overlap = 133.219
+PHY-3002 : Step(178): len = 572681, overlap = 132.344
+PHY-3002 : Step(179): len = 573183, overlap = 131.562
+PHY-3002 : Step(180): len = 573598, overlap = 132.375
+PHY-3002 : Step(181): len = 573859, overlap = 132.75
+PHY-3002 : Step(182): len = 573838, overlap = 132.156
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00212938
+PHY-3002 : Step(183): len = 575980, overlap = 131.844
+PHY-3002 : Step(184): len = 579702, overlap = 134.844
+PHY-3002 : Step(185): len = 581032, overlap = 129.969
+PHY-3002 : Step(186): len = 581923, overlap = 133.906
+PHY-3002 : Step(187): len = 582565, overlap = 139.25
+PHY-3002 : Step(188): len = 583115, overlap = 137.594
+PHY-3002 : Step(189): len = 583387, overlap = 131.969
+PHY-3002 : Step(190): len = 583956, overlap = 131.938
+PHY-3002 : Step(191): len = 584840, overlap = 133.375
+PHY-3002 : Step(192): len = 585133, overlap = 133.312
+PHY-3002 : Step(193): len = 584951, overlap = 133.5
+PHY-3002 : Step(194): len = 584991, overlap = 132.562
+PHY-3002 : Step(195): len = 585558, overlap = 131.625
+PHY-3002 : Step(196): len = 586009, overlap = 131.625
+PHY-3002 : Step(197): len = 585783, overlap = 129.906
+PHY-3002 : Step(198): len = 585704, overlap = 130
+PHY-3002 : Step(199): len = 586349, overlap = 132
+PHY-3002 : Step(200): len = 587068, overlap = 132.031
+PHY-3002 : Step(201): len = 586707, overlap = 131.062
+PHY-3002 : Step(202): len = 586714, overlap = 131.156
+PHY-3002 : Step(203): len = 587798, overlap = 130.781
+PHY-3002 : Step(204): len = 588456, overlap = 131.25
+PHY-3002 : Step(205): len = 588349, overlap = 130.5
+PHY-3002 : Step(206): len = 588598, overlap = 128.969
+PHY-3002 : Step(207): len = 589441, overlap = 128.938
+PHY-3002 : Step(208): len = 589516, overlap = 128.938
+PHY-3002 : Step(209): len = 589056, overlap = 128.562
+PHY-3002 : Step(210): len = 588900, overlap = 128.188
+PHY-3002 : Step(211): len = 589281, overlap = 124.438
+PHY-3002 : Step(212): len = 589589, overlap = 126.906
+PHY-3002 : Step(213): len = 589168, overlap = 122.906
+PHY-3002 : Step(214): len = 589131, overlap = 122.906
+PHY-3002 : Step(215): len = 589738, overlap = 124.406
+PHY-3002 : Step(216): len = 589738, overlap = 124.406
+PHY-3002 : Step(217): len = 589486, overlap = 124.406
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.020030s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (156.0%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20774.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 756768, over cnt = 1592(4%), over = 7572, worst = 63
+PHY-1001 : End global iterations; 0.798124s wall, 1.046875s user + 0.062500s system = 1.109375s CPU (139.0%)
+
+PHY-1001 : Congestion index: top1 = 84.53, top5 = 63.94, top10 = 54.63, top15 = 48.61.
+PHY-3001 : End congestion estimation; 1.100971s wall, 1.359375s user + 0.062500s system = 1.421875s CPU (129.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20596 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.012919s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000138817
+PHY-3002 : Step(218): len = 688558, overlap = 88.9688
+PHY-3002 : Step(219): len = 693726, overlap = 70.2812
+PHY-3002 : Step(220): len = 689451, overlap = 59.0625
+PHY-3002 : Step(221): len = 685938, overlap = 51
+PHY-3002 : Step(222): len = 683104, overlap = 44.6562
+PHY-3002 : Step(223): len = 681507, overlap = 38.8125
+PHY-3002 : Step(224): len = 677628, overlap = 35.2188
+PHY-3002 : Step(225): len = 674768, overlap = 36.4688
+PHY-3002 : Step(226): len = 671391, overlap = 32.625
+PHY-3002 : Step(227): len = 668877, overlap = 33.4688
+PHY-3002 : Step(228): len = 666026, overlap = 40.875
+PHY-3002 : Step(229): len = 664138, overlap = 42.9062
+PHY-3002 : Step(230): len = 661638, overlap = 48.3438
+PHY-3002 : Step(231): len = 659665, overlap = 49.5312
+PHY-3002 : Step(232): len = 657653, overlap = 53.2812
+PHY-3002 : Step(233): len = 656402, overlap = 54.1875
+PHY-3002 : Step(234): len = 654846, overlap = 50.7812
+PHY-3002 : Step(235): len = 653345, overlap = 50.4375
+PHY-3002 : Step(236): len = 650843, overlap = 53.4062
+PHY-3002 : Step(237): len = 649372, overlap = 56.3438
+PHY-3002 : Step(238): len = 648006, overlap = 58.9062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000277635
+PHY-3002 : Step(239): len = 651664, overlap = 56.4688
+PHY-3002 : Step(240): len = 654149, overlap = 56.2812
+PHY-3002 : Step(241): len = 654889, overlap = 56.6875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00047341
+PHY-3002 : Step(242): len = 661348, overlap = 56.6562
+PHY-3002 : Step(243): len = 678403, overlap = 49.0312
+PHY-3002 : Step(244): len = 682012, overlap = 50.1562
+PHY-3002 : Step(245): len = 680386, overlap = 52.2812
+PHY-3002 : Step(246): len = 678908, overlap = 52.375
+PHY-3002 : Step(247): len = 677548, overlap = 51.7812
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 92/20774.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765904, over cnt = 2725(7%), over = 12723, worst = 47
+PHY-1001 : End global iterations; 1.702622s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (135.8%)
+
+PHY-1001 : Congestion index: top1 = 93.02, top5 = 71.15, top10 = 61.19, top15 = 55.40.
+PHY-3001 : End congestion estimation; 2.089637s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (127.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20596 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.077806s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000112078
+PHY-3002 : Step(248): len = 671926, overlap = 299.906
+PHY-3002 : Step(249): len = 671875, overlap = 251.188
+PHY-3002 : Step(250): len = 666412, overlap = 223.062
+PHY-3002 : Step(251): len = 664274, overlap = 202.438
+PHY-3002 : Step(252): len = 659787, overlap = 178.812
+PHY-3002 : Step(253): len = 656179, overlap = 170.375
+PHY-3002 : Step(254): len = 650964, overlap = 161.25
+PHY-3002 : Step(255): len = 647787, overlap = 149.906
+PHY-3002 : Step(256): len = 645804, overlap = 133.969
+PHY-3002 : Step(257): len = 641886, overlap = 129.5
+PHY-3002 : Step(258): len = 640441, overlap = 128.594
+PHY-3002 : Step(259): len = 636076, overlap = 118.281
+PHY-3002 : Step(260): len = 632813, overlap = 114.188
+PHY-3002 : Step(261): len = 629840, overlap = 119.375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000224155
+PHY-3002 : Step(262): len = 631047, overlap = 108.969
+PHY-3002 : Step(263): len = 634930, overlap = 106
+PHY-3002 : Step(264): len = 637147, overlap = 103.969
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00044831
+PHY-3002 : Step(265): len = 642961, overlap = 97.0938
+PHY-3002 : Step(266): len = 649585, overlap = 90.5625
+PHY-3002 : Step(267): len = 654941, overlap = 88.2812
+PHY-3002 : Step(268): len = 654454, overlap = 85.0938
+PHY-3002 : Step(269): len = 653536, overlap = 82.9375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000896621
+PHY-3002 : Step(270): len = 658057, overlap = 79.4062
+PHY-3002 : Step(271): len = 662605, overlap = 76
+PHY-3002 : Step(272): len = 667848, overlap = 72.5312
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85090, tnet num: 20596, tinst num: 18194, tnode num: 115348, tedge num: 135718.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.719224s wall, 1.625000s user + 0.046875s system = 1.671875s CPU (97.2%)
+
+RUN-1004 : used memory is 579 MB, reserved memory is 566 MB, peak memory is 716 MB
+OPT-1001 : Total overflow 406.44 peak overflow 4.34
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 743/20774.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 771120, over cnt = 3164(8%), over = 11338, worst = 32
+PHY-1001 : End global iterations; 1.465056s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (151.4%)
+
+PHY-1001 : Congestion index: top1 = 72.41, top5 = 58.10, top10 = 51.87, top15 = 48.40.
+PHY-1001 : End incremental global routing; 1.843243s wall, 2.562500s user + 0.031250s system = 2.593750s CPU (140.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20596 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.043218s wall, 1.000000s user + 0.046875s system = 1.046875s CPU (100.4%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18063 has valid locations, 309 needs to be replaced
+PHY-3001 : design contains 18457 instances, 7966 luts, 9270 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6066 pins
+PHY-3001 : Found 1259 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 690746
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17142/21037.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 783560, over cnt = 3197(9%), over = 11368, worst = 32
+PHY-1001 : End global iterations; 0.267805s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 71.83, top5 = 58.08, top10 = 52.06, top15 = 48.58.
+PHY-3001 : End congestion estimation; 0.569160s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (115.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86123, tnet num: 20859, tinst num: 18457, tnode num: 116899, tedge num: 137258.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.668557s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (97.4%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 632 MB, peak memory is 718 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20859 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.752927s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (98.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(273): len = 689760, overlap = 0
+PHY-3002 : Step(274): len = 689162, overlap = 0
+PHY-3002 : Step(275): len = 688715, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17226/21037.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 781256, over cnt = 3205(9%), over = 11380, worst = 32
+PHY-1001 : End global iterations; 0.274335s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (119.6%)
+
+PHY-1001 : Congestion index: top1 = 72.09, top5 = 58.25, top10 = 52.27, top15 = 48.80.
+PHY-3001 : End congestion estimation; 0.584682s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (106.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20859 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.122457s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000360767
+PHY-3002 : Step(276): len = 688710, overlap = 74.5625
+PHY-3002 : Step(277): len = 688908, overlap = 75.125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000721535
+PHY-3002 : Step(278): len = 688922, overlap = 74.5312
+PHY-3002 : Step(279): len = 689472, overlap = 75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00144307
+PHY-3002 : Step(280): len = 689797, overlap = 75.0625
+PHY-3002 : Step(281): len = 690405, overlap = 75.625
+PHY-3001 : Final: Len = 690405, Over = 75.625
+PHY-3001 : End incremental placement; 5.923382s wall, 6.109375s user + 0.328125s system = 6.437500s CPU (108.7%)
+
+OPT-1001 : Total overflow 414.81 peak overflow 4.34
+OPT-1001 : End high-fanout net optimization; 9.648012s wall, 10.515625s user + 0.406250s system = 10.921875s CPU (113.2%)
+
+OPT-1001 : Current memory(MB): used = 722, reserve = 715, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17174/21037.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 786944, over cnt = 3139(8%), over = 10238, worst = 31
+PHY-1002 : len = 832760, over cnt = 2299(6%), over = 5895, worst = 16
+PHY-1002 : len = 875448, over cnt = 1147(3%), over = 2732, worst = 16
+PHY-1002 : len = 905928, over cnt = 428(1%), over = 864, worst = 12
+PHY-1002 : len = 920032, over cnt = 3(0%), over = 6, worst = 2
+PHY-1001 : End global iterations; 2.205532s wall, 2.937500s user + 0.062500s system = 3.000000s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 61.25, top5 = 52.66, top10 = 48.70, top15 = 46.23.
+OPT-1001 : End congestion update; 2.522642s wall, 3.250000s user + 0.062500s system = 3.312500s CPU (131.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20859 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.903497s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (98.6%)
+
+OPT-0007 : Start: WNS -772 TNS -2008 NUM_FEPS 9
+OPT-0007 : Iter 1: improved WNS -622 TNS -1106 NUM_FEPS 7 with 153 cells processed and 19100 slack improved
+OPT-0007 : Iter 2: improved WNS -572 TNS -792 NUM_FEPS 6 with 26 cells processed and 7816 slack improved
+OPT-0007 : Iter 3: improved WNS -572 TNS -792 NUM_FEPS 6 with 10 cells processed and 3700 slack improved
+OPT-0007 : Iter 4: improved WNS -572 TNS -792 NUM_FEPS 6 with 12 cells processed and 1150 slack improved
+OPT-0007 : Iter 5: improved WNS -572 TNS -792 NUM_FEPS 6 with 1 cells processed and 150 slack improved
+OPT-1001 : End bottleneck based optimization; 4.188889s wall, 4.875000s user + 0.078125s system = 4.953125s CPU (118.2%)
+
+OPT-1001 : Current memory(MB): used = 698, reserve = 695, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17200/21038.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922248, over cnt = 145(0%), over = 199, worst = 4
+PHY-1002 : len = 922256, over cnt = 109(0%), over = 138, worst = 4
+PHY-1002 : len = 923088, over cnt = 37(0%), over = 46, worst = 3
+PHY-1002 : len = 923952, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 924048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.982863s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.2%)
+
+PHY-1001 : Congestion index: top1 = 61.77, top5 = 52.39, top10 = 48.50, top15 = 46.17.
+OPT-1001 : End congestion update; 1.307989s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (100.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20860 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.902974s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.4%)
+
+OPT-0007 : Start: WNS -572 TNS -792 NUM_FEPS 6
+OPT-0007 : Iter 1: improved WNS -572 TNS -792 NUM_FEPS 6 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.243673s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (100.3%)
+
+OPT-1001 : Current memory(MB): used = 708, reserve = 700, peak = 739.
+OPT-1001 : End physical optimization; 18.176277s wall, 19.718750s user + 0.562500s system = 20.281250s CPU (111.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7966 LUT to BLE ...
+SYN-4008 : Packed 7966 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6136 remaining SEQ's ...
+SYN-4005 : Packed 4062 SEQ with LUT/SLICE
+SYN-4006 : 1045 single LUT's are left
+SYN-4006 : 2074 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10040/13895 primitive instances ...
+PHY-3001 : End packing; 1.867220s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6826 instances
+RUN-1001 : 3339 mslices, 3339 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17991 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9819 nets have 2 pins
+RUN-1001 : 6800 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 323 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6824 instances, 6678 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3523 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 702488, Over = 234.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7662/17991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 864488, over cnt = 2092(5%), over = 3314, worst = 9
+PHY-1002 : len = 870912, over cnt = 1446(4%), over = 2047, worst = 7
+PHY-1002 : len = 887288, over cnt = 525(1%), over = 714, worst = 6
+PHY-1002 : len = 893056, over cnt = 251(0%), over = 325, worst = 5
+PHY-1002 : len = 899320, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.949713s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (138.6%)
+
+PHY-1001 : Congestion index: top1 = 59.68, top5 = 51.96, top10 = 48.40, top15 = 45.94.
+PHY-3001 : End congestion estimation; 2.442748s wall, 3.125000s user + 0.031250s system = 3.156250s CPU (129.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72666, tnet num: 17813, tinst num: 6824, tnode num: 95066, tedge num: 120596.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.823334s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (98.5%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 622 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.822434s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.73427e-05
+PHY-3002 : Step(282): len = 687947, overlap = 233.5
+PHY-3002 : Step(283): len = 680557, overlap = 235.75
+PHY-3002 : Step(284): len = 675725, overlap = 243.75
+PHY-3002 : Step(285): len = 672034, overlap = 245.5
+PHY-3002 : Step(286): len = 669256, overlap = 248.75
+PHY-3002 : Step(287): len = 666580, overlap = 256.5
+PHY-3002 : Step(288): len = 663546, overlap = 257.5
+PHY-3002 : Step(289): len = 661082, overlap = 256.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000114685
+PHY-3002 : Step(290): len = 664169, overlap = 244.25
+PHY-3002 : Step(291): len = 668427, overlap = 234.5
+PHY-3002 : Step(292): len = 669917, overlap = 230.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000229371
+PHY-3002 : Step(293): len = 676059, overlap = 220.5
+PHY-3002 : Step(294): len = 683409, overlap = 218
+PHY-3002 : Step(295): len = 684261, overlap = 213.75
+PHY-3002 : Step(296): len = 684909, overlap = 204
+PHY-3002 : Step(297): len = 686438, overlap = 204.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.433696s wall, 0.375000s user + 0.656250s system = 1.031250s CPU (237.8%)
+
+PHY-3001 : Trial Legalized: Len = 767869
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 773/17991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 883736, over cnt = 2727(7%), over = 4695, worst = 7
+PHY-1002 : len = 903432, over cnt = 1624(4%), over = 2395, worst = 7
+PHY-1002 : len = 921288, over cnt = 691(1%), over = 1029, worst = 6
+PHY-1002 : len = 935568, over cnt = 124(0%), over = 175, worst = 4
+PHY-1002 : len = 939024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.854128s wall, 3.843750s user + 0.015625s system = 3.859375s CPU (135.2%)
+
+PHY-1001 : Congestion index: top1 = 59.35, top5 = 52.50, top10 = 48.94, top15 = 46.69.
+PHY-3001 : End congestion estimation; 3.383016s wall, 4.375000s user + 0.015625s system = 4.390625s CPU (129.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.027721s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (97.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000162287
+PHY-3002 : Step(298): len = 740198, overlap = 45
+PHY-3002 : Step(299): len = 723913, overlap = 70.5
+PHY-3002 : Step(300): len = 711100, overlap = 95.25
+PHY-3002 : Step(301): len = 703283, overlap = 120.75
+PHY-3002 : Step(302): len = 698031, overlap = 137.75
+PHY-3002 : Step(303): len = 695111, overlap = 149.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000324574
+PHY-3002 : Step(304): len = 699498, overlap = 142.25
+PHY-3002 : Step(305): len = 703700, overlap = 141
+PHY-3002 : Step(306): len = 703915, overlap = 146.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000647699
+PHY-3002 : Step(307): len = 707054, overlap = 145
+PHY-3002 : Step(308): len = 716390, overlap = 140.75
+PHY-3002 : Step(309): len = 721020, overlap = 141.75
+PHY-3002 : Step(310): len = 719780, overlap = 143
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.038841s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (120.7%)
+
+PHY-3001 : Legalized: Len = 747293, Over = 0
+PHY-3001 : Spreading special nets. 499 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.120156s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (104.0%)
+
+PHY-3001 : 713 instances has been re-located, deltaX = 244, deltaY = 423, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 757377, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72666, tnet num: 17813, tinst num: 6827, tnode num: 95066, tedge num: 120596.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.067334s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (97.5%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 635 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4336/17991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 888376, over cnt = 2515(7%), over = 4109, worst = 8
+PHY-1002 : len = 902696, over cnt = 1504(4%), over = 2141, worst = 7
+PHY-1002 : len = 917784, over cnt = 681(1%), over = 941, worst = 7
+PHY-1002 : len = 927200, over cnt = 226(0%), over = 319, worst = 5
+PHY-1002 : len = 930888, over cnt = 29(0%), over = 44, worst = 3
+PHY-1001 : End global iterations; 2.448214s wall, 3.515625s user + 0.031250s system = 3.546875s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 57.39, top5 = 51.33, top10 = 47.87, top15 = 45.62.
+PHY-1001 : End incremental global routing; 2.875193s wall, 3.937500s user + 0.031250s system = 3.968750s CPU (138.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.985996s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (99.8%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6735 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6844 instances, 6695 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3596 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 760533
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16337/18016.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934424, over cnt = 97(0%), over = 123, worst = 3
+PHY-1002 : len = 934808, over cnt = 43(0%), over = 48, worst = 2
+PHY-1002 : len = 935104, over cnt = 16(0%), over = 17, worst = 2
+PHY-1002 : len = 935352, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 935376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.007241s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.3%)
+
+PHY-1001 : Congestion index: top1 = 57.41, top5 = 51.45, top10 = 47.99, top15 = 45.74.
+PHY-3001 : End congestion estimation; 1.399777s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (100.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72849, tnet num: 17838, tinst num: 6844, tnode num: 95298, tedge num: 120853.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.059377s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (97.9%)
+
+RUN-1004 : used memory is 688 MB, reserved memory is 680 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17838 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.779468s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (79.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(311): len = 759685, overlap = 0
+PHY-3002 : Step(312): len = 759372, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16335/18016.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934096, over cnt = 36(0%), over = 57, worst = 6
+PHY-1002 : len = 934312, over cnt = 20(0%), over = 23, worst = 2
+PHY-1002 : len = 934568, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 934616, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 934640, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.915798s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (97.3%)
+
+PHY-1001 : Congestion index: top1 = 57.37, top5 = 51.32, top10 = 47.88, top15 = 45.66.
+PHY-3001 : End congestion estimation; 1.282649s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (98.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17838 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.964108s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000349276
+PHY-3002 : Step(313): len = 759299, overlap = 1
+PHY-3002 : Step(314): len = 759184, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005763s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (271.1%)
+
+PHY-3001 : Legalized: Len = 759221, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.086789s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (108.0%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 759285, Over = 0
+PHY-3001 : End incremental placement; 8.015037s wall, 7.171875s user + 0.062500s system = 7.234375s CPU (90.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 12.599955s wall, 12.859375s user + 0.125000s system = 12.984375s CPU (103.1%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 735, peak = 742.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16322/18016.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934312, over cnt = 39(0%), over = 51, worst = 3
+PHY-1002 : len = 934416, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 934488, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 934536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.719825s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (104.2%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 51.30, top10 = 47.87, top15 = 45.63.
+OPT-1001 : End congestion update; 1.086832s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (102.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17838 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.832167s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.5%)
+
+OPT-0007 : Start: WNS -499 TNS -1455 NUM_FEPS 7
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6756 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6844 instances, 6695 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3596 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 763980, Over = 0
+PHY-3001 : Spreading special nets. 27 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.074703s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (104.6%)
+
+PHY-3001 : 37 instances has been re-located, deltaX = 33, deltaY = 24, maxDist = 5.
+PHY-3001 : Final: Len = 764916, Over = 0
+PHY-3001 : End incremental legalization; 0.464649s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (97.5%)
+
+OPT-0007 : Iter 1: improved WNS -249 TNS -308 NUM_FEPS 4 with 54 cells processed and 17093 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6756 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6844 instances, 6695 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3596 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 766652, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.113638s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (68.7%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 11, deltaY = 19, maxDist = 5.
+PHY-3001 : Final: Len = 767664, Over = 0
+PHY-3001 : End incremental legalization; 0.486259s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (93.2%)
+
+OPT-0007 : Iter 2: improved WNS -249 TNS -308 NUM_FEPS 4 with 17 cells processed and 4400 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6756 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6844 instances, 6695 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3596 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 767100, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.075662s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (82.6%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 10, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 767270, Over = 0
+PHY-3001 : End incremental legalization; 0.488265s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (112.0%)
+
+OPT-0007 : Iter 3: improved WNS -249 TNS -308 NUM_FEPS 4 with 11 cells processed and 300 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6759 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6847 instances, 6698 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 767566, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.073949s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (84.5%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 4.
+PHY-3001 : Final: Len = 767766, Over = 0
+PHY-3001 : End incremental legalization; 0.461016s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (98.3%)
+
+OPT-0007 : Iter 4: improved WNS -249 TNS -657 NUM_FEPS 7 with 3 cells processed and 450 slack improved
+OPT-1001 : End bottleneck based optimization; 4.576333s wall, 4.812500s user + 0.015625s system = 4.828125s CPU (105.5%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 738, peak = 744.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15995/18019.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 943144, over cnt = 153(0%), over = 212, worst = 6
+PHY-1002 : len = 943568, over cnt = 75(0%), over = 79, worst = 4
+PHY-1002 : len = 944128, over cnt = 31(0%), over = 32, worst = 2
+PHY-1002 : len = 944784, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 944832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.068836s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (109.6%)
+
+PHY-1001 : Congestion index: top1 = 56.70, top5 = 51.16, top10 = 47.83, top15 = 45.60.
+OPT-1001 : End congestion update; 1.443699s wall, 1.500000s user + 0.031250s system = 1.531250s CPU (106.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.814315s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.8%)
+
+OPT-0007 : Start: WNS -399 TNS -2063 NUM_FEPS 7
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6759 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6847 instances, 6698 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 782742, Over = 0
+PHY-3001 : Spreading special nets. 26 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.074774s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (83.6%)
+
+PHY-3001 : 31 instances has been re-located, deltaX = 24, deltaY = 21, maxDist = 5.
+PHY-3001 : Final: Len = 783578, Over = 0
+PHY-3001 : End incremental legalization; 0.453139s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (96.5%)
+
+OPT-0007 : Iter 1: improved WNS -199 TNS -221 NUM_FEPS 2 with 92 cells processed and 26364 slack improved
+OPT-0007 : Iter 2: improved WNS -199 TNS -221 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.044341s wall, 3.187500s user + 0.031250s system = 3.218750s CPU (105.7%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 738, peak = 744.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804282s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16036/18019.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 959464, over cnt = 209(0%), over = 265, worst = 4
+PHY-1002 : len = 959464, over cnt = 120(0%), over = 142, worst = 2
+PHY-1002 : len = 960296, over cnt = 37(0%), over = 46, worst = 2
+PHY-1002 : len = 960920, over cnt = 7(0%), over = 8, worst = 2
+PHY-1002 : len = 961048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.020551s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 57.09, top5 = 51.51, top10 = 48.17, top15 = 45.90.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804080s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.0%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -349 TNS -626 NUM_FEPS 7
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.655172
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -349ps with logic level 7
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 18019 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18019 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6759 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6847 instances, 6698 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 783578, Over = 0
+PHY-3001 : End spreading; 0.065795s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.0%)
+
+PHY-3001 : Final: Len = 783578, Over = 0
+PHY-3001 : End incremental legalization; 0.439825s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (120.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.811356s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.1%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16358/18019.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 961048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.152857s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.2%)
+
+PHY-1001 : Congestion index: top1 = 57.09, top5 = 51.51, top10 = 48.17, top15 = 45.90.
+OPT-1001 : End congestion update; 0.529830s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.828383s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.0%)
+
+OPT-0007 : Start: WNS -349 TNS -626 NUM_FEPS 7
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6759 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6847 instances, 6698 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 783536, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.071877s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (108.7%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 5, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 783588, Over = 0
+PHY-3001 : End incremental legalization; 0.532830s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (96.8%)
+
+OPT-0007 : Iter 1: improved WNS -199 TNS -199 NUM_FEPS 1 with 6 cells processed and 384 slack improved
+OPT-0007 : Iter 2: improved WNS -199 TNS -199 NUM_FEPS 1 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.086495s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (98.8%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 738, peak = 744.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16340/18019.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 961064, over cnt = 12(0%), over = 13, worst = 2
+PHY-1002 : len = 961104, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 961152, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.507636s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (98.5%)
+
+PHY-1001 : Congestion index: top1 = 57.09, top5 = 51.50, top10 = 48.16, top15 = 45.91.
+OPT-1001 : End congestion update; 0.875656s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804612s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.0%)
+
+OPT-0007 : Start: WNS -349 TNS -529 NUM_FEPS 7
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6759 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6847 instances, 6698 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 783706, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065605s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.3%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 1, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 784100, Over = 0
+PHY-3001 : End incremental legalization; 0.437297s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (110.8%)
+
+OPT-0007 : Iter 1: improved WNS -249 TNS -409 NUM_FEPS 3 with 4 cells processed and 400 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6759 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6847 instances, 6698 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 783942, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066329s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.8%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 784012, Over = 0
+PHY-3001 : End incremental legalization; 0.444184s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (95.0%)
+
+OPT-0007 : Iter 2: improved WNS -249 TNS -547 NUM_FEPS 5 with 2 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -249 TNS -547 NUM_FEPS 5 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.896641s wall, 3.125000s user + 0.000000s system = 3.125000s CPU (107.9%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 738, peak = 744.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.843795s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (96.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 741, reserve = 738, peak = 744.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17840 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.803584s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.1%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16330/18019.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 961544, over cnt = 15(0%), over = 20, worst = 3
+PHY-1002 : len = 961568, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 961632, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 961664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.705670s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.6%)
+
+PHY-1001 : Congestion index: top1 = 57.09, top5 = 51.50, top10 = 48.16, top15 = 45.92.
+RUN-1001 : End congestion update; 1.076587s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (98.7%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.885583s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.4%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 738, peak = 744.
+OPT-1001 : End physical optimization; 34.884384s wall, 35.656250s user + 0.218750s system = 35.875000s CPU (102.8%)
+
+RUN-1003 : finish command "place" in 86.827428s wall, 118.046875s user + 6.578125s system = 124.625000s CPU (143.5%)
+
+RUN-1004 : used memory is 688 MB, reserved memory is 689 MB, peak memory is 744 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 2.222829s wall, 3.000000s user + 0.031250s system = 3.031250s CPU (136.4%)
+
+RUN-1004 : used memory is 688 MB, reserved memory is 689 MB, peak memory is 744 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6849 instances
+RUN-1001 : 3351 mslices, 3347 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18019 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9819 nets have 2 pins
+RUN-1001 : 6807 nets have [3 - 5] pins
+RUN-1001 : 737 nets have [6 - 10] pins
+RUN-1001 : 292 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72878, tnet num: 17841, tinst num: 6847, tnode num: 95339, tedge num: 120895.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.812376s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (96.6%)
+
+RUN-1004 : used memory is 667 MB, reserved memory is 668 MB, peak memory is 744 MB
+PHY-1001 : 3351 mslices, 3347 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17841 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891280, over cnt = 2760(7%), over = 4520, worst = 9
+PHY-1002 : len = 907264, over cnt = 1734(4%), over = 2570, worst = 9
+PHY-1002 : len = 927096, over cnt = 666(1%), over = 977, worst = 6
+PHY-1002 : len = 942320, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 942480, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.349298s wall, 4.375000s user + 0.015625s system = 4.390625s CPU (131.1%)
+
+PHY-1001 : Congestion index: top1 = 57.33, top5 = 51.31, top10 = 47.83, top15 = 45.53.
+PHY-1001 : End global routing; 3.730216s wall, 4.750000s user + 0.015625s system = 4.765625s CPU (127.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 716, reserve = 717, peak = 744.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 988, peak = 988.
+PHY-1001 : End build detailed router design. 4.418929s wall, 4.328125s user + 0.015625s system = 4.343750s CPU (98.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270592, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.724552s wall, 6.593750s user + 0.015625s system = 6.609375s CPU (98.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270648, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.558118s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (100.8%)
+
+PHY-1001 : Current memory(MB): used = 1023, reserve = 1024, peak = 1023.
+PHY-1001 : End phase 1; 7.296921s wall, 7.171875s user + 0.015625s system = 7.187500s CPU (98.5%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.3757e+06, over cnt = 1786(0%), over = 1797, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1041, peak = 1040.
+PHY-1001 : End initial routed; 40.262837s wall, 81.468750s user + 0.390625s system = 81.859375s CPU (203.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 48/16942(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -3.154 | -23.818 | 14
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.723870s wall, 3.703125s user + 0.000000s system = 3.703125s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1056, peak = 1054.
+PHY-1001 : End phase 2; 43.986775s wall, 85.171875s user + 0.390625s system = 85.562500s CPU (194.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 10 pins with SWNS -3.031ns STNS -23.667ns FEP 14.
+PHY-1001 : End OPT Iter 1; 0.187574s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.0%)
+
+PHY-1022 : len = 2.37573e+06, over cnt = 1789(0%), over = 1800, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.497186s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (100.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34479e+06, over cnt = 791(0%), over = 795, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.968819s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (169.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34032e+06, over cnt = 163(0%), over = 163, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.044269s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (140.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.3407e+06, over cnt = 27(0%), over = 27, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.661737s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (118.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34104e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.334277s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (93.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34102e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.374045s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.34098e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.509930s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.34098e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.506506s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.8%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.193996s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.34098e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.189319s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.34098e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.222772s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.34098e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.224570s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (111.3%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.34102e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 12; 0.184883s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 48/16942(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -3.032 | -23.668 | 14
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.677515s wall, 3.578125s user + 0.031250s system = 3.609375s CPU (98.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 581 feed throughs used by 417 nets
+PHY-1001 : End commit to database; 2.451584s wall, 2.421875s user + 0.031250s system = 2.453125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1160, peak = 1154.
+PHY-1001 : End phase 3; 13.538698s wall, 15.250000s user + 0.093750s system = 15.343750s CPU (113.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 8 pins with SWNS -2.899ns STNS -22.875ns FEP 14.
+PHY-1001 : End OPT Iter 1; 0.195365s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.0%)
+
+PHY-1022 : len = 2.34101e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.512583s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (97.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.899ns, -22.875ns, 14}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.198512s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34102e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.194189s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 48/16942(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.899 | -23.314 | 14
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.704007s wall, 3.593750s user + 0.015625s system = 3.609375s CPU (97.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 583 feed throughs used by 419 nets
+PHY-1001 : End commit to database; 2.605307s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (97.2%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1168, peak = 1162.
+PHY-1001 : End phase 4; 7.278838s wall, 7.093750s user + 0.015625s system = 7.109375s CPU (97.7%)
+
+PHY-1003 : Routed, final wirelength = 2.34102e+06
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1171, peak = 1165.
+PHY-1001 : End export database. 0.067900s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.0%)
+
+PHY-1001 : End detail routing; 77.024767s wall, 119.500000s user + 0.531250s system = 120.031250s CPU (155.8%)
+
+RUN-1003 : finish command "route" in 83.800206s wall, 127.171875s user + 0.562500s system = 127.734375s CPU (152.4%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1093 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10431 out of 19600 53.22%
+#reg 9416 out of 19600 48.04%
+#le 12472
+ #lut only 3056 out of 12472 24.50%
+ #reg only 2041 out of 12472 16.36%
+ #lut® 7375 out of 12472 59.13%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1790
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1406
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1296
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 969
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 133
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 75
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/u_ADconfig/reg1_syn_182.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg46_syn_201.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P170 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12472 |9404 |1027 |9447 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |526 |437 |23 |452 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |97 |82 |4 |89 |4 |0 |
+| U_ecc_gen |ecc_gen |8 |8 |0 |6 |0 |0 |
+| U_crc16_24b |crc16_24b |42 |42 |0 |23 |0 |0 |
+| exdev_ctl_a |exdev_ctl |755 |385 |96 |579 |0 |0 |
+| u_ADconfig |AD_config |181 |115 |25 |140 |0 |0 |
+| u_gen_sp |gen_sp |254 |145 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |734 |384 |96 |557 |0 |0 |
+| u_ADconfig |AD_config |169 |121 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |250 |159 |71 |116 |0 |0 |
+| sampling_fe_a |sampling_fe |3060 |2538 |306 |2034 |25 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |176 |124 |17 |145 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2851 |2402 |289 |1856 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2419 |2050 |253 |1501 |22 |0 |
+| channelPart |channel_part_8478 |133 |129 |3 |127 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1920 |1613 |197 |1111 |0 |0 |
+| adc_addr_gen |adc_addr_gen |216 |189 |27 |99 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |10 |0 |0 |
+| insert |insert |943 |663 |170 |646 |0 |0 |
+| ram_switch_state |ram_switch_state |761 |761 |0 |366 |0 |0 |
+| read_ram_i |read_ram |283 |238 |44 |194 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |154 |0 |0 |
+| read_ram_data |read_ram_data |52 |48 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |305 |242 |36 |265 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3216 |2538 |349 |2071 |25 |1 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |173 |104 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |3008 |2427 |332 |1892 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2588 |2095 |290 |1543 |22 |1 |
+| channelPart |channel_part_8478 |163 |157 |3 |129 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1960 |1602 |197 |1124 |0 |0 |
+| adc_addr_gen |adc_addr_gen |200 |173 |27 |102 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |16 |13 |3 |8 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |16 |13 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |19 |16 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| insert |insert |986 |656 |170 |677 |0 |0 |
+| ram_switch_state |ram_switch_state |774 |773 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |368 |255 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |307 |222 |73 |168 |0 |0 |
+| read_ram_data |read_ram_data_rev |61 |33 |8 |44 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9757
+ #2 2 4391
+ #3 3 1842
+ #4 4 571
+ #5 5-10 773
+ #6 11-50 574
+ #7 51-100 15
+ #8 >500 1
+ Average 2.76
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.296000s wall, 3.812500s user + 0.031250s system = 3.843750s CPU (167.4%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1094 MB, peak memory is 1165 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72878, tnet num: 17841, tinst num: 6847, tnode num: 95339, tedge num: 120895.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.765371s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.0%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1098 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17841 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.714603s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (97.5%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1101 MB, peak memory is 1165 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6847
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18019, pip num: 172776
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 583
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3256 valid insts, and 480417 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.463876s wall, 63.734375s user + 0.281250s system = 64.015625s CPU (611.8%)
+
+RUN-1004 : used memory is 1257 MB, reserved memory is 1257 MB, peak memory is 1372 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240314_173157.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_092411.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_092411.log
new file mode 100644
index 0000000..8428dc6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_092411.log
@@ -0,0 +1,2041 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 09:24:11 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.195754s wall, 2.125000s user + 0.062500s system = 2.187500s CPU (99.6%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 316 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17986 instances
+RUN-0007 : 7661 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20564 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13082 nets have 2 pins
+RUN-1001 : 6444 nets have [3 - 5] pins
+RUN-1001 : 620 nets have [6 - 10] pins
+RUN-1001 : 181 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17984 instances, 7661 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.146799s wall, 1.093750s user + 0.031250s system = 1.125000s CPU (98.1%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 514 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.927433s wall, 1.859375s user + 0.046875s system = 1.906250s CPU (98.9%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11825e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17984.
+PHY-3001 : Level 1 #clusters 2051.
+PHY-3001 : End clustering; 0.130115s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32681e+06, overlap = 447.375
+PHY-3002 : Step(2): len = 1.21277e+06, overlap = 492.031
+PHY-3002 : Step(3): len = 854256, overlap = 571.531
+PHY-3002 : Step(4): len = 796625, overlap = 595.094
+PHY-3002 : Step(5): len = 625051, overlap = 763.906
+PHY-3002 : Step(6): len = 553878, overlap = 846.75
+PHY-3002 : Step(7): len = 475465, overlap = 919.25
+PHY-3002 : Step(8): len = 435213, overlap = 966.5
+PHY-3002 : Step(9): len = 396311, overlap = 1029.19
+PHY-3002 : Step(10): len = 370878, overlap = 1031.53
+PHY-3002 : Step(11): len = 325662, overlap = 1075.22
+PHY-3002 : Step(12): len = 307603, overlap = 1115.06
+PHY-3002 : Step(13): len = 270358, overlap = 1170.19
+PHY-3002 : Step(14): len = 253854, overlap = 1221.72
+PHY-3002 : Step(15): len = 229490, overlap = 1275.16
+PHY-3002 : Step(16): len = 213861, overlap = 1309.06
+PHY-3002 : Step(17): len = 190508, overlap = 1330.88
+PHY-3002 : Step(18): len = 179455, overlap = 1361.78
+PHY-3002 : Step(19): len = 165284, overlap = 1392.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.31406e-06
+PHY-3002 : Step(20): len = 165466, overlap = 1346.91
+PHY-3002 : Step(21): len = 202919, overlap = 1205.69
+PHY-3002 : Step(22): len = 211139, overlap = 1153.94
+PHY-3002 : Step(23): len = 217503, overlap = 1084.84
+PHY-3002 : Step(24): len = 217194, overlap = 1057.38
+PHY-3002 : Step(25): len = 213766, overlap = 1039.53
+PHY-3002 : Step(26): len = 209686, overlap = 1019.31
+PHY-3002 : Step(27): len = 205682, overlap = 1025.91
+PHY-3002 : Step(28): len = 202366, overlap = 1025.41
+PHY-3002 : Step(29): len = 198815, overlap = 1041.31
+PHY-3002 : Step(30): len = 196891, overlap = 1048.53
+PHY-3002 : Step(31): len = 192947, overlap = 1032.38
+PHY-3002 : Step(32): len = 190652, overlap = 1028.38
+PHY-3002 : Step(33): len = 188982, overlap = 1047.53
+PHY-3002 : Step(34): len = 188856, overlap = 1050.19
+PHY-3002 : Step(35): len = 187822, overlap = 1046.66
+PHY-3002 : Step(36): len = 187691, overlap = 1043.84
+PHY-3002 : Step(37): len = 186699, overlap = 1045.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.62811e-06
+PHY-3002 : Step(38): len = 190190, overlap = 1023.97
+PHY-3002 : Step(39): len = 200878, overlap = 998
+PHY-3002 : Step(40): len = 204969, overlap = 973.031
+PHY-3002 : Step(41): len = 210699, overlap = 962.406
+PHY-3002 : Step(42): len = 213685, overlap = 962.031
+PHY-3002 : Step(43): len = 214913, overlap = 971.312
+PHY-3002 : Step(44): len = 214129, overlap = 962.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.25623e-06
+PHY-3002 : Step(45): len = 222317, overlap = 945.719
+PHY-3002 : Step(46): len = 241846, overlap = 887.062
+PHY-3002 : Step(47): len = 250733, overlap = 810.094
+PHY-3002 : Step(48): len = 259458, overlap = 764.75
+PHY-3002 : Step(49): len = 264898, overlap = 729.594
+PHY-3002 : Step(50): len = 268782, overlap = 717.594
+PHY-3002 : Step(51): len = 268659, overlap = 693.25
+PHY-3002 : Step(52): len = 267038, overlap = 699.969
+PHY-3002 : Step(53): len = 265608, overlap = 708.531
+PHY-3002 : Step(54): len = 263857, overlap = 714.938
+PHY-3002 : Step(55): len = 262442, overlap = 716.219
+PHY-3002 : Step(56): len = 261697, overlap = 712.75
+PHY-3002 : Step(57): len = 261651, overlap = 701.625
+PHY-3002 : Step(58): len = 261227, overlap = 706.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.05125e-05
+PHY-3002 : Step(59): len = 276346, overlap = 609.156
+PHY-3002 : Step(60): len = 291797, overlap = 571.688
+PHY-3002 : Step(61): len = 297779, overlap = 568.531
+PHY-3002 : Step(62): len = 301292, overlap = 564.406
+PHY-3002 : Step(63): len = 299531, overlap = 563.281
+PHY-3002 : Step(64): len = 300587, overlap = 555.219
+PHY-3002 : Step(65): len = 301742, overlap = 556.719
+PHY-3002 : Step(66): len = 303460, overlap = 538.031
+PHY-3002 : Step(67): len = 301977, overlap = 542.531
+PHY-3002 : Step(68): len = 300507, overlap = 528.469
+PHY-3002 : Step(69): len = 299876, overlap = 522.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.10249e-05
+PHY-3002 : Step(70): len = 318230, overlap = 482.656
+PHY-3002 : Step(71): len = 329376, overlap = 452.5
+PHY-3002 : Step(72): len = 333339, overlap = 419.688
+PHY-3002 : Step(73): len = 334752, overlap = 392.281
+PHY-3002 : Step(74): len = 333824, overlap = 357.469
+PHY-3002 : Step(75): len = 335637, overlap = 379.844
+PHY-3002 : Step(76): len = 334442, overlap = 390.5
+PHY-3002 : Step(77): len = 334205, overlap = 407.562
+PHY-3002 : Step(78): len = 334333, overlap = 392.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.20498e-05
+PHY-3002 : Step(79): len = 350059, overlap = 360.938
+PHY-3002 : Step(80): len = 361689, overlap = 339.031
+PHY-3002 : Step(81): len = 364498, overlap = 329.688
+PHY-3002 : Step(82): len = 368120, overlap = 324.688
+PHY-3002 : Step(83): len = 371135, overlap = 305.406
+PHY-3002 : Step(84): len = 373997, overlap = 280.5
+PHY-3002 : Step(85): len = 371594, overlap = 279.188
+PHY-3002 : Step(86): len = 373031, overlap = 280.469
+PHY-3002 : Step(87): len = 374790, overlap = 279.188
+PHY-3002 : Step(88): len = 376019, overlap = 266.062
+PHY-3002 : Step(89): len = 375474, overlap = 260.156
+PHY-3002 : Step(90): len = 377506, overlap = 264.469
+PHY-3002 : Step(91): len = 379997, overlap = 270.062
+PHY-3002 : Step(92): len = 381499, overlap = 250.094
+PHY-3002 : Step(93): len = 378396, overlap = 252.562
+PHY-3002 : Step(94): len = 378137, overlap = 257.031
+PHY-3002 : Step(95): len = 377776, overlap = 258.812
+PHY-3002 : Step(96): len = 378238, overlap = 260.094
+PHY-3002 : Step(97): len = 377541, overlap = 259.375
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.40997e-05
+PHY-3002 : Step(98): len = 393731, overlap = 263.688
+PHY-3002 : Step(99): len = 403714, overlap = 270.438
+PHY-3002 : Step(100): len = 402161, overlap = 260.656
+PHY-3002 : Step(101): len = 403139, overlap = 265.25
+PHY-3002 : Step(102): len = 406115, overlap = 263.562
+PHY-3002 : Step(103): len = 409921, overlap = 261.969
+PHY-3002 : Step(104): len = 409057, overlap = 261.656
+PHY-3002 : Step(105): len = 411247, overlap = 265.344
+PHY-3002 : Step(106): len = 415044, overlap = 267.875
+PHY-3002 : Step(107): len = 417805, overlap = 267
+PHY-3002 : Step(108): len = 414534, overlap = 279.844
+PHY-3002 : Step(109): len = 413890, overlap = 267.531
+PHY-3002 : Step(110): len = 415583, overlap = 257.938
+PHY-3002 : Step(111): len = 417219, overlap = 249.938
+PHY-3002 : Step(112): len = 413916, overlap = 234.875
+PHY-3002 : Step(113): len = 414176, overlap = 247.031
+PHY-3002 : Step(114): len = 415397, overlap = 239.5
+PHY-3002 : Step(115): len = 416638, overlap = 231.375
+PHY-3002 : Step(116): len = 414219, overlap = 227.656
+PHY-3002 : Step(117): len = 414070, overlap = 224.562
+PHY-3002 : Step(118): len = 415000, overlap = 225.969
+PHY-3002 : Step(119): len = 416356, overlap = 230.719
+PHY-3002 : Step(120): len = 414329, overlap = 243.5
+PHY-3002 : Step(121): len = 414525, overlap = 240.781
+PHY-3002 : Step(122): len = 415219, overlap = 251.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168199
+PHY-3002 : Step(123): len = 427793, overlap = 228.094
+PHY-3002 : Step(124): len = 434978, overlap = 211.5
+PHY-3002 : Step(125): len = 434224, overlap = 212.938
+PHY-3002 : Step(126): len = 434893, overlap = 214.719
+PHY-3002 : Step(127): len = 437387, overlap = 214.312
+PHY-3002 : Step(128): len = 440422, overlap = 218.344
+PHY-3002 : Step(129): len = 439475, overlap = 220.5
+PHY-3002 : Step(130): len = 439959, overlap = 218.125
+PHY-3002 : Step(131): len = 442104, overlap = 214.969
+PHY-3002 : Step(132): len = 443728, overlap = 215.188
+PHY-3002 : Step(133): len = 442552, overlap = 226.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000315424
+PHY-3002 : Step(134): len = 449199, overlap = 215
+PHY-3002 : Step(135): len = 456791, overlap = 208.969
+PHY-3002 : Step(136): len = 458741, overlap = 221.25
+PHY-3002 : Step(137): len = 460138, overlap = 210.938
+PHY-3002 : Step(138): len = 461978, overlap = 206.938
+PHY-3002 : Step(139): len = 463732, overlap = 200.469
+PHY-3002 : Step(140): len = 463075, overlap = 203.844
+PHY-3002 : Step(141): len = 464420, overlap = 206.25
+PHY-3002 : Step(142): len = 466826, overlap = 197.656
+PHY-3002 : Step(143): len = 468395, overlap = 196.719
+PHY-3002 : Step(144): len = 468161, overlap = 197.438
+PHY-3002 : Step(145): len = 468919, overlap = 193.844
+PHY-3002 : Step(146): len = 470408, overlap = 190.969
+PHY-3002 : Step(147): len = 471038, overlap = 194.094
+PHY-3002 : Step(148): len = 470098, overlap = 194.125
+PHY-3002 : Step(149): len = 469787, overlap = 192.844
+PHY-3002 : Step(150): len = 470962, overlap = 194.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000597386
+PHY-3002 : Step(151): len = 477356, overlap = 187.469
+PHY-3002 : Step(152): len = 485467, overlap = 177.438
+PHY-3002 : Step(153): len = 487792, overlap = 172.25
+PHY-3002 : Step(154): len = 489820, overlap = 169.969
+PHY-3002 : Step(155): len = 492289, overlap = 166.719
+PHY-3002 : Step(156): len = 494288, overlap = 161.812
+PHY-3002 : Step(157): len = 494621, overlap = 167.094
+PHY-3002 : Step(158): len = 495412, overlap = 158.875
+PHY-3002 : Step(159): len = 497530, overlap = 158.125
+PHY-3002 : Step(160): len = 499660, overlap = 161.844
+PHY-3002 : Step(161): len = 499659, overlap = 155.344
+PHY-3002 : Step(162): len = 500171, overlap = 145.469
+PHY-3002 : Step(163): len = 501354, overlap = 144.875
+PHY-3002 : Step(164): len = 502419, overlap = 141.625
+PHY-3002 : Step(165): len = 502507, overlap = 135.938
+PHY-3002 : Step(166): len = 502911, overlap = 136.219
+PHY-3002 : Step(167): len = 503441, overlap = 133.781
+PHY-3002 : Step(168): len = 503676, overlap = 133.844
+PHY-3002 : Step(169): len = 503613, overlap = 131.625
+PHY-3002 : Step(170): len = 503662, overlap = 133.656
+PHY-3002 : Step(171): len = 503864, overlap = 139.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108125
+PHY-3002 : Step(172): len = 508017, overlap = 138.406
+PHY-3002 : Step(173): len = 515100, overlap = 140.438
+PHY-3002 : Step(174): len = 516366, overlap = 136.719
+PHY-3002 : Step(175): len = 517528, overlap = 132.312
+PHY-3002 : Step(176): len = 519652, overlap = 132.719
+PHY-3002 : Step(177): len = 520672, overlap = 132.875
+PHY-3002 : Step(178): len = 520221, overlap = 132.375
+PHY-3002 : Step(179): len = 520126, overlap = 135.25
+PHY-3002 : Step(180): len = 521307, overlap = 133.188
+PHY-3002 : Step(181): len = 522214, overlap = 132.5
+PHY-3002 : Step(182): len = 521960, overlap = 133.5
+PHY-3002 : Step(183): len = 521951, overlap = 135.812
+PHY-3002 : Step(184): len = 522274, overlap = 134.25
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00187339
+PHY-3002 : Step(185): len = 525598, overlap = 136.688
+PHY-3002 : Step(186): len = 531982, overlap = 134.781
+PHY-3002 : Step(187): len = 533798, overlap = 129.438
+PHY-3002 : Step(188): len = 534889, overlap = 126.938
+PHY-3002 : Step(189): len = 535931, overlap = 126.094
+PHY-3002 : Step(190): len = 536614, overlap = 125.531
+PHY-3002 : Step(191): len = 537630, overlap = 128.594
+PHY-3002 : Step(192): len = 538953, overlap = 129.156
+PHY-3002 : Step(193): len = 539831, overlap = 128.594
+PHY-3002 : Step(194): len = 540970, overlap = 124.75
+PHY-3002 : Step(195): len = 542306, overlap = 125.406
+PHY-3002 : Step(196): len = 542817, overlap = 125.406
+PHY-3002 : Step(197): len = 543125, overlap = 123.969
+PHY-3002 : Step(198): len = 543331, overlap = 123.969
+PHY-3002 : Step(199): len = 543607, overlap = 125.344
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00307474
+PHY-3002 : Step(200): len = 546970, overlap = 124.781
+PHY-3002 : Step(201): len = 555249, overlap = 108.75
+PHY-3002 : Step(202): len = 560298, overlap = 101.938
+PHY-3002 : Step(203): len = 566036, overlap = 104.688
+PHY-3002 : Step(204): len = 569242, overlap = 103.969
+PHY-3002 : Step(205): len = 572082, overlap = 105.062
+PHY-3002 : Step(206): len = 573488, overlap = 100.906
+PHY-3002 : Step(207): len = 574436, overlap = 101.594
+PHY-3002 : Step(208): len = 574997, overlap = 98.375
+PHY-3002 : Step(209): len = 575327, overlap = 96.875
+PHY-3002 : Step(210): len = 575154, overlap = 96.2812
+PHY-3002 : Step(211): len = 574947, overlap = 90.3438
+PHY-3002 : Step(212): len = 574615, overlap = 96.1562
+PHY-3002 : Step(213): len = 574424, overlap = 96.1562
+PHY-3002 : Step(214): len = 574285, overlap = 91.1562
+PHY-3002 : Step(215): len = 574158, overlap = 90.1562
+PHY-3002 : Step(216): len = 573866, overlap = 87.6562
+PHY-3002 : Step(217): len = 573742, overlap = 90.125
+PHY-3002 : Step(218): len = 573607, overlap = 89.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.016138s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (96.8%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753960, over cnt = 1673(4%), over = 7641, worst = 41
+PHY-1001 : End global iterations; 0.702252s wall, 0.937500s user + 0.046875s system = 0.984375s CPU (140.2%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 63.38, top10 = 53.94, top15 = 48.26.
+PHY-3001 : End congestion estimation; 0.955643s wall, 1.203125s user + 0.046875s system = 1.250000s CPU (130.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.857965s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012894
+PHY-3002 : Step(219): len = 682872, overlap = 60.7812
+PHY-3002 : Step(220): len = 680164, overlap = 61.5
+PHY-3002 : Step(221): len = 671439, overlap = 58.2812
+PHY-3002 : Step(222): len = 665226, overlap = 60.6875
+PHY-3002 : Step(223): len = 663081, overlap = 55.8438
+PHY-3002 : Step(224): len = 662916, overlap = 53.5938
+PHY-3002 : Step(225): len = 660482, overlap = 53.4375
+PHY-3002 : Step(226): len = 656745, overlap = 53.25
+PHY-3002 : Step(227): len = 653517, overlap = 53.7188
+PHY-3002 : Step(228): len = 651915, overlap = 50.4688
+PHY-3002 : Step(229): len = 650566, overlap = 43.9375
+PHY-3002 : Step(230): len = 649789, overlap = 39.6562
+PHY-3002 : Step(231): len = 649010, overlap = 39.6875
+PHY-3002 : Step(232): len = 648983, overlap = 36.4375
+PHY-3002 : Step(233): len = 648835, overlap = 39.7188
+PHY-3002 : Step(234): len = 649183, overlap = 37.0625
+PHY-3002 : Step(235): len = 647443, overlap = 37.6562
+PHY-3002 : Step(236): len = 646551, overlap = 37.75
+PHY-3002 : Step(237): len = 644304, overlap = 38.4688
+PHY-3002 : Step(238): len = 642657, overlap = 46.9062
+PHY-3002 : Step(239): len = 640494, overlap = 55.25
+PHY-3002 : Step(240): len = 638385, overlap = 57.375
+PHY-3002 : Step(241): len = 636246, overlap = 62.2812
+PHY-3002 : Step(242): len = 634318, overlap = 64.0625
+PHY-3002 : Step(243): len = 632554, overlap = 66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025788
+PHY-3002 : Step(244): len = 636935, overlap = 63.2812
+PHY-3002 : Step(245): len = 642468, overlap = 58.875
+PHY-3002 : Step(246): len = 644067, overlap = 55.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479888
+PHY-3002 : Step(247): len = 655065, overlap = 49.3125
+PHY-3002 : Step(248): len = 673391, overlap = 48.2188
+PHY-3002 : Step(249): len = 686922, overlap = 44.4375
+PHY-3002 : Step(250): len = 689884, overlap = 43.6875
+PHY-3002 : Step(251): len = 689070, overlap = 41.375
+PHY-3002 : Step(252): len = 686972, overlap = 40.5625
+PHY-3002 : Step(253): len = 686400, overlap = 38.8438
+PHY-3002 : Step(254): len = 686300, overlap = 37.125
+PHY-3002 : Step(255): len = 687195, overlap = 36.875
+PHY-3002 : Step(256): len = 688672, overlap = 36.3125
+PHY-3002 : Step(257): len = 687776, overlap = 38.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000959777
+PHY-3002 : Step(258): len = 693185, overlap = 37.9375
+PHY-3002 : Step(259): len = 707793, overlap = 42.5625
+PHY-3002 : Step(260): len = 721904, overlap = 45.25
+PHY-3002 : Step(261): len = 720538, overlap = 45.125
+PHY-3002 : Step(262): len = 718584, overlap = 47.0625
+PHY-3002 : Step(263): len = 718363, overlap = 47.125
+PHY-3002 : Step(264): len = 719234, overlap = 46.2812
+PHY-3002 : Step(265): len = 718781, overlap = 48.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00167098
+PHY-3002 : Step(266): len = 722104, overlap = 49.2188
+PHY-3002 : Step(267): len = 730523, overlap = 49.75
+PHY-3002 : Step(268): len = 737525, overlap = 49.1875
+PHY-3002 : Step(269): len = 740778, overlap = 49.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 74/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825680, over cnt = 2877(8%), over = 14308, worst = 47
+PHY-1001 : End global iterations; 1.511790s wall, 2.046875s user + 0.062500s system = 2.109375s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 102.03, top5 = 79.19, top10 = 68.21, top15 = 61.55.
+PHY-3001 : End congestion estimation; 1.788296s wall, 2.312500s user + 0.062500s system = 2.375000s CPU (132.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.888206s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124258
+PHY-3002 : Step(270): len = 725463, overlap = 236.562
+PHY-3002 : Step(271): len = 714675, overlap = 193.031
+PHY-3002 : Step(272): len = 701615, overlap = 166.75
+PHY-3002 : Step(273): len = 689587, overlap = 158.375
+PHY-3002 : Step(274): len = 680492, overlap = 144.562
+PHY-3002 : Step(275): len = 672516, overlap = 132.812
+PHY-3002 : Step(276): len = 666832, overlap = 120.75
+PHY-3002 : Step(277): len = 661263, overlap = 110.562
+PHY-3002 : Step(278): len = 655318, overlap = 116.375
+PHY-3002 : Step(279): len = 649278, overlap = 130
+PHY-3002 : Step(280): len = 643735, overlap = 130.25
+PHY-3002 : Step(281): len = 639232, overlap = 127.812
+PHY-3002 : Step(282): len = 634588, overlap = 129.969
+PHY-3002 : Step(283): len = 632464, overlap = 131.406
+PHY-3002 : Step(284): len = 628294, overlap = 126.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000248516
+PHY-3002 : Step(285): len = 629070, overlap = 123.781
+PHY-3002 : Step(286): len = 629965, overlap = 121.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000410701
+PHY-3002 : Step(287): len = 632475, overlap = 120.031
+PHY-3002 : Step(288): len = 642103, overlap = 112.312
+PHY-3002 : Step(289): len = 646065, overlap = 106.562
+PHY-3002 : Step(290): len = 643239, overlap = 108.25
+PHY-3002 : Step(291): len = 641402, overlap = 106.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000710718
+PHY-3002 : Step(292): len = 645464, overlap = 105.312
+PHY-3002 : Step(293): len = 650386, overlap = 94.7812
+PHY-3002 : Step(294): len = 655979, overlap = 89.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00142144
+PHY-3002 : Step(295): len = 657103, overlap = 88.4062
+PHY-3002 : Step(296): len = 661829, overlap = 85.6562
+PHY-3002 : Step(297): len = 669725, overlap = 77.25
+PHY-3002 : Step(298): len = 674047, overlap = 72.9375
+PHY-3002 : Step(299): len = 675876, overlap = 71.2188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.470152s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 563 MB, peak memory is 712 MB
+OPT-1001 : Total overflow 378.78 peak overflow 2.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 541/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777144, over cnt = 3139(8%), over = 11076, worst = 28
+PHY-1001 : End global iterations; 1.539023s wall, 2.015625s user + 0.031250s system = 2.046875s CPU (133.0%)
+
+PHY-1001 : Congestion index: top1 = 71.70, top5 = 58.36, top10 = 52.43, top15 = 48.72.
+PHY-1001 : End incremental global routing; 1.875640s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (127.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.916721s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.6%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 318 needs to be replaced
+PHY-3001 : design contains 18256 instances, 7754 luts, 9281 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6080 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700079
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17267/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793176, over cnt = 3172(9%), over = 11083, worst = 28
+PHY-1001 : End global iterations; 0.253771s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (117.0%)
+
+PHY-1001 : Congestion index: top1 = 71.14, top5 = 58.22, top10 = 52.62, top15 = 49.03.
+PHY-3001 : End congestion estimation; 0.510852s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (110.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85043, tnet num: 20658, tinst num: 18256, tnode num: 115859, tedge num: 135500.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.464941s wall, 1.390625s user + 0.062500s system = 1.453125s CPU (99.2%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 627 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.450289s wall, 2.343750s user + 0.093750s system = 2.437500s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(300): len = 699095, overlap = 0.1875
+PHY-3002 : Step(301): len = 698633, overlap = 0
+PHY-3002 : Step(302): len = 698393, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17369/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790720, over cnt = 3169(9%), over = 11146, worst = 28
+PHY-1001 : End global iterations; 0.206132s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (121.3%)
+
+PHY-1001 : Congestion index: top1 = 71.81, top5 = 58.63, top10 = 52.89, top15 = 49.25.
+PHY-3001 : End congestion estimation; 0.472887s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (109.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.022942s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000436837
+PHY-3002 : Step(303): len = 698158, overlap = 72.9375
+PHY-3002 : Step(304): len = 698336, overlap = 73.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000873674
+PHY-3002 : Step(305): len = 698525, overlap = 73.0625
+PHY-3002 : Step(306): len = 698983, overlap = 73.5625
+PHY-3001 : Final: Len = 698983, Over = 73.5625
+PHY-3001 : End incremental placement; 5.108964s wall, 5.250000s user + 0.328125s system = 5.578125s CPU (109.2%)
+
+OPT-1001 : Total overflow 384.31 peak overflow 2.78
+OPT-1001 : End high-fanout net optimization; 8.429842s wall, 9.046875s user + 0.359375s system = 9.406250s CPU (111.6%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 710, peak = 736.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17297/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793536, over cnt = 3069(8%), over = 10071, worst = 28
+PHY-1002 : len = 834904, over cnt = 2268(6%), over = 6024, worst = 23
+PHY-1002 : len = 878272, over cnt = 1104(3%), over = 2756, worst = 23
+PHY-1002 : len = 909920, over cnt = 279(0%), over = 702, worst = 13
+PHY-1002 : len = 919472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.784973s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.59, top10 = 48.02, top15 = 45.70.
+OPT-1001 : End congestion update; 2.052391s wall, 2.671875s user + 0.046875s system = 2.718750s CPU (132.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.801809s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.4%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 119 cells processed and 18250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 53 cells processed and 6850 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1900 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 850 slack improved
+OPT-1001 : End bottleneck based optimization; 3.260800s wall, 3.875000s user + 0.046875s system = 3.921875s CPU (120.3%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 689, peak = 736.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17333/20842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920464, over cnt = 83(0%), over = 110, worst = 4
+PHY-1002 : len = 920512, over cnt = 40(0%), over = 43, worst = 3
+PHY-1002 : len = 920776, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 921040, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 921072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.817038s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 51.38, top10 = 47.82, top15 = 45.53.
+OPT-1001 : End congestion update; 1.090855s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (103.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.791914s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.999528s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (101.6%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 696, peak = 736.
+OPT-1001 : End physical optimization; 15.460349s wall, 16.781250s user + 0.468750s system = 17.250000s CPU (111.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7754 LUT to BLE ...
+SYN-4008 : Packed 7754 LUT and 3134 SEQ to BLE.
+SYN-4003 : Packing 6153 remaining SEQ's ...
+SYN-4005 : Packed 4101 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2052 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9806/13661 primitive instances ...
+PHY-3001 : End packing; 1.610326s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6670 instances
+RUN-1001 : 3261 mslices, 3261 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17832 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6509 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6668 instances, 6522 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3515 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 705686, Over = 204.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7445/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858864, over cnt = 2009(5%), over = 3264, worst = 8
+PHY-1002 : len = 867896, over cnt = 1189(3%), over = 1689, worst = 7
+PHY-1002 : len = 880112, over cnt = 514(1%), over = 700, worst = 6
+PHY-1002 : len = 887272, over cnt = 163(0%), over = 222, worst = 5
+PHY-1002 : len = 890768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.773028s wall, 2.500000s user + 0.031250s system = 2.531250s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 57.39, top5 = 50.20, top10 = 46.73, top15 = 44.49.
+PHY-3001 : End congestion estimation; 2.196534s wall, 2.921875s user + 0.031250s system = 2.953125s CPU (134.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6668, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.588391s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.3%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 620 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.436831s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.26697e-05
+PHY-3002 : Step(307): len = 691602, overlap = 206
+PHY-3002 : Step(308): len = 683836, overlap = 205.25
+PHY-3002 : Step(309): len = 677655, overlap = 206.75
+PHY-3002 : Step(310): len = 672841, overlap = 216.25
+PHY-3002 : Step(311): len = 669449, overlap = 225
+PHY-3002 : Step(312): len = 666398, overlap = 225.25
+PHY-3002 : Step(313): len = 664858, overlap = 218.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000125339
+PHY-3002 : Step(314): len = 666869, overlap = 208.75
+PHY-3002 : Step(315): len = 670486, overlap = 203.75
+PHY-3002 : Step(316): len = 671644, overlap = 199.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000250679
+PHY-3002 : Step(317): len = 677534, overlap = 198.25
+PHY-3002 : Step(318): len = 684375, overlap = 186.75
+PHY-3002 : Step(319): len = 684183, overlap = 186.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.389482s wall, 0.359375s user + 0.625000s system = 0.984375s CPU (252.7%)
+
+PHY-3001 : Trial Legalized: Len = 757719
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 975/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872424, over cnt = 2646(7%), over = 4451, worst = 7
+PHY-1002 : len = 892264, over cnt = 1457(4%), over = 2022, worst = 7
+PHY-1002 : len = 912312, over cnt = 398(1%), over = 525, worst = 5
+PHY-1002 : len = 919384, over cnt = 79(0%), over = 100, worst = 5
+PHY-1002 : len = 921248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.435364s wall, 3.453125s user + 0.046875s system = 3.500000s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 56.68, top5 = 50.88, top10 = 47.48, top15 = 45.26.
+PHY-3001 : End congestion estimation; 2.893107s wall, 3.921875s user + 0.046875s system = 3.968750s CPU (137.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.849047s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171654
+PHY-3002 : Step(320): len = 732552, overlap = 37.25
+PHY-3002 : Step(321): len = 717815, overlap = 56.75
+PHY-3002 : Step(322): len = 705260, overlap = 79.75
+PHY-3002 : Step(323): len = 697585, overlap = 105.75
+PHY-3002 : Step(324): len = 692369, overlap = 121
+PHY-3002 : Step(325): len = 690073, overlap = 130.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343309
+PHY-3002 : Step(326): len = 694281, overlap = 126.5
+PHY-3002 : Step(327): len = 698775, overlap = 122.25
+PHY-3002 : Step(328): len = 700530, overlap = 125.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000686617
+PHY-3002 : Step(329): len = 703663, overlap = 123.75
+PHY-3002 : Step(330): len = 708517, overlap = 120.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033902s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (92.2%)
+
+PHY-3001 : Legalized: Len = 735420, Over = 0
+PHY-3001 : Spreading special nets. 441 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.095215s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (114.9%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 183, deltaY = 345, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 744855, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6671, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.884700s wall, 1.859375s user + 0.031250s system = 1.890625s CPU (100.3%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 645 MB, peak memory is 736 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4683/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874512, over cnt = 2464(7%), over = 3852, worst = 8
+PHY-1002 : len = 886000, over cnt = 1564(4%), over = 2201, worst = 6
+PHY-1002 : len = 906104, over cnt = 411(1%), over = 514, worst = 5
+PHY-1002 : len = 913792, over cnt = 70(0%), over = 85, worst = 5
+PHY-1002 : len = 915416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.126177s wall, 2.968750s user + 0.046875s system = 3.015625s CPU (141.8%)
+
+PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.95, top10 = 46.69, top15 = 44.63.
+PHY-1001 : End incremental global routing; 2.505157s wall, 3.359375s user + 0.046875s system = 3.406250s CPU (136.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.851686s wall, 0.781250s user + 0.062500s system = 0.843750s CPU (99.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6579 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750654
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16211/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922952, over cnt = 103(0%), over = 140, worst = 8
+PHY-1002 : len = 923128, over cnt = 58(0%), over = 74, worst = 8
+PHY-1002 : len = 923920, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 924112, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 924224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.787891s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (111.1%)
+
+PHY-1001 : Congestion index: top1 = 56.29, top5 = 50.12, top10 = 46.94, top15 = 44.88.
+PHY-3001 : End congestion estimation; 1.107784s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (107.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71542, tnet num: 17675, tinst num: 6692, tnode num: 93911, tedge num: 118783.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.834143s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (98.8%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 661 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.709592s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(331): len = 748232, overlap = 0
+PHY-3002 : Step(332): len = 747363, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16198/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919288, over cnt = 71(0%), over = 97, worst = 4
+PHY-1002 : len = 919528, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 920032, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 920080, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 920112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.852293s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.97, top10 = 46.77, top15 = 44.70.
+PHY-3001 : End congestion estimation; 1.173785s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (105.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.850102s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (97.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000157527
+PHY-3002 : Step(333): len = 747253, overlap = 1
+PHY-3002 : Step(334): len = 747381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005474s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 747516, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065830s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.9%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 747582, Over = 0
+PHY-3001 : End incremental placement; 6.320437s wall, 6.625000s user + 0.125000s system = 6.750000s CPU (106.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.152703s wall, 11.234375s user + 0.234375s system = 11.468750s CPU (113.0%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16175/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919680, over cnt = 54(0%), over = 70, worst = 4
+PHY-1002 : len = 919672, over cnt = 35(0%), over = 44, worst = 3
+PHY-1002 : len = 920096, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 920168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.603084s wall, 0.593750s user + 0.015625s system = 0.609375s CPU (101.0%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.95, top10 = 46.76, top15 = 44.70.
+OPT-1001 : End congestion update; 0.921868s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (101.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.707909s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.3%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 756770, Over = 0
+PHY-3001 : Spreading special nets. 30 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063591s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.3%)
+
+PHY-3001 : 41 instances has been re-located, deltaX = 12, deltaY = 27, maxDist = 3.
+PHY-3001 : Final: Len = 757514, Over = 0
+PHY-3001 : End incremental legalization; 0.393252s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (103.3%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 60 cells processed and 22074 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758204, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060289s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.7%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 16, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758608, Over = 0
+PHY-3001 : End incremental legalization; 0.399029s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.8%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 4156 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758812, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058604s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 7, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 759358, Over = 0
+PHY-3001 : End incremental legalization; 0.375111s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (104.1%)
+
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 18 cells processed and 1161 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759597, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056986s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.7%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 759599, Over = 0
+PHY-3001 : End incremental legalization; 0.371217s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (96.8%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization; 3.719700s wall, 3.796875s user + 0.062500s system = 3.859375s CPU (103.8%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 733, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15721/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930944, over cnt = 193(0%), over = 264, worst = 6
+PHY-1002 : len = 931160, over cnt = 92(0%), over = 103, worst = 3
+PHY-1002 : len = 931928, over cnt = 35(0%), over = 35, worst = 1
+PHY-1002 : len = 932424, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932504, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.847931s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (101.3%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 49.54, top10 = 46.48, top15 = 44.48.
+OPT-1001 : End congestion update; 1.165500s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (101.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.706182s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759705, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059021s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.9%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 759739, Over = 0
+PHY-3001 : End incremental legalization; 0.386458s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.383709s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (104.2%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 733, peak = 739.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.888790s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16201/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932536, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 932560, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 932624, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 932744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 932808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.766948s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.8%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.58, top10 = 46.48, top15 = 44.49.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.737515s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 21.127755s wall, 22.343750s user + 0.343750s system = 22.687500s CPU (107.4%)
+
+RUN-1003 : finish command "place" in 67.664631s wall, 101.828125s user + 7.328125s system = 109.156250s CPU (161.3%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 602 MB, peak memory is 739 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.661707s wall, 2.859375s user + 0.062500s system = 2.921875s CPU (175.8%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 603 MB, peak memory is 739 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6701 instances
+RUN-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17857 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 734 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.571305s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.4%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 625 MB, peak memory is 739 MB
+PHY-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862800, over cnt = 2648(7%), over = 4341, worst = 9
+PHY-1002 : len = 880744, over cnt = 1618(4%), over = 2343, worst = 9
+PHY-1002 : len = 903616, over cnt = 451(1%), over = 577, worst = 6
+PHY-1002 : len = 912696, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 913024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.073098s wall, 4.093750s user + 0.093750s system = 4.187500s CPU (136.3%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.00, top10 = 45.84, top15 = 43.81.
+PHY-1001 : End global routing; 3.408179s wall, 4.437500s user + 0.093750s system = 4.531250s CPU (133.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 705, reserve = 708, peak = 739.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 978, reserve = 982, peak = 978.
+PHY-1001 : End build detailed router design. 4.151844s wall, 4.046875s user + 0.109375s system = 4.156250s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270736, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.164709s wall, 5.156250s user + 0.000000s system = 5.156250s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270792, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.470560s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1015, reserve = 1019, peak = 1015.
+PHY-1001 : End phase 1; 5.646985s wall, 5.640625s user + 0.000000s system = 5.640625s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1032, peak = 1030.
+PHY-1001 : End initial routed; 34.801727s wall, 64.687500s user + 0.265625s system = 64.953125s CPU (186.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.225666s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1042, peak = 1042.
+PHY-1001 : End phase 2; 38.027459s wall, 67.906250s user + 0.265625s system = 68.171875s CPU (179.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135777s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%)
+
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.402159s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26109e+06, over cnt = 626(0%), over = 627, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.322781s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (171.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25966e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.683166s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (153.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25927e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.457667s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (109.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25919e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.315198s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (104.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.283933s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (99.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.291264s wall, 3.281250s user + 0.015625s system = 3.296875s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.236346s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1151, peak = 1146.
+PHY-1001 : End phase 3; 9.393936s wall, 10.671875s user + 0.062500s system = 10.734375s CPU (114.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.137110s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.6%)
+
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.388014s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.245714s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.339179s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (98.9%)
+
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1158, peak = 1153.
+PHY-1001 : End phase 4; 5.998622s wall, 5.968750s user + 0.000000s system = 5.968750s CPU (99.5%)
+
+PHY-1003 : Routed, final wirelength = 2.25928e+06
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1163, peak = 1157.
+PHY-1001 : End export database. 0.060926s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (76.9%)
+
+PHY-1001 : End detail routing; 63.678074s wall, 94.671875s user + 0.453125s system = 95.125000s CPU (149.4%)
+
+RUN-1003 : finish command "route" in 69.715748s wall, 101.703125s user + 0.562500s system = 102.265625s CPU (146.7%)
+
+RUN-1004 : used memory is 1072 MB, reserved memory is 1090 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10187 out of 19600 51.97%
+#reg 9425 out of 19600 48.09%
+#le 12209
+ #lut only 2784 out of 12209 22.80%
+ #reg only 2022 out of 12209 16.56%
+ #lut® 7403 out of 12209 60.64%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1380
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1287
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 961
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 131
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_307.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P170 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12209 |9160 |1027 |9456 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |457 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |97 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |42 |42 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |759 |371 |96 |575 |0 |0 |
+| u_ADconfig |AD_config |187 |121 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |260 |165 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |384 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |173 |121 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |254 |145 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2935 |2382 |306 |2076 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |170 |93 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort |2735 |2268 |289 |1906 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2326 |1968 |253 |1555 |22 |0 |
+| channelPart |channel_part_8478 |141 |135 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |50 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1807 |1513 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |208 |181 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |961 |694 |170 |656 |0 |0 |
+| ram_switch_state |ram_switch_state |638 |638 |0 |372 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |48 |41 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |235 |36 |273 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3122 |2458 |349 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |115 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2917 |2332 |332 |1914 |25 |1 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2476 |1975 |290 |1550 |22 |1 |
+| channelPart |channel_part_8478 |130 |124 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1909 |1532 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |202 |174 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |1003 |657 |170 |701 |0 |0 |
+| ram_switch_state |ram_switch_state |704 |701 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |352 |251 |81 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |162 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |41 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9896
+ #2 2 4222
+ #3 3 1721
+ #4 4 562
+ #5 5-10 766
+ #6 11-50 583
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.048922s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (172.3%)
+
+RUN-1004 : used memory is 1073 MB, reserved memory is 1091 MB, peak memory is 1157 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.577008s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.1%)
+
+RUN-1004 : used memory is 1076 MB, reserved memory is 1094 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.463246s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.3%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1109 MB, peak memory is 1157 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6699
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17857, pip num: 168201
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 529
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3230 valid insts, and 469612 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.833728s wall, 65.984375s user + 0.312500s system = 66.296875s CPU (674.2%)
+
+RUN-1004 : used memory is 1243 MB, reserved memory is 1243 MB, peak memory is 1358 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_092411.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_114359.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_114359.log
new file mode 100644
index 0000000..1069361
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_114359.log
@@ -0,0 +1,2041 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 11:43:59 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.313523s wall, 2.187500s user + 0.125000s system = 2.312500s CPU (100.0%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 315 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17986 instances
+RUN-0007 : 7661 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20564 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13082 nets have 2 pins
+RUN-1001 : 6444 nets have [3 - 5] pins
+RUN-1001 : 620 nets have [6 - 10] pins
+RUN-1001 : 181 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17984 instances, 7661 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.241676s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.4%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 514 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.080643s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (99.9%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11825e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17984.
+PHY-3001 : Level 1 #clusters 2051.
+PHY-3001 : End clustering; 0.140709s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (144.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32681e+06, overlap = 447.375
+PHY-3002 : Step(2): len = 1.21277e+06, overlap = 492.031
+PHY-3002 : Step(3): len = 854256, overlap = 571.531
+PHY-3002 : Step(4): len = 796625, overlap = 595.094
+PHY-3002 : Step(5): len = 625051, overlap = 763.906
+PHY-3002 : Step(6): len = 553878, overlap = 846.75
+PHY-3002 : Step(7): len = 475465, overlap = 919.25
+PHY-3002 : Step(8): len = 435213, overlap = 966.5
+PHY-3002 : Step(9): len = 396311, overlap = 1029.19
+PHY-3002 : Step(10): len = 370878, overlap = 1031.53
+PHY-3002 : Step(11): len = 325662, overlap = 1075.22
+PHY-3002 : Step(12): len = 307603, overlap = 1115.06
+PHY-3002 : Step(13): len = 270358, overlap = 1170.19
+PHY-3002 : Step(14): len = 253854, overlap = 1221.72
+PHY-3002 : Step(15): len = 229490, overlap = 1275.16
+PHY-3002 : Step(16): len = 213861, overlap = 1309.06
+PHY-3002 : Step(17): len = 190508, overlap = 1330.88
+PHY-3002 : Step(18): len = 179455, overlap = 1361.78
+PHY-3002 : Step(19): len = 165284, overlap = 1392.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.31406e-06
+PHY-3002 : Step(20): len = 165466, overlap = 1346.91
+PHY-3002 : Step(21): len = 202919, overlap = 1205.69
+PHY-3002 : Step(22): len = 211139, overlap = 1153.94
+PHY-3002 : Step(23): len = 217503, overlap = 1084.84
+PHY-3002 : Step(24): len = 217194, overlap = 1057.38
+PHY-3002 : Step(25): len = 213766, overlap = 1039.53
+PHY-3002 : Step(26): len = 209686, overlap = 1019.31
+PHY-3002 : Step(27): len = 205682, overlap = 1025.91
+PHY-3002 : Step(28): len = 202366, overlap = 1025.41
+PHY-3002 : Step(29): len = 198815, overlap = 1041.31
+PHY-3002 : Step(30): len = 196891, overlap = 1048.53
+PHY-3002 : Step(31): len = 192947, overlap = 1032.38
+PHY-3002 : Step(32): len = 190652, overlap = 1028.38
+PHY-3002 : Step(33): len = 188982, overlap = 1047.53
+PHY-3002 : Step(34): len = 188856, overlap = 1050.19
+PHY-3002 : Step(35): len = 187822, overlap = 1046.66
+PHY-3002 : Step(36): len = 187691, overlap = 1043.84
+PHY-3002 : Step(37): len = 186699, overlap = 1045.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.62811e-06
+PHY-3002 : Step(38): len = 190190, overlap = 1023.97
+PHY-3002 : Step(39): len = 200878, overlap = 998
+PHY-3002 : Step(40): len = 204969, overlap = 973.031
+PHY-3002 : Step(41): len = 210699, overlap = 962.406
+PHY-3002 : Step(42): len = 213685, overlap = 962.031
+PHY-3002 : Step(43): len = 214913, overlap = 971.312
+PHY-3002 : Step(44): len = 214129, overlap = 962.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.25623e-06
+PHY-3002 : Step(45): len = 222317, overlap = 945.719
+PHY-3002 : Step(46): len = 241846, overlap = 887.062
+PHY-3002 : Step(47): len = 250733, overlap = 810.094
+PHY-3002 : Step(48): len = 259458, overlap = 764.75
+PHY-3002 : Step(49): len = 264898, overlap = 729.594
+PHY-3002 : Step(50): len = 268782, overlap = 717.594
+PHY-3002 : Step(51): len = 268659, overlap = 693.25
+PHY-3002 : Step(52): len = 267038, overlap = 699.969
+PHY-3002 : Step(53): len = 265608, overlap = 708.531
+PHY-3002 : Step(54): len = 263857, overlap = 714.938
+PHY-3002 : Step(55): len = 262442, overlap = 716.219
+PHY-3002 : Step(56): len = 261697, overlap = 712.75
+PHY-3002 : Step(57): len = 261651, overlap = 701.625
+PHY-3002 : Step(58): len = 261227, overlap = 706.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.05125e-05
+PHY-3002 : Step(59): len = 276346, overlap = 609.156
+PHY-3002 : Step(60): len = 291797, overlap = 571.688
+PHY-3002 : Step(61): len = 297779, overlap = 568.531
+PHY-3002 : Step(62): len = 301292, overlap = 564.406
+PHY-3002 : Step(63): len = 299531, overlap = 563.281
+PHY-3002 : Step(64): len = 300587, overlap = 555.219
+PHY-3002 : Step(65): len = 301742, overlap = 556.719
+PHY-3002 : Step(66): len = 303460, overlap = 538.031
+PHY-3002 : Step(67): len = 301977, overlap = 542.531
+PHY-3002 : Step(68): len = 300507, overlap = 528.469
+PHY-3002 : Step(69): len = 299876, overlap = 522.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.10249e-05
+PHY-3002 : Step(70): len = 318230, overlap = 482.656
+PHY-3002 : Step(71): len = 329376, overlap = 452.5
+PHY-3002 : Step(72): len = 333339, overlap = 419.688
+PHY-3002 : Step(73): len = 334752, overlap = 392.281
+PHY-3002 : Step(74): len = 333824, overlap = 357.469
+PHY-3002 : Step(75): len = 335637, overlap = 379.844
+PHY-3002 : Step(76): len = 334442, overlap = 390.5
+PHY-3002 : Step(77): len = 334205, overlap = 407.562
+PHY-3002 : Step(78): len = 334333, overlap = 392.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.20498e-05
+PHY-3002 : Step(79): len = 350059, overlap = 360.938
+PHY-3002 : Step(80): len = 361689, overlap = 339.031
+PHY-3002 : Step(81): len = 364498, overlap = 329.688
+PHY-3002 : Step(82): len = 368120, overlap = 324.688
+PHY-3002 : Step(83): len = 371135, overlap = 305.406
+PHY-3002 : Step(84): len = 373997, overlap = 280.5
+PHY-3002 : Step(85): len = 371594, overlap = 279.188
+PHY-3002 : Step(86): len = 373031, overlap = 280.469
+PHY-3002 : Step(87): len = 374790, overlap = 279.188
+PHY-3002 : Step(88): len = 376019, overlap = 266.062
+PHY-3002 : Step(89): len = 375474, overlap = 260.156
+PHY-3002 : Step(90): len = 377506, overlap = 264.469
+PHY-3002 : Step(91): len = 379997, overlap = 270.062
+PHY-3002 : Step(92): len = 381499, overlap = 250.094
+PHY-3002 : Step(93): len = 378396, overlap = 252.562
+PHY-3002 : Step(94): len = 378137, overlap = 257.031
+PHY-3002 : Step(95): len = 377776, overlap = 258.812
+PHY-3002 : Step(96): len = 378238, overlap = 260.094
+PHY-3002 : Step(97): len = 377541, overlap = 259.375
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.40997e-05
+PHY-3002 : Step(98): len = 393731, overlap = 263.688
+PHY-3002 : Step(99): len = 403714, overlap = 270.438
+PHY-3002 : Step(100): len = 402161, overlap = 260.656
+PHY-3002 : Step(101): len = 403139, overlap = 265.25
+PHY-3002 : Step(102): len = 406115, overlap = 263.562
+PHY-3002 : Step(103): len = 409921, overlap = 261.969
+PHY-3002 : Step(104): len = 409057, overlap = 261.656
+PHY-3002 : Step(105): len = 411247, overlap = 265.344
+PHY-3002 : Step(106): len = 415044, overlap = 267.875
+PHY-3002 : Step(107): len = 417805, overlap = 267
+PHY-3002 : Step(108): len = 414534, overlap = 279.844
+PHY-3002 : Step(109): len = 413890, overlap = 267.531
+PHY-3002 : Step(110): len = 415583, overlap = 257.938
+PHY-3002 : Step(111): len = 417219, overlap = 249.938
+PHY-3002 : Step(112): len = 413916, overlap = 234.875
+PHY-3002 : Step(113): len = 414176, overlap = 247.031
+PHY-3002 : Step(114): len = 415397, overlap = 239.5
+PHY-3002 : Step(115): len = 416638, overlap = 231.375
+PHY-3002 : Step(116): len = 414219, overlap = 227.656
+PHY-3002 : Step(117): len = 414070, overlap = 224.562
+PHY-3002 : Step(118): len = 415000, overlap = 225.969
+PHY-3002 : Step(119): len = 416356, overlap = 230.719
+PHY-3002 : Step(120): len = 414329, overlap = 243.5
+PHY-3002 : Step(121): len = 414525, overlap = 240.781
+PHY-3002 : Step(122): len = 415219, overlap = 251.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168199
+PHY-3002 : Step(123): len = 427793, overlap = 228.094
+PHY-3002 : Step(124): len = 434978, overlap = 211.5
+PHY-3002 : Step(125): len = 434224, overlap = 212.938
+PHY-3002 : Step(126): len = 434893, overlap = 214.719
+PHY-3002 : Step(127): len = 437387, overlap = 214.312
+PHY-3002 : Step(128): len = 440422, overlap = 218.344
+PHY-3002 : Step(129): len = 439475, overlap = 220.5
+PHY-3002 : Step(130): len = 439959, overlap = 218.125
+PHY-3002 : Step(131): len = 442104, overlap = 214.969
+PHY-3002 : Step(132): len = 443728, overlap = 215.188
+PHY-3002 : Step(133): len = 442552, overlap = 226.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000315424
+PHY-3002 : Step(134): len = 449199, overlap = 215
+PHY-3002 : Step(135): len = 456791, overlap = 208.969
+PHY-3002 : Step(136): len = 458741, overlap = 221.25
+PHY-3002 : Step(137): len = 460138, overlap = 210.938
+PHY-3002 : Step(138): len = 461978, overlap = 206.938
+PHY-3002 : Step(139): len = 463732, overlap = 200.469
+PHY-3002 : Step(140): len = 463075, overlap = 203.844
+PHY-3002 : Step(141): len = 464420, overlap = 206.25
+PHY-3002 : Step(142): len = 466826, overlap = 197.656
+PHY-3002 : Step(143): len = 468395, overlap = 196.719
+PHY-3002 : Step(144): len = 468161, overlap = 197.438
+PHY-3002 : Step(145): len = 468919, overlap = 193.844
+PHY-3002 : Step(146): len = 470408, overlap = 190.969
+PHY-3002 : Step(147): len = 471038, overlap = 194.094
+PHY-3002 : Step(148): len = 470098, overlap = 194.125
+PHY-3002 : Step(149): len = 469787, overlap = 192.844
+PHY-3002 : Step(150): len = 470962, overlap = 194.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000597386
+PHY-3002 : Step(151): len = 477356, overlap = 187.469
+PHY-3002 : Step(152): len = 485467, overlap = 177.438
+PHY-3002 : Step(153): len = 487792, overlap = 172.25
+PHY-3002 : Step(154): len = 489820, overlap = 169.969
+PHY-3002 : Step(155): len = 492289, overlap = 166.719
+PHY-3002 : Step(156): len = 494288, overlap = 161.812
+PHY-3002 : Step(157): len = 494621, overlap = 167.094
+PHY-3002 : Step(158): len = 495412, overlap = 158.875
+PHY-3002 : Step(159): len = 497530, overlap = 158.125
+PHY-3002 : Step(160): len = 499660, overlap = 161.844
+PHY-3002 : Step(161): len = 499659, overlap = 155.344
+PHY-3002 : Step(162): len = 500171, overlap = 145.469
+PHY-3002 : Step(163): len = 501354, overlap = 144.875
+PHY-3002 : Step(164): len = 502419, overlap = 141.625
+PHY-3002 : Step(165): len = 502507, overlap = 135.938
+PHY-3002 : Step(166): len = 502911, overlap = 136.219
+PHY-3002 : Step(167): len = 503441, overlap = 133.781
+PHY-3002 : Step(168): len = 503676, overlap = 133.844
+PHY-3002 : Step(169): len = 503613, overlap = 131.625
+PHY-3002 : Step(170): len = 503662, overlap = 133.656
+PHY-3002 : Step(171): len = 503864, overlap = 139.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108125
+PHY-3002 : Step(172): len = 508017, overlap = 138.406
+PHY-3002 : Step(173): len = 515100, overlap = 140.438
+PHY-3002 : Step(174): len = 516366, overlap = 136.719
+PHY-3002 : Step(175): len = 517528, overlap = 132.312
+PHY-3002 : Step(176): len = 519652, overlap = 132.719
+PHY-3002 : Step(177): len = 520672, overlap = 132.875
+PHY-3002 : Step(178): len = 520221, overlap = 132.375
+PHY-3002 : Step(179): len = 520126, overlap = 135.25
+PHY-3002 : Step(180): len = 521307, overlap = 133.188
+PHY-3002 : Step(181): len = 522214, overlap = 132.5
+PHY-3002 : Step(182): len = 521960, overlap = 133.5
+PHY-3002 : Step(183): len = 521951, overlap = 135.812
+PHY-3002 : Step(184): len = 522274, overlap = 134.25
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00187339
+PHY-3002 : Step(185): len = 525598, overlap = 136.688
+PHY-3002 : Step(186): len = 531982, overlap = 134.781
+PHY-3002 : Step(187): len = 533798, overlap = 129.438
+PHY-3002 : Step(188): len = 534889, overlap = 126.938
+PHY-3002 : Step(189): len = 535931, overlap = 126.094
+PHY-3002 : Step(190): len = 536614, overlap = 125.531
+PHY-3002 : Step(191): len = 537630, overlap = 128.594
+PHY-3002 : Step(192): len = 538953, overlap = 129.156
+PHY-3002 : Step(193): len = 539831, overlap = 128.594
+PHY-3002 : Step(194): len = 540970, overlap = 124.75
+PHY-3002 : Step(195): len = 542306, overlap = 125.406
+PHY-3002 : Step(196): len = 542817, overlap = 125.406
+PHY-3002 : Step(197): len = 543125, overlap = 123.969
+PHY-3002 : Step(198): len = 543331, overlap = 123.969
+PHY-3002 : Step(199): len = 543607, overlap = 125.344
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00307474
+PHY-3002 : Step(200): len = 546970, overlap = 124.781
+PHY-3002 : Step(201): len = 555249, overlap = 108.75
+PHY-3002 : Step(202): len = 560298, overlap = 101.938
+PHY-3002 : Step(203): len = 566036, overlap = 104.688
+PHY-3002 : Step(204): len = 569242, overlap = 103.969
+PHY-3002 : Step(205): len = 572082, overlap = 105.062
+PHY-3002 : Step(206): len = 573488, overlap = 100.906
+PHY-3002 : Step(207): len = 574436, overlap = 101.594
+PHY-3002 : Step(208): len = 574997, overlap = 98.375
+PHY-3002 : Step(209): len = 575327, overlap = 96.875
+PHY-3002 : Step(210): len = 575154, overlap = 96.2812
+PHY-3002 : Step(211): len = 574947, overlap = 90.3438
+PHY-3002 : Step(212): len = 574615, overlap = 96.1562
+PHY-3002 : Step(213): len = 574424, overlap = 96.1562
+PHY-3002 : Step(214): len = 574285, overlap = 91.1562
+PHY-3002 : Step(215): len = 574158, overlap = 90.1562
+PHY-3002 : Step(216): len = 573866, overlap = 87.6562
+PHY-3002 : Step(217): len = 573742, overlap = 90.125
+PHY-3002 : Step(218): len = 573607, overlap = 89.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015229s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (205.2%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753960, over cnt = 1673(4%), over = 7641, worst = 41
+PHY-1001 : End global iterations; 0.756598s wall, 1.140625s user + 0.140625s system = 1.281250s CPU (169.3%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 63.38, top10 = 53.94, top15 = 48.26.
+PHY-3001 : End congestion estimation; 1.018897s wall, 1.406250s user + 0.140625s system = 1.546875s CPU (151.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.924889s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012894
+PHY-3002 : Step(219): len = 682872, overlap = 60.7812
+PHY-3002 : Step(220): len = 680164, overlap = 61.5
+PHY-3002 : Step(221): len = 671439, overlap = 58.2812
+PHY-3002 : Step(222): len = 665226, overlap = 60.6875
+PHY-3002 : Step(223): len = 663081, overlap = 55.8438
+PHY-3002 : Step(224): len = 662916, overlap = 53.5938
+PHY-3002 : Step(225): len = 660482, overlap = 53.4375
+PHY-3002 : Step(226): len = 656745, overlap = 53.25
+PHY-3002 : Step(227): len = 653517, overlap = 53.7188
+PHY-3002 : Step(228): len = 651915, overlap = 50.4688
+PHY-3002 : Step(229): len = 650566, overlap = 43.9375
+PHY-3002 : Step(230): len = 649789, overlap = 39.6562
+PHY-3002 : Step(231): len = 649010, overlap = 39.6875
+PHY-3002 : Step(232): len = 648983, overlap = 36.4375
+PHY-3002 : Step(233): len = 648835, overlap = 39.7188
+PHY-3002 : Step(234): len = 649183, overlap = 37.0625
+PHY-3002 : Step(235): len = 647443, overlap = 37.6562
+PHY-3002 : Step(236): len = 646551, overlap = 37.75
+PHY-3002 : Step(237): len = 644304, overlap = 38.4688
+PHY-3002 : Step(238): len = 642657, overlap = 46.9062
+PHY-3002 : Step(239): len = 640494, overlap = 55.25
+PHY-3002 : Step(240): len = 638385, overlap = 57.375
+PHY-3002 : Step(241): len = 636246, overlap = 62.2812
+PHY-3002 : Step(242): len = 634318, overlap = 64.0625
+PHY-3002 : Step(243): len = 632554, overlap = 66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025788
+PHY-3002 : Step(244): len = 636935, overlap = 63.2812
+PHY-3002 : Step(245): len = 642468, overlap = 58.875
+PHY-3002 : Step(246): len = 644067, overlap = 55.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479888
+PHY-3002 : Step(247): len = 655065, overlap = 49.3125
+PHY-3002 : Step(248): len = 673391, overlap = 48.2188
+PHY-3002 : Step(249): len = 686922, overlap = 44.4375
+PHY-3002 : Step(250): len = 689884, overlap = 43.6875
+PHY-3002 : Step(251): len = 689070, overlap = 41.375
+PHY-3002 : Step(252): len = 686972, overlap = 40.5625
+PHY-3002 : Step(253): len = 686400, overlap = 38.8438
+PHY-3002 : Step(254): len = 686300, overlap = 37.125
+PHY-3002 : Step(255): len = 687195, overlap = 36.875
+PHY-3002 : Step(256): len = 688672, overlap = 36.3125
+PHY-3002 : Step(257): len = 687776, overlap = 38.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000959777
+PHY-3002 : Step(258): len = 693185, overlap = 37.9375
+PHY-3002 : Step(259): len = 707793, overlap = 42.5625
+PHY-3002 : Step(260): len = 721904, overlap = 45.25
+PHY-3002 : Step(261): len = 720538, overlap = 45.125
+PHY-3002 : Step(262): len = 718584, overlap = 47.0625
+PHY-3002 : Step(263): len = 718363, overlap = 47.125
+PHY-3002 : Step(264): len = 719234, overlap = 46.2812
+PHY-3002 : Step(265): len = 718781, overlap = 48.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00167098
+PHY-3002 : Step(266): len = 722104, overlap = 49.2188
+PHY-3002 : Step(267): len = 730523, overlap = 49.75
+PHY-3002 : Step(268): len = 737525, overlap = 49.1875
+PHY-3002 : Step(269): len = 740778, overlap = 49.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 74/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825680, over cnt = 2877(8%), over = 14308, worst = 47
+PHY-1001 : End global iterations; 1.692327s wall, 2.375000s user + 0.046875s system = 2.421875s CPU (143.1%)
+
+PHY-1001 : Congestion index: top1 = 102.03, top5 = 79.19, top10 = 68.21, top15 = 61.55.
+PHY-3001 : End congestion estimation; 1.991556s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (135.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.007552s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124258
+PHY-3002 : Step(270): len = 725463, overlap = 236.562
+PHY-3002 : Step(271): len = 714675, overlap = 193.031
+PHY-3002 : Step(272): len = 701615, overlap = 166.75
+PHY-3002 : Step(273): len = 689587, overlap = 158.375
+PHY-3002 : Step(274): len = 680492, overlap = 144.562
+PHY-3002 : Step(275): len = 672516, overlap = 132.812
+PHY-3002 : Step(276): len = 666832, overlap = 120.75
+PHY-3002 : Step(277): len = 661263, overlap = 110.562
+PHY-3002 : Step(278): len = 655318, overlap = 116.375
+PHY-3002 : Step(279): len = 649278, overlap = 130
+PHY-3002 : Step(280): len = 643735, overlap = 130.25
+PHY-3002 : Step(281): len = 639232, overlap = 127.812
+PHY-3002 : Step(282): len = 634588, overlap = 129.969
+PHY-3002 : Step(283): len = 632464, overlap = 131.406
+PHY-3002 : Step(284): len = 628294, overlap = 126.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000248516
+PHY-3002 : Step(285): len = 629070, overlap = 123.781
+PHY-3002 : Step(286): len = 629965, overlap = 121.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000410701
+PHY-3002 : Step(287): len = 632475, overlap = 120.031
+PHY-3002 : Step(288): len = 642103, overlap = 112.312
+PHY-3002 : Step(289): len = 646065, overlap = 106.562
+PHY-3002 : Step(290): len = 643239, overlap = 108.25
+PHY-3002 : Step(291): len = 641402, overlap = 106.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000710718
+PHY-3002 : Step(292): len = 645464, overlap = 105.312
+PHY-3002 : Step(293): len = 650386, overlap = 94.7812
+PHY-3002 : Step(294): len = 655979, overlap = 89.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00142144
+PHY-3002 : Step(295): len = 657103, overlap = 88.4062
+PHY-3002 : Step(296): len = 661829, overlap = 85.6562
+PHY-3002 : Step(297): len = 669725, overlap = 77.25
+PHY-3002 : Step(298): len = 674047, overlap = 72.9375
+PHY-3002 : Step(299): len = 675876, overlap = 71.2188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.540963s wall, 1.500000s user + 0.046875s system = 1.546875s CPU (100.4%)
+
+RUN-1004 : used memory is 577 MB, reserved memory is 564 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 378.78 peak overflow 2.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 541/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777144, over cnt = 3139(8%), over = 11076, worst = 28
+PHY-1001 : End global iterations; 1.758855s wall, 2.593750s user + 0.109375s system = 2.703125s CPU (153.7%)
+
+PHY-1001 : Congestion index: top1 = 71.70, top5 = 58.36, top10 = 52.43, top15 = 48.72.
+PHY-1001 : End incremental global routing; 2.143266s wall, 2.968750s user + 0.109375s system = 3.078125s CPU (143.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.981879s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.3%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 318 needs to be replaced
+PHY-3001 : design contains 18256 instances, 7754 luts, 9281 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6080 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700079
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17267/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793176, over cnt = 3172(9%), over = 11083, worst = 28
+PHY-1001 : End global iterations; 0.273897s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (142.6%)
+
+PHY-1001 : Congestion index: top1 = 71.14, top5 = 58.22, top10 = 52.62, top15 = 49.03.
+PHY-3001 : End congestion estimation; 0.555234s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (118.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85043, tnet num: 20658, tinst num: 18256, tnode num: 115859, tedge num: 135500.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.568548s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.6%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 615 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.594914s wall, 2.562500s user + 0.031250s system = 2.593750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(300): len = 699095, overlap = 0.1875
+PHY-3002 : Step(301): len = 698633, overlap = 0
+PHY-3002 : Step(302): len = 698393, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17369/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790720, over cnt = 3169(9%), over = 11146, worst = 28
+PHY-1001 : End global iterations; 0.230003s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (163.0%)
+
+PHY-1001 : Congestion index: top1 = 71.81, top5 = 58.63, top10 = 52.89, top15 = 49.25.
+PHY-3001 : End congestion estimation; 0.514722s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (124.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.006964s wall, 0.968750s user + 0.046875s system = 1.015625s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000436837
+PHY-3002 : Step(303): len = 698158, overlap = 72.9375
+PHY-3002 : Step(304): len = 698336, overlap = 73.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000873674
+PHY-3002 : Step(305): len = 698525, overlap = 73.0625
+PHY-3002 : Step(306): len = 698983, overlap = 73.5625
+PHY-3001 : Final: Len = 698983, Over = 73.5625
+PHY-3001 : End incremental placement; 5.391569s wall, 6.171875s user + 0.218750s system = 6.390625s CPU (118.5%)
+
+OPT-1001 : Total overflow 384.31 peak overflow 2.78
+OPT-1001 : End high-fanout net optimization; 9.247828s wall, 10.937500s user + 0.328125s system = 11.265625s CPU (121.8%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 709, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17297/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793536, over cnt = 3069(8%), over = 10071, worst = 28
+PHY-1002 : len = 834904, over cnt = 2268(6%), over = 6024, worst = 23
+PHY-1002 : len = 878272, over cnt = 1104(3%), over = 2756, worst = 23
+PHY-1002 : len = 909920, over cnt = 279(0%), over = 702, worst = 13
+PHY-1002 : len = 919472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.989758s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (128.0%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.59, top10 = 48.02, top15 = 45.70.
+OPT-1001 : End congestion update; 2.294799s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (124.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.896963s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.3%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 119 cells processed and 18250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 53 cells processed and 6850 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1900 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 850 slack improved
+OPT-1001 : End bottleneck based optimization; 3.634779s wall, 4.156250s user + 0.015625s system = 4.171875s CPU (114.8%)
+
+OPT-1001 : Current memory(MB): used = 696, reserve = 692, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17333/20842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920464, over cnt = 83(0%), over = 110, worst = 4
+PHY-1002 : len = 920512, over cnt = 40(0%), over = 43, worst = 3
+PHY-1002 : len = 920776, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 921040, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 921072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.791765s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 51.38, top10 = 47.82, top15 = 45.53.
+OPT-1001 : End congestion update; 1.087173s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (106.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.852469s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.8%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.065298s wall, 2.125000s user + 0.015625s system = 2.140625s CPU (103.6%)
+
+OPT-1001 : Current memory(MB): used = 708, reserve = 700, peak = 735.
+OPT-1001 : End physical optimization; 16.816393s wall, 19.125000s user + 0.437500s system = 19.562500s CPU (116.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7754 LUT to BLE ...
+SYN-4008 : Packed 7754 LUT and 3134 SEQ to BLE.
+SYN-4003 : Packing 6153 remaining SEQ's ...
+SYN-4005 : Packed 4101 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2052 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9806/13661 primitive instances ...
+PHY-3001 : End packing; 1.783776s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6670 instances
+RUN-1001 : 3261 mslices, 3261 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17832 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6509 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6668 instances, 6522 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3515 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 705686, Over = 204.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7445/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858864, over cnt = 2009(5%), over = 3264, worst = 8
+PHY-1002 : len = 867896, over cnt = 1189(3%), over = 1689, worst = 7
+PHY-1002 : len = 880112, over cnt = 514(1%), over = 700, worst = 6
+PHY-1002 : len = 887272, over cnt = 163(0%), over = 222, worst = 5
+PHY-1002 : len = 890768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.872196s wall, 2.578125s user + 0.031250s system = 2.609375s CPU (139.4%)
+
+PHY-1001 : Congestion index: top1 = 57.39, top5 = 50.20, top10 = 46.73, top15 = 44.49.
+PHY-3001 : End congestion estimation; 2.311974s wall, 3.015625s user + 0.031250s system = 3.046875s CPU (131.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6668, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.716969s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (100.1%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 614 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.672655s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.26697e-05
+PHY-3002 : Step(307): len = 691602, overlap = 206
+PHY-3002 : Step(308): len = 683836, overlap = 205.25
+PHY-3002 : Step(309): len = 677655, overlap = 206.75
+PHY-3002 : Step(310): len = 672841, overlap = 216.25
+PHY-3002 : Step(311): len = 669449, overlap = 225
+PHY-3002 : Step(312): len = 666398, overlap = 225.25
+PHY-3002 : Step(313): len = 664858, overlap = 218.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000125339
+PHY-3002 : Step(314): len = 666869, overlap = 208.75
+PHY-3002 : Step(315): len = 670486, overlap = 203.75
+PHY-3002 : Step(316): len = 671644, overlap = 199.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000250679
+PHY-3002 : Step(317): len = 677534, overlap = 198.25
+PHY-3002 : Step(318): len = 684375, overlap = 186.75
+PHY-3002 : Step(319): len = 684183, overlap = 186.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.420309s wall, 0.343750s user + 0.703125s system = 1.046875s CPU (249.1%)
+
+PHY-3001 : Trial Legalized: Len = 757719
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 975/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872424, over cnt = 2646(7%), over = 4451, worst = 7
+PHY-1002 : len = 892264, over cnt = 1457(4%), over = 2022, worst = 7
+PHY-1002 : len = 912312, over cnt = 398(1%), over = 525, worst = 5
+PHY-1002 : len = 919384, over cnt = 79(0%), over = 100, worst = 5
+PHY-1002 : len = 921248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.744503s wall, 3.921875s user + 0.093750s system = 4.015625s CPU (146.3%)
+
+PHY-1001 : Congestion index: top1 = 56.68, top5 = 50.88, top10 = 47.48, top15 = 45.26.
+PHY-3001 : End congestion estimation; 3.250916s wall, 4.421875s user + 0.093750s system = 4.515625s CPU (138.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.927495s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171654
+PHY-3002 : Step(320): len = 732552, overlap = 37.25
+PHY-3002 : Step(321): len = 717815, overlap = 56.75
+PHY-3002 : Step(322): len = 705260, overlap = 79.75
+PHY-3002 : Step(323): len = 697585, overlap = 105.75
+PHY-3002 : Step(324): len = 692369, overlap = 121
+PHY-3002 : Step(325): len = 690073, overlap = 130.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343309
+PHY-3002 : Step(326): len = 694281, overlap = 126.5
+PHY-3002 : Step(327): len = 698775, overlap = 122.25
+PHY-3002 : Step(328): len = 700530, overlap = 125.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000686617
+PHY-3002 : Step(329): len = 703663, overlap = 123.75
+PHY-3002 : Step(330): len = 708517, overlap = 120.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034113s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (91.6%)
+
+PHY-3001 : Legalized: Len = 735420, Over = 0
+PHY-3001 : Spreading special nets. 441 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.108410s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (86.5%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 183, deltaY = 345, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 744855, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6671, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.001908s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (99.1%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 635 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4683/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874512, over cnt = 2464(7%), over = 3852, worst = 8
+PHY-1002 : len = 886000, over cnt = 1564(4%), over = 2201, worst = 6
+PHY-1002 : len = 906104, over cnt = 411(1%), over = 514, worst = 5
+PHY-1002 : len = 913792, over cnt = 70(0%), over = 85, worst = 5
+PHY-1002 : len = 915416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.386337s wall, 3.203125s user + 0.046875s system = 3.250000s CPU (136.2%)
+
+PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.95, top10 = 46.69, top15 = 44.63.
+PHY-1001 : End incremental global routing; 2.797284s wall, 3.609375s user + 0.046875s system = 3.656250s CPU (130.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.922972s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.9%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6579 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750654
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16211/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922952, over cnt = 103(0%), over = 140, worst = 8
+PHY-1002 : len = 923128, over cnt = 58(0%), over = 74, worst = 8
+PHY-1002 : len = 923920, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 924112, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 924224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.849212s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (103.0%)
+
+PHY-1001 : Congestion index: top1 = 56.29, top5 = 50.12, top10 = 46.94, top15 = 44.88.
+PHY-3001 : End congestion estimation; 1.195937s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71542, tnet num: 17675, tinst num: 6692, tnode num: 93911, tedge num: 118783.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.970564s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (99.9%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 656 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.918668s wall, 2.890625s user + 0.031250s system = 2.921875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(331): len = 748232, overlap = 0
+PHY-3002 : Step(332): len = 747363, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16198/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919288, over cnt = 71(0%), over = 97, worst = 4
+PHY-1002 : len = 919528, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 920032, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 920080, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 920112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.852121s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (104.5%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.97, top10 = 46.77, top15 = 44.70.
+PHY-3001 : End congestion estimation; 1.197285s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (101.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.914707s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000157527
+PHY-3002 : Step(333): len = 747253, overlap = 1
+PHY-3002 : Step(334): len = 747381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.008103s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (192.8%)
+
+PHY-3001 : Legalized: Len = 747516, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065555s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.2%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 747582, Over = 0
+PHY-3001 : End incremental placement; 6.733457s wall, 6.843750s user + 0.187500s system = 7.031250s CPU (104.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.980134s wall, 11.875000s user + 0.250000s system = 12.125000s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 731, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16175/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919680, over cnt = 54(0%), over = 70, worst = 4
+PHY-1002 : len = 919672, over cnt = 35(0%), over = 44, worst = 3
+PHY-1002 : len = 920096, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 920168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.703382s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (104.4%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.95, top10 = 46.76, top15 = 44.70.
+OPT-1001 : End congestion update; 1.070315s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.768373s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.6%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 756770, Over = 0
+PHY-3001 : Spreading special nets. 30 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067985s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.9%)
+
+PHY-3001 : 41 instances has been re-located, deltaX = 12, deltaY = 27, maxDist = 3.
+PHY-3001 : Final: Len = 757514, Over = 0
+PHY-3001 : End incremental legalization; 0.421766s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (118.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 60 cells processed and 22074 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758204, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065318s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 16, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758608, Over = 0
+PHY-3001 : End incremental legalization; 0.415984s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (124.0%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 4156 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758812, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064353s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.1%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 7, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 759358, Over = 0
+PHY-3001 : End incremental legalization; 0.415353s wall, 0.421875s user + 0.031250s system = 0.453125s CPU (109.1%)
+
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 18 cells processed and 1161 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759597, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063713s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.1%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 759599, Over = 0
+PHY-3001 : End incremental legalization; 0.410465s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.8%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization; 4.101331s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (106.3%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15721/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930944, over cnt = 193(0%), over = 264, worst = 6
+PHY-1002 : len = 931160, over cnt = 92(0%), over = 103, worst = 3
+PHY-1002 : len = 931928, over cnt = 35(0%), over = 35, worst = 1
+PHY-1002 : len = 932424, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932504, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.923064s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 49.54, top10 = 46.48, top15 = 44.48.
+OPT-1001 : End congestion update; 1.265444s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (105.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.760981s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759705, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063242s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.8%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 759739, Over = 0
+PHY-3001 : End incremental legalization; 0.405605s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (107.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.565826s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (103.5%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.758012s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16201/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932536, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 932560, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 932624, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 932744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 932808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.816452s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.58, top10 = 46.48, top15 = 44.49.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.772756s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.612990s wall, 23.921875s user + 0.312500s system = 24.234375s CPU (107.2%)
+
+RUN-1003 : finish command "place" in 75.016275s wall, 115.062500s user + 8.062500s system = 123.125000s CPU (164.1%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 649 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.837575s wall, 3.093750s user + 0.031250s system = 3.125000s CPU (170.1%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 650 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6701 instances
+RUN-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17857 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 734 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.695605s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (98.6%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 620 MB, peak memory is 737 MB
+PHY-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862800, over cnt = 2648(7%), over = 4341, worst = 9
+PHY-1002 : len = 880744, over cnt = 1618(4%), over = 2343, worst = 9
+PHY-1002 : len = 903616, over cnt = 451(1%), over = 577, worst = 6
+PHY-1002 : len = 912696, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 913024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.445196s wall, 4.515625s user + 0.015625s system = 4.531250s CPU (131.5%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.00, top10 = 45.84, top15 = 43.81.
+PHY-1001 : End global routing; 3.800679s wall, 4.859375s user + 0.015625s system = 4.875000s CPU (128.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 710, reserve = 712, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 979, reserve = 981, peak = 979.
+PHY-1001 : End build detailed router design. 4.332956s wall, 4.296875s user + 0.031250s system = 4.328125s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270736, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.691579s wall, 5.687500s user + 0.000000s system = 5.687500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270792, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.491316s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (101.8%)
+
+PHY-1001 : Current memory(MB): used = 1016, reserve = 1018, peak = 1016.
+PHY-1001 : End phase 1; 6.198475s wall, 6.187500s user + 0.015625s system = 6.203125s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1032, peak = 1032.
+PHY-1001 : End initial routed; 38.996428s wall, 72.390625s user + 0.359375s system = 72.750000s CPU (186.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.519974s wall, 3.500000s user + 0.015625s system = 3.515625s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1046, peak = 1046.
+PHY-1001 : End phase 2; 42.516476s wall, 75.890625s user + 0.375000s system = 76.265625s CPU (179.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.142770s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.429032s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26109e+06, over cnt = 626(0%), over = 627, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.458328s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (165.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25966e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.713198s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (146.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25927e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.482166s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (110.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25919e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.326252s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (110.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.262798s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.490219s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.396678s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1157, peak = 1152.
+PHY-1001 : End phase 3; 9.985421s wall, 11.328125s user + 0.015625s system = 11.343750s CPU (113.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.139887s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.5%)
+
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.406004s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.476108s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.444370s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1164, peak = 1159.
+PHY-1001 : End phase 4; 6.354514s wall, 6.359375s user + 0.000000s system = 6.359375s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.25928e+06
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1169, peak = 1163.
+PHY-1001 : End export database. 0.063855s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.9%)
+
+PHY-1001 : End detail routing; 69.874008s wall, 104.546875s user + 0.437500s system = 104.984375s CPU (150.2%)
+
+RUN-1003 : finish command "route" in 76.509529s wall, 112.218750s user + 0.453125s system = 112.671875s CPU (147.3%)
+
+RUN-1004 : used memory is 1083 MB, reserved memory is 1090 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10187 out of 19600 51.97%
+#reg 9425 out of 19600 48.09%
+#le 12209
+ #lut only 2784 out of 12209 22.80%
+ #reg only 2022 out of 12209 16.56%
+ #lut® 7403 out of 12209 60.64%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1380
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1287
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 961
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 131
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_307.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P170 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12209 |9160 |1027 |9456 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |457 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |97 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |42 |42 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |759 |371 |96 |575 |0 |0 |
+| u_ADconfig |AD_config |187 |121 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |260 |165 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |384 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |173 |121 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |254 |145 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2935 |2382 |306 |2076 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |170 |93 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort |2735 |2268 |289 |1906 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2326 |1968 |253 |1555 |22 |0 |
+| channelPart |channel_part_8478 |141 |135 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |50 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1807 |1513 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |208 |181 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |961 |694 |170 |656 |0 |0 |
+| ram_switch_state |ram_switch_state |638 |638 |0 |372 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |48 |41 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |235 |36 |273 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3122 |2458 |349 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |115 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2917 |2332 |332 |1914 |25 |1 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2476 |1975 |290 |1550 |22 |1 |
+| channelPart |channel_part_8478 |130 |124 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1909 |1532 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |202 |174 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |1003 |657 |170 |701 |0 |0 |
+| ram_switch_state |ram_switch_state |704 |701 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |352 |251 |81 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |162 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |41 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9896
+ #2 2 4222
+ #3 3 1721
+ #4 4 562
+ #5 5-10 766
+ #6 11-50 583
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.154800s wall, 3.734375s user + 0.000000s system = 3.734375s CPU (173.3%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1092 MB, peak memory is 1163 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.714768s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (100.2%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1096 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.556004s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (98.4%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1098 MB, peak memory is 1163 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6699
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17857, pip num: 168201
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 529
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3230 valid insts, and 469612 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.874632s wall, 66.312500s user + 0.281250s system = 66.593750s CPU (674.4%)
+
+RUN-1004 : used memory is 1245 MB, reserved memory is 1245 MB, peak memory is 1360 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_114359.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_115727.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_115727.log
new file mode 100644
index 0000000..170de8a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_115727.log
@@ -0,0 +1,2041 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 11:57:27 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.342036s wall, 2.265625s user + 0.062500s system = 2.328125s CPU (99.4%)
+
+RUN-1004 : used memory is 347 MB, reserved memory is 315 MB, peak memory is 351 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2946 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2214 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17986 instances
+RUN-0007 : 7661 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20564 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13082 nets have 2 pins
+RUN-1001 : 6444 nets have [3 - 5] pins
+RUN-1001 : 620 nets have [6 - 10] pins
+RUN-1001 : 181 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17984 instances, 7661 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5953 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.262385s wall, 1.218750s user + 0.046875s system = 1.265625s CPU (100.3%)
+
+RUN-1004 : used memory is 539 MB, reserved memory is 514 MB, peak memory is 539 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.406307s wall, 2.312500s user + 0.078125s system = 2.390625s CPU (99.3%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11825e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17984.
+PHY-3001 : Level 1 #clusters 2051.
+PHY-3001 : End clustering; 0.142702s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32681e+06, overlap = 447.375
+PHY-3002 : Step(2): len = 1.21277e+06, overlap = 492.031
+PHY-3002 : Step(3): len = 854256, overlap = 571.531
+PHY-3002 : Step(4): len = 796625, overlap = 595.094
+PHY-3002 : Step(5): len = 625051, overlap = 763.906
+PHY-3002 : Step(6): len = 553878, overlap = 846.75
+PHY-3002 : Step(7): len = 475465, overlap = 919.25
+PHY-3002 : Step(8): len = 435213, overlap = 966.5
+PHY-3002 : Step(9): len = 396311, overlap = 1029.19
+PHY-3002 : Step(10): len = 370878, overlap = 1031.53
+PHY-3002 : Step(11): len = 325662, overlap = 1075.22
+PHY-3002 : Step(12): len = 307603, overlap = 1115.06
+PHY-3002 : Step(13): len = 270358, overlap = 1170.19
+PHY-3002 : Step(14): len = 253854, overlap = 1221.72
+PHY-3002 : Step(15): len = 229490, overlap = 1275.16
+PHY-3002 : Step(16): len = 213861, overlap = 1309.06
+PHY-3002 : Step(17): len = 190508, overlap = 1330.88
+PHY-3002 : Step(18): len = 179455, overlap = 1361.78
+PHY-3002 : Step(19): len = 165284, overlap = 1392.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.31406e-06
+PHY-3002 : Step(20): len = 165466, overlap = 1346.91
+PHY-3002 : Step(21): len = 202919, overlap = 1205.69
+PHY-3002 : Step(22): len = 211139, overlap = 1153.94
+PHY-3002 : Step(23): len = 217503, overlap = 1084.84
+PHY-3002 : Step(24): len = 217194, overlap = 1057.38
+PHY-3002 : Step(25): len = 213766, overlap = 1039.53
+PHY-3002 : Step(26): len = 209686, overlap = 1019.31
+PHY-3002 : Step(27): len = 205682, overlap = 1025.91
+PHY-3002 : Step(28): len = 202366, overlap = 1025.41
+PHY-3002 : Step(29): len = 198815, overlap = 1041.31
+PHY-3002 : Step(30): len = 196891, overlap = 1048.53
+PHY-3002 : Step(31): len = 192947, overlap = 1032.38
+PHY-3002 : Step(32): len = 190652, overlap = 1028.38
+PHY-3002 : Step(33): len = 188982, overlap = 1047.53
+PHY-3002 : Step(34): len = 188856, overlap = 1050.19
+PHY-3002 : Step(35): len = 187822, overlap = 1046.66
+PHY-3002 : Step(36): len = 187691, overlap = 1043.84
+PHY-3002 : Step(37): len = 186699, overlap = 1045.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.62811e-06
+PHY-3002 : Step(38): len = 190190, overlap = 1023.97
+PHY-3002 : Step(39): len = 200878, overlap = 998
+PHY-3002 : Step(40): len = 204969, overlap = 973.031
+PHY-3002 : Step(41): len = 210699, overlap = 962.406
+PHY-3002 : Step(42): len = 213685, overlap = 962.031
+PHY-3002 : Step(43): len = 214913, overlap = 971.312
+PHY-3002 : Step(44): len = 214129, overlap = 962.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.25623e-06
+PHY-3002 : Step(45): len = 222317, overlap = 945.719
+PHY-3002 : Step(46): len = 241846, overlap = 887.062
+PHY-3002 : Step(47): len = 250733, overlap = 810.094
+PHY-3002 : Step(48): len = 259458, overlap = 764.75
+PHY-3002 : Step(49): len = 264898, overlap = 729.594
+PHY-3002 : Step(50): len = 268782, overlap = 717.594
+PHY-3002 : Step(51): len = 268659, overlap = 693.25
+PHY-3002 : Step(52): len = 267038, overlap = 699.969
+PHY-3002 : Step(53): len = 265608, overlap = 708.531
+PHY-3002 : Step(54): len = 263857, overlap = 714.938
+PHY-3002 : Step(55): len = 262442, overlap = 716.219
+PHY-3002 : Step(56): len = 261697, overlap = 712.75
+PHY-3002 : Step(57): len = 261651, overlap = 701.625
+PHY-3002 : Step(58): len = 261227, overlap = 706.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.05125e-05
+PHY-3002 : Step(59): len = 276346, overlap = 609.156
+PHY-3002 : Step(60): len = 291797, overlap = 571.688
+PHY-3002 : Step(61): len = 297779, overlap = 568.531
+PHY-3002 : Step(62): len = 301292, overlap = 564.406
+PHY-3002 : Step(63): len = 299531, overlap = 563.281
+PHY-3002 : Step(64): len = 300587, overlap = 555.219
+PHY-3002 : Step(65): len = 301742, overlap = 556.719
+PHY-3002 : Step(66): len = 303460, overlap = 538.031
+PHY-3002 : Step(67): len = 301977, overlap = 542.531
+PHY-3002 : Step(68): len = 300507, overlap = 528.469
+PHY-3002 : Step(69): len = 299876, overlap = 522.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.10249e-05
+PHY-3002 : Step(70): len = 318230, overlap = 482.656
+PHY-3002 : Step(71): len = 329376, overlap = 452.5
+PHY-3002 : Step(72): len = 333339, overlap = 419.688
+PHY-3002 : Step(73): len = 334752, overlap = 392.281
+PHY-3002 : Step(74): len = 333824, overlap = 357.469
+PHY-3002 : Step(75): len = 335637, overlap = 379.844
+PHY-3002 : Step(76): len = 334442, overlap = 390.5
+PHY-3002 : Step(77): len = 334205, overlap = 407.562
+PHY-3002 : Step(78): len = 334333, overlap = 392.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.20498e-05
+PHY-3002 : Step(79): len = 350059, overlap = 360.938
+PHY-3002 : Step(80): len = 361689, overlap = 339.031
+PHY-3002 : Step(81): len = 364498, overlap = 329.688
+PHY-3002 : Step(82): len = 368120, overlap = 324.688
+PHY-3002 : Step(83): len = 371135, overlap = 305.406
+PHY-3002 : Step(84): len = 373997, overlap = 280.5
+PHY-3002 : Step(85): len = 371594, overlap = 279.188
+PHY-3002 : Step(86): len = 373031, overlap = 280.469
+PHY-3002 : Step(87): len = 374790, overlap = 279.188
+PHY-3002 : Step(88): len = 376019, overlap = 266.062
+PHY-3002 : Step(89): len = 375474, overlap = 260.156
+PHY-3002 : Step(90): len = 377506, overlap = 264.469
+PHY-3002 : Step(91): len = 379997, overlap = 270.062
+PHY-3002 : Step(92): len = 381499, overlap = 250.094
+PHY-3002 : Step(93): len = 378396, overlap = 252.562
+PHY-3002 : Step(94): len = 378137, overlap = 257.031
+PHY-3002 : Step(95): len = 377776, overlap = 258.812
+PHY-3002 : Step(96): len = 378238, overlap = 260.094
+PHY-3002 : Step(97): len = 377541, overlap = 259.375
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.40997e-05
+PHY-3002 : Step(98): len = 393731, overlap = 263.688
+PHY-3002 : Step(99): len = 403714, overlap = 270.438
+PHY-3002 : Step(100): len = 402161, overlap = 260.656
+PHY-3002 : Step(101): len = 403139, overlap = 265.25
+PHY-3002 : Step(102): len = 406115, overlap = 263.562
+PHY-3002 : Step(103): len = 409921, overlap = 261.969
+PHY-3002 : Step(104): len = 409057, overlap = 261.656
+PHY-3002 : Step(105): len = 411247, overlap = 265.344
+PHY-3002 : Step(106): len = 415044, overlap = 267.875
+PHY-3002 : Step(107): len = 417805, overlap = 267
+PHY-3002 : Step(108): len = 414534, overlap = 279.844
+PHY-3002 : Step(109): len = 413890, overlap = 267.531
+PHY-3002 : Step(110): len = 415583, overlap = 257.938
+PHY-3002 : Step(111): len = 417219, overlap = 249.938
+PHY-3002 : Step(112): len = 413916, overlap = 234.875
+PHY-3002 : Step(113): len = 414176, overlap = 247.031
+PHY-3002 : Step(114): len = 415397, overlap = 239.5
+PHY-3002 : Step(115): len = 416638, overlap = 231.375
+PHY-3002 : Step(116): len = 414219, overlap = 227.656
+PHY-3002 : Step(117): len = 414070, overlap = 224.562
+PHY-3002 : Step(118): len = 415000, overlap = 225.969
+PHY-3002 : Step(119): len = 416356, overlap = 230.719
+PHY-3002 : Step(120): len = 414329, overlap = 243.5
+PHY-3002 : Step(121): len = 414525, overlap = 240.781
+PHY-3002 : Step(122): len = 415219, overlap = 251.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168199
+PHY-3002 : Step(123): len = 427793, overlap = 228.094
+PHY-3002 : Step(124): len = 434978, overlap = 211.5
+PHY-3002 : Step(125): len = 434224, overlap = 212.938
+PHY-3002 : Step(126): len = 434893, overlap = 214.719
+PHY-3002 : Step(127): len = 437387, overlap = 214.312
+PHY-3002 : Step(128): len = 440422, overlap = 218.344
+PHY-3002 : Step(129): len = 439475, overlap = 220.5
+PHY-3002 : Step(130): len = 439959, overlap = 218.125
+PHY-3002 : Step(131): len = 442104, overlap = 214.969
+PHY-3002 : Step(132): len = 443728, overlap = 215.188
+PHY-3002 : Step(133): len = 442552, overlap = 226.062
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000315424
+PHY-3002 : Step(134): len = 449199, overlap = 215
+PHY-3002 : Step(135): len = 456791, overlap = 208.969
+PHY-3002 : Step(136): len = 458741, overlap = 221.25
+PHY-3002 : Step(137): len = 460138, overlap = 210.938
+PHY-3002 : Step(138): len = 461978, overlap = 206.938
+PHY-3002 : Step(139): len = 463732, overlap = 200.469
+PHY-3002 : Step(140): len = 463075, overlap = 203.844
+PHY-3002 : Step(141): len = 464420, overlap = 206.25
+PHY-3002 : Step(142): len = 466826, overlap = 197.656
+PHY-3002 : Step(143): len = 468395, overlap = 196.719
+PHY-3002 : Step(144): len = 468161, overlap = 197.438
+PHY-3002 : Step(145): len = 468919, overlap = 193.844
+PHY-3002 : Step(146): len = 470408, overlap = 190.969
+PHY-3002 : Step(147): len = 471038, overlap = 194.094
+PHY-3002 : Step(148): len = 470098, overlap = 194.125
+PHY-3002 : Step(149): len = 469787, overlap = 192.844
+PHY-3002 : Step(150): len = 470962, overlap = 194.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000597386
+PHY-3002 : Step(151): len = 477356, overlap = 187.469
+PHY-3002 : Step(152): len = 485467, overlap = 177.438
+PHY-3002 : Step(153): len = 487792, overlap = 172.25
+PHY-3002 : Step(154): len = 489820, overlap = 169.969
+PHY-3002 : Step(155): len = 492289, overlap = 166.719
+PHY-3002 : Step(156): len = 494288, overlap = 161.812
+PHY-3002 : Step(157): len = 494621, overlap = 167.094
+PHY-3002 : Step(158): len = 495412, overlap = 158.875
+PHY-3002 : Step(159): len = 497530, overlap = 158.125
+PHY-3002 : Step(160): len = 499660, overlap = 161.844
+PHY-3002 : Step(161): len = 499659, overlap = 155.344
+PHY-3002 : Step(162): len = 500171, overlap = 145.469
+PHY-3002 : Step(163): len = 501354, overlap = 144.875
+PHY-3002 : Step(164): len = 502419, overlap = 141.625
+PHY-3002 : Step(165): len = 502507, overlap = 135.938
+PHY-3002 : Step(166): len = 502911, overlap = 136.219
+PHY-3002 : Step(167): len = 503441, overlap = 133.781
+PHY-3002 : Step(168): len = 503676, overlap = 133.844
+PHY-3002 : Step(169): len = 503613, overlap = 131.625
+PHY-3002 : Step(170): len = 503662, overlap = 133.656
+PHY-3002 : Step(171): len = 503864, overlap = 139.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108125
+PHY-3002 : Step(172): len = 508017, overlap = 138.406
+PHY-3002 : Step(173): len = 515100, overlap = 140.438
+PHY-3002 : Step(174): len = 516366, overlap = 136.719
+PHY-3002 : Step(175): len = 517528, overlap = 132.312
+PHY-3002 : Step(176): len = 519652, overlap = 132.719
+PHY-3002 : Step(177): len = 520672, overlap = 132.875
+PHY-3002 : Step(178): len = 520221, overlap = 132.375
+PHY-3002 : Step(179): len = 520126, overlap = 135.25
+PHY-3002 : Step(180): len = 521307, overlap = 133.188
+PHY-3002 : Step(181): len = 522214, overlap = 132.5
+PHY-3002 : Step(182): len = 521960, overlap = 133.5
+PHY-3002 : Step(183): len = 521951, overlap = 135.812
+PHY-3002 : Step(184): len = 522274, overlap = 134.25
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00187339
+PHY-3002 : Step(185): len = 525598, overlap = 136.688
+PHY-3002 : Step(186): len = 531982, overlap = 134.781
+PHY-3002 : Step(187): len = 533798, overlap = 129.438
+PHY-3002 : Step(188): len = 534889, overlap = 126.938
+PHY-3002 : Step(189): len = 535931, overlap = 126.094
+PHY-3002 : Step(190): len = 536614, overlap = 125.531
+PHY-3002 : Step(191): len = 537630, overlap = 128.594
+PHY-3002 : Step(192): len = 538953, overlap = 129.156
+PHY-3002 : Step(193): len = 539831, overlap = 128.594
+PHY-3002 : Step(194): len = 540970, overlap = 124.75
+PHY-3002 : Step(195): len = 542306, overlap = 125.406
+PHY-3002 : Step(196): len = 542817, overlap = 125.406
+PHY-3002 : Step(197): len = 543125, overlap = 123.969
+PHY-3002 : Step(198): len = 543331, overlap = 123.969
+PHY-3002 : Step(199): len = 543607, overlap = 125.344
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00307474
+PHY-3002 : Step(200): len = 546970, overlap = 124.781
+PHY-3002 : Step(201): len = 555249, overlap = 108.75
+PHY-3002 : Step(202): len = 560298, overlap = 101.938
+PHY-3002 : Step(203): len = 566036, overlap = 104.688
+PHY-3002 : Step(204): len = 569242, overlap = 103.969
+PHY-3002 : Step(205): len = 572082, overlap = 105.062
+PHY-3002 : Step(206): len = 573488, overlap = 100.906
+PHY-3002 : Step(207): len = 574436, overlap = 101.594
+PHY-3002 : Step(208): len = 574997, overlap = 98.375
+PHY-3002 : Step(209): len = 575327, overlap = 96.875
+PHY-3002 : Step(210): len = 575154, overlap = 96.2812
+PHY-3002 : Step(211): len = 574947, overlap = 90.3438
+PHY-3002 : Step(212): len = 574615, overlap = 96.1562
+PHY-3002 : Step(213): len = 574424, overlap = 96.1562
+PHY-3002 : Step(214): len = 574285, overlap = 91.1562
+PHY-3002 : Step(215): len = 574158, overlap = 90.1562
+PHY-3002 : Step(216): len = 573866, overlap = 87.6562
+PHY-3002 : Step(217): len = 573742, overlap = 90.125
+PHY-3002 : Step(218): len = 573607, overlap = 89.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.018067s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (86.5%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753960, over cnt = 1673(4%), over = 7641, worst = 41
+PHY-1001 : End global iterations; 0.779959s wall, 1.093750s user + 0.062500s system = 1.156250s CPU (148.2%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 63.38, top10 = 53.94, top15 = 48.26.
+PHY-3001 : End congestion estimation; 1.048562s wall, 1.359375s user + 0.062500s system = 1.421875s CPU (135.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.936387s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012894
+PHY-3002 : Step(219): len = 682872, overlap = 60.7812
+PHY-3002 : Step(220): len = 680164, overlap = 61.5
+PHY-3002 : Step(221): len = 671439, overlap = 58.2812
+PHY-3002 : Step(222): len = 665226, overlap = 60.6875
+PHY-3002 : Step(223): len = 663081, overlap = 55.8438
+PHY-3002 : Step(224): len = 662916, overlap = 53.5938
+PHY-3002 : Step(225): len = 660482, overlap = 53.4375
+PHY-3002 : Step(226): len = 656745, overlap = 53.25
+PHY-3002 : Step(227): len = 653517, overlap = 53.7188
+PHY-3002 : Step(228): len = 651915, overlap = 50.4688
+PHY-3002 : Step(229): len = 650566, overlap = 43.9375
+PHY-3002 : Step(230): len = 649789, overlap = 39.6562
+PHY-3002 : Step(231): len = 649010, overlap = 39.6875
+PHY-3002 : Step(232): len = 648983, overlap = 36.4375
+PHY-3002 : Step(233): len = 648835, overlap = 39.7188
+PHY-3002 : Step(234): len = 649183, overlap = 37.0625
+PHY-3002 : Step(235): len = 647443, overlap = 37.6562
+PHY-3002 : Step(236): len = 646551, overlap = 37.75
+PHY-3002 : Step(237): len = 644304, overlap = 38.4688
+PHY-3002 : Step(238): len = 642657, overlap = 46.9062
+PHY-3002 : Step(239): len = 640494, overlap = 55.25
+PHY-3002 : Step(240): len = 638385, overlap = 57.375
+PHY-3002 : Step(241): len = 636246, overlap = 62.2812
+PHY-3002 : Step(242): len = 634318, overlap = 64.0625
+PHY-3002 : Step(243): len = 632554, overlap = 66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025788
+PHY-3002 : Step(244): len = 636935, overlap = 63.2812
+PHY-3002 : Step(245): len = 642468, overlap = 58.875
+PHY-3002 : Step(246): len = 644067, overlap = 55.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479888
+PHY-3002 : Step(247): len = 655065, overlap = 49.3125
+PHY-3002 : Step(248): len = 673391, overlap = 48.2188
+PHY-3002 : Step(249): len = 686922, overlap = 44.4375
+PHY-3002 : Step(250): len = 689884, overlap = 43.6875
+PHY-3002 : Step(251): len = 689070, overlap = 41.375
+PHY-3002 : Step(252): len = 686972, overlap = 40.5625
+PHY-3002 : Step(253): len = 686400, overlap = 38.8438
+PHY-3002 : Step(254): len = 686300, overlap = 37.125
+PHY-3002 : Step(255): len = 687195, overlap = 36.875
+PHY-3002 : Step(256): len = 688672, overlap = 36.3125
+PHY-3002 : Step(257): len = 687776, overlap = 38.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000959777
+PHY-3002 : Step(258): len = 693185, overlap = 37.9375
+PHY-3002 : Step(259): len = 707793, overlap = 42.5625
+PHY-3002 : Step(260): len = 721904, overlap = 45.25
+PHY-3002 : Step(261): len = 720538, overlap = 45.125
+PHY-3002 : Step(262): len = 718584, overlap = 47.0625
+PHY-3002 : Step(263): len = 718363, overlap = 47.125
+PHY-3002 : Step(264): len = 719234, overlap = 46.2812
+PHY-3002 : Step(265): len = 718781, overlap = 48.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00167098
+PHY-3002 : Step(266): len = 722104, overlap = 49.2188
+PHY-3002 : Step(267): len = 730523, overlap = 49.75
+PHY-3002 : Step(268): len = 737525, overlap = 49.1875
+PHY-3002 : Step(269): len = 740778, overlap = 49.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 74/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825680, over cnt = 2877(8%), over = 14308, worst = 47
+PHY-1001 : End global iterations; 1.651099s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (137.2%)
+
+PHY-1001 : Congestion index: top1 = 102.03, top5 = 79.19, top10 = 68.21, top15 = 61.55.
+PHY-3001 : End congestion estimation; 1.947071s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (131.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.962442s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124258
+PHY-3002 : Step(270): len = 725463, overlap = 236.562
+PHY-3002 : Step(271): len = 714675, overlap = 193.031
+PHY-3002 : Step(272): len = 701615, overlap = 166.75
+PHY-3002 : Step(273): len = 689587, overlap = 158.375
+PHY-3002 : Step(274): len = 680492, overlap = 144.562
+PHY-3002 : Step(275): len = 672516, overlap = 132.812
+PHY-3002 : Step(276): len = 666832, overlap = 120.75
+PHY-3002 : Step(277): len = 661263, overlap = 110.562
+PHY-3002 : Step(278): len = 655318, overlap = 116.375
+PHY-3002 : Step(279): len = 649278, overlap = 130
+PHY-3002 : Step(280): len = 643735, overlap = 130.25
+PHY-3002 : Step(281): len = 639232, overlap = 127.812
+PHY-3002 : Step(282): len = 634588, overlap = 129.969
+PHY-3002 : Step(283): len = 632464, overlap = 131.406
+PHY-3002 : Step(284): len = 628294, overlap = 126.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000248516
+PHY-3002 : Step(285): len = 629070, overlap = 123.781
+PHY-3002 : Step(286): len = 629965, overlap = 121.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000410701
+PHY-3002 : Step(287): len = 632475, overlap = 120.031
+PHY-3002 : Step(288): len = 642103, overlap = 112.312
+PHY-3002 : Step(289): len = 646065, overlap = 106.562
+PHY-3002 : Step(290): len = 643239, overlap = 108.25
+PHY-3002 : Step(291): len = 641402, overlap = 106.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000710718
+PHY-3002 : Step(292): len = 645464, overlap = 105.312
+PHY-3002 : Step(293): len = 650386, overlap = 94.7812
+PHY-3002 : Step(294): len = 655979, overlap = 89.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00142144
+PHY-3002 : Step(295): len = 657103, overlap = 88.4062
+PHY-3002 : Step(296): len = 661829, overlap = 85.6562
+PHY-3002 : Step(297): len = 669725, overlap = 77.25
+PHY-3002 : Step(298): len = 674047, overlap = 72.9375
+PHY-3002 : Step(299): len = 675876, overlap = 71.2188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83961, tnet num: 20386, tinst num: 17984, tnode num: 114219, tedge num: 133880.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.565044s wall, 1.531250s user + 0.031250s system = 1.562500s CPU (99.8%)
+
+RUN-1004 : used memory is 584 MB, reserved memory is 564 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 378.78 peak overflow 2.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 541/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777144, over cnt = 3139(8%), over = 11076, worst = 28
+PHY-1001 : End global iterations; 1.729981s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 71.70, top5 = 58.36, top10 = 52.43, top15 = 48.72.
+PHY-1001 : End incremental global routing; 2.108214s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (132.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.993123s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.1%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 318 needs to be replaced
+PHY-3001 : design contains 18256 instances, 7754 luts, 9281 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6080 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700079
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17267/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793176, over cnt = 3172(9%), over = 11083, worst = 28
+PHY-1001 : End global iterations; 0.271533s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (143.9%)
+
+PHY-1001 : Congestion index: top1 = 71.14, top5 = 58.22, top10 = 52.62, top15 = 49.03.
+PHY-3001 : End congestion estimation; 0.557104s wall, 0.640625s user + 0.015625s system = 0.656250s CPU (117.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85043, tnet num: 20658, tinst num: 18256, tnode num: 115859, tedge num: 135500.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.618513s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.4%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 615 MB, peak memory is 723 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.097003s wall, 3.078125s user + 0.015625s system = 3.093750s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(300): len = 699095, overlap = 0.1875
+PHY-3002 : Step(301): len = 698633, overlap = 0
+PHY-3002 : Step(302): len = 698393, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17369/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790720, over cnt = 3169(9%), over = 11146, worst = 28
+PHY-1001 : End global iterations; 0.231740s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (114.6%)
+
+PHY-1001 : Congestion index: top1 = 71.81, top5 = 58.63, top10 = 52.89, top15 = 49.25.
+PHY-3001 : End congestion estimation; 0.522599s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (107.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.013320s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000436837
+PHY-3002 : Step(303): len = 698158, overlap = 72.9375
+PHY-3002 : Step(304): len = 698336, overlap = 73.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000873674
+PHY-3002 : Step(305): len = 698525, overlap = 73.0625
+PHY-3002 : Step(306): len = 698983, overlap = 73.5625
+PHY-3001 : Final: Len = 698983, Over = 73.5625
+PHY-3001 : End incremental placement; 5.917622s wall, 6.265625s user + 0.187500s system = 6.453125s CPU (109.0%)
+
+OPT-1001 : Total overflow 384.31 peak overflow 2.78
+OPT-1001 : End high-fanout net optimization; 9.596983s wall, 10.625000s user + 0.187500s system = 10.812500s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 724, reserve = 710, peak = 742.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17297/20836.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793536, over cnt = 3069(8%), over = 10071, worst = 28
+PHY-1002 : len = 834904, over cnt = 2268(6%), over = 6024, worst = 23
+PHY-1002 : len = 878272, over cnt = 1104(3%), over = 2756, worst = 23
+PHY-1002 : len = 909920, over cnt = 279(0%), over = 702, worst = 13
+PHY-1002 : len = 919472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.014412s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (128.8%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.59, top10 = 48.02, top15 = 45.70.
+OPT-1001 : End congestion update; 2.318337s wall, 2.890625s user + 0.000000s system = 2.890625s CPU (124.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20658 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.850207s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (101.1%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 119 cells processed and 18250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 53 cells processed and 6850 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1900 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 850 slack improved
+OPT-1001 : End bottleneck based optimization; 3.603282s wall, 4.171875s user + 0.000000s system = 4.171875s CPU (115.8%)
+
+OPT-1001 : Current memory(MB): used = 703, reserve = 691, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17333/20842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920464, over cnt = 83(0%), over = 110, worst = 4
+PHY-1002 : len = 920512, over cnt = 40(0%), over = 43, worst = 3
+PHY-1002 : len = 920776, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 921040, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 921072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.776726s wall, 0.812500s user + 0.046875s system = 0.859375s CPU (110.6%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 51.38, top10 = 47.82, top15 = 45.53.
+OPT-1001 : End congestion update; 1.075665s wall, 1.109375s user + 0.046875s system = 1.156250s CPU (107.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.854817s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.7%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.062475s wall, 2.078125s user + 0.046875s system = 2.125000s CPU (103.0%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 699, peak = 742.
+OPT-1001 : End physical optimization; 17.165798s wall, 18.796875s user + 0.265625s system = 19.062500s CPU (111.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7754 LUT to BLE ...
+SYN-4008 : Packed 7754 LUT and 3134 SEQ to BLE.
+SYN-4003 : Packing 6153 remaining SEQ's ...
+SYN-4005 : Packed 4101 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2052 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9806/13661 primitive instances ...
+PHY-3001 : End packing; 1.812540s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6670 instances
+RUN-1001 : 3261 mslices, 3261 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17832 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6509 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6668 instances, 6522 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3515 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 705686, Over = 204.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7445/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858864, over cnt = 2009(5%), over = 3264, worst = 8
+PHY-1002 : len = 867896, over cnt = 1189(3%), over = 1689, worst = 7
+PHY-1002 : len = 880112, over cnt = 514(1%), over = 700, worst = 6
+PHY-1002 : len = 887272, over cnt = 163(0%), over = 222, worst = 5
+PHY-1002 : len = 890768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.924067s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 57.39, top5 = 50.20, top10 = 46.73, top15 = 44.49.
+PHY-3001 : End congestion estimation; 2.376176s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (135.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6668, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.742928s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (99.5%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 615 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.673065s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.26697e-05
+PHY-3002 : Step(307): len = 691602, overlap = 206
+PHY-3002 : Step(308): len = 683836, overlap = 205.25
+PHY-3002 : Step(309): len = 677655, overlap = 206.75
+PHY-3002 : Step(310): len = 672841, overlap = 216.25
+PHY-3002 : Step(311): len = 669449, overlap = 225
+PHY-3002 : Step(312): len = 666398, overlap = 225.25
+PHY-3002 : Step(313): len = 664858, overlap = 218.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000125339
+PHY-3002 : Step(314): len = 666869, overlap = 208.75
+PHY-3002 : Step(315): len = 670486, overlap = 203.75
+PHY-3002 : Step(316): len = 671644, overlap = 199.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000250679
+PHY-3002 : Step(317): len = 677534, overlap = 198.25
+PHY-3002 : Step(318): len = 684375, overlap = 186.75
+PHY-3002 : Step(319): len = 684183, overlap = 186.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.426084s wall, 0.390625s user + 0.703125s system = 1.093750s CPU (256.7%)
+
+PHY-3001 : Trial Legalized: Len = 757719
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 975/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872424, over cnt = 2646(7%), over = 4451, worst = 7
+PHY-1002 : len = 892264, over cnt = 1457(4%), over = 2022, worst = 7
+PHY-1002 : len = 912312, over cnt = 398(1%), over = 525, worst = 5
+PHY-1002 : len = 919384, over cnt = 79(0%), over = 100, worst = 5
+PHY-1002 : len = 921248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.815001s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (141.0%)
+
+PHY-1001 : Congestion index: top1 = 56.68, top5 = 50.88, top10 = 47.48, top15 = 45.26.
+PHY-3001 : End congestion estimation; 3.316295s wall, 4.468750s user + 0.015625s system = 4.484375s CPU (135.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.931634s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171654
+PHY-3002 : Step(320): len = 732552, overlap = 37.25
+PHY-3002 : Step(321): len = 717815, overlap = 56.75
+PHY-3002 : Step(322): len = 705260, overlap = 79.75
+PHY-3002 : Step(323): len = 697585, overlap = 105.75
+PHY-3002 : Step(324): len = 692369, overlap = 121
+PHY-3002 : Step(325): len = 690073, overlap = 130.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343309
+PHY-3002 : Step(326): len = 694281, overlap = 126.5
+PHY-3002 : Step(327): len = 698775, overlap = 122.25
+PHY-3002 : Step(328): len = 700530, overlap = 125.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000686617
+PHY-3002 : Step(329): len = 703663, overlap = 123.75
+PHY-3002 : Step(330): len = 708517, overlap = 120.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034890s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.6%)
+
+PHY-3001 : Legalized: Len = 735420, Over = 0
+PHY-3001 : Spreading special nets. 441 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.105723s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (103.5%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 183, deltaY = 345, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 744855, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71314, tnet num: 17654, tinst num: 6671, tnode num: 93631, tedge num: 118491.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.998657s wall, 1.953125s user + 0.031250s system = 1.984375s CPU (99.3%)
+
+RUN-1004 : used memory is 637 MB, reserved memory is 647 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4683/17832.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874512, over cnt = 2464(7%), over = 3852, worst = 8
+PHY-1002 : len = 886000, over cnt = 1564(4%), over = 2201, worst = 6
+PHY-1002 : len = 906104, over cnt = 411(1%), over = 514, worst = 5
+PHY-1002 : len = 913792, over cnt = 70(0%), over = 85, worst = 5
+PHY-1002 : len = 915416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.408783s wall, 3.343750s user + 0.046875s system = 3.390625s CPU (140.8%)
+
+PHY-1001 : Congestion index: top1 = 56.27, top5 = 49.95, top10 = 46.69, top15 = 44.63.
+PHY-1001 : End incremental global routing; 2.821898s wall, 3.765625s user + 0.046875s system = 3.812500s CPU (135.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17654 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.939942s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.7%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6579 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 750654
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16211/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922952, over cnt = 103(0%), over = 140, worst = 8
+PHY-1002 : len = 923128, over cnt = 58(0%), over = 74, worst = 8
+PHY-1002 : len = 923920, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 924112, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 924224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.880024s wall, 0.890625s user + 0.046875s system = 0.937500s CPU (106.5%)
+
+PHY-1001 : Congestion index: top1 = 56.29, top5 = 50.12, top10 = 46.94, top15 = 44.88.
+PHY-3001 : End congestion estimation; 1.236299s wall, 1.250000s user + 0.046875s system = 1.296875s CPU (104.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71542, tnet num: 17675, tinst num: 6692, tnode num: 93911, tedge num: 118783.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.965869s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (99.4%)
+
+RUN-1004 : used memory is 663 MB, reserved memory is 661 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.909195s wall, 2.828125s user + 0.046875s system = 2.875000s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(331): len = 748232, overlap = 0
+PHY-3002 : Step(332): len = 747363, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16198/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919288, over cnt = 71(0%), over = 97, worst = 4
+PHY-1002 : len = 919528, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 920032, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 920080, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 920112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.859440s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (107.3%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.97, top10 = 46.77, top15 = 44.70.
+PHY-3001 : End congestion estimation; 1.202072s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (105.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.919103s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000157527
+PHY-3002 : Step(333): len = 747253, overlap = 1
+PHY-3002 : Step(334): len = 747381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005283s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (295.8%)
+
+PHY-3001 : Legalized: Len = 747516, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065375s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.5%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 747582, Over = 0
+PHY-3001 : End incremental placement; 6.804795s wall, 6.781250s user + 0.171875s system = 6.953125s CPU (102.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.086822s wall, 12.015625s user + 0.218750s system = 12.234375s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 737, peak = 746.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16175/17853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919680, over cnt = 54(0%), over = 70, worst = 4
+PHY-1002 : len = 919672, over cnt = 35(0%), over = 44, worst = 3
+PHY-1002 : len = 920096, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 920168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.668148s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (107.6%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.95, top10 = 46.76, top15 = 44.70.
+OPT-1001 : End congestion update; 1.008653s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (102.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.763324s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.3%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 756770, Over = 0
+PHY-3001 : Spreading special nets. 30 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068407s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.4%)
+
+PHY-3001 : 41 instances has been re-located, deltaX = 12, deltaY = 27, maxDist = 3.
+PHY-3001 : Final: Len = 757514, Over = 0
+PHY-3001 : End incremental legalization; 0.426062s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (117.4%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 60 cells processed and 22074 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758204, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062929s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.3%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 16, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758608, Over = 0
+PHY-3001 : End incremental legalization; 0.480418s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (123.6%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 4156 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6604 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6692 instances, 6543 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758812, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067510s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (115.7%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 7, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 759358, Over = 0
+PHY-3001 : End incremental legalization; 0.476747s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.6%)
+
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 18 cells processed and 1161 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759597, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069149s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.4%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 759599, Over = 0
+PHY-3001 : End incremental legalization; 0.445174s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (101.8%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization; 4.283871s wall, 4.578125s user + 0.015625s system = 4.593750s CPU (107.2%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 735, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15721/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930944, over cnt = 193(0%), over = 264, worst = 6
+PHY-1002 : len = 931160, over cnt = 92(0%), over = 103, worst = 3
+PHY-1002 : len = 931928, over cnt = 35(0%), over = 35, worst = 1
+PHY-1002 : len = 932424, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932504, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.901744s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (109.2%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 49.54, top10 = 46.48, top15 = 44.48.
+OPT-1001 : End congestion update; 1.245468s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (107.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.755228s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.3%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6611 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6699 instances, 6550 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3586 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 759705, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062819s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 759739, Over = 0
+PHY-3001 : End incremental legalization; 0.402799s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (128.0%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.535807s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (107.8%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 735, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.756223s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16201/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932536, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 932560, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 932624, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 932744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 932808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.806397s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.8%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.58, top10 = 46.48, top15 = 44.49.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.762079s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.843797s wall, 24.187500s user + 0.296875s system = 24.484375s CPU (107.2%)
+
+RUN-1003 : finish command "place" in 74.982882s wall, 111.609375s user + 7.562500s system = 119.171875s CPU (158.9%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 599 MB, peak memory is 746 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.820221s wall, 3.109375s user + 0.000000s system = 3.109375s CPU (170.8%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 600 MB, peak memory is 746 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6701 instances
+RUN-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17857 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9958 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 734 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.705798s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.8%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 631 MB, peak memory is 746 MB
+PHY-1001 : 3281 mslices, 3269 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862800, over cnt = 2648(7%), over = 4341, worst = 9
+PHY-1002 : len = 880744, over cnt = 1618(4%), over = 2343, worst = 9
+PHY-1002 : len = 903616, over cnt = 451(1%), over = 577, worst = 6
+PHY-1002 : len = 912696, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 913024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.467417s wall, 4.500000s user + 0.046875s system = 4.546875s CPU (131.1%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.00, top10 = 45.84, top15 = 43.81.
+PHY-1001 : End global routing; 3.829705s wall, 4.859375s user + 0.046875s system = 4.906250s CPU (128.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 716, reserve = 710, peak = 746.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 987, reserve = 981, peak = 987.
+PHY-1001 : End build detailed router design. 4.323283s wall, 4.265625s user + 0.062500s system = 4.328125s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270736, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.857670s wall, 5.828125s user + 0.031250s system = 5.859375s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270792, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.493192s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.2%)
+
+PHY-1001 : Current memory(MB): used = 1022, reserve = 1017, peak = 1022.
+PHY-1001 : End phase 1; 6.362861s wall, 6.328125s user + 0.031250s system = 6.359375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1031, peak = 1036.
+PHY-1001 : End initial routed; 39.042223s wall, 73.781250s user + 0.406250s system = 74.187500s CPU (190.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.492934s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1048, peak = 1054.
+PHY-1001 : End phase 2; 42.535227s wall, 77.265625s user + 0.406250s system = 77.671875s CPU (182.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.147177s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.2%)
+
+PHY-1022 : len = 2.28925e+06, over cnt = 1715(0%), over = 1720, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.437961s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26109e+06, over cnt = 626(0%), over = 627, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.573292s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (166.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25966e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.822901s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (150.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25927e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.486668s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (109.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25919e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.326486s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (105.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.260252s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (102.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.466000s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.382374s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (98.4%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1157, peak = 1159.
+PHY-1001 : End phase 3; 10.177979s wall, 11.656250s user + 0.000000s system = 11.656250s CPU (114.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.146562s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.9%)
+
+PHY-1022 : len = 2.25928e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.415514s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16780(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.547942s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (99.5%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 529 feed throughs used by 395 nets
+PHY-1001 : End commit to database; 2.466482s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1165, peak = 1167.
+PHY-1001 : End phase 4; 6.456425s wall, 6.406250s user + 0.015625s system = 6.421875s CPU (99.5%)
+
+PHY-1003 : Routed, final wirelength = 2.25928e+06
+PHY-1001 : Current memory(MB): used = 1171, reserve = 1170, peak = 1171.
+PHY-1001 : End export database. 0.067312s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (116.1%)
+
+PHY-1001 : End detail routing; 70.351189s wall, 106.421875s user + 0.515625s system = 106.937500s CPU (152.0%)
+
+RUN-1003 : finish command "route" in 77.071165s wall, 114.109375s user + 0.609375s system = 114.718750s CPU (148.8%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1092 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10187 out of 19600 51.97%
+#reg 9425 out of 19600 48.09%
+#le 12209
+ #lut only 2784 out of 12209 22.80%
+ #reg only 2022 out of 12209 16.56%
+ #lut® 7403 out of 12209 60.64%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1380
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1287
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 961
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 131
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_307.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE NONE
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE NONE
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P170 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12209 |9160 |1027 |9456 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |457 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |97 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |42 |42 |0 |19 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |759 |371 |96 |575 |0 |0 |
+| u_ADconfig |AD_config |187 |121 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |260 |165 |71 |119 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |384 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |173 |121 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |254 |145 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2935 |2382 |306 |2076 |25 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |170 |93 |17 |140 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort |2735 |2268 |289 |1906 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2326 |1968 |253 |1555 |22 |0 |
+| channelPart |channel_part_8478 |141 |135 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |50 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1807 |1513 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |208 |181 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |961 |694 |170 |656 |0 |0 |
+| ram_switch_state |ram_switch_state |638 |638 |0 |372 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |48 |41 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |235 |36 |273 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3122 |2458 |349 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |171 |115 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2917 |2332 |332 |1914 |25 |1 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2476 |1975 |290 |1550 |22 |1 |
+| channelPart |channel_part_8478 |130 |124 |3 |126 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1909 |1532 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |202 |174 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |1003 |657 |170 |701 |0 |0 |
+| ram_switch_state |ram_switch_state |704 |701 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |352 |251 |81 |203 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |162 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |41 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9896
+ #2 2 4222
+ #3 3 1721
+ #4 4 562
+ #5 5-10 766
+ #6 11-50 583
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.157640s wall, 3.718750s user + 0.015625s system = 3.734375s CPU (173.1%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1092 MB, peak memory is 1171 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71607, tnet num: 17679, tinst num: 6699, tnode num: 93998, tedge num: 118892.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.675976s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (99.8%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1096 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.621481s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (100.2%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1110 MB, peak memory is 1171 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6699
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17857, pip num: 168201
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 529
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3230 valid insts, and 469612 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.874696s wall, 65.140625s user + 0.296875s system = 65.437500s CPU (662.7%)
+
+RUN-1004 : used memory is 1254 MB, reserved memory is 1248 MB, peak memory is 1369 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_115727.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_135807.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_135807.log
new file mode 100644
index 0000000..4e2b49b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_135807.log
@@ -0,0 +1,2148 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 13:58:07 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.313929s wall, 2.171875s user + 0.125000s system = 2.296875s CPU (99.3%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 316 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17987 instances
+RUN-0007 : 7662 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20565 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13088 nets have 2 pins
+RUN-1001 : 6442 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 178 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17985 instances, 7662 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83999, tnet num: 20387, tinst num: 17985, tnode num: 114266, tedge num: 133954.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.286128s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (99.6%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 514 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.143405s wall, 2.109375s user + 0.031250s system = 2.140625s CPU (99.9%)
+
+PHY-3001 : Found 1252 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.04709e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17985.
+PHY-3001 : Level 1 #clusters 2093.
+PHY-3001 : End clustering; 0.138062s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32153e+06, overlap = 454.281
+PHY-3002 : Step(2): len = 1.22336e+06, overlap = 498.031
+PHY-3002 : Step(3): len = 865736, overlap = 561.156
+PHY-3002 : Step(4): len = 794082, overlap = 610.406
+PHY-3002 : Step(5): len = 611119, overlap = 754.531
+PHY-3002 : Step(6): len = 539691, overlap = 801.375
+PHY-3002 : Step(7): len = 462772, overlap = 904.469
+PHY-3002 : Step(8): len = 414645, overlap = 940.125
+PHY-3002 : Step(9): len = 382084, overlap = 1007.16
+PHY-3002 : Step(10): len = 348412, overlap = 1058.81
+PHY-3002 : Step(11): len = 319713, overlap = 1087.34
+PHY-3002 : Step(12): len = 285101, overlap = 1139.75
+PHY-3002 : Step(13): len = 271590, overlap = 1194.16
+PHY-3002 : Step(14): len = 239354, overlap = 1276.62
+PHY-3002 : Step(15): len = 225261, overlap = 1306.19
+PHY-3002 : Step(16): len = 197792, overlap = 1346.31
+PHY-3002 : Step(17): len = 193175, overlap = 1356.59
+PHY-3002 : Step(18): len = 172105, overlap = 1378.81
+PHY-3002 : Step(19): len = 167653, overlap = 1405.72
+PHY-3002 : Step(20): len = 151262, overlap = 1442.38
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.21019e-06
+PHY-3002 : Step(21): len = 153356, overlap = 1398.62
+PHY-3002 : Step(22): len = 186579, overlap = 1254.44
+PHY-3002 : Step(23): len = 197752, overlap = 1194.81
+PHY-3002 : Step(24): len = 206211, overlap = 1158.94
+PHY-3002 : Step(25): len = 204887, overlap = 1143.59
+PHY-3002 : Step(26): len = 204973, overlap = 1140.03
+PHY-3002 : Step(27): len = 200489, overlap = 1151.84
+PHY-3002 : Step(28): len = 198315, overlap = 1155.53
+PHY-3002 : Step(29): len = 195079, overlap = 1131.19
+PHY-3002 : Step(30): len = 194530, overlap = 1114.34
+PHY-3002 : Step(31): len = 192202, overlap = 1107.62
+PHY-3002 : Step(32): len = 190962, overlap = 1113.91
+PHY-3002 : Step(33): len = 189192, overlap = 1114.59
+PHY-3002 : Step(34): len = 188940, overlap = 1098.03
+PHY-3002 : Step(35): len = 188303, overlap = 1103.22
+PHY-3002 : Step(36): len = 189128, overlap = 1105.91
+PHY-3002 : Step(37): len = 188540, overlap = 1091.97
+PHY-3002 : Step(38): len = 189795, overlap = 1049.69
+PHY-3002 : Step(39): len = 189266, overlap = 1033.94
+PHY-3002 : Step(40): len = 188850, overlap = 1035.91
+PHY-3002 : Step(41): len = 187392, overlap = 1051.06
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.42038e-06
+PHY-3002 : Step(42): len = 193766, overlap = 1046.75
+PHY-3002 : Step(43): len = 206493, overlap = 1010.44
+PHY-3002 : Step(44): len = 209323, overlap = 982.406
+PHY-3002 : Step(45): len = 213601, overlap = 948.844
+PHY-3002 : Step(46): len = 215731, overlap = 942.938
+PHY-3002 : Step(47): len = 216163, overlap = 951.031
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.84077e-06
+PHY-3002 : Step(48): len = 226572, overlap = 918.875
+PHY-3002 : Step(49): len = 246937, overlap = 892.281
+PHY-3002 : Step(50): len = 256057, overlap = 850.188
+PHY-3002 : Step(51): len = 260519, overlap = 810.188
+PHY-3002 : Step(52): len = 260159, overlap = 793.875
+PHY-3002 : Step(53): len = 260273, overlap = 778.156
+PHY-3002 : Step(54): len = 258478, overlap = 744.969
+PHY-3002 : Step(55): len = 256626, overlap = 745.156
+PHY-3002 : Step(56): len = 256517, overlap = 746.219
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.68154e-06
+PHY-3002 : Step(57): len = 269863, overlap = 722.312
+PHY-3002 : Step(58): len = 288907, overlap = 640
+PHY-3002 : Step(59): len = 300210, overlap = 571.594
+PHY-3002 : Step(60): len = 306866, overlap = 537.906
+PHY-3002 : Step(61): len = 307083, overlap = 541.719
+PHY-3002 : Step(62): len = 309324, overlap = 512.781
+PHY-3002 : Step(63): len = 306802, overlap = 505.219
+PHY-3002 : Step(64): len = 305600, overlap = 504.906
+PHY-3002 : Step(65): len = 304432, overlap = 521.281
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.93631e-05
+PHY-3002 : Step(66): len = 321107, overlap = 483.281
+PHY-3002 : Step(67): len = 335523, overlap = 465.156
+PHY-3002 : Step(68): len = 338542, overlap = 448.188
+PHY-3002 : Step(69): len = 342071, overlap = 455.406
+PHY-3002 : Step(70): len = 340230, overlap = 418.062
+PHY-3002 : Step(71): len = 341271, overlap = 421.531
+PHY-3002 : Step(72): len = 341094, overlap = 403.5
+PHY-3002 : Step(73): len = 343854, overlap = 391.062
+PHY-3002 : Step(74): len = 344245, overlap = 388.062
+PHY-3002 : Step(75): len = 344848, overlap = 389.594
+PHY-3002 : Step(76): len = 343943, overlap = 377.625
+PHY-3002 : Step(77): len = 344267, overlap = 370.344
+PHY-3002 : Step(78): len = 344584, overlap = 366.156
+PHY-3002 : Step(79): len = 344117, overlap = 373.969
+PHY-3002 : Step(80): len = 342697, overlap = 373.781
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.87261e-05
+PHY-3002 : Step(81): len = 356790, overlap = 343.094
+PHY-3002 : Step(82): len = 365756, overlap = 327.719
+PHY-3002 : Step(83): len = 369028, overlap = 320.25
+PHY-3002 : Step(84): len = 369873, overlap = 309.906
+PHY-3002 : Step(85): len = 370314, overlap = 306.344
+PHY-3002 : Step(86): len = 371930, overlap = 295.125
+PHY-3002 : Step(87): len = 370971, overlap = 275.25
+PHY-3002 : Step(88): len = 375174, overlap = 268.125
+PHY-3002 : Step(89): len = 377809, overlap = 263.375
+PHY-3002 : Step(90): len = 379723, overlap = 264.75
+PHY-3002 : Step(91): len = 379047, overlap = 266.156
+PHY-3002 : Step(92): len = 380631, overlap = 270.531
+PHY-3002 : Step(93): len = 381368, overlap = 267.312
+PHY-3002 : Step(94): len = 383564, overlap = 264.719
+PHY-3002 : Step(95): len = 383350, overlap = 265.219
+PHY-3002 : Step(96): len = 383356, overlap = 264.344
+PHY-3002 : Step(97): len = 383793, overlap = 263.125
+PHY-3002 : Step(98): len = 384043, overlap = 258
+PHY-3002 : Step(99): len = 382719, overlap = 245.594
+PHY-3002 : Step(100): len = 383434, overlap = 244.531
+PHY-3002 : Step(101): len = 382815, overlap = 242.969
+PHY-3002 : Step(102): len = 383910, overlap = 248.094
+PHY-3002 : Step(103): len = 381868, overlap = 240.375
+PHY-3002 : Step(104): len = 382653, overlap = 235.344
+PHY-3002 : Step(105): len = 382722, overlap = 240.75
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.74523e-05
+PHY-3002 : Step(106): len = 397287, overlap = 232.156
+PHY-3002 : Step(107): len = 407159, overlap = 223.094
+PHY-3002 : Step(108): len = 407424, overlap = 222.938
+PHY-3002 : Step(109): len = 408115, overlap = 217.469
+PHY-3002 : Step(110): len = 408832, overlap = 220.062
+PHY-3002 : Step(111): len = 410440, overlap = 209.5
+PHY-3002 : Step(112): len = 410033, overlap = 212.719
+PHY-3002 : Step(113): len = 411115, overlap = 214.375
+PHY-3002 : Step(114): len = 412134, overlap = 209.938
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154905
+PHY-3002 : Step(115): len = 424282, overlap = 217.844
+PHY-3002 : Step(116): len = 433471, overlap = 208.812
+PHY-3002 : Step(117): len = 433664, overlap = 207.969
+PHY-3002 : Step(118): len = 435444, overlap = 196.938
+PHY-3002 : Step(119): len = 439019, overlap = 190.5
+PHY-3002 : Step(120): len = 442451, overlap = 187.75
+PHY-3002 : Step(121): len = 440783, overlap = 180.719
+PHY-3002 : Step(122): len = 441167, overlap = 183.469
+PHY-3002 : Step(123): len = 443662, overlap = 166.344
+PHY-3002 : Step(124): len = 445738, overlap = 165.094
+PHY-3002 : Step(125): len = 443357, overlap = 160.75
+PHY-3002 : Step(126): len = 442712, overlap = 161.938
+PHY-3002 : Step(127): len = 444030, overlap = 160.875
+PHY-3002 : Step(128): len = 445978, overlap = 163.75
+PHY-3002 : Step(129): len = 444987, overlap = 158.406
+PHY-3002 : Step(130): len = 445469, overlap = 155.656
+PHY-3002 : Step(131): len = 446530, overlap = 161.812
+PHY-3002 : Step(132): len = 447153, overlap = 163.562
+PHY-3002 : Step(133): len = 445973, overlap = 163.219
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000287854
+PHY-3002 : Step(134): len = 453659, overlap = 158.719
+PHY-3002 : Step(135): len = 460356, overlap = 161
+PHY-3002 : Step(136): len = 461057, overlap = 156.469
+PHY-3002 : Step(137): len = 462774, overlap = 160.375
+PHY-3002 : Step(138): len = 466526, overlap = 162.469
+PHY-3002 : Step(139): len = 470195, overlap = 155.812
+PHY-3002 : Step(140): len = 469666, overlap = 159.781
+PHY-3002 : Step(141): len = 470169, overlap = 167.469
+PHY-3002 : Step(142): len = 471605, overlap = 169.062
+PHY-3002 : Step(143): len = 472607, overlap = 171.969
+PHY-3002 : Step(144): len = 470850, overlap = 171.75
+PHY-3002 : Step(145): len = 470522, overlap = 179.5
+PHY-3002 : Step(146): len = 472033, overlap = 184.438
+PHY-3002 : Step(147): len = 472515, overlap = 183.625
+PHY-3002 : Step(148): len = 471346, overlap = 183.156
+PHY-3002 : Step(149): len = 471175, overlap = 183.469
+PHY-3002 : Step(150): len = 472345, overlap = 183.062
+PHY-3002 : Step(151): len = 474427, overlap = 184.469
+PHY-3002 : Step(152): len = 473063, overlap = 186.875
+PHY-3002 : Step(153): len = 472992, overlap = 186.906
+PHY-3002 : Step(154): len = 473490, overlap = 188.125
+PHY-3002 : Step(155): len = 473857, overlap = 191.188
+PHY-3002 : Step(156): len = 473320, overlap = 186
+PHY-3002 : Step(157): len = 473390, overlap = 187.844
+PHY-3002 : Step(158): len = 474503, overlap = 194.562
+PHY-3002 : Step(159): len = 475554, overlap = 187.062
+PHY-3002 : Step(160): len = 474632, overlap = 187.594
+PHY-3002 : Step(161): len = 474632, overlap = 187.594
+PHY-3002 : Step(162): len = 474755, overlap = 188.844
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000520569
+PHY-3002 : Step(163): len = 481289, overlap = 198.125
+PHY-3002 : Step(164): len = 489056, overlap = 187.438
+PHY-3002 : Step(165): len = 490417, overlap = 182.188
+PHY-3002 : Step(166): len = 491678, overlap = 171.688
+PHY-3002 : Step(167): len = 494895, overlap = 179.938
+PHY-3002 : Step(168): len = 496316, overlap = 179.812
+PHY-3002 : Step(169): len = 493556, overlap = 174.719
+PHY-3002 : Step(170): len = 493024, overlap = 172.969
+PHY-3002 : Step(171): len = 495366, overlap = 164.031
+PHY-3002 : Step(172): len = 497445, overlap = 153.312
+PHY-3002 : Step(173): len = 496553, overlap = 156.562
+PHY-3002 : Step(174): len = 496635, overlap = 152.75
+PHY-3002 : Step(175): len = 498310, overlap = 149.938
+PHY-3002 : Step(176): len = 499363, overlap = 147.562
+PHY-3002 : Step(177): len = 498743, overlap = 149.719
+PHY-3002 : Step(178): len = 498799, overlap = 145.812
+PHY-3002 : Step(179): len = 499372, overlap = 143.875
+PHY-3002 : Step(180): len = 499636, overlap = 147.969
+PHY-3002 : Step(181): len = 499495, overlap = 149.75
+PHY-3002 : Step(182): len = 499791, overlap = 148.312
+PHY-3002 : Step(183): len = 500532, overlap = 148.188
+PHY-3002 : Step(184): len = 500806, overlap = 151.906
+PHY-3002 : Step(185): len = 500113, overlap = 149.688
+PHY-3002 : Step(186): len = 499999, overlap = 152.875
+PHY-3002 : Step(187): len = 500573, overlap = 153.625
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000996236
+PHY-3002 : Step(188): len = 504185, overlap = 150.281
+PHY-3002 : Step(189): len = 510511, overlap = 138.125
+PHY-3002 : Step(190): len = 512470, overlap = 134.094
+PHY-3002 : Step(191): len = 513755, overlap = 133
+PHY-3002 : Step(192): len = 514832, overlap = 133.156
+PHY-3002 : Step(193): len = 515388, overlap = 133
+PHY-3002 : Step(194): len = 515089, overlap = 128.594
+PHY-3002 : Step(195): len = 515066, overlap = 126.469
+PHY-3002 : Step(196): len = 515655, overlap = 130.438
+PHY-3002 : Step(197): len = 516176, overlap = 130.719
+PHY-3002 : Step(198): len = 516592, overlap = 129.25
+PHY-3002 : Step(199): len = 516717, overlap = 129.438
+PHY-3002 : Step(200): len = 516670, overlap = 134.406
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00171148
+PHY-3002 : Step(201): len = 519271, overlap = 131.156
+PHY-3002 : Step(202): len = 522985, overlap = 130.125
+PHY-3002 : Step(203): len = 523785, overlap = 130.656
+PHY-3002 : Step(204): len = 524288, overlap = 128.281
+PHY-3002 : Step(205): len = 525127, overlap = 131.25
+PHY-3002 : Step(206): len = 525790, overlap = 130
+PHY-3002 : Step(207): len = 526658, overlap = 130.844
+PHY-3002 : Step(208): len = 528114, overlap = 131.562
+PHY-3002 : Step(209): len = 529431, overlap = 130.125
+PHY-3002 : Step(210): len = 530192, overlap = 126.656
+PHY-3002 : Step(211): len = 530513, overlap = 126.594
+PHY-3002 : Step(212): len = 530755, overlap = 131.312
+PHY-3002 : Step(213): len = 531287, overlap = 129.281
+PHY-3002 : Step(214): len = 531812, overlap = 128.875
+PHY-3002 : Step(215): len = 531829, overlap = 129.75
+PHY-3002 : Step(216): len = 531908, overlap = 129.688
+PHY-3002 : Step(217): len = 532740, overlap = 126.875
+PHY-3002 : Step(218): len = 533259, overlap = 123.562
+PHY-3002 : Step(219): len = 533035, overlap = 124.781
+PHY-3002 : Step(220): len = 533035, overlap = 124.781
+PHY-3002 : Step(221): len = 533134, overlap = 124.719
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.018011s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (86.8%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710688, over cnt = 1617(4%), over = 7397, worst = 36
+PHY-1001 : End global iterations; 0.731033s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (145.3%)
+
+PHY-1001 : Congestion index: top1 = 84.25, top5 = 62.94, top10 = 53.26, top15 = 47.34.
+PHY-3001 : End congestion estimation; 1.038250s wall, 1.312500s user + 0.046875s system = 1.359375s CPU (130.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.969946s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (46.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001519
+PHY-3002 : Step(222): len = 647869, overlap = 73.8125
+PHY-3002 : Step(223): len = 646613, overlap = 78.875
+PHY-3002 : Step(224): len = 639545, overlap = 84.9688
+PHY-3002 : Step(225): len = 635233, overlap = 81.8125
+PHY-3002 : Step(226): len = 636716, overlap = 67.8438
+PHY-3002 : Step(227): len = 639817, overlap = 59.6562
+PHY-3002 : Step(228): len = 637029, overlap = 58.25
+PHY-3002 : Step(229): len = 634130, overlap = 57.0938
+PHY-3002 : Step(230): len = 632229, overlap = 50.5625
+PHY-3002 : Step(231): len = 630604, overlap = 45.125
+PHY-3002 : Step(232): len = 628270, overlap = 43.375
+PHY-3002 : Step(233): len = 626213, overlap = 43.3438
+PHY-3002 : Step(234): len = 625050, overlap = 43.5
+PHY-3002 : Step(235): len = 628222, overlap = 36.25
+PHY-3002 : Step(236): len = 628134, overlap = 32.6875
+PHY-3002 : Step(237): len = 626822, overlap = 33.0312
+PHY-3002 : Step(238): len = 625425, overlap = 33.0938
+PHY-3002 : Step(239): len = 625324, overlap = 34.125
+PHY-3002 : Step(240): len = 623940, overlap = 32.8438
+PHY-3002 : Step(241): len = 622491, overlap = 32.2188
+PHY-3002 : Step(242): len = 620667, overlap = 30.3125
+PHY-3002 : Step(243): len = 621122, overlap = 36.5312
+PHY-3002 : Step(244): len = 620153, overlap = 36.625
+PHY-3002 : Step(245): len = 618679, overlap = 40.2812
+PHY-3002 : Step(246): len = 617465, overlap = 40.625
+PHY-3002 : Step(247): len = 617743, overlap = 40.5625
+PHY-3002 : Step(248): len = 616563, overlap = 42.125
+PHY-3002 : Step(249): len = 615910, overlap = 42.8438
+PHY-3002 : Step(250): len = 614074, overlap = 42.8125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000303799
+PHY-3002 : Step(251): len = 616277, overlap = 42.8438
+PHY-3002 : Step(252): len = 619151, overlap = 42.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 108/20565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 703416, over cnt = 2653(7%), over = 11448, worst = 69
+PHY-1001 : End global iterations; 1.788085s wall, 2.421875s user + 0.031250s system = 2.453125s CPU (137.2%)
+
+PHY-1001 : Congestion index: top1 = 82.63, top5 = 65.66, top10 = 57.18, top15 = 51.91.
+PHY-3001 : End congestion estimation; 2.075496s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (131.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.400509s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.19607e-05
+PHY-3002 : Step(253): len = 616751, overlap = 275.688
+PHY-3002 : Step(254): len = 620541, overlap = 206.844
+PHY-3002 : Step(255): len = 619790, overlap = 203.781
+PHY-3002 : Step(256): len = 615749, overlap = 190.438
+PHY-3002 : Step(257): len = 613037, overlap = 169.688
+PHY-3002 : Step(258): len = 611362, overlap = 162.375
+PHY-3002 : Step(259): len = 607867, overlap = 160.469
+PHY-3002 : Step(260): len = 606318, overlap = 155.219
+PHY-3002 : Step(261): len = 605330, overlap = 155.062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000183921
+PHY-3002 : Step(262): len = 604145, overlap = 152
+PHY-3002 : Step(263): len = 606409, overlap = 146.656
+PHY-3002 : Step(264): len = 608223, overlap = 138.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000367843
+PHY-3002 : Step(265): len = 616500, overlap = 121.5
+PHY-3002 : Step(266): len = 625479, overlap = 105.031
+PHY-3002 : Step(267): len = 631776, overlap = 98.0312
+PHY-3002 : Step(268): len = 630889, overlap = 97.875
+PHY-3002 : Step(269): len = 628756, overlap = 92.0938
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83999, tnet num: 20387, tinst num: 17985, tnode num: 114266, tedge num: 133954.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.584445s wall, 1.562500s user + 0.031250s system = 1.593750s CPU (100.6%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 563 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 410.06 peak overflow 3.31
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1603/20565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725984, over cnt = 2976(8%), over = 10930, worst = 24
+PHY-1001 : End global iterations; 1.287101s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (150.5%)
+
+PHY-1001 : Congestion index: top1 = 73.17, top5 = 57.04, top10 = 50.54, top15 = 46.92.
+PHY-1001 : End incremental global routing; 1.648048s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (138.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.020710s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (99.5%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17853 has valid locations, 302 needs to be replaced
+PHY-3001 : design contains 18240 instances, 7747 luts, 9272 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6072 pins
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 651242
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16940/20820.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740544, over cnt = 3033(8%), over = 10907, worst = 24
+PHY-1001 : End global iterations; 0.257227s wall, 0.390625s user + 0.046875s system = 0.437500s CPU (170.1%)
+
+PHY-1001 : Congestion index: top1 = 72.76, top5 = 57.00, top10 = 50.78, top15 = 47.27.
+PHY-3001 : End congestion estimation; 0.605983s wall, 0.734375s user + 0.046875s system = 0.781250s CPU (128.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85020, tnet num: 20642, tinst num: 18240, tnode num: 115812, tedge num: 135486.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.564263s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (98.9%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 612 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.584290s wall, 2.515625s user + 0.046875s system = 2.562500s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 650301, overlap = 0.125
+PHY-3002 : Step(271): len = 649831, overlap = 0.4375
+PHY-3002 : Step(272): len = 649457, overlap = 0.125
+PHY-3002 : Step(273): len = 649226, overlap = 0.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17017/20820.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737264, over cnt = 3014(8%), over = 10963, worst = 24
+PHY-1001 : End global iterations; 0.218795s wall, 0.234375s user + 0.031250s system = 0.265625s CPU (121.4%)
+
+PHY-1001 : Congestion index: top1 = 73.60, top5 = 57.07, top10 = 50.78, top15 = 47.27.
+PHY-3001 : End congestion estimation; 0.547090s wall, 0.562500s user + 0.031250s system = 0.593750s CPU (108.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.121147s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000478718
+PHY-3002 : Step(274): len = 649205, overlap = 93.9062
+PHY-3002 : Step(275): len = 649398, overlap = 93.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000957436
+PHY-3002 : Step(276): len = 649545, overlap = 93.5625
+PHY-3002 : Step(277): len = 650171, overlap = 93.2812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00183245
+PHY-3002 : Step(278): len = 650445, overlap = 93.375
+PHY-3002 : Step(279): len = 651041, overlap = 92.8125
+PHY-3001 : Final: Len = 651041, Over = 92.8125
+PHY-3001 : End incremental placement; 5.710864s wall, 6.250000s user + 0.250000s system = 6.500000s CPU (113.8%)
+
+OPT-1001 : Total overflow 415.22 peak overflow 3.31
+OPT-1001 : End high-fanout net optimization; 8.951344s wall, 10.234375s user + 0.250000s system = 10.484375s CPU (117.1%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 707, peak = 731.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16959/20820.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741384, over cnt = 2959(8%), over = 9899, worst = 24
+PHY-1002 : len = 792192, over cnt = 2017(5%), over = 5041, worst = 20
+PHY-1002 : len = 826272, over cnt = 945(2%), over = 2301, worst = 18
+PHY-1002 : len = 860464, over cnt = 102(0%), over = 180, worst = 12
+PHY-1002 : len = 862656, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.116213s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 57.74, top5 = 50.40, top10 = 46.60, top15 = 44.18.
+OPT-1001 : End congestion update; 2.404327s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (133.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.855616s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.4%)
+
+OPT-0007 : Start: WNS -87 TNS -174 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 122 cells processed and 19150 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 44 cells processed and 2950 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 350 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 800 slack improved
+OPT-1001 : End bottleneck based optimization; 3.704947s wall, 4.531250s user + 0.000000s system = 4.531250s CPU (122.3%)
+
+OPT-1001 : Current memory(MB): used = 689, reserve = 684, peak = 731.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17000/20826.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863024, over cnt = 91(0%), over = 126, worst = 4
+PHY-1002 : len = 862352, over cnt = 51(0%), over = 63, worst = 3
+PHY-1002 : len = 862504, over cnt = 34(0%), over = 41, worst = 3
+PHY-1002 : len = 863128, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 863160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.806060s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (110.5%)
+
+PHY-1001 : Congestion index: top1 = 58.02, top5 = 50.57, top10 = 46.67, top15 = 44.21.
+OPT-1001 : End congestion update; 1.109192s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (108.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20648 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.958905s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.4%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 25 cells processed and 8700 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.266646s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (104.1%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 698, peak = 731.
+OPT-1001 : End physical optimization; 16.830101s wall, 19.078125s user + 0.312500s system = 19.390625s CPU (115.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7747 LUT to BLE ...
+SYN-4008 : Packed 7747 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6143 remaining SEQ's ...
+SYN-4005 : Packed 3846 SEQ with LUT/SLICE
+SYN-4006 : 1046 single LUT's are left
+SYN-4006 : 2297 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10044/13899 primitive instances ...
+PHY-3001 : End packing; 1.785796s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6759 instances
+RUN-1001 : 3305 mslices, 3306 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17819 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9968 nets have 2 pins
+RUN-1001 : 6496 nets have [3 - 5] pins
+RUN-1001 : 736 nets have [6 - 10] pins
+RUN-1001 : 285 nets have [11 - 20] pins
+RUN-1001 : 301 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6757 instances, 6611 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3484 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 662917, Over = 221
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7745/17819.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 814448, over cnt = 1970(5%), over = 3199, worst = 9
+PHY-1002 : len = 823336, over cnt = 1236(3%), over = 1711, worst = 9
+PHY-1002 : len = 836648, over cnt = 408(1%), over = 557, worst = 7
+PHY-1002 : len = 842680, over cnt = 156(0%), over = 216, worst = 5
+PHY-1002 : len = 846736, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.870533s wall, 2.484375s user + 0.015625s system = 2.500000s CPU (133.7%)
+
+PHY-1001 : Congestion index: top1 = 57.78, top5 = 50.51, top10 = 46.62, top15 = 44.09.
+PHY-3001 : End congestion estimation; 2.288847s wall, 2.906250s user + 0.015625s system = 2.921875s CPU (127.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71298, tnet num: 17641, tinst num: 6757, tnode num: 93557, tedge num: 118513.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.772993s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (98.7%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 609 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.697208s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.41492e-05
+PHY-3002 : Step(280): len = 650707, overlap = 229.5
+PHY-3002 : Step(281): len = 644067, overlap = 231.25
+PHY-3002 : Step(282): len = 639649, overlap = 229
+PHY-3002 : Step(283): len = 636262, overlap = 237.75
+PHY-3002 : Step(284): len = 633236, overlap = 242.5
+PHY-3002 : Step(285): len = 630116, overlap = 246.25
+PHY-3002 : Step(286): len = 627211, overlap = 247.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000108298
+PHY-3002 : Step(287): len = 630605, overlap = 239.5
+PHY-3002 : Step(288): len = 632858, overlap = 237
+PHY-3002 : Step(289): len = 633449, overlap = 238.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000216597
+PHY-3002 : Step(290): len = 641261, overlap = 222.5
+PHY-3002 : Step(291): len = 649359, overlap = 210.75
+PHY-3002 : Step(292): len = 648684, overlap = 213
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.405402s wall, 0.343750s user + 0.562500s system = 0.906250s CPU (223.5%)
+
+PHY-3001 : Trial Legalized: Len = 733375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 968/17819.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841912, over cnt = 2601(7%), over = 4357, worst = 9
+PHY-1002 : len = 857592, over cnt = 1666(4%), over = 2453, worst = 7
+PHY-1002 : len = 876264, over cnt = 704(2%), over = 1029, worst = 7
+PHY-1002 : len = 886568, over cnt = 292(0%), over = 434, worst = 7
+PHY-1002 : len = 894032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.629693s wall, 3.828125s user + 0.093750s system = 3.921875s CPU (149.1%)
+
+PHY-1001 : Congestion index: top1 = 56.25, top5 = 50.14, top10 = 47.02, top15 = 44.93.
+PHY-3001 : End congestion estimation; 3.130566s wall, 4.312500s user + 0.109375s system = 4.421875s CPU (141.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.968397s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000163731
+PHY-3002 : Step(293): len = 705969, overlap = 40.25
+PHY-3002 : Step(294): len = 689533, overlap = 65.25
+PHY-3002 : Step(295): len = 675893, overlap = 94.25
+PHY-3002 : Step(296): len = 667776, overlap = 113
+PHY-3002 : Step(297): len = 662852, overlap = 123.25
+PHY-3002 : Step(298): len = 659841, overlap = 136.75
+PHY-3002 : Step(299): len = 658251, overlap = 145.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000327461
+PHY-3002 : Step(300): len = 662347, overlap = 140.25
+PHY-3002 : Step(301): len = 666598, overlap = 137.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000654923
+PHY-3002 : Step(302): len = 671053, overlap = 132.75
+PHY-3002 : Step(303): len = 680771, overlap = 128.25
+PHY-3002 : Step(304): len = 681476, overlap = 125.75
+PHY-3002 : Step(305): len = 681779, overlap = 132.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.042783s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (109.6%)
+
+PHY-3001 : Legalized: Len = 712068, Over = 0
+PHY-3001 : Spreading special nets. 386 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.103608s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (105.6%)
+
+PHY-3001 : 564 instances has been re-located, deltaX = 194, deltaY = 328, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 720905, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71298, tnet num: 17641, tinst num: 6760, tnode num: 93557, tedge num: 118513.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.940578s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (99.0%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 629 MB, peak memory is 731 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3685/17819.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838920, over cnt = 2404(6%), over = 3969, worst = 8
+PHY-1002 : len = 852648, over cnt = 1441(4%), over = 2163, worst = 7
+PHY-1002 : len = 871904, over cnt = 493(1%), over = 676, worst = 6
+PHY-1002 : len = 881008, over cnt = 76(0%), over = 100, worst = 4
+PHY-1002 : len = 882776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.204315s wall, 3.125000s user + 0.046875s system = 3.171875s CPU (143.9%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.49, top15 = 43.38.
+PHY-1001 : End incremental global routing; 2.613306s wall, 3.531250s user + 0.046875s system = 3.578125s CPU (136.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.014714s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (98.5%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6668 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 724327
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16200/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886488, over cnt = 75(0%), over = 85, worst = 3
+PHY-1002 : len = 886536, over cnt = 37(0%), over = 38, worst = 2
+PHY-1002 : len = 886880, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 886888, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 886936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.820744s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.57, top15 = 43.47.
+PHY-3001 : End congestion estimation; 1.158606s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (102.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71487, tnet num: 17671, tinst num: 6779, tnode num: 93791, tedge num: 118765.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.976996s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (98.8%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 652 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.914506s wall, 2.843750s user + 0.046875s system = 2.890625s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(306): len = 724327, overlap = 0
+PHY-3002 : Step(307): len = 724327, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.134954s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.6%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.57, top15 = 43.47.
+PHY-3001 : End congestion estimation; 0.461917s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.911876s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000460749
+PHY-3002 : Step(308): len = 724327, overlap = 0
+PHY-3002 : Step(309): len = 724327, overlap = 0
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.008389s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (186.2%)
+
+PHY-3001 : Legalized: Len = 724301, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063755s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.0%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 724319, Over = 0
+PHY-3001 : End incremental placement; 5.992373s wall, 5.968750s user + 0.140625s system = 6.109375s CPU (102.0%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.182940s wall, 11.156250s user + 0.203125s system = 11.359375s CPU (111.6%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 730, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16207/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 887064, over cnt = 13(0%), over = 17, worst = 3
+PHY-1002 : len = 887056, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 887192, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 887208, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.577962s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (100.0%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.49, top10 = 45.56, top15 = 43.47.
+OPT-1001 : End congestion update; 0.910975s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.759296s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.8%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730011, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065882s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.9%)
+
+PHY-3001 : 37 instances has been re-located, deltaX = 15, deltaY = 29, maxDist = 2.
+PHY-3001 : Final: Len = 730717, Over = 0
+PHY-3001 : End incremental legalization; 0.416820s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (116.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 52 cells processed and 20553 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730601, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063747s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.0%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 7, deltaY = 12, maxDist = 4.
+PHY-3001 : Final: Len = 730927, Over = 0
+PHY-3001 : End incremental legalization; 0.410380s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.0%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 26 cells processed and 2806 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3558 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730923, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.074070s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (84.4%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 6, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 731139, Over = 0
+PHY-3001 : End incremental legalization; 0.435340s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.5%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 1210 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 731762, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.071787s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (87.1%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 731784, Over = 0
+PHY-3001 : End incremental legalization; 0.469944s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (116.4%)
+
+OPT-0007 : Iter 4: improved WNS 71 TNS 0 NUM_FEPS 0 with 5 cells processed and 500 slack improved
+OPT-1001 : End bottleneck based optimization; 4.020248s wall, 4.421875s user + 0.015625s system = 4.437500s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 730, peak = 736.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15820/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 894680, over cnt = 154(0%), over = 205, worst = 5
+PHY-1002 : len = 894944, over cnt = 87(0%), over = 106, worst = 5
+PHY-1002 : len = 895392, over cnt = 21(0%), over = 23, worst = 2
+PHY-1002 : len = 895584, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 895800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.872854s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 54.44, top5 = 48.72, top10 = 45.62, top15 = 43.54.
+OPT-1001 : End congestion update; 1.212921s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (106.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.782341s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 732158, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065070s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.1%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 10, deltaY = 9, maxDist = 5.
+PHY-3001 : Final: Len = 732786, Over = 0
+PHY-3001 : End incremental legalization; 0.470928s wall, 0.546875s user + 0.031250s system = 0.578125s CPU (122.8%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 2650 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.603887s wall, 2.750000s user + 0.046875s system = 2.796875s CPU (107.4%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 730, peak = 736.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.780838s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16144/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896584, over cnt = 40(0%), over = 46, worst = 3
+PHY-1002 : len = 896504, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 896552, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 896808, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.834225s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (101.1%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.783268s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.344828
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 732786, Over = 0
+PHY-3001 : End spreading; 0.064287s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : Final: Len = 732786, Over = 0
+PHY-3001 : End incremental legalization; 0.425212s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.783298s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.7%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139048s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (89.9%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+OPT-1001 : End congestion update; 0.486591s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.781540s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6785 instances, 6636 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3559 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 732770, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066020s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (118.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 732786, Over = 0
+PHY-3001 : End incremental legalization; 0.425354s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (121.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.818203s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (110.0%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 730, peak = 736.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.141428s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.4%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+OPT-1001 : End congestion update; 0.480628s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.819298s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.477819s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (100.4%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 730, peak = 736.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.774107s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 733, reserve = 730, peak = 736.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.763894s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.2%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16219/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136342s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.1%)
+
+PHY-1001 : Congestion index: top1 = 54.81, top5 = 48.80, top10 = 45.66, top15 = 43.55.
+RUN-1001 : End congestion update; 0.474759s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.0%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.241818s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.7%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 730, peak = 736.
+OPT-1001 : End physical optimization; 28.432824s wall, 30.109375s user + 0.265625s system = 30.375000s CPU (106.8%)
+
+RUN-1003 : finish command "place" in 77.194041s wall, 107.406250s user + 6.734375s system = 114.140625s CPU (147.9%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 631 MB, peak memory is 736 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.771144s wall, 3.078125s user + 0.062500s system = 3.140625s CPU (177.3%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 632 MB, peak memory is 736 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6787 instances
+RUN-1001 : 3319 mslices, 3317 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17854 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9976 nets have 2 pins
+RUN-1001 : 6502 nets have [3 - 5] pins
+RUN-1001 : 744 nets have [6 - 10] pins
+RUN-1001 : 289 nets have [11 - 20] pins
+RUN-1001 : 314 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71537, tnet num: 17676, tinst num: 6785, tnode num: 93861, tedge num: 118841.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.709406s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.6%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 653 MB, peak memory is 736 MB
+PHY-1001 : 3319 mslices, 3317 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[16] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 830312, over cnt = 2619(7%), over = 4410, worst = 9
+PHY-1002 : len = 846104, over cnt = 1755(4%), over = 2653, worst = 8
+PHY-1002 : len = 862128, over cnt = 971(2%), over = 1435, worst = 6
+PHY-1002 : len = 885176, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 885400, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.140723s wall, 4.281250s user + 0.031250s system = 4.312500s CPU (137.3%)
+
+PHY-1001 : Congestion index: top1 = 54.72, top5 = 48.76, top10 = 45.46, top15 = 43.38.
+PHY-1001 : End global routing; 3.496052s wall, 4.640625s user + 0.031250s system = 4.671875s CPU (133.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 710, reserve = 709, peak = 736.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 983, peak = 982.
+PHY-1001 : End build detailed router design. 4.333754s wall, 4.296875s user + 0.031250s system = 4.328125s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266240, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.885675s wall, 5.875000s user + 0.015625s system = 5.890625s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266296, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.480608s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (97.5%)
+
+PHY-1001 : Current memory(MB): used = 1019, reserve = 1020, peak = 1019.
+PHY-1001 : End phase 1; 6.378200s wall, 6.359375s user + 0.015625s system = 6.375000s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24995e+06, over cnt = 1702(0%), over = 1706, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1028, peak = 1030.
+PHY-1001 : End initial routed; 30.105015s wall, 65.296875s user + 0.250000s system = 65.546875s CPU (217.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16776(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.947 | -0.947 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.508027s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1041, reserve = 1041, peak = 1041.
+PHY-1001 : End phase 2; 33.613108s wall, 68.781250s user + 0.250000s system = 69.031250s CPU (205.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.147264s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.5%)
+
+PHY-1022 : len = 2.24995e+06, over cnt = 1703(0%), over = 1707, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.442742s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.22148e+06, over cnt = 644(0%), over = 645, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.275791s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (166.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.21816e+06, over cnt = 118(0%), over = 118, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.778135s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (164.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.21888e+06, over cnt = 27(0%), over = 27, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.308673s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (131.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2193e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.267485s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (111.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.254247s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.263037s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.330825s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.199077s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.212395s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.251038s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.283313s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (104.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.21932e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.359401s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.21933e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.191102s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.21931e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.174640s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16776(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.509613s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 508 feed throughs used by 381 nets
+PHY-1001 : End commit to database; 2.380180s wall, 2.328125s user + 0.046875s system = 2.375000s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1144, reserve = 1146, peak = 1144.
+PHY-1001 : End phase 3; 11.928951s wall, 13.343750s user + 0.046875s system = 13.390625s CPU (112.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.155593s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.4%)
+
+PHY-1022 : len = 2.21931e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.425564s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.805ns, -0.805ns, 1}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2193e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.179541s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16776(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.947 | -0.947 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.634892s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1157, peak = 1154.
+PHY-1001 : End phase 4; 4.293098s wall, 4.265625s user + 0.000000s system = 4.265625s CPU (99.4%)
+
+PHY-1003 : Routed, final wirelength = 2.2193e+06
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1157, peak = 1154.
+PHY-1001 : End export database. 0.064042s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.6%)
+
+PHY-1001 : End detail routing; 61.038491s wall, 97.546875s user + 0.343750s system = 97.890625s CPU (160.4%)
+
+RUN-1003 : finish command "route" in 67.384906s wall, 105.031250s user + 0.375000s system = 105.406250s CPU (156.4%)
+
+RUN-1004 : used memory is 1079 MB, reserved memory is 1082 MB, peak memory is 1154 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10181 out of 19600 51.94%
+#reg 9426 out of 19600 48.09%
+#le 12449
+ #lut only 3023 out of 12449 24.28%
+ #reg only 2268 out of 12449 18.22%
+ #lut® 7158 out of 12449 57.50%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1783
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1374
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1268
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 960
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 139
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg0_syn_140.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_381.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P11 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P119 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P140 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12449 |9154 |1027 |9460 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |542 |448 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |102 |4 |94 |4 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |6 |0 |0 |
+| U_crc16_24b |crc16_24b |34 |34 |0 |19 |0 |0 |
+| exdev_ctl_a |exdev_ctl |763 |384 |96 |581 |0 |0 |
+| u_ADconfig |AD_config |189 |108 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |256 |165 |71 |118 |0 |0 |
+| exdev_ctl_b |exdev_ctl |744 |356 |96 |567 |0 |0 |
+| u_ADconfig |AD_config |176 |94 |25 |131 |0 |0 |
+| u_gen_sp |gen_sp |251 |151 |71 |119 |0 |0 |
+| sampling_fe_a |sampling_fe |2985 |2409 |306 |2065 |25 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |165 |117 |17 |136 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2790 |2274 |289 |1899 |25 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2371 |1946 |253 |1556 |22 |0 |
+| channelPart |channel_part_8478 |145 |141 |3 |137 |0 |0 |
+| fifo_adc |fifo_adc |52 |43 |9 |37 |0 |0 |
+| ram_switch |ram_switch |1860 |1503 |197 |1163 |0 |0 |
+| adc_addr_gen |adc_addr_gen |220 |193 |27 |116 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |982 |655 |170 |677 |0 |0 |
+| ram_switch_state |ram_switch_state |658 |655 |0 |370 |0 |0 |
+| read_ram_i |read_ram |283 |238 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |232 |192 |40 |153 |0 |0 |
+| read_ram_data |read_ram_data |50 |45 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |321 |235 |36 |276 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3240 |2551 |349 |2052 |25 |1 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |182 |102 |17 |152 |0 |0 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_sort |sort_rev |3022 |2433 |332 |1864 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2599 |2106 |290 |1505 |22 |1 |
+| channelPart |channel_part_8478 |124 |120 |3 |119 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 |
+| ram_switch |ram_switch |2021 |1673 |197 |1103 |0 |0 |
+| adc_addr_gen |adc_addr_gen |205 |178 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |7 |0 |0 |
+| insert |insert |969 |648 |170 |671 |0 |0 |
+| ram_switch_state |ram_switch_state |847 |847 |0 |327 |0 |0 |
+| read_ram_i |read_ram_rev |363 |244 |81 |211 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |298 |213 |73 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |65 |31 |8 |46 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9914
+ #2 2 4230
+ #3 3 1690
+ #4 4 579
+ #5 5-10 783
+ #6 11-50 550
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.198566s wall, 3.843750s user + 0.015625s system = 3.859375s CPU (175.5%)
+
+RUN-1004 : used memory is 1080 MB, reserved memory is 1083 MB, peak memory is 1154 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71537, tnet num: 17676, tinst num: 6785, tnode num: 93861, tedge num: 118841.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.743607s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.5%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1087 MB, peak memory is 1154 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.607183s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.1%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1092 MB, peak memory is 1154 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6785
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17854, pip num: 166832
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 508
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 466630 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.706951s wall, 63.437500s user + 0.265625s system = 63.703125s CPU (656.3%)
+
+RUN-1004 : used memory is 1242 MB, reserved memory is 1241 MB, peak memory is 1357 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_135807.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_140409.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_140409.log
new file mode 100644
index 0000000..c3597c1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_140409.log
@@ -0,0 +1,258 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 14:04:09 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 508 feed throughs used by 381 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db hg_anlogic_pr.db" in 12.512183s wall, 12.171875s user + 0.265625s system = 12.437500s CPU (99.4%)
+
+RUN-1004 : used memory is 793 MB, reserved memory is 785 MB, peak memory is 820 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6785
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17854, pip num: 166832
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 508
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 466630 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.992985s wall, 62.046875s user + 0.156250s system = 62.203125s CPU (622.5%)
+
+RUN-1004 : used memory is 819 MB, reserved memory is 821 MB, peak memory is 1086 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_140409.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_142526.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_142526.log
new file mode 100644
index 0000000..7124be4
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_142526.log
@@ -0,0 +1,2165 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 14:25:26 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.336532s wall, 2.218750s user + 0.093750s system = 2.312500s CPU (99.0%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 315 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17999 instances
+RUN-0007 : 7674 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20577 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13091 nets have 2 pins
+RUN-1001 : 6451 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17997 instances, 7674 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.244730s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (100.4%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 513 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.090370s wall, 2.046875s user + 0.046875s system = 2.093750s CPU (100.2%)
+
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.97121e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17997.
+PHY-3001 : Level 1 #clusters 2079.
+PHY-3001 : End clustering; 0.144643s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (118.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31367e+06, overlap = 443.438
+PHY-3002 : Step(2): len = 1.2294e+06, overlap = 486.125
+PHY-3002 : Step(3): len = 875782, overlap = 560.594
+PHY-3002 : Step(4): len = 798923, overlap = 601.969
+PHY-3002 : Step(5): len = 641758, overlap = 743.312
+PHY-3002 : Step(6): len = 570495, overlap = 800.875
+PHY-3002 : Step(7): len = 486549, overlap = 870.969
+PHY-3002 : Step(8): len = 437691, overlap = 925
+PHY-3002 : Step(9): len = 401477, overlap = 981.781
+PHY-3002 : Step(10): len = 365241, overlap = 1042.06
+PHY-3002 : Step(11): len = 327157, overlap = 1107.09
+PHY-3002 : Step(12): len = 299533, overlap = 1128.97
+PHY-3002 : Step(13): len = 278253, overlap = 1200.31
+PHY-3002 : Step(14): len = 248289, overlap = 1280.03
+PHY-3002 : Step(15): len = 237739, overlap = 1335.94
+PHY-3002 : Step(16): len = 205556, overlap = 1381.72
+PHY-3002 : Step(17): len = 193198, overlap = 1381.34
+PHY-3002 : Step(18): len = 172725, overlap = 1399.28
+PHY-3002 : Step(19): len = 166556, overlap = 1422.09
+PHY-3002 : Step(20): len = 148481, overlap = 1453.16
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.11523e-06
+PHY-3002 : Step(21): len = 150350, overlap = 1409.84
+PHY-3002 : Step(22): len = 184148, overlap = 1279.47
+PHY-3002 : Step(23): len = 192105, overlap = 1220.28
+PHY-3002 : Step(24): len = 200234, overlap = 1165.25
+PHY-3002 : Step(25): len = 199572, overlap = 1120.31
+PHY-3002 : Step(26): len = 199326, overlap = 1118.69
+PHY-3002 : Step(27): len = 195889, overlap = 1109.88
+PHY-3002 : Step(28): len = 192973, overlap = 1083.44
+PHY-3002 : Step(29): len = 191423, overlap = 1092.5
+PHY-3002 : Step(30): len = 190165, overlap = 1082.84
+PHY-3002 : Step(31): len = 188086, overlap = 1070.78
+PHY-3002 : Step(32): len = 186123, overlap = 1069.59
+PHY-3002 : Step(33): len = 184580, overlap = 1075.47
+PHY-3002 : Step(34): len = 182237, overlap = 1087.72
+PHY-3002 : Step(35): len = 181472, overlap = 1092.66
+PHY-3002 : Step(36): len = 179872, overlap = 1090.16
+PHY-3002 : Step(37): len = 179076, overlap = 1083.28
+PHY-3002 : Step(38): len = 179220, overlap = 1088.91
+PHY-3002 : Step(39): len = 179593, overlap = 1083.09
+PHY-3002 : Step(40): len = 179215, overlap = 1096.53
+PHY-3002 : Step(41): len = 177373, overlap = 1087.91
+PHY-3002 : Step(42): len = 176934, overlap = 1083.78
+PHY-3002 : Step(43): len = 175306, overlap = 1092.62
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.23046e-06
+PHY-3002 : Step(44): len = 178570, overlap = 1086.06
+PHY-3002 : Step(45): len = 187856, overlap = 1056.28
+PHY-3002 : Step(46): len = 192492, overlap = 1047.22
+PHY-3002 : Step(47): len = 198801, overlap = 1022.66
+PHY-3002 : Step(48): len = 202380, overlap = 996.969
+PHY-3002 : Step(49): len = 203592, overlap = 976.812
+PHY-3002 : Step(50): len = 201393, overlap = 954.562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.46092e-06
+PHY-3002 : Step(51): len = 209014, overlap = 915.812
+PHY-3002 : Step(52): len = 226062, overlap = 834
+PHY-3002 : Step(53): len = 234714, overlap = 782.781
+PHY-3002 : Step(54): len = 239487, overlap = 782.188
+PHY-3002 : Step(55): len = 243045, overlap = 753.625
+PHY-3002 : Step(56): len = 245287, overlap = 749.531
+PHY-3002 : Step(57): len = 244198, overlap = 741.125
+PHY-3002 : Step(58): len = 244100, overlap = 749.188
+PHY-3002 : Step(59): len = 242691, overlap = 750.375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.92183e-06
+PHY-3002 : Step(60): len = 258933, overlap = 711.344
+PHY-3002 : Step(61): len = 276627, overlap = 625.844
+PHY-3002 : Step(62): len = 282614, overlap = 599.594
+PHY-3002 : Step(63): len = 284482, overlap = 573.125
+PHY-3002 : Step(64): len = 283554, overlap = 564.312
+PHY-3002 : Step(65): len = 282897, overlap = 556.5
+PHY-3002 : Step(66): len = 283149, overlap = 558.125
+PHY-3002 : Step(67): len = 284250, overlap = 558.656
+PHY-3002 : Step(68): len = 283695, overlap = 549.531
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.78437e-05
+PHY-3002 : Step(69): len = 298897, overlap = 516.906
+PHY-3002 : Step(70): len = 313803, overlap = 467.312
+PHY-3002 : Step(71): len = 319442, overlap = 450.031
+PHY-3002 : Step(72): len = 323544, overlap = 427.5
+PHY-3002 : Step(73): len = 323423, overlap = 409.688
+PHY-3002 : Step(74): len = 323390, overlap = 402.188
+PHY-3002 : Step(75): len = 321916, overlap = 394.531
+PHY-3002 : Step(76): len = 322659, overlap = 396.188
+PHY-3002 : Step(77): len = 323421, overlap = 390
+PHY-3002 : Step(78): len = 324312, overlap = 387.438
+PHY-3002 : Step(79): len = 324731, overlap = 390.469
+PHY-3002 : Step(80): len = 324690, overlap = 405.344
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.56873e-05
+PHY-3002 : Step(81): len = 339216, overlap = 382.719
+PHY-3002 : Step(82): len = 353542, overlap = 365.469
+PHY-3002 : Step(83): len = 357595, overlap = 338.562
+PHY-3002 : Step(84): len = 360363, overlap = 326.5
+PHY-3002 : Step(85): len = 361190, overlap = 316.656
+PHY-3002 : Step(86): len = 363044, overlap = 307.938
+PHY-3002 : Step(87): len = 363538, overlap = 304.969
+PHY-3002 : Step(88): len = 365350, overlap = 311.844
+PHY-3002 : Step(89): len = 370355, overlap = 309.781
+PHY-3002 : Step(90): len = 373478, overlap = 277.125
+PHY-3002 : Step(91): len = 374132, overlap = 267.781
+PHY-3002 : Step(92): len = 373111, overlap = 256.031
+PHY-3002 : Step(93): len = 374331, overlap = 256.625
+PHY-3002 : Step(94): len = 374662, overlap = 251.656
+PHY-3002 : Step(95): len = 372570, overlap = 251.219
+PHY-3002 : Step(96): len = 371050, overlap = 245.969
+PHY-3002 : Step(97): len = 369277, overlap = 236.594
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.13747e-05
+PHY-3002 : Step(98): len = 384890, overlap = 248.719
+PHY-3002 : Step(99): len = 395077, overlap = 237.688
+PHY-3002 : Step(100): len = 395860, overlap = 212.938
+PHY-3002 : Step(101): len = 398911, overlap = 217.594
+PHY-3002 : Step(102): len = 400433, overlap = 209.188
+PHY-3002 : Step(103): len = 402091, overlap = 207.031
+PHY-3002 : Step(104): len = 398839, overlap = 208.438
+PHY-3002 : Step(105): len = 398605, overlap = 199.438
+PHY-3002 : Step(106): len = 399573, overlap = 210.375
+PHY-3002 : Step(107): len = 400792, overlap = 209.219
+PHY-3002 : Step(108): len = 399260, overlap = 202.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000141893
+PHY-3002 : Step(109): len = 412524, overlap = 190.125
+PHY-3002 : Step(110): len = 423343, overlap = 184.062
+PHY-3002 : Step(111): len = 423838, overlap = 171.188
+PHY-3002 : Step(112): len = 425185, overlap = 173.281
+PHY-3002 : Step(113): len = 427166, overlap = 177.688
+PHY-3002 : Step(114): len = 428966, overlap = 172.781
+PHY-3002 : Step(115): len = 427537, overlap = 178
+PHY-3002 : Step(116): len = 428958, overlap = 181.906
+PHY-3002 : Step(117): len = 431638, overlap = 177.312
+PHY-3002 : Step(118): len = 433787, overlap = 181.938
+PHY-3002 : Step(119): len = 431827, overlap = 179.406
+PHY-3002 : Step(120): len = 431999, overlap = 182.75
+PHY-3002 : Step(121): len = 433646, overlap = 186.281
+PHY-3002 : Step(122): len = 435187, overlap = 184.125
+PHY-3002 : Step(123): len = 432604, overlap = 190.188
+PHY-3002 : Step(124): len = 432943, overlap = 195.062
+PHY-3002 : Step(125): len = 436269, overlap = 197.594
+PHY-3002 : Step(126): len = 439132, overlap = 199.75
+PHY-3002 : Step(127): len = 435856, overlap = 206.031
+PHY-3002 : Step(128): len = 435551, overlap = 205.188
+PHY-3002 : Step(129): len = 438653, overlap = 196.438
+PHY-3002 : Step(130): len = 441077, overlap = 198.719
+PHY-3002 : Step(131): len = 437522, overlap = 203.094
+PHY-3002 : Step(132): len = 437320, overlap = 202.156
+PHY-3002 : Step(133): len = 439014, overlap = 204.406
+PHY-3002 : Step(134): len = 439606, overlap = 198.125
+PHY-3002 : Step(135): len = 437721, overlap = 202.812
+PHY-3002 : Step(136): len = 437554, overlap = 191.156
+PHY-3002 : Step(137): len = 438685, overlap = 203.188
+PHY-3002 : Step(138): len = 439154, overlap = 199.5
+PHY-3002 : Step(139): len = 437426, overlap = 185.188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.0002667
+PHY-3002 : Step(140): len = 447527, overlap = 170.656
+PHY-3002 : Step(141): len = 456295, overlap = 170.062
+PHY-3002 : Step(142): len = 455126, overlap = 161.156
+PHY-3002 : Step(143): len = 455566, overlap = 163.625
+PHY-3002 : Step(144): len = 458405, overlap = 167.906
+PHY-3002 : Step(145): len = 461078, overlap = 168
+PHY-3002 : Step(146): len = 459484, overlap = 160.594
+PHY-3002 : Step(147): len = 459693, overlap = 160.906
+PHY-3002 : Step(148): len = 462668, overlap = 163.969
+PHY-3002 : Step(149): len = 464956, overlap = 164.125
+PHY-3002 : Step(150): len = 462570, overlap = 167.219
+PHY-3002 : Step(151): len = 461977, overlap = 168.531
+PHY-3002 : Step(152): len = 463385, overlap = 169
+PHY-3002 : Step(153): len = 464468, overlap = 174.938
+PHY-3002 : Step(154): len = 462091, overlap = 177.938
+PHY-3002 : Step(155): len = 461909, overlap = 176.906
+PHY-3002 : Step(156): len = 462950, overlap = 173.375
+PHY-3002 : Step(157): len = 463688, overlap = 175.375
+PHY-3002 : Step(158): len = 462795, overlap = 178.031
+PHY-3002 : Step(159): len = 463036, overlap = 179.969
+PHY-3002 : Step(160): len = 463948, overlap = 178.875
+PHY-3002 : Step(161): len = 464131, overlap = 178.188
+PHY-3002 : Step(162): len = 463068, overlap = 173.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000482763
+PHY-3002 : Step(163): len = 469329, overlap = 172.375
+PHY-3002 : Step(164): len = 475097, overlap = 173.344
+PHY-3002 : Step(165): len = 475080, overlap = 167.656
+PHY-3002 : Step(166): len = 475774, overlap = 169.281
+PHY-3002 : Step(167): len = 478181, overlap = 165.344
+PHY-3002 : Step(168): len = 479792, overlap = 158.094
+PHY-3002 : Step(169): len = 479178, overlap = 157.562
+PHY-3002 : Step(170): len = 479447, overlap = 153.75
+PHY-3002 : Step(171): len = 481533, overlap = 160.688
+PHY-3002 : Step(172): len = 482648, overlap = 161.469
+PHY-3002 : Step(173): len = 481718, overlap = 154.156
+PHY-3002 : Step(174): len = 481683, overlap = 152.938
+PHY-3002 : Step(175): len = 482535, overlap = 150.344
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000867386
+PHY-3002 : Step(176): len = 488642, overlap = 144.125
+PHY-3002 : Step(177): len = 499852, overlap = 133.094
+PHY-3002 : Step(178): len = 505259, overlap = 126.75
+PHY-3002 : Step(179): len = 509904, overlap = 129.219
+PHY-3002 : Step(180): len = 512754, overlap = 134.844
+PHY-3002 : Step(181): len = 513598, overlap = 134.469
+PHY-3002 : Step(182): len = 511808, overlap = 124.125
+PHY-3002 : Step(183): len = 510977, overlap = 122.125
+PHY-3002 : Step(184): len = 512356, overlap = 132.125
+PHY-3002 : Step(185): len = 513518, overlap = 131.938
+PHY-3002 : Step(186): len = 512550, overlap = 129.219
+PHY-3002 : Step(187): len = 512115, overlap = 137.625
+PHY-3002 : Step(188): len = 512657, overlap = 140.469
+PHY-3002 : Step(189): len = 513427, overlap = 142.375
+PHY-3002 : Step(190): len = 512831, overlap = 141.281
+PHY-3002 : Step(191): len = 512643, overlap = 142.344
+PHY-3002 : Step(192): len = 513062, overlap = 143.25
+PHY-3002 : Step(193): len = 513259, overlap = 141.094
+PHY-3002 : Step(194): len = 512604, overlap = 138.531
+PHY-3002 : Step(195): len = 512251, overlap = 140.781
+PHY-3002 : Step(196): len = 512355, overlap = 135.281
+PHY-3002 : Step(197): len = 512785, overlap = 136.094
+PHY-3002 : Step(198): len = 512166, overlap = 137.781
+PHY-3002 : Step(199): len = 512058, overlap = 140.312
+PHY-3002 : Step(200): len = 512282, overlap = 140.312
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00158333
+PHY-3002 : Step(201): len = 515022, overlap = 138.312
+PHY-3002 : Step(202): len = 518907, overlap = 139.469
+PHY-3002 : Step(203): len = 520191, overlap = 137.719
+PHY-3002 : Step(204): len = 520955, overlap = 139.031
+PHY-3002 : Step(205): len = 522010, overlap = 139.844
+PHY-3002 : Step(206): len = 522611, overlap = 138.156
+PHY-3002 : Step(207): len = 522648, overlap = 137.969
+PHY-3002 : Step(208): len = 522788, overlap = 138.281
+PHY-3002 : Step(209): len = 523483, overlap = 138.719
+PHY-3002 : Step(210): len = 524292, overlap = 138.906
+PHY-3002 : Step(211): len = 524457, overlap = 134.344
+PHY-3002 : Step(212): len = 524484, overlap = 134.219
+PHY-3002 : Step(213): len = 524724, overlap = 135.094
+PHY-3002 : Step(214): len = 524875, overlap = 136.156
+PHY-3002 : Step(215): len = 525036, overlap = 135.156
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012576s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (124.2%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 693600, over cnt = 1544(4%), over = 7424, worst = 43
+PHY-1001 : End global iterations; 0.700383s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (153.9%)
+
+PHY-1001 : Congestion index: top1 = 81.12, top5 = 62.06, top10 = 52.51, top15 = 46.52.
+PHY-3001 : End congestion estimation; 0.953799s wall, 1.296875s user + 0.046875s system = 1.343750s CPU (140.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.918991s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000125282
+PHY-3002 : Step(216): len = 629930, overlap = 78.375
+PHY-3002 : Step(217): len = 627753, overlap = 79.0625
+PHY-3002 : Step(218): len = 621867, overlap = 70.6562
+PHY-3002 : Step(219): len = 617130, overlap = 59.375
+PHY-3002 : Step(220): len = 616555, overlap = 54.4062
+PHY-3002 : Step(221): len = 616504, overlap = 49.5938
+PHY-3002 : Step(222): len = 613558, overlap = 53
+PHY-3002 : Step(223): len = 610185, overlap = 50.125
+PHY-3002 : Step(224): len = 609005, overlap = 44.0625
+PHY-3002 : Step(225): len = 606149, overlap = 38.5
+PHY-3002 : Step(226): len = 602743, overlap = 35.3438
+PHY-3002 : Step(227): len = 601039, overlap = 37.2812
+PHY-3002 : Step(228): len = 599920, overlap = 34.0312
+PHY-3002 : Step(229): len = 598610, overlap = 34.9688
+PHY-3002 : Step(230): len = 598435, overlap = 34.375
+PHY-3002 : Step(231): len = 597975, overlap = 37.7188
+PHY-3002 : Step(232): len = 597349, overlap = 38.125
+PHY-3002 : Step(233): len = 596296, overlap = 38.5
+PHY-3002 : Step(234): len = 595909, overlap = 38.7812
+PHY-3002 : Step(235): len = 594744, overlap = 40.0312
+PHY-3002 : Step(236): len = 593418, overlap = 42.3438
+PHY-3002 : Step(237): len = 592406, overlap = 43.4062
+PHY-3002 : Step(238): len = 591111, overlap = 48.4062
+PHY-3002 : Step(239): len = 589582, overlap = 48.375
+PHY-3002 : Step(240): len = 587546, overlap = 49.0625
+PHY-3002 : Step(241): len = 586214, overlap = 50.6875
+PHY-3002 : Step(242): len = 585507, overlap = 54.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000250564
+PHY-3002 : Step(243): len = 587829, overlap = 54.2188
+PHY-3002 : Step(244): len = 593457, overlap = 54.375
+PHY-3002 : Step(245): len = 598703, overlap = 54.0312
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000501127
+PHY-3002 : Step(246): len = 602442, overlap = 52.8125
+PHY-3002 : Step(247): len = 614112, overlap = 51.875
+PHY-3002 : Step(248): len = 631182, overlap = 51.625
+PHY-3002 : Step(249): len = 631420, overlap = 49.0625
+PHY-3002 : Step(250): len = 630502, overlap = 46.2812
+PHY-3002 : Step(251): len = 629434, overlap = 44.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 50/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 711944, over cnt = 2639(7%), over = 12705, worst = 70
+PHY-1001 : End global iterations; 1.757644s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 87.24, top5 = 69.80, top10 = 60.98, top15 = 55.43.
+PHY-3001 : End congestion estimation; 2.034774s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (131.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.944185s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000102239
+PHY-3002 : Step(252): len = 623578, overlap = 270.562
+PHY-3002 : Step(253): len = 622061, overlap = 204.312
+PHY-3002 : Step(254): len = 616560, overlap = 169.656
+PHY-3002 : Step(255): len = 611346, overlap = 154.656
+PHY-3002 : Step(256): len = 604615, overlap = 146.312
+PHY-3002 : Step(257): len = 601674, overlap = 139.906
+PHY-3002 : Step(258): len = 598608, overlap = 122.625
+PHY-3002 : Step(259): len = 595583, overlap = 124.594
+PHY-3002 : Step(260): len = 592645, overlap = 120.062
+PHY-3002 : Step(261): len = 589327, overlap = 116.562
+PHY-3002 : Step(262): len = 585879, overlap = 116.031
+PHY-3002 : Step(263): len = 582729, overlap = 124.969
+PHY-3002 : Step(264): len = 579981, overlap = 131.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000204478
+PHY-3002 : Step(265): len = 580899, overlap = 125.219
+PHY-3002 : Step(266): len = 582744, overlap = 120.688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000345479
+PHY-3002 : Step(267): len = 584784, overlap = 117.906
+PHY-3002 : Step(268): len = 592297, overlap = 106.875
+PHY-3002 : Step(269): len = 597351, overlap = 99.5
+PHY-3002 : Step(270): len = 598278, overlap = 96
+PHY-3002 : Step(271): len = 599136, overlap = 94.7188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.846232s wall, 1.812500s user + 0.015625s system = 1.828125s CPU (99.0%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 563 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 424.53 peak overflow 4.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 735/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 694320, over cnt = 3015(8%), over = 10711, worst = 32
+PHY-1001 : End global iterations; 1.430480s wall, 2.015625s user + 0.046875s system = 2.062500s CPU (144.2%)
+
+PHY-1001 : Congestion index: top1 = 69.40, top5 = 56.60, top10 = 50.60, top15 = 47.00.
+PHY-1001 : End incremental global routing; 1.790488s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (134.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.979011s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (99.0%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17866 has valid locations, 321 needs to be replaced
+PHY-3001 : design contains 18272 instances, 7769 luts, 9282 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6076 pins
+PHY-3001 : Found 1268 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 622359
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16812/20852.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710528, over cnt = 3048(8%), over = 10756, worst = 32
+PHY-1001 : End global iterations; 0.255639s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (158.9%)
+
+PHY-1001 : Congestion index: top1 = 69.38, top5 = 56.80, top10 = 50.92, top15 = 47.38.
+PHY-3001 : End congestion estimation; 0.529540s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (126.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85144, tnet num: 20674, tinst num: 18272, tnode num: 115971, tedge num: 135670.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.607486s wall, 1.562500s user + 0.046875s system = 1.609375s CPU (100.1%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 615 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20674 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.679092s wall, 2.640625s user + 0.046875s system = 2.687500s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(272): len = 621584, overlap = 0.09375
+PHY-3002 : Step(273): len = 621187, overlap = 0.09375
+PHY-3002 : Step(274): len = 621110, overlap = 0.09375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16929/20852.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708416, over cnt = 3059(8%), over = 10835, worst = 32
+PHY-1001 : End global iterations; 0.194580s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (128.5%)
+
+PHY-1001 : Congestion index: top1 = 69.63, top5 = 57.19, top10 = 51.19, top15 = 47.61.
+PHY-3001 : End congestion estimation; 0.484350s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (109.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20674 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.006281s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000371454
+PHY-3002 : Step(275): len = 620976, overlap = 97
+PHY-3002 : Step(276): len = 621154, overlap = 96.5938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000742907
+PHY-3002 : Step(277): len = 621358, overlap = 96.4375
+PHY-3002 : Step(278): len = 622013, overlap = 96.6875
+PHY-3001 : Final: Len = 622013, Over = 96.6875
+PHY-3001 : End incremental placement; 5.421393s wall, 5.890625s user + 0.296875s system = 6.187500s CPU (114.1%)
+
+OPT-1001 : Total overflow 430.41 peak overflow 4.00
+OPT-1001 : End high-fanout net optimization; 8.772268s wall, 9.890625s user + 0.343750s system = 10.234375s CPU (116.7%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 709, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16866/20852.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710256, over cnt = 3018(8%), over = 9838, worst = 32
+PHY-1002 : len = 755152, over cnt = 2208(6%), over = 5644, worst = 18
+PHY-1002 : len = 785712, over cnt = 1467(4%), over = 3395, worst = 18
+PHY-1002 : len = 821664, over cnt = 528(1%), over = 1160, worst = 13
+PHY-1002 : len = 842336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.816748s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (134.2%)
+
+PHY-1001 : Congestion index: top1 = 57.74, top5 = 50.31, top10 = 46.88, top15 = 44.59.
+OPT-1001 : End congestion update; 2.103604s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (130.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20674 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.864727s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.4%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 120 cells processed and 13950 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 32 cells processed and 3200 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 0 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 500 slack improved
+OPT-1001 : End bottleneck based optimization; 3.445318s wall, 4.046875s user + 0.031250s system = 4.078125s CPU (118.4%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 708, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16930/20856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843200, over cnt = 70(0%), over = 90, worst = 5
+PHY-1002 : len = 843024, over cnt = 40(0%), over = 41, worst = 2
+PHY-1002 : len = 843104, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 843232, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 843416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.736814s wall, 0.765625s user + 0.046875s system = 0.812500s CPU (110.3%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 50.03, top10 = 46.68, top15 = 44.44.
+OPT-1001 : End congestion update; 1.019918s wall, 1.046875s user + 0.046875s system = 1.093750s CPU (107.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.852731s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.8%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 31 cells processed and 5600 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.007748s wall, 2.031250s user + 0.046875s system = 2.078125s CPU (103.5%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 708, peak = 733.
+OPT-1001 : End physical optimization; 16.398100s wall, 18.218750s user + 0.437500s system = 18.656250s CPU (113.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7769 LUT to BLE ...
+SYN-4008 : Packed 7769 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6151 remaining SEQ's ...
+SYN-4005 : Packed 3861 SEQ with LUT/SLICE
+SYN-4006 : 1044 single LUT's are left
+SYN-4006 : 2290 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10059/13914 primitive instances ...
+PHY-3001 : End packing; 1.852411s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6774 instances
+RUN-1001 : 3313 mslices, 3313 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17849 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9967 nets have 2 pins
+RUN-1001 : 6503 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 284 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6772 instances, 6626 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3507 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 634499, Over = 241
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7615/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790848, over cnt = 1944(5%), over = 3174, worst = 7
+PHY-1002 : len = 798288, over cnt = 1259(3%), over = 1787, worst = 7
+PHY-1002 : len = 811768, over cnt = 519(1%), over = 677, worst = 6
+PHY-1002 : len = 822144, over cnt = 62(0%), over = 71, worst = 4
+PHY-1002 : len = 824024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.738114s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (143.8%)
+
+PHY-1001 : Congestion index: top1 = 57.44, top5 = 50.63, top10 = 46.72, top15 = 44.10.
+PHY-3001 : End congestion estimation; 2.188814s wall, 2.921875s user + 0.031250s system = 2.953125s CPU (134.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71386, tnet num: 17671, tinst num: 6772, tnode num: 93664, tedge num: 118630.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.737975s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.7%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 617 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.662156s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.14251e-05
+PHY-3002 : Step(279): len = 622923, overlap = 233.75
+PHY-3002 : Step(280): len = 617539, overlap = 234.75
+PHY-3002 : Step(281): len = 614526, overlap = 239.75
+PHY-3002 : Step(282): len = 611639, overlap = 238.25
+PHY-3002 : Step(283): len = 609112, overlap = 238.25
+PHY-3002 : Step(284): len = 606985, overlap = 237.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00010285
+PHY-3002 : Step(285): len = 611035, overlap = 230.25
+PHY-3002 : Step(286): len = 615155, overlap = 221.75
+PHY-3002 : Step(287): len = 615043, overlap = 217.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.0002057
+PHY-3002 : Step(288): len = 625348, overlap = 200.75
+PHY-3002 : Step(289): len = 630634, overlap = 195
+PHY-3002 : Step(290): len = 628300, overlap = 192.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000411401
+PHY-3002 : Step(291): len = 634694, overlap = 183.25
+PHY-3002 : Step(292): len = 646086, overlap = 176.25
+PHY-3002 : Step(293): len = 646444, overlap = 179.5
+PHY-3002 : Step(294): len = 644248, overlap = 178.5
+PHY-3002 : Step(295): len = 642948, overlap = 175.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.453809s wall, 0.453125s user + 0.718750s system = 1.171875s CPU (258.2%)
+
+PHY-3001 : Trial Legalized: Len = 717638
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 848/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825480, over cnt = 2637(7%), over = 4413, worst = 7
+PHY-1002 : len = 843200, over cnt = 1569(4%), over = 2279, worst = 7
+PHY-1002 : len = 863096, over cnt = 550(1%), over = 733, worst = 6
+PHY-1002 : len = 868808, over cnt = 243(0%), over = 294, worst = 4
+PHY-1002 : len = 874376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.660145s wall, 4.031250s user + 0.062500s system = 4.093750s CPU (153.9%)
+
+PHY-1001 : Congestion index: top1 = 55.32, top5 = 49.94, top10 = 46.64, top15 = 44.49.
+PHY-3001 : End congestion estimation; 3.145036s wall, 4.500000s user + 0.062500s system = 4.562500s CPU (145.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.955569s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000179322
+PHY-3002 : Step(296): len = 690331, overlap = 32.25
+PHY-3002 : Step(297): len = 674555, overlap = 53.5
+PHY-3002 : Step(298): len = 659992, overlap = 83.25
+PHY-3002 : Step(299): len = 651072, overlap = 103.25
+PHY-3002 : Step(300): len = 645401, overlap = 115.75
+PHY-3002 : Step(301): len = 640736, overlap = 134.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000358644
+PHY-3002 : Step(302): len = 644922, overlap = 132.75
+PHY-3002 : Step(303): len = 649120, overlap = 131.25
+PHY-3002 : Step(304): len = 650071, overlap = 129.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000717289
+PHY-3002 : Step(305): len = 652245, overlap = 129.25
+PHY-3002 : Step(306): len = 656788, overlap = 128.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.038385s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (122.1%)
+
+PHY-3001 : Legalized: Len = 684280, Over = 0
+PHY-3001 : Spreading special nets. 421 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.104807s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (89.5%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 185, deltaY = 351, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 693394, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71386, tnet num: 17671, tinst num: 6775, tnode num: 93664, tedge num: 118630.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.989414s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (99.7%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 630 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 5093/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 819992, over cnt = 2356(6%), over = 3728, worst = 6
+PHY-1002 : len = 832752, over cnt = 1445(4%), over = 1966, worst = 6
+PHY-1002 : len = 850752, over cnt = 373(1%), over = 510, worst = 6
+PHY-1002 : len = 856168, over cnt = 88(0%), over = 122, worst = 4
+PHY-1002 : len = 858608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.221833s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 54.63, top5 = 48.53, top10 = 45.29, top15 = 43.20.
+PHY-1001 : End incremental global routing; 2.618564s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (137.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.936754s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (98.4%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6681 has valid locations, 34 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700311
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16201/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 867960, over cnt = 117(0%), over = 157, worst = 7
+PHY-1002 : len = 868192, over cnt = 64(0%), over = 74, worst = 4
+PHY-1002 : len = 868672, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 868840, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 868968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.857233s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 48.91, top10 = 45.66, top15 = 43.55.
+PHY-3001 : End congestion estimation; 1.201899s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (105.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71654, tnet num: 17696, tinst num: 6803, tnode num: 94007, tedge num: 118969.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.041136s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (100.3%)
+
+RUN-1004 : used memory is 649 MB, reserved memory is 659 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.978996s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(307): len = 698959, overlap = 0
+PHY-3002 : Step(308): len = 697986, overlap = 0
+PHY-3002 : Step(309): len = 697382, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16186/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 864264, over cnt = 71(0%), over = 104, worst = 5
+PHY-1002 : len = 864496, over cnt = 39(0%), over = 44, worst = 4
+PHY-1002 : len = 864880, over cnt = 16(0%), over = 17, worst = 2
+PHY-1002 : len = 865104, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 865136, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.845972s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (107.1%)
+
+PHY-1001 : Congestion index: top1 = 54.59, top5 = 48.62, top10 = 45.37, top15 = 43.33.
+PHY-3001 : End congestion estimation; 1.179309s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (106.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.902164s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00039289
+PHY-3002 : Step(310): len = 697361, overlap = 3
+PHY-3002 : Step(311): len = 697177, overlap = 2.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005525s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (282.8%)
+
+PHY-3001 : Legalized: Len = 697487, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066123s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (118.2%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 3, deltaY = 6, maxDist = 3.
+PHY-3001 : Final: Len = 697593, Over = 0
+PHY-3001 : End incremental placement; 6.801474s wall, 6.890625s user + 0.218750s system = 7.109375s CPU (104.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.877708s wall, 11.953125s user + 0.218750s system = 12.171875s CPU (111.9%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16155/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865032, over cnt = 78(0%), over = 109, worst = 6
+PHY-1002 : len = 865216, over cnt = 55(0%), over = 64, worst = 3
+PHY-1002 : len = 865608, over cnt = 23(0%), over = 24, worst = 2
+PHY-1002 : len = 865848, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 865952, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.854133s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (111.6%)
+
+PHY-1001 : Congestion index: top1 = 54.66, top5 = 48.63, top10 = 45.38, top15 = 43.30.
+OPT-1001 : End congestion update; 1.188920s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (109.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.904507s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.2%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 706436, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063907s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (122.2%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 6, deltaY = 29, maxDist = 3.
+PHY-3001 : Final: Len = 706504, Over = 0
+PHY-3001 : End incremental legalization; 0.416971s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.4%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 59 cells processed and 20640 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 706760, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065254s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.7%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 706874, Over = 0
+PHY-3001 : End incremental legalization; 0.416036s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (93.9%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 13 cells processed and 1493 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707436, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060273s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.7%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 707450, Over = 0
+PHY-3001 : End incremental legalization; 0.416014s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.4%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 700 slack improved
+OPT-1001 : End bottleneck based optimization; 3.782999s wall, 3.953125s user + 0.031250s system = 3.984375s CPU (105.3%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15895/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874888, over cnt = 153(0%), over = 189, worst = 3
+PHY-1002 : len = 875200, over cnt = 91(0%), over = 100, worst = 3
+PHY-1002 : len = 876000, over cnt = 26(0%), over = 31, worst = 2
+PHY-1002 : len = 876456, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 876536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.894240s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (110.1%)
+
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.63, top10 = 45.39, top15 = 43.32.
+OPT-1001 : End congestion update; 1.239180s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (107.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.785279s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (101.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707718, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070065s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.5%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.457045s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 2050 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.638526s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (103.6%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 734.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.763423s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16188/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876608, over cnt = 30(0%), over = 34, worst = 3
+PHY-1002 : len = 876664, over cnt = 20(0%), over = 21, worst = 2
+PHY-1002 : len = 876792, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.715766s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (104.8%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.784278s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.655172
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707622, Over = 0
+PHY-3001 : End spreading; 0.063643s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.2%)
+
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.485333s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.767334s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.8%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16225/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139371s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.9%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+OPT-1001 : End congestion update; 0.478318s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.761060s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707628, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064610s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (120.9%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.412932s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (124.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.771345s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (105.9%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16225/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.143596s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.9%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+OPT-1001 : End congestion update; 0.485657s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.769476s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707628, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063153s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.457053s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707628, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063141s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.457913s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (102.4%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.575217s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 734.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.764047s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 734.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.816763s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.5%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16225/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.143246s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.2%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+RUN-1001 : End congestion update; 0.489855s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (102.1%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.309735s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (100.2%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 734.
+OPT-1001 : End physical optimization; 29.977138s wall, 31.531250s user + 0.296875s system = 31.828125s CPU (106.2%)
+
+RUN-1003 : finish command "place" in 77.651110s wall, 109.312500s user + 7.203125s system = 116.515625s CPU (150.1%)
+
+RUN-1004 : used memory is 675 MB, reserved memory is 684 MB, peak memory is 734 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.792896s wall, 3.093750s user + 0.031250s system = 3.125000s CPU (174.3%)
+
+RUN-1004 : used memory is 675 MB, reserved memory is 685 MB, peak memory is 734 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6808 instances
+RUN-1001 : 3330 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17874 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9957 nets have 2 pins
+RUN-1001 : 6510 nets have [3 - 5] pins
+RUN-1001 : 748 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 299 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71680, tnet num: 17696, tinst num: 6806, tnode num: 94044, tedge num: 119007.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.735889s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.9%)
+
+RUN-1004 : used memory is 656 MB, reserved memory is 656 MB, peak memory is 734 MB
+PHY-1001 : 3330 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 805976, over cnt = 2641(7%), over = 4426, worst = 9
+PHY-1002 : len = 824760, over cnt = 1662(4%), over = 2375, worst = 9
+PHY-1002 : len = 842896, over cnt = 694(1%), over = 1010, worst = 9
+PHY-1002 : len = 858520, over cnt = 11(0%), over = 25, worst = 6
+PHY-1002 : len = 858984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.165466s wall, 4.218750s user + 0.015625s system = 4.234375s CPU (133.8%)
+
+PHY-1001 : Congestion index: top1 = 53.64, top5 = 48.13, top10 = 45.03, top15 = 42.95.
+PHY-1001 : End global routing; 3.526471s wall, 4.593750s user + 0.015625s system = 4.609375s CPU (130.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 711, reserve = 711, peak = 734.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 982, peak = 982.
+PHY-1001 : End build detailed router design. 4.501997s wall, 4.468750s user + 0.031250s system = 4.500000s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267320, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.770239s wall, 5.734375s user + 0.015625s system = 5.750000s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267376, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.597710s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (96.7%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1018, peak = 1018.
+PHY-1001 : End phase 1; 6.381427s wall, 6.328125s user + 0.015625s system = 6.343750s CPU (99.4%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.198e+06, over cnt = 1678(0%), over = 1691, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1031, peak = 1033.
+PHY-1001 : End initial routed; 27.412776s wall, 64.140625s user + 0.234375s system = 64.375000s CPU (234.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16794(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.784 | -0.784 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.551182s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1040, peak = 1040.
+PHY-1001 : End phase 2; 30.964022s wall, 67.703125s user + 0.234375s system = 67.937500s CPU (219.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.144103s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.6%)
+
+PHY-1022 : len = 2.198e+06, over cnt = 1678(0%), over = 1691, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.440729s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.17426e+06, over cnt = 620(0%), over = 621, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.204696s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (192.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.17319e+06, over cnt = 138(0%), over = 138, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.804230s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (134.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.17389e+06, over cnt = 25(0%), over = 25, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.321497s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (121.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.17394e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.214070s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.17423e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.271565s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (103.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.17427e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.260811s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.17427e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.338516s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (101.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.17428e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.186324s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.17433e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.178664s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16794(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.501628s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 509 feed throughs used by 367 nets
+PHY-1001 : End commit to database; 2.395953s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1136, reserve = 1139, peak = 1136.
+PHY-1001 : End phase 3; 10.566596s wall, 11.984375s user + 0.031250s system = 12.015625s CPU (113.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.145752s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.5%)
+
+PHY-1022 : len = 2.17433e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.415133s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16794(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.527886s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 509 feed throughs used by 367 nets
+PHY-1001 : End commit to database; 2.422807s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1145, reserve = 1148, peak = 1145.
+PHY-1001 : End phase 4; 6.398341s wall, 6.390625s user + 0.000000s system = 6.390625s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.17433e+06
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1150, peak = 1147.
+PHY-1001 : End export database. 0.063711s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.1%)
+
+PHY-1001 : End detail routing; 59.302464s wall, 97.375000s user + 0.312500s system = 97.687500s CPU (164.7%)
+
+RUN-1003 : finish command "route" in 65.694722s wall, 104.843750s user + 0.328125s system = 105.171875s CPU (160.1%)
+
+RUN-1004 : used memory is 1075 MB, reserved memory is 1078 MB, peak memory is 1147 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10205 out of 19600 52.07%
+#reg 9423 out of 19600 48.08%
+#le 12468
+ #lut only 3045 out of 12468 24.42%
+ #reg only 2263 out of 12468 18.15%
+ #lut® 7160 out of 12468 57.43%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1804
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1379
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1275
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 957
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 132
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 73
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg0_syn_149.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg47_syn_243.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P118 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P110 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P143 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12468 |9178 |1027 |9457 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |547 |448 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |96 |81 |4 |85 |4 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |40 |40 |0 |22 |0 |0 |
+| exdev_ctl_a |exdev_ctl |769 |389 |96 |580 |0 |0 |
+| u_ADconfig |AD_config |189 |126 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |263 |170 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |742 |329 |96 |563 |0 |0 |
+| u_ADconfig |AD_config |172 |108 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |258 |157 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |3039 |2431 |306 |2071 |25 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |177 |103 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_sort |sort |2830 |2325 |289 |1891 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2385 |2019 |253 |1536 |22 |0 |
+| channelPart |channel_part_8478 |133 |119 |3 |127 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1884 |1594 |197 |1157 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |124 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| insert |insert |966 |703 |170 |655 |0 |0 |
+| ram_switch_state |ram_switch_state |697 |697 |0 |378 |0 |0 |
+| read_ram_i |read_ram |283 |238 |44 |184 |0 |0 |
+| read_ram_addr |read_ram_addr |236 |196 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |45 |40 |4 |31 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |304 |195 |36 |258 |3 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3227 |2539 |349 |2078 |25 |1 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |177 |96 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_sort |sort_rev |3020 |2426 |332 |1900 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2576 |2084 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |129 |113 |3 |125 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1997 |1653 |197 |1136 |0 |0 |
+| adc_addr_gen |adc_addr_gen |199 |172 |27 |92 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |2 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |992 |675 |170 |688 |0 |0 |
+| ram_switch_state |ram_switch_state |806 |806 |0 |356 |0 |0 |
+| read_ram_i |read_ram_rev |362 |247 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |303 |218 |73 |168 |0 |0 |
+| read_ram_data |read_ram_data_rev |59 |29 |8 |44 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9895
+ #2 2 4221
+ #3 3 1705
+ #4 4 581
+ #5 5-10 784
+ #6 11-50 579
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.209900s wall, 3.828125s user + 0.015625s system = 3.843750s CPU (173.9%)
+
+RUN-1004 : used memory is 1077 MB, reserved memory is 1079 MB, peak memory is 1147 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71680, tnet num: 17696, tinst num: 6806, tnode num: 94044, tedge num: 119007.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.712959s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.4%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1083 MB, peak memory is 1147 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.554598s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.5%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1085 MB, peak memory is 1147 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6806
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17874, pip num: 165901
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 509
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 465041 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.957874s wall, 63.015625s user + 0.203125s system = 63.218750s CPU (634.9%)
+
+RUN-1004 : used memory is 1240 MB, reserved memory is 1239 MB, peak memory is 1355 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_142526.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_144655.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_144655.log
new file mode 100644
index 0000000..51da5f5
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_144655.log
@@ -0,0 +1,2165 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 14:46:55 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.250483s wall, 2.140625s user + 0.109375s system = 2.250000s CPU (100.0%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 315 MB, peak memory is 344 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17999 instances
+RUN-0007 : 7674 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20577 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13091 nets have 2 pins
+RUN-1001 : 6451 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17997 instances, 7674 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.198187s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (99.1%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 514 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.999039s wall, 1.937500s user + 0.062500s system = 2.000000s CPU (100.0%)
+
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.97121e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17997.
+PHY-3001 : Level 1 #clusters 2079.
+PHY-3001 : End clustering; 0.134546s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (104.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31367e+06, overlap = 443.438
+PHY-3002 : Step(2): len = 1.2294e+06, overlap = 486.125
+PHY-3002 : Step(3): len = 875782, overlap = 560.594
+PHY-3002 : Step(4): len = 798923, overlap = 601.969
+PHY-3002 : Step(5): len = 641758, overlap = 743.312
+PHY-3002 : Step(6): len = 570495, overlap = 800.875
+PHY-3002 : Step(7): len = 486549, overlap = 870.969
+PHY-3002 : Step(8): len = 437691, overlap = 925
+PHY-3002 : Step(9): len = 401477, overlap = 981.781
+PHY-3002 : Step(10): len = 365241, overlap = 1042.06
+PHY-3002 : Step(11): len = 327157, overlap = 1107.09
+PHY-3002 : Step(12): len = 299533, overlap = 1128.97
+PHY-3002 : Step(13): len = 278253, overlap = 1200.31
+PHY-3002 : Step(14): len = 248289, overlap = 1280.03
+PHY-3002 : Step(15): len = 237739, overlap = 1335.94
+PHY-3002 : Step(16): len = 205556, overlap = 1381.72
+PHY-3002 : Step(17): len = 193198, overlap = 1381.34
+PHY-3002 : Step(18): len = 172725, overlap = 1399.28
+PHY-3002 : Step(19): len = 166556, overlap = 1422.09
+PHY-3002 : Step(20): len = 148481, overlap = 1453.16
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.11523e-06
+PHY-3002 : Step(21): len = 150350, overlap = 1409.84
+PHY-3002 : Step(22): len = 184148, overlap = 1279.47
+PHY-3002 : Step(23): len = 192105, overlap = 1220.28
+PHY-3002 : Step(24): len = 200234, overlap = 1165.25
+PHY-3002 : Step(25): len = 199572, overlap = 1120.31
+PHY-3002 : Step(26): len = 199326, overlap = 1118.69
+PHY-3002 : Step(27): len = 195889, overlap = 1109.88
+PHY-3002 : Step(28): len = 192973, overlap = 1083.44
+PHY-3002 : Step(29): len = 191423, overlap = 1092.5
+PHY-3002 : Step(30): len = 190165, overlap = 1082.84
+PHY-3002 : Step(31): len = 188086, overlap = 1070.78
+PHY-3002 : Step(32): len = 186123, overlap = 1069.59
+PHY-3002 : Step(33): len = 184580, overlap = 1075.47
+PHY-3002 : Step(34): len = 182237, overlap = 1087.72
+PHY-3002 : Step(35): len = 181472, overlap = 1092.66
+PHY-3002 : Step(36): len = 179872, overlap = 1090.16
+PHY-3002 : Step(37): len = 179076, overlap = 1083.28
+PHY-3002 : Step(38): len = 179220, overlap = 1088.91
+PHY-3002 : Step(39): len = 179593, overlap = 1083.09
+PHY-3002 : Step(40): len = 179215, overlap = 1096.53
+PHY-3002 : Step(41): len = 177373, overlap = 1087.91
+PHY-3002 : Step(42): len = 176934, overlap = 1083.78
+PHY-3002 : Step(43): len = 175306, overlap = 1092.62
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.23046e-06
+PHY-3002 : Step(44): len = 178570, overlap = 1086.06
+PHY-3002 : Step(45): len = 187856, overlap = 1056.28
+PHY-3002 : Step(46): len = 192492, overlap = 1047.22
+PHY-3002 : Step(47): len = 198801, overlap = 1022.66
+PHY-3002 : Step(48): len = 202380, overlap = 996.969
+PHY-3002 : Step(49): len = 203592, overlap = 976.812
+PHY-3002 : Step(50): len = 201393, overlap = 954.562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.46092e-06
+PHY-3002 : Step(51): len = 209014, overlap = 915.812
+PHY-3002 : Step(52): len = 226062, overlap = 834
+PHY-3002 : Step(53): len = 234714, overlap = 782.781
+PHY-3002 : Step(54): len = 239487, overlap = 782.188
+PHY-3002 : Step(55): len = 243045, overlap = 753.625
+PHY-3002 : Step(56): len = 245287, overlap = 749.531
+PHY-3002 : Step(57): len = 244198, overlap = 741.125
+PHY-3002 : Step(58): len = 244100, overlap = 749.188
+PHY-3002 : Step(59): len = 242691, overlap = 750.375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.92183e-06
+PHY-3002 : Step(60): len = 258933, overlap = 711.344
+PHY-3002 : Step(61): len = 276627, overlap = 625.844
+PHY-3002 : Step(62): len = 282614, overlap = 599.594
+PHY-3002 : Step(63): len = 284482, overlap = 573.125
+PHY-3002 : Step(64): len = 283554, overlap = 564.312
+PHY-3002 : Step(65): len = 282897, overlap = 556.5
+PHY-3002 : Step(66): len = 283149, overlap = 558.125
+PHY-3002 : Step(67): len = 284250, overlap = 558.656
+PHY-3002 : Step(68): len = 283695, overlap = 549.531
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.78437e-05
+PHY-3002 : Step(69): len = 298897, overlap = 516.906
+PHY-3002 : Step(70): len = 313803, overlap = 467.312
+PHY-3002 : Step(71): len = 319442, overlap = 450.031
+PHY-3002 : Step(72): len = 323544, overlap = 427.5
+PHY-3002 : Step(73): len = 323423, overlap = 409.688
+PHY-3002 : Step(74): len = 323390, overlap = 402.188
+PHY-3002 : Step(75): len = 321916, overlap = 394.531
+PHY-3002 : Step(76): len = 322659, overlap = 396.188
+PHY-3002 : Step(77): len = 323421, overlap = 390
+PHY-3002 : Step(78): len = 324312, overlap = 387.438
+PHY-3002 : Step(79): len = 324731, overlap = 390.469
+PHY-3002 : Step(80): len = 324690, overlap = 405.344
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.56873e-05
+PHY-3002 : Step(81): len = 339216, overlap = 382.719
+PHY-3002 : Step(82): len = 353542, overlap = 365.469
+PHY-3002 : Step(83): len = 357595, overlap = 338.562
+PHY-3002 : Step(84): len = 360363, overlap = 326.5
+PHY-3002 : Step(85): len = 361190, overlap = 316.656
+PHY-3002 : Step(86): len = 363044, overlap = 307.938
+PHY-3002 : Step(87): len = 363538, overlap = 304.969
+PHY-3002 : Step(88): len = 365350, overlap = 311.844
+PHY-3002 : Step(89): len = 370355, overlap = 309.781
+PHY-3002 : Step(90): len = 373478, overlap = 277.125
+PHY-3002 : Step(91): len = 374132, overlap = 267.781
+PHY-3002 : Step(92): len = 373111, overlap = 256.031
+PHY-3002 : Step(93): len = 374331, overlap = 256.625
+PHY-3002 : Step(94): len = 374662, overlap = 251.656
+PHY-3002 : Step(95): len = 372570, overlap = 251.219
+PHY-3002 : Step(96): len = 371050, overlap = 245.969
+PHY-3002 : Step(97): len = 369277, overlap = 236.594
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.13747e-05
+PHY-3002 : Step(98): len = 384890, overlap = 248.719
+PHY-3002 : Step(99): len = 395077, overlap = 237.688
+PHY-3002 : Step(100): len = 395860, overlap = 212.938
+PHY-3002 : Step(101): len = 398911, overlap = 217.594
+PHY-3002 : Step(102): len = 400433, overlap = 209.188
+PHY-3002 : Step(103): len = 402091, overlap = 207.031
+PHY-3002 : Step(104): len = 398839, overlap = 208.438
+PHY-3002 : Step(105): len = 398605, overlap = 199.438
+PHY-3002 : Step(106): len = 399573, overlap = 210.375
+PHY-3002 : Step(107): len = 400792, overlap = 209.219
+PHY-3002 : Step(108): len = 399260, overlap = 202.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000141893
+PHY-3002 : Step(109): len = 412524, overlap = 190.125
+PHY-3002 : Step(110): len = 423343, overlap = 184.062
+PHY-3002 : Step(111): len = 423838, overlap = 171.188
+PHY-3002 : Step(112): len = 425185, overlap = 173.281
+PHY-3002 : Step(113): len = 427166, overlap = 177.688
+PHY-3002 : Step(114): len = 428966, overlap = 172.781
+PHY-3002 : Step(115): len = 427537, overlap = 178
+PHY-3002 : Step(116): len = 428958, overlap = 181.906
+PHY-3002 : Step(117): len = 431638, overlap = 177.312
+PHY-3002 : Step(118): len = 433787, overlap = 181.938
+PHY-3002 : Step(119): len = 431827, overlap = 179.406
+PHY-3002 : Step(120): len = 431999, overlap = 182.75
+PHY-3002 : Step(121): len = 433646, overlap = 186.281
+PHY-3002 : Step(122): len = 435187, overlap = 184.125
+PHY-3002 : Step(123): len = 432604, overlap = 190.188
+PHY-3002 : Step(124): len = 432943, overlap = 195.062
+PHY-3002 : Step(125): len = 436269, overlap = 197.594
+PHY-3002 : Step(126): len = 439132, overlap = 199.75
+PHY-3002 : Step(127): len = 435856, overlap = 206.031
+PHY-3002 : Step(128): len = 435551, overlap = 205.188
+PHY-3002 : Step(129): len = 438653, overlap = 196.438
+PHY-3002 : Step(130): len = 441077, overlap = 198.719
+PHY-3002 : Step(131): len = 437522, overlap = 203.094
+PHY-3002 : Step(132): len = 437320, overlap = 202.156
+PHY-3002 : Step(133): len = 439014, overlap = 204.406
+PHY-3002 : Step(134): len = 439606, overlap = 198.125
+PHY-3002 : Step(135): len = 437721, overlap = 202.812
+PHY-3002 : Step(136): len = 437554, overlap = 191.156
+PHY-3002 : Step(137): len = 438685, overlap = 203.188
+PHY-3002 : Step(138): len = 439154, overlap = 199.5
+PHY-3002 : Step(139): len = 437426, overlap = 185.188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.0002667
+PHY-3002 : Step(140): len = 447527, overlap = 170.656
+PHY-3002 : Step(141): len = 456295, overlap = 170.062
+PHY-3002 : Step(142): len = 455126, overlap = 161.156
+PHY-3002 : Step(143): len = 455566, overlap = 163.625
+PHY-3002 : Step(144): len = 458405, overlap = 167.906
+PHY-3002 : Step(145): len = 461078, overlap = 168
+PHY-3002 : Step(146): len = 459484, overlap = 160.594
+PHY-3002 : Step(147): len = 459693, overlap = 160.906
+PHY-3002 : Step(148): len = 462668, overlap = 163.969
+PHY-3002 : Step(149): len = 464956, overlap = 164.125
+PHY-3002 : Step(150): len = 462570, overlap = 167.219
+PHY-3002 : Step(151): len = 461977, overlap = 168.531
+PHY-3002 : Step(152): len = 463385, overlap = 169
+PHY-3002 : Step(153): len = 464468, overlap = 174.938
+PHY-3002 : Step(154): len = 462091, overlap = 177.938
+PHY-3002 : Step(155): len = 461909, overlap = 176.906
+PHY-3002 : Step(156): len = 462950, overlap = 173.375
+PHY-3002 : Step(157): len = 463688, overlap = 175.375
+PHY-3002 : Step(158): len = 462795, overlap = 178.031
+PHY-3002 : Step(159): len = 463036, overlap = 179.969
+PHY-3002 : Step(160): len = 463948, overlap = 178.875
+PHY-3002 : Step(161): len = 464131, overlap = 178.188
+PHY-3002 : Step(162): len = 463068, overlap = 173.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000482763
+PHY-3002 : Step(163): len = 469329, overlap = 172.375
+PHY-3002 : Step(164): len = 475097, overlap = 173.344
+PHY-3002 : Step(165): len = 475080, overlap = 167.656
+PHY-3002 : Step(166): len = 475774, overlap = 169.281
+PHY-3002 : Step(167): len = 478181, overlap = 165.344
+PHY-3002 : Step(168): len = 479792, overlap = 158.094
+PHY-3002 : Step(169): len = 479178, overlap = 157.562
+PHY-3002 : Step(170): len = 479447, overlap = 153.75
+PHY-3002 : Step(171): len = 481533, overlap = 160.688
+PHY-3002 : Step(172): len = 482648, overlap = 161.469
+PHY-3002 : Step(173): len = 481718, overlap = 154.156
+PHY-3002 : Step(174): len = 481683, overlap = 152.938
+PHY-3002 : Step(175): len = 482535, overlap = 150.344
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000867386
+PHY-3002 : Step(176): len = 488642, overlap = 144.125
+PHY-3002 : Step(177): len = 499852, overlap = 133.094
+PHY-3002 : Step(178): len = 505259, overlap = 126.75
+PHY-3002 : Step(179): len = 509904, overlap = 129.219
+PHY-3002 : Step(180): len = 512754, overlap = 134.844
+PHY-3002 : Step(181): len = 513598, overlap = 134.469
+PHY-3002 : Step(182): len = 511808, overlap = 124.125
+PHY-3002 : Step(183): len = 510977, overlap = 122.125
+PHY-3002 : Step(184): len = 512356, overlap = 132.125
+PHY-3002 : Step(185): len = 513518, overlap = 131.938
+PHY-3002 : Step(186): len = 512550, overlap = 129.219
+PHY-3002 : Step(187): len = 512115, overlap = 137.625
+PHY-3002 : Step(188): len = 512657, overlap = 140.469
+PHY-3002 : Step(189): len = 513427, overlap = 142.375
+PHY-3002 : Step(190): len = 512831, overlap = 141.281
+PHY-3002 : Step(191): len = 512643, overlap = 142.344
+PHY-3002 : Step(192): len = 513062, overlap = 143.25
+PHY-3002 : Step(193): len = 513259, overlap = 141.094
+PHY-3002 : Step(194): len = 512604, overlap = 138.531
+PHY-3002 : Step(195): len = 512251, overlap = 140.781
+PHY-3002 : Step(196): len = 512355, overlap = 135.281
+PHY-3002 : Step(197): len = 512785, overlap = 136.094
+PHY-3002 : Step(198): len = 512166, overlap = 137.781
+PHY-3002 : Step(199): len = 512058, overlap = 140.312
+PHY-3002 : Step(200): len = 512282, overlap = 140.312
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00158333
+PHY-3002 : Step(201): len = 515022, overlap = 138.312
+PHY-3002 : Step(202): len = 518907, overlap = 139.469
+PHY-3002 : Step(203): len = 520191, overlap = 137.719
+PHY-3002 : Step(204): len = 520955, overlap = 139.031
+PHY-3002 : Step(205): len = 522010, overlap = 139.844
+PHY-3002 : Step(206): len = 522611, overlap = 138.156
+PHY-3002 : Step(207): len = 522648, overlap = 137.969
+PHY-3002 : Step(208): len = 522788, overlap = 138.281
+PHY-3002 : Step(209): len = 523483, overlap = 138.719
+PHY-3002 : Step(210): len = 524292, overlap = 138.906
+PHY-3002 : Step(211): len = 524457, overlap = 134.344
+PHY-3002 : Step(212): len = 524484, overlap = 134.219
+PHY-3002 : Step(213): len = 524724, overlap = 135.094
+PHY-3002 : Step(214): len = 524875, overlap = 136.156
+PHY-3002 : Step(215): len = 525036, overlap = 135.156
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013238s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (236.1%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 693600, over cnt = 1544(4%), over = 7424, worst = 43
+PHY-1001 : End global iterations; 0.668338s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (133.3%)
+
+PHY-1001 : Congestion index: top1 = 81.12, top5 = 62.06, top10 = 52.51, top15 = 46.52.
+PHY-3001 : End congestion estimation; 0.901945s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (124.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.918991s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000125282
+PHY-3002 : Step(216): len = 629930, overlap = 78.375
+PHY-3002 : Step(217): len = 627753, overlap = 79.0625
+PHY-3002 : Step(218): len = 621867, overlap = 70.6562
+PHY-3002 : Step(219): len = 617130, overlap = 59.375
+PHY-3002 : Step(220): len = 616555, overlap = 54.4062
+PHY-3002 : Step(221): len = 616504, overlap = 49.5938
+PHY-3002 : Step(222): len = 613558, overlap = 53
+PHY-3002 : Step(223): len = 610185, overlap = 50.125
+PHY-3002 : Step(224): len = 609005, overlap = 44.0625
+PHY-3002 : Step(225): len = 606149, overlap = 38.5
+PHY-3002 : Step(226): len = 602743, overlap = 35.3438
+PHY-3002 : Step(227): len = 601039, overlap = 37.2812
+PHY-3002 : Step(228): len = 599920, overlap = 34.0312
+PHY-3002 : Step(229): len = 598610, overlap = 34.9688
+PHY-3002 : Step(230): len = 598435, overlap = 34.375
+PHY-3002 : Step(231): len = 597975, overlap = 37.7188
+PHY-3002 : Step(232): len = 597349, overlap = 38.125
+PHY-3002 : Step(233): len = 596296, overlap = 38.5
+PHY-3002 : Step(234): len = 595909, overlap = 38.7812
+PHY-3002 : Step(235): len = 594744, overlap = 40.0312
+PHY-3002 : Step(236): len = 593418, overlap = 42.3438
+PHY-3002 : Step(237): len = 592406, overlap = 43.4062
+PHY-3002 : Step(238): len = 591111, overlap = 48.4062
+PHY-3002 : Step(239): len = 589582, overlap = 48.375
+PHY-3002 : Step(240): len = 587546, overlap = 49.0625
+PHY-3002 : Step(241): len = 586214, overlap = 50.6875
+PHY-3002 : Step(242): len = 585507, overlap = 54.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000250564
+PHY-3002 : Step(243): len = 587829, overlap = 54.2188
+PHY-3002 : Step(244): len = 593457, overlap = 54.375
+PHY-3002 : Step(245): len = 598703, overlap = 54.0312
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000501127
+PHY-3002 : Step(246): len = 602442, overlap = 52.8125
+PHY-3002 : Step(247): len = 614112, overlap = 51.875
+PHY-3002 : Step(248): len = 631182, overlap = 51.625
+PHY-3002 : Step(249): len = 631420, overlap = 49.0625
+PHY-3002 : Step(250): len = 630502, overlap = 46.2812
+PHY-3002 : Step(251): len = 629434, overlap = 44.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 50/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 711944, over cnt = 2639(7%), over = 12705, worst = 70
+PHY-1001 : End global iterations; 1.643476s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (134.1%)
+
+PHY-1001 : Congestion index: top1 = 87.24, top5 = 69.80, top10 = 60.98, top15 = 55.43.
+PHY-3001 : End congestion estimation; 1.911833s wall, 2.453125s user + 0.015625s system = 2.468750s CPU (129.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.510800s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000102239
+PHY-3002 : Step(252): len = 623578, overlap = 270.562
+PHY-3002 : Step(253): len = 622061, overlap = 204.312
+PHY-3002 : Step(254): len = 616560, overlap = 169.656
+PHY-3002 : Step(255): len = 611346, overlap = 154.656
+PHY-3002 : Step(256): len = 604615, overlap = 146.312
+PHY-3002 : Step(257): len = 601674, overlap = 139.906
+PHY-3002 : Step(258): len = 598608, overlap = 122.625
+PHY-3002 : Step(259): len = 595583, overlap = 124.594
+PHY-3002 : Step(260): len = 592645, overlap = 120.062
+PHY-3002 : Step(261): len = 589327, overlap = 116.562
+PHY-3002 : Step(262): len = 585879, overlap = 116.031
+PHY-3002 : Step(263): len = 582729, overlap = 124.969
+PHY-3002 : Step(264): len = 579981, overlap = 131.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000204478
+PHY-3002 : Step(265): len = 580899, overlap = 125.219
+PHY-3002 : Step(266): len = 582744, overlap = 120.688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000345479
+PHY-3002 : Step(267): len = 584784, overlap = 117.906
+PHY-3002 : Step(268): len = 592297, overlap = 106.875
+PHY-3002 : Step(269): len = 597351, overlap = 99.5
+PHY-3002 : Step(270): len = 598278, overlap = 96
+PHY-3002 : Step(271): len = 599136, overlap = 94.7188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.543660s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (100.2%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 562 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 424.53 peak overflow 4.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 735/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 694320, over cnt = 3015(8%), over = 10711, worst = 32
+PHY-1001 : End global iterations; 1.328462s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 69.40, top5 = 56.60, top10 = 50.60, top15 = 47.00.
+PHY-1001 : End incremental global routing; 1.664434s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (131.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.927184s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (99.4%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17866 has valid locations, 321 needs to be replaced
+PHY-3001 : design contains 18272 instances, 7769 luts, 9282 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6076 pins
+PHY-3001 : Found 1268 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 622359
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16812/20852.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710528, over cnt = 3048(8%), over = 10756, worst = 32
+PHY-1001 : End global iterations; 0.238009s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 69.38, top5 = 56.80, top10 = 50.92, top15 = 47.38.
+PHY-3001 : End congestion estimation; 0.496518s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (119.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85144, tnet num: 20674, tinst num: 18272, tnode num: 115971, tedge num: 135670.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.494335s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (99.3%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 613 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20674 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.470598s wall, 2.406250s user + 0.062500s system = 2.468750s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(272): len = 621584, overlap = 0.09375
+PHY-3002 : Step(273): len = 621187, overlap = 0.09375
+PHY-3002 : Step(274): len = 621110, overlap = 0.09375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16929/20852.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708416, over cnt = 3059(8%), over = 10835, worst = 32
+PHY-1001 : End global iterations; 0.182643s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (145.4%)
+
+PHY-1001 : Congestion index: top1 = 69.63, top5 = 57.19, top10 = 51.19, top15 = 47.61.
+PHY-3001 : End congestion estimation; 0.442011s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (120.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20674 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.960220s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000371454
+PHY-3002 : Step(275): len = 620976, overlap = 97
+PHY-3002 : Step(276): len = 621154, overlap = 96.5938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000742907
+PHY-3002 : Step(277): len = 621358, overlap = 96.4375
+PHY-3002 : Step(278): len = 622013, overlap = 96.6875
+PHY-3001 : Final: Len = 622013, Over = 96.6875
+PHY-3001 : End incremental placement; 5.044769s wall, 5.234375s user + 0.250000s system = 5.484375s CPU (108.7%)
+
+OPT-1001 : Total overflow 430.41 peak overflow 4.00
+OPT-1001 : End high-fanout net optimization; 8.182326s wall, 8.921875s user + 0.281250s system = 9.203125s CPU (112.5%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 708, peak = 732.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16866/20852.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710256, over cnt = 3018(8%), over = 9838, worst = 32
+PHY-1002 : len = 755152, over cnt = 2208(6%), over = 5644, worst = 18
+PHY-1002 : len = 785712, over cnt = 1467(4%), over = 3395, worst = 18
+PHY-1002 : len = 821664, over cnt = 528(1%), over = 1160, worst = 13
+PHY-1002 : len = 842336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.830504s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (133.2%)
+
+PHY-1001 : Congestion index: top1 = 57.74, top5 = 50.31, top10 = 46.88, top15 = 44.59.
+OPT-1001 : End congestion update; 2.126832s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (128.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20674 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.888493s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 120 cells processed and 13950 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 32 cells processed and 3200 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 0 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 500 slack improved
+OPT-1001 : End bottleneck based optimization; 3.467686s wall, 4.078125s user + 0.000000s system = 4.078125s CPU (117.6%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 691, peak = 732.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16930/20856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843200, over cnt = 70(0%), over = 90, worst = 5
+PHY-1002 : len = 843024, over cnt = 40(0%), over = 41, worst = 2
+PHY-1002 : len = 843104, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 843232, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 843416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.785739s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.4%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 50.03, top10 = 46.68, top15 = 44.44.
+OPT-1001 : End congestion update; 1.093215s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (100.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.885751s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.6%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 31 cells processed and 5600 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.119323s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (100.3%)
+
+OPT-1001 : Current memory(MB): used = 703, reserve = 697, peak = 732.
+OPT-1001 : End physical optimization; 15.648418s wall, 16.984375s user + 0.296875s system = 17.281250s CPU (110.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7769 LUT to BLE ...
+SYN-4008 : Packed 7769 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6151 remaining SEQ's ...
+SYN-4005 : Packed 3861 SEQ with LUT/SLICE
+SYN-4006 : 1044 single LUT's are left
+SYN-4006 : 2290 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10059/13914 primitive instances ...
+PHY-3001 : End packing; 1.886321s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6774 instances
+RUN-1001 : 3313 mslices, 3313 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17849 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9967 nets have 2 pins
+RUN-1001 : 6503 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 284 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6772 instances, 6626 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3507 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 634499, Over = 241
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7615/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790848, over cnt = 1944(5%), over = 3174, worst = 7
+PHY-1002 : len = 798288, over cnt = 1259(3%), over = 1787, worst = 7
+PHY-1002 : len = 811768, over cnt = 519(1%), over = 677, worst = 6
+PHY-1002 : len = 822144, over cnt = 62(0%), over = 71, worst = 4
+PHY-1002 : len = 824024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.793566s wall, 2.562500s user + 0.031250s system = 2.593750s CPU (144.6%)
+
+PHY-1001 : Congestion index: top1 = 57.44, top5 = 50.63, top10 = 46.72, top15 = 44.10.
+PHY-3001 : End congestion estimation; 2.240702s wall, 3.031250s user + 0.031250s system = 3.062500s CPU (136.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71386, tnet num: 17671, tinst num: 6772, tnode num: 93664, tedge num: 118630.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.825727s wall, 1.796875s user + 0.031250s system = 1.828125s CPU (100.1%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 607 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.777432s wall, 2.734375s user + 0.046875s system = 2.781250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.14251e-05
+PHY-3002 : Step(279): len = 622923, overlap = 233.75
+PHY-3002 : Step(280): len = 617539, overlap = 234.75
+PHY-3002 : Step(281): len = 614526, overlap = 239.75
+PHY-3002 : Step(282): len = 611639, overlap = 238.25
+PHY-3002 : Step(283): len = 609112, overlap = 238.25
+PHY-3002 : Step(284): len = 606985, overlap = 237.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00010285
+PHY-3002 : Step(285): len = 611035, overlap = 230.25
+PHY-3002 : Step(286): len = 615155, overlap = 221.75
+PHY-3002 : Step(287): len = 615043, overlap = 217.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.0002057
+PHY-3002 : Step(288): len = 625348, overlap = 200.75
+PHY-3002 : Step(289): len = 630634, overlap = 195
+PHY-3002 : Step(290): len = 628300, overlap = 192.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000411401
+PHY-3002 : Step(291): len = 634694, overlap = 183.25
+PHY-3002 : Step(292): len = 646086, overlap = 176.25
+PHY-3002 : Step(293): len = 646444, overlap = 179.5
+PHY-3002 : Step(294): len = 644248, overlap = 178.5
+PHY-3002 : Step(295): len = 642948, overlap = 175.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.473504s wall, 0.328125s user + 0.796875s system = 1.125000s CPU (237.6%)
+
+PHY-3001 : Trial Legalized: Len = 717638
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 848/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825480, over cnt = 2637(7%), over = 4413, worst = 7
+PHY-1002 : len = 843200, over cnt = 1569(4%), over = 2279, worst = 7
+PHY-1002 : len = 863096, over cnt = 550(1%), over = 733, worst = 6
+PHY-1002 : len = 868808, over cnt = 243(0%), over = 294, worst = 4
+PHY-1002 : len = 874376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.694086s wall, 4.015625s user + 0.062500s system = 4.078125s CPU (151.4%)
+
+PHY-1001 : Congestion index: top1 = 55.32, top5 = 49.94, top10 = 46.64, top15 = 44.49.
+PHY-3001 : End congestion estimation; 3.198451s wall, 4.515625s user + 0.062500s system = 4.578125s CPU (143.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.949547s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000179322
+PHY-3002 : Step(296): len = 690331, overlap = 32.25
+PHY-3002 : Step(297): len = 674555, overlap = 53.5
+PHY-3002 : Step(298): len = 659992, overlap = 83.25
+PHY-3002 : Step(299): len = 651072, overlap = 103.25
+PHY-3002 : Step(300): len = 645401, overlap = 115.75
+PHY-3002 : Step(301): len = 640736, overlap = 134.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000358644
+PHY-3002 : Step(302): len = 644922, overlap = 132.75
+PHY-3002 : Step(303): len = 649120, overlap = 131.25
+PHY-3002 : Step(304): len = 650071, overlap = 129.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000717289
+PHY-3002 : Step(305): len = 652245, overlap = 129.25
+PHY-3002 : Step(306): len = 656788, overlap = 128.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037798s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (124.0%)
+
+PHY-3001 : Legalized: Len = 684280, Over = 0
+PHY-3001 : Spreading special nets. 421 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.118642s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (92.2%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 185, deltaY = 351, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 693394, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71386, tnet num: 17671, tinst num: 6775, tnode num: 93664, tedge num: 118630.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.112671s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (99.8%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 644 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 5093/17849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 819992, over cnt = 2356(6%), over = 3728, worst = 6
+PHY-1002 : len = 832752, over cnt = 1445(4%), over = 1966, worst = 6
+PHY-1002 : len = 850752, over cnt = 373(1%), over = 510, worst = 6
+PHY-1002 : len = 856168, over cnt = 88(0%), over = 122, worst = 4
+PHY-1002 : len = 858608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.244439s wall, 3.203125s user + 0.062500s system = 3.265625s CPU (145.5%)
+
+PHY-1001 : Congestion index: top1 = 54.63, top5 = 48.53, top10 = 45.29, top15 = 43.20.
+PHY-1001 : End incremental global routing; 2.637039s wall, 3.609375s user + 0.062500s system = 3.671875s CPU (139.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.866588s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.2%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6681 has valid locations, 34 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 700311
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16201/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 867960, over cnt = 117(0%), over = 157, worst = 7
+PHY-1002 : len = 868192, over cnt = 64(0%), over = 74, worst = 4
+PHY-1002 : len = 868672, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 868840, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 868968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.812209s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (103.9%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 48.91, top10 = 45.66, top15 = 43.55.
+PHY-3001 : End congestion estimation; 1.128218s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (103.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71654, tnet num: 17696, tinst num: 6803, tnode num: 94007, tedge num: 118969.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.874092s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.0%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 654 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.764219s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(307): len = 698959, overlap = 0
+PHY-3002 : Step(308): len = 697986, overlap = 0
+PHY-3002 : Step(309): len = 697382, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16186/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 864264, over cnt = 71(0%), over = 104, worst = 5
+PHY-1002 : len = 864496, over cnt = 39(0%), over = 44, worst = 4
+PHY-1002 : len = 864880, over cnt = 16(0%), over = 17, worst = 2
+PHY-1002 : len = 865104, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 865136, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.807967s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (104.4%)
+
+PHY-1001 : Congestion index: top1 = 54.59, top5 = 48.62, top10 = 45.37, top15 = 43.33.
+PHY-3001 : End congestion estimation; 1.134432s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (103.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.931687s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00039289
+PHY-3002 : Step(310): len = 697361, overlap = 3
+PHY-3002 : Step(311): len = 697177, overlap = 2.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006163s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 697487, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068388s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.4%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 3, deltaY = 6, maxDist = 3.
+PHY-3001 : Final: Len = 697593, Over = 0
+PHY-3001 : End incremental placement; 6.477453s wall, 6.546875s user + 0.171875s system = 6.718750s CPU (103.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.478902s wall, 11.500000s user + 0.234375s system = 11.734375s CPU (112.0%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16155/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865032, over cnt = 78(0%), over = 109, worst = 6
+PHY-1002 : len = 865216, over cnt = 55(0%), over = 64, worst = 3
+PHY-1002 : len = 865608, over cnt = 23(0%), over = 24, worst = 2
+PHY-1002 : len = 865848, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 865952, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.878583s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (104.9%)
+
+PHY-1001 : Congestion index: top1 = 54.66, top5 = 48.63, top10 = 45.38, top15 = 43.30.
+OPT-1001 : End congestion update; 1.228536s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (103.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.785805s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (97.4%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 706436, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069302s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.2%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 6, deltaY = 29, maxDist = 3.
+PHY-3001 : Final: Len = 706504, Over = 0
+PHY-3001 : End incremental legalization; 0.441077s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 59 cells processed and 20640 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 706760, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066979s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 706874, Over = 0
+PHY-3001 : End incremental legalization; 0.429795s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.2%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 13 cells processed and 1493 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707436, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065775s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.0%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 707450, Over = 0
+PHY-3001 : End incremental legalization; 0.436082s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (93.2%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 700 slack improved
+OPT-1001 : End bottleneck based optimization; 3.783391s wall, 3.812500s user + 0.000000s system = 3.812500s CPU (100.8%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15895/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874888, over cnt = 153(0%), over = 189, worst = 3
+PHY-1002 : len = 875200, over cnt = 91(0%), over = 100, worst = 3
+PHY-1002 : len = 876000, over cnt = 26(0%), over = 31, worst = 2
+PHY-1002 : len = 876456, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 876536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.883449s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.63, top10 = 45.39, top15 = 43.32.
+OPT-1001 : End congestion update; 1.231233s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (104.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.919281s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (85.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707718, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065322s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.436036s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (118.3%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 2050 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.734986s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.783640s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16188/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876608, over cnt = 30(0%), over = 34, worst = 3
+PHY-1002 : len = 876664, over cnt = 20(0%), over = 21, worst = 2
+PHY-1002 : len = 876792, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.842519s wall, 0.703125s user + 0.015625s system = 0.718750s CPU (85.3%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.817012s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (97.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.655172
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707622, Over = 0
+PHY-3001 : End spreading; 0.059026s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.9%)
+
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.400977s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.723444s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.4%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16225/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.129749s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.3%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+OPT-1001 : End congestion update; 0.444208s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.722713s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707628, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059266s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.1%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.392664s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (123.4%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.672718s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (112.1%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16225/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.131844s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+OPT-1001 : End congestion update; 0.443126s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.723788s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.3%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707628, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059492s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.1%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.405707s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6718 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6806 instances, 6657 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 707628, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065121s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (72.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 707622, Over = 0
+PHY-3001 : End incremental legalization; 0.424636s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (114.1%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.305029s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (101.7%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.802233s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 735.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.791805s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.6%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16225/17874.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.141134s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.6%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.61, top10 = 45.38, top15 = 43.29.
+RUN-1001 : End congestion update; 0.484757s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.9%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.279662s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 735.
+OPT-1001 : End physical optimization; 29.509071s wall, 30.687500s user + 0.312500s system = 31.000000s CPU (105.1%)
+
+RUN-1003 : finish command "place" in 76.347104s wall, 107.953125s user + 6.859375s system = 114.812500s CPU (150.4%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 642 MB, peak memory is 735 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.862347s wall, 3.156250s user + 0.015625s system = 3.171875s CPU (170.3%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 642 MB, peak memory is 735 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6808 instances
+RUN-1001 : 3330 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17874 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9957 nets have 2 pins
+RUN-1001 : 6510 nets have [3 - 5] pins
+RUN-1001 : 748 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 299 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71680, tnet num: 17696, tinst num: 6806, tnode num: 94044, tedge num: 119007.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.788793s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (99.6%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 612 MB, peak memory is 735 MB
+PHY-1001 : 3330 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 805976, over cnt = 2641(7%), over = 4426, worst = 9
+PHY-1002 : len = 824760, over cnt = 1662(4%), over = 2375, worst = 9
+PHY-1002 : len = 842896, over cnt = 694(1%), over = 1010, worst = 9
+PHY-1002 : len = 858520, over cnt = 11(0%), over = 25, worst = 6
+PHY-1002 : len = 858984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.063134s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (133.6%)
+
+PHY-1001 : Congestion index: top1 = 53.64, top5 = 48.13, top10 = 45.03, top15 = 42.95.
+PHY-1001 : End global routing; 3.423363s wall, 4.437500s user + 0.015625s system = 4.453125s CPU (130.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 703, reserve = 706, peak = 735.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 978, reserve = 982, peak = 978.
+PHY-1001 : End build detailed router design. 4.469034s wall, 4.406250s user + 0.062500s system = 4.468750s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267320, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.886058s wall, 5.859375s user + 0.000000s system = 5.859375s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267376, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.529689s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1014, reserve = 1019, peak = 1014.
+PHY-1001 : End phase 1; 6.428766s wall, 6.406250s user + 0.000000s system = 6.406250s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.198e+06, over cnt = 1678(0%), over = 1691, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1034, peak = 1031.
+PHY-1001 : End initial routed; 26.682450s wall, 62.687500s user + 0.406250s system = 63.093750s CPU (236.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16794(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.784 | -0.784 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.301345s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1041, reserve = 1042, peak = 1041.
+PHY-1001 : End phase 2; 29.983861s wall, 65.984375s user + 0.406250s system = 66.390625s CPU (221.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.133055s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.9%)
+
+PHY-1022 : len = 2.198e+06, over cnt = 1678(0%), over = 1691, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.402317s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.17426e+06, over cnt = 620(0%), over = 621, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.105934s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (192.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.17319e+06, over cnt = 138(0%), over = 138, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.730004s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (134.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.17389e+06, over cnt = 25(0%), over = 25, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.325226s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (129.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.17394e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.206855s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.17423e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.274094s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (102.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.17427e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.251116s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.17427e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.312749s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.17428e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.167547s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.17433e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.164291s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (104.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16794(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.299195s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 509 feed throughs used by 367 nets
+PHY-1001 : End commit to database; 2.255621s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1137, reserve = 1143, peak = 1137.
+PHY-1001 : End phase 3; 9.917309s wall, 11.265625s user + 0.000000s system = 11.265625s CPU (113.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.136016s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.9%)
+
+PHY-1022 : len = 2.17433e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.382732s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16794(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.486830s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 509 feed throughs used by 367 nets
+PHY-1001 : End commit to database; 2.475417s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1152, peak = 1146.
+PHY-1001 : End phase 4; 6.370924s wall, 6.375000s user + 0.000000s system = 6.375000s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.17433e+06
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1154, peak = 1147.
+PHY-1001 : End export database. 0.067616s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.4%)
+
+PHY-1001 : End detail routing; 57.668295s wall, 94.937500s user + 0.468750s system = 95.406250s CPU (165.4%)
+
+RUN-1003 : finish command "route" in 64.080893s wall, 102.328125s user + 0.531250s system = 102.859375s CPU (160.5%)
+
+RUN-1004 : used memory is 1077 MB, reserved memory is 1078 MB, peak memory is 1147 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10205 out of 19600 52.07%
+#reg 9423 out of 19600 48.08%
+#le 12468
+ #lut only 3045 out of 12468 24.42%
+ #reg only 2263 out of 12468 18.15%
+ #lut® 7160 out of 12468 57.43%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1804
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1379
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1275
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 957
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 132
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 73
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg0_syn_149.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg47_syn_243.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P118 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P110 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P143 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12468 |9178 |1027 |9457 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |547 |448 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |96 |81 |4 |85 |4 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |40 |40 |0 |22 |0 |0 |
+| exdev_ctl_a |exdev_ctl |769 |389 |96 |580 |0 |0 |
+| u_ADconfig |AD_config |189 |126 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |263 |170 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |742 |329 |96 |563 |0 |0 |
+| u_ADconfig |AD_config |172 |108 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |258 |157 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |3039 |2431 |306 |2071 |25 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |177 |103 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_sort |sort |2830 |2325 |289 |1891 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2385 |2019 |253 |1536 |22 |0 |
+| channelPart |channel_part_8478 |133 |119 |3 |127 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1884 |1594 |197 |1157 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |124 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| insert |insert |966 |703 |170 |655 |0 |0 |
+| ram_switch_state |ram_switch_state |697 |697 |0 |378 |0 |0 |
+| read_ram_i |read_ram |283 |238 |44 |184 |0 |0 |
+| read_ram_addr |read_ram_addr |236 |196 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |45 |40 |4 |31 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |304 |195 |36 |258 |3 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3227 |2539 |349 |2078 |25 |1 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |177 |96 |17 |148 |0 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_sort |sort_rev |3020 |2426 |332 |1900 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2576 |2084 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |129 |113 |3 |125 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1997 |1653 |197 |1136 |0 |0 |
+| adc_addr_gen |adc_addr_gen |199 |172 |27 |92 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |2 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |992 |675 |170 |688 |0 |0 |
+| ram_switch_state |ram_switch_state |806 |806 |0 |356 |0 |0 |
+| read_ram_i |read_ram_rev |362 |247 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |303 |218 |73 |168 |0 |0 |
+| read_ram_data |read_ram_data_rev |59 |29 |8 |44 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9895
+ #2 2 4221
+ #3 3 1705
+ #4 4 581
+ #5 5-10 784
+ #6 11-50 579
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.206274s wall, 3.812500s user + 0.015625s system = 3.828125s CPU (173.5%)
+
+RUN-1004 : used memory is 1078 MB, reserved memory is 1079 MB, peak memory is 1147 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71680, tnet num: 17696, tinst num: 6806, tnode num: 94044, tedge num: 119007.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.753758s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (99.8%)
+
+RUN-1004 : used memory is 1083 MB, reserved memory is 1084 MB, peak memory is 1147 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.614687s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.6%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1086 MB, peak memory is 1147 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6806
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17874, pip num: 165901
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 509
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 465041 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.260125s wall, 66.578125s user + 0.390625s system = 66.968750s CPU (652.7%)
+
+RUN-1004 : used memory is 1235 MB, reserved memory is 1236 MB, peak memory is 1350 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_144655.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_150021.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_150021.log
new file mode 100644
index 0000000..8756148
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_150021.log
@@ -0,0 +1,1995 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 15:00:21 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.351553s wall, 2.187500s user + 0.156250s system = 2.343750s CPU (99.7%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 315 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17999 instances
+RUN-0007 : 7674 luts, 9102 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20577 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13091 nets have 2 pins
+RUN-1001 : 6451 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17997 instances, 7674 luts, 9102 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5957 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.254338s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (100.9%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 514 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.118928s wall, 2.093750s user + 0.031250s system = 2.125000s CPU (100.3%)
+
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.97121e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17997.
+PHY-3001 : Level 1 #clusters 2088.
+PHY-3001 : End clustering; 0.157206s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (129.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31482e+06, overlap = 442.125
+PHY-3002 : Step(2): len = 1.22899e+06, overlap = 487.75
+PHY-3002 : Step(3): len = 877442, overlap = 563.5
+PHY-3002 : Step(4): len = 801289, overlap = 594.094
+PHY-3002 : Step(5): len = 643593, overlap = 744.188
+PHY-3002 : Step(6): len = 571466, overlap = 799.562
+PHY-3002 : Step(7): len = 487557, overlap = 867.25
+PHY-3002 : Step(8): len = 441949, overlap = 922.188
+PHY-3002 : Step(9): len = 403126, overlap = 985.781
+PHY-3002 : Step(10): len = 365940, overlap = 1048.38
+PHY-3002 : Step(11): len = 326618, overlap = 1111.94
+PHY-3002 : Step(12): len = 298627, overlap = 1133.25
+PHY-3002 : Step(13): len = 276167, overlap = 1203.5
+PHY-3002 : Step(14): len = 244447, overlap = 1274.78
+PHY-3002 : Step(15): len = 231999, overlap = 1339.09
+PHY-3002 : Step(16): len = 209427, overlap = 1358.12
+PHY-3002 : Step(17): len = 194807, overlap = 1344.31
+PHY-3002 : Step(18): len = 171058, overlap = 1396.69
+PHY-3002 : Step(19): len = 160579, overlap = 1414.75
+PHY-3002 : Step(20): len = 149083, overlap = 1445.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.24902e-06
+PHY-3002 : Step(21): len = 150445, overlap = 1412.44
+PHY-3002 : Step(22): len = 185898, overlap = 1262.78
+PHY-3002 : Step(23): len = 197759, overlap = 1218.62
+PHY-3002 : Step(24): len = 204132, overlap = 1151.09
+PHY-3002 : Step(25): len = 202527, overlap = 1110.5
+PHY-3002 : Step(26): len = 201904, overlap = 1091.72
+PHY-3002 : Step(27): len = 199160, overlap = 1089.28
+PHY-3002 : Step(28): len = 196040, overlap = 1086.28
+PHY-3002 : Step(29): len = 195219, overlap = 1083.72
+PHY-3002 : Step(30): len = 194405, overlap = 1067.31
+PHY-3002 : Step(31): len = 193251, overlap = 1053.19
+PHY-3002 : Step(32): len = 191212, overlap = 1036.78
+PHY-3002 : Step(33): len = 190542, overlap = 1032.38
+PHY-3002 : Step(34): len = 188674, overlap = 1039.62
+PHY-3002 : Step(35): len = 186799, overlap = 1053.97
+PHY-3002 : Step(36): len = 185187, overlap = 1058.19
+PHY-3002 : Step(37): len = 182828, overlap = 1041.06
+PHY-3002 : Step(38): len = 182581, overlap = 1042.16
+PHY-3002 : Step(39): len = 181592, overlap = 1032.88
+PHY-3002 : Step(40): len = 181024, overlap = 1039.5
+PHY-3002 : Step(41): len = 179468, overlap = 1036.16
+PHY-3002 : Step(42): len = 178402, overlap = 1037.28
+PHY-3002 : Step(43): len = 177137, overlap = 1045
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.49804e-06
+PHY-3002 : Step(44): len = 181367, overlap = 1036.12
+PHY-3002 : Step(45): len = 192904, overlap = 1044.75
+PHY-3002 : Step(46): len = 196497, overlap = 1012.78
+PHY-3002 : Step(47): len = 200859, overlap = 1000.84
+PHY-3002 : Step(48): len = 203251, overlap = 939.531
+PHY-3002 : Step(49): len = 205334, overlap = 910.094
+PHY-3002 : Step(50): len = 204884, overlap = 903.562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.99609e-06
+PHY-3002 : Step(51): len = 213263, overlap = 861.562
+PHY-3002 : Step(52): len = 228954, overlap = 807.688
+PHY-3002 : Step(53): len = 238486, overlap = 770.875
+PHY-3002 : Step(54): len = 246463, overlap = 763.688
+PHY-3002 : Step(55): len = 249433, overlap = 755.625
+PHY-3002 : Step(56): len = 251699, overlap = 757.75
+PHY-3002 : Step(57): len = 249892, overlap = 753.781
+PHY-3002 : Step(58): len = 250506, overlap = 761.875
+PHY-3002 : Step(59): len = 249667, overlap = 747.125
+PHY-3002 : Step(60): len = 248533, overlap = 743.781
+PHY-3002 : Step(61): len = 247500, overlap = 743.656
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.99217e-06
+PHY-3002 : Step(62): len = 262401, overlap = 700.125
+PHY-3002 : Step(63): len = 276907, overlap = 626.125
+PHY-3002 : Step(64): len = 282073, overlap = 595.25
+PHY-3002 : Step(65): len = 286336, overlap = 590.688
+PHY-3002 : Step(66): len = 287680, overlap = 589.844
+PHY-3002 : Step(67): len = 288593, overlap = 569.406
+PHY-3002 : Step(68): len = 287280, overlap = 584.812
+PHY-3002 : Step(69): len = 288285, overlap = 563.188
+PHY-3002 : Step(70): len = 288513, overlap = 566.469
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.99843e-05
+PHY-3002 : Step(71): len = 303595, overlap = 493.781
+PHY-3002 : Step(72): len = 317353, overlap = 472.062
+PHY-3002 : Step(73): len = 323219, overlap = 463.5
+PHY-3002 : Step(74): len = 328732, overlap = 429.625
+PHY-3002 : Step(75): len = 330479, overlap = 375.875
+PHY-3002 : Step(76): len = 333540, overlap = 370.688
+PHY-3002 : Step(77): len = 336474, overlap = 361.844
+PHY-3002 : Step(78): len = 338100, overlap = 365.812
+PHY-3002 : Step(79): len = 337706, overlap = 381.094
+PHY-3002 : Step(80): len = 337809, overlap = 393.812
+PHY-3002 : Step(81): len = 336881, overlap = 385.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.99687e-05
+PHY-3002 : Step(82): len = 352080, overlap = 394.969
+PHY-3002 : Step(83): len = 365108, overlap = 391.531
+PHY-3002 : Step(84): len = 367421, overlap = 362.344
+PHY-3002 : Step(85): len = 368559, overlap = 340.562
+PHY-3002 : Step(86): len = 370693, overlap = 330.125
+PHY-3002 : Step(87): len = 373419, overlap = 317.594
+PHY-3002 : Step(88): len = 373946, overlap = 310.5
+PHY-3002 : Step(89): len = 376010, overlap = 298.969
+PHY-3002 : Step(90): len = 379843, overlap = 298.688
+PHY-3002 : Step(91): len = 382828, overlap = 298.969
+PHY-3002 : Step(92): len = 380626, overlap = 277.781
+PHY-3002 : Step(93): len = 381229, overlap = 271.594
+PHY-3002 : Step(94): len = 382691, overlap = 269.969
+PHY-3002 : Step(95): len = 381718, overlap = 265.719
+PHY-3002 : Step(96): len = 379948, overlap = 272.625
+PHY-3002 : Step(97): len = 380777, overlap = 280.469
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.99374e-05
+PHY-3002 : Step(98): len = 395240, overlap = 269.219
+PHY-3002 : Step(99): len = 406724, overlap = 248.375
+PHY-3002 : Step(100): len = 404855, overlap = 240.062
+PHY-3002 : Step(101): len = 406641, overlap = 240.719
+PHY-3002 : Step(102): len = 411999, overlap = 235.719
+PHY-3002 : Step(103): len = 414805, overlap = 241.594
+PHY-3002 : Step(104): len = 410284, overlap = 230.375
+PHY-3002 : Step(105): len = 409999, overlap = 226.906
+PHY-3002 : Step(106): len = 411548, overlap = 232.656
+PHY-3002 : Step(107): len = 413336, overlap = 233.375
+PHY-3002 : Step(108): len = 409116, overlap = 226.5
+PHY-3002 : Step(109): len = 409127, overlap = 230.875
+PHY-3002 : Step(110): len = 410415, overlap = 231.156
+PHY-3002 : Step(111): len = 411513, overlap = 230.625
+PHY-3002 : Step(112): len = 408239, overlap = 223.094
+PHY-3002 : Step(113): len = 407833, overlap = 223.125
+PHY-3002 : Step(114): len = 409174, overlap = 217.906
+PHY-3002 : Step(115): len = 411227, overlap = 228.531
+PHY-3002 : Step(116): len = 408999, overlap = 213.5
+PHY-3002 : Step(117): len = 409449, overlap = 219.875
+PHY-3002 : Step(118): len = 410169, overlap = 215.5
+PHY-3002 : Step(119): len = 410805, overlap = 214.875
+PHY-3002 : Step(120): len = 408854, overlap = 215.875
+PHY-3002 : Step(121): len = 409142, overlap = 220.906
+PHY-3002 : Step(122): len = 410507, overlap = 219.531
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000159875
+PHY-3002 : Step(123): len = 422471, overlap = 214.219
+PHY-3002 : Step(124): len = 430979, overlap = 210.375
+PHY-3002 : Step(125): len = 429083, overlap = 203.688
+PHY-3002 : Step(126): len = 429864, overlap = 209.094
+PHY-3002 : Step(127): len = 435322, overlap = 196.594
+PHY-3002 : Step(128): len = 439233, overlap = 196.219
+PHY-3002 : Step(129): len = 436326, overlap = 190.75
+PHY-3002 : Step(130): len = 437063, overlap = 192.219
+PHY-3002 : Step(131): len = 439077, overlap = 191.781
+PHY-3002 : Step(132): len = 440717, overlap = 200.656
+PHY-3002 : Step(133): len = 439312, overlap = 191.438
+PHY-3002 : Step(134): len = 439448, overlap = 190.969
+PHY-3002 : Step(135): len = 440847, overlap = 195.438
+PHY-3002 : Step(136): len = 441876, overlap = 194.25
+PHY-3002 : Step(137): len = 440199, overlap = 198.906
+PHY-3002 : Step(138): len = 440008, overlap = 198.156
+PHY-3002 : Step(139): len = 440753, overlap = 195.312
+PHY-3002 : Step(140): len = 441023, overlap = 196.5
+PHY-3002 : Step(141): len = 440351, overlap = 192.375
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000305382
+PHY-3002 : Step(142): len = 449315, overlap = 197.531
+PHY-3002 : Step(143): len = 457366, overlap = 182.719
+PHY-3002 : Step(144): len = 457809, overlap = 176.406
+PHY-3002 : Step(145): len = 458754, overlap = 169.188
+PHY-3002 : Step(146): len = 462014, overlap = 164.438
+PHY-3002 : Step(147): len = 464354, overlap = 159.375
+PHY-3002 : Step(148): len = 462604, overlap = 153.406
+PHY-3002 : Step(149): len = 462283, overlap = 159.031
+PHY-3002 : Step(150): len = 465311, overlap = 154.625
+PHY-3002 : Step(151): len = 468198, overlap = 156.531
+PHY-3002 : Step(152): len = 465817, overlap = 158.094
+PHY-3002 : Step(153): len = 465593, overlap = 161.281
+PHY-3002 : Step(154): len = 468457, overlap = 168.719
+PHY-3002 : Step(155): len = 470336, overlap = 168.094
+PHY-3002 : Step(156): len = 468420, overlap = 167.719
+PHY-3002 : Step(157): len = 468050, overlap = 168.719
+PHY-3002 : Step(158): len = 469452, overlap = 164
+PHY-3002 : Step(159): len = 470189, overlap = 167.719
+PHY-3002 : Step(160): len = 469102, overlap = 174.219
+PHY-3002 : Step(161): len = 469244, overlap = 178.719
+PHY-3002 : Step(162): len = 470940, overlap = 175.594
+PHY-3002 : Step(163): len = 471904, overlap = 176.812
+PHY-3002 : Step(164): len = 469847, overlap = 179.938
+PHY-3002 : Step(165): len = 469559, overlap = 178
+PHY-3002 : Step(166): len = 471194, overlap = 180.062
+PHY-3002 : Step(167): len = 472425, overlap = 183.031
+PHY-3002 : Step(168): len = 470887, overlap = 183.531
+PHY-3002 : Step(169): len = 470751, overlap = 183.625
+PHY-3002 : Step(170): len = 471647, overlap = 189.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000577667
+PHY-3002 : Step(171): len = 478244, overlap = 179.031
+PHY-3002 : Step(172): len = 486798, overlap = 168.5
+PHY-3002 : Step(173): len = 490380, overlap = 163.594
+PHY-3002 : Step(174): len = 493506, overlap = 161.75
+PHY-3002 : Step(175): len = 497416, overlap = 161.156
+PHY-3002 : Step(176): len = 499972, overlap = 161.844
+PHY-3002 : Step(177): len = 497979, overlap = 155.375
+PHY-3002 : Step(178): len = 497497, overlap = 149.844
+PHY-3002 : Step(179): len = 498991, overlap = 157.469
+PHY-3002 : Step(180): len = 499697, overlap = 160.938
+PHY-3002 : Step(181): len = 498383, overlap = 160.312
+PHY-3002 : Step(182): len = 498043, overlap = 161.656
+PHY-3002 : Step(183): len = 499066, overlap = 167.625
+PHY-3002 : Step(184): len = 499688, overlap = 168.281
+PHY-3002 : Step(185): len = 498730, overlap = 165.031
+PHY-3002 : Step(186): len = 498595, overlap = 159.719
+PHY-3002 : Step(187): len = 500150, overlap = 163.125
+PHY-3002 : Step(188): len = 501097, overlap = 167.281
+PHY-3002 : Step(189): len = 500562, overlap = 157.219
+PHY-3002 : Step(190): len = 500595, overlap = 155.188
+PHY-3002 : Step(191): len = 501482, overlap = 166.719
+PHY-3002 : Step(192): len = 501807, overlap = 167.312
+PHY-3002 : Step(193): len = 501249, overlap = 162.062
+PHY-3002 : Step(194): len = 501264, overlap = 158.719
+PHY-3002 : Step(195): len = 501954, overlap = 161.469
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00107028
+PHY-3002 : Step(196): len = 505721, overlap = 159.406
+PHY-3002 : Step(197): len = 511338, overlap = 150.469
+PHY-3002 : Step(198): len = 512611, overlap = 145.219
+PHY-3002 : Step(199): len = 513528, overlap = 148.594
+PHY-3002 : Step(200): len = 515100, overlap = 140.438
+PHY-3002 : Step(201): len = 515955, overlap = 138.375
+PHY-3002 : Step(202): len = 515774, overlap = 136.938
+PHY-3002 : Step(203): len = 515829, overlap = 138.25
+PHY-3002 : Step(204): len = 516843, overlap = 133.812
+PHY-3002 : Step(205): len = 517548, overlap = 138
+PHY-3002 : Step(206): len = 517250, overlap = 143.438
+PHY-3002 : Step(207): len = 517168, overlap = 143.438
+PHY-3002 : Step(208): len = 517392, overlap = 137.031
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015236s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (102.6%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 689056, over cnt = 1533(4%), over = 7153, worst = 41
+PHY-1001 : End global iterations; 0.747945s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (146.2%)
+
+PHY-1001 : Congestion index: top1 = 82.74, top5 = 61.17, top10 = 51.75, top15 = 46.08.
+PHY-3001 : End congestion estimation; 0.996455s wall, 1.265625s user + 0.062500s system = 1.328125s CPU (133.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.925974s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (101.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000125154
+PHY-3002 : Step(209): len = 623885, overlap = 82.4062
+PHY-3002 : Step(210): len = 623553, overlap = 75.5312
+PHY-3002 : Step(211): len = 616349, overlap = 71.1562
+PHY-3002 : Step(212): len = 611700, overlap = 70.5938
+PHY-3002 : Step(213): len = 611422, overlap = 66.375
+PHY-3002 : Step(214): len = 612892, overlap = 61.2812
+PHY-3002 : Step(215): len = 608600, overlap = 53.5312
+PHY-3002 : Step(216): len = 605273, overlap = 47.8438
+PHY-3002 : Step(217): len = 603735, overlap = 46.4688
+PHY-3002 : Step(218): len = 601618, overlap = 47.125
+PHY-3002 : Step(219): len = 598637, overlap = 44.0625
+PHY-3002 : Step(220): len = 596702, overlap = 40
+PHY-3002 : Step(221): len = 595990, overlap = 36.5
+PHY-3002 : Step(222): len = 596392, overlap = 40.8438
+PHY-3002 : Step(223): len = 597475, overlap = 40.1875
+PHY-3002 : Step(224): len = 597067, overlap = 42.8438
+PHY-3002 : Step(225): len = 596122, overlap = 49.625
+PHY-3002 : Step(226): len = 596198, overlap = 55
+PHY-3002 : Step(227): len = 594956, overlap = 58.5938
+PHY-3002 : Step(228): len = 593514, overlap = 60.4688
+PHY-3002 : Step(229): len = 592558, overlap = 58.1875
+PHY-3002 : Step(230): len = 592532, overlap = 57.75
+PHY-3002 : Step(231): len = 591392, overlap = 60.3125
+PHY-3002 : Step(232): len = 589952, overlap = 59.6562
+PHY-3002 : Step(233): len = 588119, overlap = 59.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000250307
+PHY-3002 : Step(234): len = 592144, overlap = 56.4062
+PHY-3002 : Step(235): len = 594802, overlap = 56.1562
+PHY-3002 : Step(236): len = 596959, overlap = 55.9375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000455054
+PHY-3002 : Step(237): len = 601387, overlap = 56.2812
+PHY-3002 : Step(238): len = 614744, overlap = 50.125
+PHY-3002 : Step(239): len = 620060, overlap = 47.375
+PHY-3002 : Step(240): len = 622850, overlap = 45.9375
+PHY-3002 : Step(241): len = 626338, overlap = 42.8125
+PHY-3002 : Step(242): len = 627959, overlap = 38.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 56/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708152, over cnt = 2683(7%), over = 12234, worst = 42
+PHY-1001 : End global iterations; 1.748204s wall, 2.531250s user + 0.015625s system = 2.546875s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 86.06, top5 = 66.82, top10 = 58.27, top15 = 53.06.
+PHY-3001 : End congestion estimation; 2.033325s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (139.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.951266s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000110034
+PHY-3002 : Step(243): len = 621923, overlap = 248.969
+PHY-3002 : Step(244): len = 621790, overlap = 189.781
+PHY-3002 : Step(245): len = 616790, overlap = 176.312
+PHY-3002 : Step(246): len = 612321, overlap = 165.875
+PHY-3002 : Step(247): len = 608613, overlap = 149.688
+PHY-3002 : Step(248): len = 605249, overlap = 138.281
+PHY-3002 : Step(249): len = 602192, overlap = 131.062
+PHY-3002 : Step(250): len = 598107, overlap = 123.875
+PHY-3002 : Step(251): len = 595706, overlap = 114.562
+PHY-3002 : Step(252): len = 594317, overlap = 113.844
+PHY-3002 : Step(253): len = 590625, overlap = 115.438
+PHY-3002 : Step(254): len = 587535, overlap = 113.062
+PHY-3002 : Step(255): len = 585219, overlap = 111.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000220068
+PHY-3002 : Step(256): len = 586358, overlap = 107.469
+PHY-3002 : Step(257): len = 589166, overlap = 105.844
+PHY-3002 : Step(258): len = 590697, overlap = 100.812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000440135
+PHY-3002 : Step(259): len = 594602, overlap = 96.6562
+PHY-3002 : Step(260): len = 600766, overlap = 89.6875
+PHY-3002 : Step(261): len = 602173, overlap = 87.8125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000813956
+PHY-3002 : Step(262): len = 606192, overlap = 86.5625
+PHY-3002 : Step(263): len = 614466, overlap = 79.6875
+PHY-3002 : Step(264): len = 618714, overlap = 71.625
+PHY-3002 : Step(265): len = 621192, overlap = 65.625
+PHY-3002 : Step(266): len = 622669, overlap = 63.5938
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84038, tnet num: 20399, tinst num: 17997, tnode num: 114305, tedge num: 134008.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.590253s wall, 1.531250s user + 0.046875s system = 1.578125s CPU (99.2%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 562 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 388.03 peak overflow 2.88
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 901/20577.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719056, over cnt = 3061(8%), over = 10955, worst = 21
+PHY-1001 : End global iterations; 1.401684s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (142.7%)
+
+PHY-1001 : Congestion index: top1 = 68.08, top5 = 56.30, top10 = 50.55, top15 = 47.06.
+PHY-1001 : End incremental global routing; 1.763545s wall, 2.328125s user + 0.015625s system = 2.343750s CPU (132.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20399 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.980250s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.4%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17865 has valid locations, 314 needs to be replaced
+PHY-3001 : design contains 18264 instances, 7784 luts, 9259 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6074 pins
+PHY-3001 : Found 1268 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 645931
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17257/20844.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733640, over cnt = 3108(8%), over = 11070, worst = 21
+PHY-1001 : End global iterations; 0.268127s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 68.49, top5 = 56.56, top10 = 50.85, top15 = 47.41.
+PHY-3001 : End congestion estimation; 0.560221s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (122.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85096, tnet num: 20666, tinst num: 18264, tnode num: 115859, tedge num: 135590.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.602732s wall, 1.546875s user + 0.046875s system = 1.593750s CPU (99.4%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 610 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20666 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.628359s wall, 2.546875s user + 0.078125s system = 2.625000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(267): len = 644902, overlap = 0.25
+PHY-3002 : Step(268): len = 644623, overlap = 0.1875
+PHY-3002 : Step(269): len = 644432, overlap = 0.125
+PHY-3002 : Step(270): len = 644142, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17323/20844.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730360, over cnt = 3098(8%), over = 11127, worst = 21
+PHY-1001 : End global iterations; 0.219602s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (135.2%)
+
+PHY-1001 : Congestion index: top1 = 69.25, top5 = 57.23, top10 = 51.39, top15 = 47.72.
+PHY-3001 : End congestion estimation; 0.496161s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (116.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20666 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.000517s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000450219
+PHY-3002 : Step(271): len = 643686, overlap = 66.6562
+PHY-3002 : Step(272): len = 643615, overlap = 66.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000900438
+PHY-3002 : Step(273): len = 644008, overlap = 66.2812
+PHY-3002 : Step(274): len = 644465, overlap = 65.5625
+PHY-3001 : Final: Len = 644465, Over = 65.5625
+PHY-3001 : End incremental placement; 5.484324s wall, 5.625000s user + 0.328125s system = 5.953125s CPU (108.5%)
+
+OPT-1001 : Total overflow 393.44 peak overflow 2.88
+OPT-1001 : End high-fanout net optimization; 8.974461s wall, 9.687500s user + 0.343750s system = 10.031250s CPU (111.8%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 709, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17310/20844.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733696, over cnt = 3060(8%), over = 10100, worst = 21
+PHY-1002 : len = 789096, over cnt = 2062(5%), over = 4791, worst = 19
+PHY-1002 : len = 822096, over cnt = 980(2%), over = 2173, worst = 19
+PHY-1002 : len = 844384, over cnt = 331(0%), over = 680, worst = 19
+PHY-1002 : len = 855856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.108643s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (141.5%)
+
+PHY-1001 : Congestion index: top1 = 55.65, top5 = 49.35, top10 = 45.95, top15 = 43.82.
+OPT-1001 : End congestion update; 2.388938s wall, 3.250000s user + 0.015625s system = 3.265625s CPU (136.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20666 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.862688s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.6%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 139 cells processed and 18000 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 19 cells processed and 2500 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 9 cells processed and 800 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved
+OPT-1001 : End bottleneck based optimization; 3.691370s wall, 4.546875s user + 0.015625s system = 4.562500s CPU (123.6%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 693, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17330/20849.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856464, over cnt = 89(0%), over = 124, worst = 3
+PHY-1002 : len = 856408, over cnt = 36(0%), over = 44, worst = 3
+PHY-1002 : len = 856664, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 856744, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 856920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.787604s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (101.2%)
+
+PHY-1001 : Congestion index: top1 = 55.69, top5 = 49.32, top10 = 46.04, top15 = 43.84.
+OPT-1001 : End congestion update; 1.090157s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (101.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.888317s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.3%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 6250 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.109937s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (100.7%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 697, peak = 733.
+OPT-1001 : End physical optimization; 16.694038s wall, 18.312500s user + 0.421875s system = 18.734375s CPU (112.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7784 LUT to BLE ...
+SYN-4008 : Packed 7784 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6129 remaining SEQ's ...
+SYN-4005 : Packed 3958 SEQ with LUT/SLICE
+SYN-4006 : 989 single LUT's are left
+SYN-4006 : 2171 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9955/13810 primitive instances ...
+PHY-3001 : End packing; 1.806987s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6736 instances
+RUN-1001 : 3294 mslices, 3294 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17843 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9976 nets have 2 pins
+RUN-1001 : 6511 nets have [3 - 5] pins
+RUN-1001 : 733 nets have [6 - 10] pins
+RUN-1001 : 307 nets have [11 - 20] pins
+RUN-1001 : 285 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6734 instances, 6588 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3494 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 653777, Over = 208
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7620/17843.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 804008, over cnt = 1906(5%), over = 3111, worst = 8
+PHY-1002 : len = 810480, over cnt = 1215(3%), over = 1735, worst = 8
+PHY-1002 : len = 823816, over cnt = 495(1%), over = 656, worst = 5
+PHY-1002 : len = 831992, over cnt = 130(0%), over = 171, worst = 5
+PHY-1002 : len = 834536, over cnt = 13(0%), over = 22, worst = 4
+PHY-1001 : End global iterations; 1.746963s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (138.6%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 49.40, top10 = 45.75, top15 = 43.44.
+PHY-3001 : End congestion estimation; 2.177025s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (130.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71379, tnet num: 17665, tinst num: 6734, tnode num: 93621, tedge num: 118596.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.743282s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.4%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 610 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17665 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.677550s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.08833e-05
+PHY-3002 : Step(275): len = 641670, overlap = 200
+PHY-3002 : Step(276): len = 634720, overlap = 204.25
+PHY-3002 : Step(277): len = 630144, overlap = 213
+PHY-3002 : Step(278): len = 626841, overlap = 226.25
+PHY-3002 : Step(279): len = 624144, overlap = 232
+PHY-3002 : Step(280): len = 621661, overlap = 234.75
+PHY-3002 : Step(281): len = 619598, overlap = 231.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000121767
+PHY-3002 : Step(282): len = 621181, overlap = 224
+PHY-3002 : Step(283): len = 624866, overlap = 218.75
+PHY-3002 : Step(284): len = 627686, overlap = 211.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000243533
+PHY-3002 : Step(285): len = 632892, overlap = 208.75
+PHY-3002 : Step(286): len = 638372, overlap = 199.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000487066
+PHY-3002 : Step(287): len = 643371, overlap = 191.5
+PHY-3002 : Step(288): len = 654948, overlap = 178.25
+PHY-3002 : Step(289): len = 655325, overlap = 178.5
+PHY-3002 : Step(290): len = 654365, overlap = 173.25
+PHY-3002 : Step(291): len = 654550, overlap = 170.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.408329s wall, 0.390625s user + 0.734375s system = 1.125000s CPU (275.5%)
+
+PHY-3001 : Trial Legalized: Len = 726596
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 952/17843.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840408, over cnt = 2590(7%), over = 4250, worst = 8
+PHY-1002 : len = 856000, over cnt = 1568(4%), over = 2202, worst = 6
+PHY-1002 : len = 877128, over cnt = 459(1%), over = 608, worst = 5
+PHY-1002 : len = 887312, over cnt = 39(0%), over = 40, worst = 2
+PHY-1002 : len = 888384, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.573199s wall, 3.828125s user + 0.015625s system = 3.843750s CPU (149.4%)
+
+PHY-1001 : Congestion index: top1 = 53.53, top5 = 48.44, top10 = 45.85, top15 = 44.02.
+PHY-3001 : End congestion estimation; 3.078621s wall, 4.343750s user + 0.015625s system = 4.359375s CPU (141.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17665 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.912222s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000173011
+PHY-3002 : Step(292): len = 700958, overlap = 35
+PHY-3002 : Step(293): len = 685818, overlap = 58
+PHY-3002 : Step(294): len = 672151, overlap = 84
+PHY-3002 : Step(295): len = 663514, overlap = 109.25
+PHY-3002 : Step(296): len = 655572, overlap = 140.75
+PHY-3002 : Step(297): len = 652121, overlap = 153
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000346022
+PHY-3002 : Step(298): len = 655572, overlap = 145.75
+PHY-3002 : Step(299): len = 658506, overlap = 143.5
+PHY-3002 : Step(300): len = 660652, overlap = 142.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000692044
+PHY-3002 : Step(301): len = 662540, overlap = 135.25
+PHY-3002 : Step(302): len = 667120, overlap = 126.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.040918s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (114.6%)
+
+PHY-3001 : Legalized: Len = 695631, Over = 0
+PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.103616s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (105.6%)
+
+PHY-3001 : 594 instances has been re-located, deltaX = 195, deltaY = 335, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 703991, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71379, tnet num: 17665, tinst num: 6737, tnode num: 93621, tedge num: 118596.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.993958s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (99.5%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 637 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4877/17843.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 831672, over cnt = 2327(6%), over = 3720, worst = 7
+PHY-1002 : len = 844832, over cnt = 1293(3%), over = 1774, worst = 6
+PHY-1002 : len = 857632, over cnt = 536(1%), over = 736, worst = 6
+PHY-1002 : len = 862648, over cnt = 300(0%), over = 416, worst = 6
+PHY-1002 : len = 869288, over cnt = 7(0%), over = 7, worst = 1
+PHY-1001 : End global iterations; 2.080581s wall, 3.203125s user + 0.015625s system = 3.218750s CPU (154.7%)
+
+PHY-1001 : Congestion index: top1 = 52.61, top5 = 47.72, top10 = 44.84, top15 = 42.96.
+PHY-1001 : End incremental global routing; 2.505285s wall, 3.625000s user + 0.015625s system = 3.640625s CPU (145.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17665 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.952489s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (100.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6756 instances, 6607 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 708671
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16248/17863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874776, over cnt = 88(0%), over = 115, worst = 4
+PHY-1002 : len = 875024, over cnt = 38(0%), over = 43, worst = 3
+PHY-1002 : len = 875424, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 875560, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 875608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.835222s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.2%)
+
+PHY-1001 : Congestion index: top1 = 52.74, top5 = 47.79, top10 = 44.98, top15 = 43.11.
+PHY-3001 : End congestion estimation; 1.172423s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71551, tnet num: 17685, tinst num: 6756, tnode num: 93831, tedge num: 118825.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.001740s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (99.9%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 644 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.944088s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(303): len = 708091, overlap = 0
+PHY-3002 : Step(304): len = 707686, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16246/17863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874072, over cnt = 57(0%), over = 79, worst = 4
+PHY-1002 : len = 874184, over cnt = 26(0%), over = 31, worst = 3
+PHY-1002 : len = 874376, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 874504, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 874520, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.800669s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (107.3%)
+
+PHY-1001 : Congestion index: top1 = 52.52, top5 = 47.78, top10 = 44.89, top15 = 43.02.
+PHY-3001 : End congestion estimation; 1.137203s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (104.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.916015s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000505955
+PHY-3002 : Step(305): len = 707545, overlap = 0.5
+PHY-3002 : Step(306): len = 707381, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005883s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (265.6%)
+
+PHY-3001 : Legalized: Len = 707434, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066550s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.4%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 6, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 707766, Over = 0
+PHY-3001 : End incremental placement; 6.699750s wall, 6.828125s user + 0.093750s system = 6.921875s CPU (103.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.919177s wall, 12.250000s user + 0.140625s system = 12.390625s CPU (113.5%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 737, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16219/17863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874312, over cnt = 72(0%), over = 87, worst = 5
+PHY-1002 : len = 874464, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 874608, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 874792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.646452s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (108.8%)
+
+PHY-1001 : Congestion index: top1 = 52.54, top5 = 47.76, top10 = 44.94, top15 = 43.07.
+OPT-1001 : End congestion update; 0.982481s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (105.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.769696s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.5%)
+
+OPT-0007 : Start: WNS -129 TNS -129 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6668 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6756 instances, 6607 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 714281, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.072140s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (108.3%)
+
+PHY-3001 : 37 instances has been re-located, deltaX = 12, deltaY = 36, maxDist = 3.
+PHY-3001 : Final: Len = 714857, Over = 0
+PHY-3001 : End incremental legalization; 0.422543s wall, 0.421875s user + 0.031250s system = 0.453125s CPU (107.2%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 58 cells processed and 20611 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6668 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6756 instances, 6607 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 715493, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070717s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (110.5%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 11, deltaY = 5, maxDist = 4.
+PHY-3001 : Final: Len = 715823, Over = 0
+PHY-3001 : End incremental legalization; 0.506992s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.7%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 24 cells processed and 2032 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6676 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6764 instances, 6615 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 717179, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066085s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (118.2%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 2, deltaY = 14, maxDist = 2.
+PHY-3001 : Final: Len = 717613, Over = 0
+PHY-3001 : End incremental legalization; 0.436357s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.3%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 8 cells processed and 1338 slack improved
+OPT-1001 : End bottleneck based optimization; 3.587406s wall, 3.828125s user + 0.031250s system = 3.859375s CPU (107.6%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 737, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15873/17867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 884472, over cnt = 180(0%), over = 230, worst = 4
+PHY-1002 : len = 884696, over cnt = 100(0%), over = 106, worst = 2
+PHY-1002 : len = 885696, over cnt = 27(0%), over = 29, worst = 2
+PHY-1002 : len = 885984, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 886016, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.908789s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (108.3%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.83, top10 = 45.07, top15 = 43.25.
+OPT-1001 : End congestion update; 1.248252s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (105.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.777794s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.4%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6676 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6764 instances, 6615 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 717527, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064295s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 4.
+PHY-3001 : Final: Len = 717735, Over = 0
+PHY-3001 : End incremental legalization; 0.458593s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 2350 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.616498s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (106.9%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 737, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.768362s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16224/17867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886008, over cnt = 28(0%), over = 29, worst = 2
+PHY-1002 : len = 886000, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 886136, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 886184, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 886272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.816716s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.5%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.81, top10 = 45.07, top15 = 43.25.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.770468s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.034483
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.075374s wall, 23.796875s user + 0.187500s system = 23.984375s CPU (108.6%)
+
+RUN-1003 : finish command "place" in 69.745702s wall, 101.671875s user + 6.500000s system = 108.171875s CPU (155.1%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 636 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.782860s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (176.2%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 637 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6766 instances
+RUN-1001 : 3304 mslices, 3311 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17867 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9968 nets have 2 pins
+RUN-1001 : 6519 nets have [3 - 5] pins
+RUN-1001 : 740 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 295 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71621, tnet num: 17689, tinst num: 6764, tnode num: 93925, tedge num: 118924.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.765290s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.0%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 660 MB, peak memory is 737 MB
+PHY-1001 : 3304 mslices, 3311 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 818720, over cnt = 2583(7%), over = 4209, worst = 8
+PHY-1002 : len = 836088, over cnt = 1547(4%), over = 2220, worst = 6
+PHY-1002 : len = 856424, over cnt = 501(1%), over = 702, worst = 5
+PHY-1002 : len = 868088, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 868232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.335091s wall, 4.375000s user + 0.000000s system = 4.375000s CPU (131.2%)
+
+PHY-1001 : Congestion index: top1 = 52.56, top5 = 47.56, top10 = 44.82, top15 = 42.92.
+PHY-1001 : End global routing; 3.699369s wall, 4.734375s user + 0.000000s system = 4.734375s CPU (128.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 711, reserve = 716, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 983, reserve = 984, peak = 983.
+PHY-1001 : End build detailed router design. 4.333908s wall, 4.296875s user + 0.046875s system = 4.343750s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 269424, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.809396s wall, 5.765625s user + 0.015625s system = 5.781250s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 269480, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.501619s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1019, reserve = 1021, peak = 1019.
+PHY-1001 : End phase 1; 6.326330s wall, 6.281250s user + 0.015625s system = 6.296875s CPU (99.5%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.23296e+06, over cnt = 1864(0%), over = 1876, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1034, reserve = 1033, peak = 1034.
+PHY-1001 : End initial routed; 27.082533s wall, 63.046875s user + 0.171875s system = 63.218750s CPU (233.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16790(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.808 | -0.808 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.487190s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1049, peak = 1047.
+PHY-1001 : End phase 2; 30.569786s wall, 66.515625s user + 0.171875s system = 66.687500s CPU (218.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.802ns STNS -0.802ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.140628s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.0%)
+
+PHY-1022 : len = 2.23298e+06, over cnt = 1865(0%), over = 1877, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.429046s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.19628e+06, over cnt = 629(0%), over = 629, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.860540s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (173.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.1947e+06, over cnt = 129(0%), over = 129, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.733509s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (155.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.19472e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.399875s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (113.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.19494e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.240703s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (103.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.19501e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.246115s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.19506e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 6; 0.215494s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16790(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.802 | -0.802 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.511853s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 604 feed throughs used by 428 nets
+PHY-1001 : End commit to database; 2.360850s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (100.6%)
+
+PHY-1001 : Current memory(MB): used = 1144, reserve = 1149, peak = 1144.
+PHY-1001 : End phase 3; 10.437459s wall, 12.218750s user + 0.031250s system = 12.250000s CPU (117.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.802ns STNS -0.802ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.147088s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.2%)
+
+PHY-1022 : len = 2.19506e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.416093s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.802ns, -0.802ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16790(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.802 | -0.802 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.563837s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 604 feed throughs used by 428 nets
+PHY-1001 : End commit to database; 2.462286s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1158, peak = 1152.
+PHY-1001 : End phase 4; 6.468460s wall, 6.468750s user + 0.000000s system = 6.468750s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.19506e+06
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1160, peak = 1154.
+PHY-1001 : End export database. 0.166249s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.4%)
+
+PHY-1001 : End detail routing; 58.722934s wall, 96.375000s user + 0.265625s system = 96.640625s CPU (164.6%)
+
+RUN-1003 : finish command "route" in 65.332360s wall, 104.015625s user + 0.281250s system = 104.296875s CPU (159.6%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1083 MB, peak memory is 1154 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10220 out of 19600 52.14%
+#reg 9406 out of 19600 47.99%
+#le 12357
+ #lut only 2951 out of 12357 23.88%
+ #reg only 2137 out of 12357 17.29%
+ #lut® 7269 out of 12357 58.82%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1797
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1369
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1272
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 959
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 135
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg0_syn_146.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_283.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P118 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P110 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P143 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12357 |9193 |1027 |9440 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |536 |459 |23 |437 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |86 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |41 |41 |0 |21 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |747 |379 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |180 |124 |25 |138 |0 |0 |
+| u_gen_sp |gen_sp |256 |148 |71 |124 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |352 |96 |568 |0 |0 |
+| u_ADconfig |AD_config |175 |95 |25 |133 |0 |0 |
+| u_gen_sp |gen_sp |247 |150 |71 |114 |0 |0 |
+| sampling_fe_a |sampling_fe |3037 |2457 |306 |2099 |25 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |179 |100 |17 |149 |0 |0 |
+| u0_soft_n |cdc_sync |6 |0 |0 |6 |0 |0 |
+| u_sort |sort |2829 |2348 |289 |1921 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |0 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |8 |4 |0 |8 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2399 |2045 |253 |1560 |22 |0 |
+| channelPart |channel_part_8478 |133 |125 |3 |129 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |41 |0 |0 |
+| ram_switch |ram_switch |1890 |1608 |197 |1171 |0 |0 |
+| adc_addr_gen |adc_addr_gen |230 |203 |27 |129 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |17 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| insert |insert |926 |671 |170 |633 |0 |0 |
+| ram_switch_state |ram_switch_state |734 |734 |0 |409 |0 |0 |
+| read_ram_i |read_ram |281 |234 |44 |196 |0 |0 |
+| read_ram_addr |read_ram_addr |225 |185 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |50 |43 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |333 |233 |36 |279 |3 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3208 |2502 |349 |2076 |25 |1 |
+| u0_soft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |173 |82 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u_sort |sort_rev |3001 |2403 |332 |1898 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |4 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2579 |2081 |290 |1542 |22 |1 |
+| channelPart |channel_part_8478 |133 |123 |3 |129 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |42 |0 |1 |
+| ram_switch |ram_switch |1994 |1631 |197 |1128 |0 |0 |
+| adc_addr_gen |adc_addr_gen |198 |171 |27 |96 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |5 |0 |0 |
+| insert |insert |982 |646 |170 |696 |0 |0 |
+| ram_switch_state |ram_switch_state |814 |814 |0 |336 |0 |0 |
+| read_ram_i |read_ram_rev |363 |258 |81 |214 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |303 |223 |73 |171 |0 |0 |
+| read_ram_data |read_ram_data_rev |60 |35 |8 |43 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9906
+ #2 2 4224
+ #3 3 1698
+ #4 4 594
+ #5 5-10 786
+ #6 11-50 550
+ #7 51-100 13
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.182770s wall, 3.796875s user + 0.015625s system = 3.812500s CPU (174.7%)
+
+RUN-1004 : used memory is 1082 MB, reserved memory is 1085 MB, peak memory is 1154 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71621, tnet num: 17689, tinst num: 6764, tnode num: 93925, tedge num: 118924.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.713811s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.4%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1089 MB, peak memory is 1154 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.542117s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (100.3%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1092 MB, peak memory is 1154 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6764
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17867, pip num: 166736
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 604
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 467100 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.582924s wall, 61.062500s user + 0.125000s system = 61.187500s CPU (638.5%)
+
+RUN-1004 : used memory is 1243 MB, reserved memory is 1243 MB, peak memory is 1358 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_150021.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_163759.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_163759.log
new file mode 100644
index 0000000..740da5f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240315_163759.log
@@ -0,0 +1,2134 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Fri Mar 15 16:37:59 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 59 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.201826s wall, 2.125000s user + 0.078125s system = 2.203125s CPU (100.1%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 310 MB, peak memory is 338 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2940 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17957 instances
+RUN-0007 : 7642 luts, 9092 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20535 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13069 nets have 2 pins
+RUN-1001 : 6434 nets have [3 - 5] pins
+RUN-1001 : 614 nets have [6 - 10] pins
+RUN-1001 : 182 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2017
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17955 instances, 7642 luts, 9092 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5947 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83886, tnet num: 20357, tinst num: 17955, tnode num: 114123, tedge num: 133788.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.165222s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (100.6%)
+
+RUN-1004 : used memory is 527 MB, reserved memory is 508 MB, peak memory is 527 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20357 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.932218s wall, 1.890625s user + 0.046875s system = 1.937500s CPU (100.3%)
+
+PHY-3001 : Found 1253 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.0985e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17955.
+PHY-3001 : Level 1 #clusters 2051.
+PHY-3001 : End clustering; 0.125712s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (124.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.33549e+06, overlap = 464.844
+PHY-3002 : Step(2): len = 1.22477e+06, overlap = 513.5
+PHY-3002 : Step(3): len = 874301, overlap = 601.75
+PHY-3002 : Step(4): len = 795257, overlap = 645.781
+PHY-3002 : Step(5): len = 633099, overlap = 724.75
+PHY-3002 : Step(6): len = 560071, overlap = 789.594
+PHY-3002 : Step(7): len = 479912, overlap = 879.812
+PHY-3002 : Step(8): len = 426345, overlap = 947.75
+PHY-3002 : Step(9): len = 392510, overlap = 1005.03
+PHY-3002 : Step(10): len = 351603, overlap = 1074.91
+PHY-3002 : Step(11): len = 320558, overlap = 1119.78
+PHY-3002 : Step(12): len = 294892, overlap = 1193.25
+PHY-3002 : Step(13): len = 268147, overlap = 1252.78
+PHY-3002 : Step(14): len = 239769, overlap = 1312.16
+PHY-3002 : Step(15): len = 218073, overlap = 1348.81
+PHY-3002 : Step(16): len = 198223, overlap = 1372.84
+PHY-3002 : Step(17): len = 174862, overlap = 1414.41
+PHY-3002 : Step(18): len = 164215, overlap = 1430.75
+PHY-3002 : Step(19): len = 150609, overlap = 1465.28
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.21162e-06
+PHY-3002 : Step(20): len = 150638, overlap = 1450.19
+PHY-3002 : Step(21): len = 187736, overlap = 1319.78
+PHY-3002 : Step(22): len = 201417, overlap = 1218.75
+PHY-3002 : Step(23): len = 210825, overlap = 1144.97
+PHY-3002 : Step(24): len = 209540, overlap = 1129.81
+PHY-3002 : Step(25): len = 206958, overlap = 1097.53
+PHY-3002 : Step(26): len = 205380, overlap = 1083.47
+PHY-3002 : Step(27): len = 201163, overlap = 1081.03
+PHY-3002 : Step(28): len = 198168, overlap = 1092.97
+PHY-3002 : Step(29): len = 195211, overlap = 1079.94
+PHY-3002 : Step(30): len = 191882, overlap = 1076.56
+PHY-3002 : Step(31): len = 188913, overlap = 1071.34
+PHY-3002 : Step(32): len = 186732, overlap = 1055.59
+PHY-3002 : Step(33): len = 183135, overlap = 1042
+PHY-3002 : Step(34): len = 181362, overlap = 1060.97
+PHY-3002 : Step(35): len = 179364, overlap = 1068
+PHY-3002 : Step(36): len = 178317, overlap = 1068.03
+PHY-3002 : Step(37): len = 176260, overlap = 1062.34
+PHY-3002 : Step(38): len = 176598, overlap = 1056.81
+PHY-3002 : Step(39): len = 174825, overlap = 1065.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.42325e-06
+PHY-3002 : Step(40): len = 181653, overlap = 1048.59
+PHY-3002 : Step(41): len = 195733, overlap = 1011.09
+PHY-3002 : Step(42): len = 201612, overlap = 998.469
+PHY-3002 : Step(43): len = 207373, overlap = 985.906
+PHY-3002 : Step(44): len = 208948, overlap = 980.469
+PHY-3002 : Step(45): len = 211094, overlap = 970.969
+PHY-3002 : Step(46): len = 209259, overlap = 961.688
+PHY-3002 : Step(47): len = 209068, overlap = 947.062
+PHY-3002 : Step(48): len = 206510, overlap = 945.781
+PHY-3002 : Step(49): len = 206768, overlap = 956.625
+PHY-3002 : Step(50): len = 205049, overlap = 965.844
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.8465e-06
+PHY-3002 : Step(51): len = 214123, overlap = 952.281
+PHY-3002 : Step(52): len = 233995, overlap = 870.812
+PHY-3002 : Step(53): len = 242539, overlap = 833.219
+PHY-3002 : Step(54): len = 247553, overlap = 792.344
+PHY-3002 : Step(55): len = 250862, overlap = 773.875
+PHY-3002 : Step(56): len = 253527, overlap = 761.438
+PHY-3002 : Step(57): len = 253269, overlap = 751.625
+PHY-3002 : Step(58): len = 253751, overlap = 739.281
+PHY-3002 : Step(59): len = 254264, overlap = 730.375
+PHY-3002 : Step(60): len = 255417, overlap = 727.188
+PHY-3002 : Step(61): len = 255802, overlap = 726.719
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.693e-06
+PHY-3002 : Step(62): len = 273961, overlap = 678.75
+PHY-3002 : Step(63): len = 294828, overlap = 594.938
+PHY-3002 : Step(64): len = 302527, overlap = 552.688
+PHY-3002 : Step(65): len = 304873, overlap = 538.344
+PHY-3002 : Step(66): len = 301457, overlap = 543.781
+PHY-3002 : Step(67): len = 300782, overlap = 514.75
+PHY-3002 : Step(68): len = 300280, overlap = 504
+PHY-3002 : Step(69): len = 301076, overlap = 482.062
+PHY-3002 : Step(70): len = 301900, overlap = 461.625
+PHY-3002 : Step(71): len = 301981, overlap = 463.5
+PHY-3002 : Step(72): len = 302232, overlap = 453.656
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.9386e-05
+PHY-3002 : Step(73): len = 322311, overlap = 427.625
+PHY-3002 : Step(74): len = 338468, overlap = 415.469
+PHY-3002 : Step(75): len = 343706, overlap = 408.75
+PHY-3002 : Step(76): len = 345397, overlap = 399.75
+PHY-3002 : Step(77): len = 341668, overlap = 400.406
+PHY-3002 : Step(78): len = 341734, overlap = 391.125
+PHY-3002 : Step(79): len = 341358, overlap = 379.625
+PHY-3002 : Step(80): len = 341902, overlap = 376.062
+PHY-3002 : Step(81): len = 340123, overlap = 370.375
+PHY-3002 : Step(82): len = 339988, overlap = 373.156
+PHY-3002 : Step(83): len = 339437, overlap = 384.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.8772e-05
+PHY-3002 : Step(84): len = 356333, overlap = 351.562
+PHY-3002 : Step(85): len = 369789, overlap = 332.125
+PHY-3002 : Step(86): len = 374840, overlap = 315.688
+PHY-3002 : Step(87): len = 377969, overlap = 305.438
+PHY-3002 : Step(88): len = 379026, overlap = 280.781
+PHY-3002 : Step(89): len = 381873, overlap = 266.125
+PHY-3002 : Step(90): len = 378074, overlap = 273.094
+PHY-3002 : Step(91): len = 379758, overlap = 270.156
+PHY-3002 : Step(92): len = 380827, overlap = 273.531
+PHY-3002 : Step(93): len = 381787, overlap = 274.688
+PHY-3002 : Step(94): len = 378822, overlap = 281.031
+PHY-3002 : Step(95): len = 379171, overlap = 278.312
+PHY-3002 : Step(96): len = 380153, overlap = 273.531
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.7544e-05
+PHY-3002 : Step(97): len = 396441, overlap = 266.156
+PHY-3002 : Step(98): len = 408904, overlap = 263.656
+PHY-3002 : Step(99): len = 409288, overlap = 244.344
+PHY-3002 : Step(100): len = 409829, overlap = 236.281
+PHY-3002 : Step(101): len = 412767, overlap = 250.5
+PHY-3002 : Step(102): len = 415605, overlap = 255
+PHY-3002 : Step(103): len = 414753, overlap = 256.312
+PHY-3002 : Step(104): len = 413819, overlap = 260.719
+PHY-3002 : Step(105): len = 415328, overlap = 259.406
+PHY-3002 : Step(106): len = 417394, overlap = 252.531
+PHY-3002 : Step(107): len = 415937, overlap = 238.062
+PHY-3002 : Step(108): len = 416566, overlap = 233.094
+PHY-3002 : Step(109): len = 416782, overlap = 224.469
+PHY-3002 : Step(110): len = 416081, overlap = 225.719
+PHY-3002 : Step(111): len = 415038, overlap = 222.844
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000155088
+PHY-3002 : Step(112): len = 429707, overlap = 225.531
+PHY-3002 : Step(113): len = 437022, overlap = 217.719
+PHY-3002 : Step(114): len = 435427, overlap = 205.719
+PHY-3002 : Step(115): len = 436050, overlap = 203
+PHY-3002 : Step(116): len = 439047, overlap = 204.281
+PHY-3002 : Step(117): len = 442224, overlap = 200.031
+PHY-3002 : Step(118): len = 441982, overlap = 194.875
+PHY-3002 : Step(119): len = 443212, overlap = 189.75
+PHY-3002 : Step(120): len = 445313, overlap = 188.938
+PHY-3002 : Step(121): len = 447234, overlap = 176.719
+PHY-3002 : Step(122): len = 445745, overlap = 171.344
+PHY-3002 : Step(123): len = 445958, overlap = 175.625
+PHY-3002 : Step(124): len = 446805, overlap = 177.062
+PHY-3002 : Step(125): len = 447390, overlap = 179.188
+PHY-3002 : Step(126): len = 446799, overlap = 171.719
+PHY-3002 : Step(127): len = 447853, overlap = 167.906
+PHY-3002 : Step(128): len = 448795, overlap = 172.094
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000310176
+PHY-3002 : Step(129): len = 459406, overlap = 169.156
+PHY-3002 : Step(130): len = 467670, overlap = 145.531
+PHY-3002 : Step(131): len = 467731, overlap = 139.938
+PHY-3002 : Step(132): len = 468544, overlap = 141.875
+PHY-3002 : Step(133): len = 471034, overlap = 130.688
+PHY-3002 : Step(134): len = 473720, overlap = 133.625
+PHY-3002 : Step(135): len = 475057, overlap = 132.531
+PHY-3002 : Step(136): len = 478379, overlap = 143.812
+PHY-3002 : Step(137): len = 480859, overlap = 135.531
+PHY-3002 : Step(138): len = 482728, overlap = 132.656
+PHY-3002 : Step(139): len = 481189, overlap = 131.031
+PHY-3002 : Step(140): len = 480598, overlap = 131.406
+PHY-3002 : Step(141): len = 480595, overlap = 139.219
+PHY-3002 : Step(142): len = 480694, overlap = 143.094
+PHY-3002 : Step(143): len = 480627, overlap = 142.594
+PHY-3002 : Step(144): len = 481011, overlap = 145.438
+PHY-3002 : Step(145): len = 481395, overlap = 147.25
+PHY-3002 : Step(146): len = 481623, overlap = 150.531
+PHY-3002 : Step(147): len = 480757, overlap = 153
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000600808
+PHY-3002 : Step(148): len = 487977, overlap = 148.875
+PHY-3002 : Step(149): len = 492965, overlap = 150.281
+PHY-3002 : Step(150): len = 493192, overlap = 146.031
+PHY-3002 : Step(151): len = 493810, overlap = 144.75
+PHY-3002 : Step(152): len = 496354, overlap = 147.344
+PHY-3002 : Step(153): len = 498101, overlap = 147.469
+PHY-3002 : Step(154): len = 497932, overlap = 146.906
+PHY-3002 : Step(155): len = 498275, overlap = 148.312
+PHY-3002 : Step(156): len = 500365, overlap = 146.344
+PHY-3002 : Step(157): len = 501499, overlap = 151.844
+PHY-3002 : Step(158): len = 500579, overlap = 149.875
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109928
+PHY-3002 : Step(159): len = 504290, overlap = 150.312
+PHY-3002 : Step(160): len = 508788, overlap = 145.281
+PHY-3002 : Step(161): len = 510366, overlap = 144.156
+PHY-3002 : Step(162): len = 512679, overlap = 142.031
+PHY-3002 : Step(163): len = 515255, overlap = 140.438
+PHY-3002 : Step(164): len = 517034, overlap = 139.5
+PHY-3002 : Step(165): len = 516267, overlap = 138
+PHY-3002 : Step(166): len = 516242, overlap = 131.906
+PHY-3002 : Step(167): len = 517942, overlap = 130.188
+PHY-3002 : Step(168): len = 519103, overlap = 130.531
+PHY-3002 : Step(169): len = 518613, overlap = 127
+PHY-3002 : Step(170): len = 519015, overlap = 121.125
+PHY-3002 : Step(171): len = 520663, overlap = 116.625
+PHY-3002 : Step(172): len = 521264, overlap = 114.375
+PHY-3002 : Step(173): len = 520379, overlap = 117.812
+PHY-3002 : Step(174): len = 520252, overlap = 120.812
+PHY-3002 : Step(175): len = 521090, overlap = 116.812
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00193534
+PHY-3002 : Step(176): len = 522761, overlap = 118.188
+PHY-3002 : Step(177): len = 527301, overlap = 120.844
+PHY-3002 : Step(178): len = 530215, overlap = 123.344
+PHY-3002 : Step(179): len = 531888, overlap = 126.375
+PHY-3002 : Step(180): len = 531752, overlap = 121.062
+PHY-3002 : Step(181): len = 531743, overlap = 122.281
+PHY-3002 : Step(182): len = 532778, overlap = 122.875
+PHY-3002 : Step(183): len = 533606, overlap = 125.219
+PHY-3002 : Step(184): len = 533538, overlap = 126.188
+PHY-3002 : Step(185): len = 533607, overlap = 126.188
+PHY-3002 : Step(186): len = 534558, overlap = 125.562
+PHY-3002 : Step(187): len = 535246, overlap = 123.25
+PHY-3002 : Step(188): len = 534846, overlap = 122.594
+PHY-3002 : Step(189): len = 534846, overlap = 122.594
+PHY-3002 : Step(190): len = 534962, overlap = 127
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014564s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (107.3%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20535.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710560, over cnt = 1665(4%), over = 7825, worst = 43
+PHY-1001 : End global iterations; 0.706457s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (132.7%)
+
+PHY-1001 : Congestion index: top1 = 85.13, top5 = 63.07, top10 = 53.22, top15 = 47.43.
+PHY-3001 : End congestion estimation; 0.940448s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (126.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20357 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.839607s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000145793
+PHY-3002 : Step(191): len = 649850, overlap = 84.3438
+PHY-3002 : Step(192): len = 651288, overlap = 66.1562
+PHY-3002 : Step(193): len = 645581, overlap = 64.0625
+PHY-3002 : Step(194): len = 641053, overlap = 60.0938
+PHY-3002 : Step(195): len = 639157, overlap = 61.1562
+PHY-3002 : Step(196): len = 638815, overlap = 58.9375
+PHY-3002 : Step(197): len = 637112, overlap = 60.75
+PHY-3002 : Step(198): len = 634776, overlap = 54.2188
+PHY-3002 : Step(199): len = 632216, overlap = 50.4688
+PHY-3002 : Step(200): len = 630133, overlap = 44.6875
+PHY-3002 : Step(201): len = 628239, overlap = 35.2812
+PHY-3002 : Step(202): len = 625948, overlap = 29.5
+PHY-3002 : Step(203): len = 624976, overlap = 26.875
+PHY-3002 : Step(204): len = 625994, overlap = 28.5312
+PHY-3002 : Step(205): len = 626016, overlap = 31.5938
+PHY-3002 : Step(206): len = 625757, overlap = 32.5938
+PHY-3002 : Step(207): len = 624016, overlap = 35.8438
+PHY-3002 : Step(208): len = 622784, overlap = 39.9375
+PHY-3002 : Step(209): len = 621919, overlap = 40.125
+PHY-3002 : Step(210): len = 621878, overlap = 41.4688
+PHY-3002 : Step(211): len = 620745, overlap = 39.75
+PHY-3002 : Step(212): len = 619069, overlap = 42.875
+PHY-3002 : Step(213): len = 617682, overlap = 41.6562
+PHY-3002 : Step(214): len = 617549, overlap = 39.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000291586
+PHY-3002 : Step(215): len = 621493, overlap = 36.5625
+PHY-3002 : Step(216): len = 624451, overlap = 34.4375
+PHY-3002 : Step(217): len = 627174, overlap = 33.7812
+PHY-3002 : Step(218): len = 629880, overlap = 33.6875
+PHY-3002 : Step(219): len = 631825, overlap = 34.5938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000583173
+PHY-3002 : Step(220): len = 638155, overlap = 35.2188
+PHY-3002 : Step(221): len = 651605, overlap = 38.125
+PHY-3002 : Step(222): len = 667631, overlap = 38.3125
+PHY-3002 : Step(223): len = 663904, overlap = 39.25
+PHY-3002 : Step(224): len = 660513, overlap = 40.4375
+PHY-3002 : Step(225): len = 657167, overlap = 42.375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 70/20535.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743032, over cnt = 2818(8%), over = 12671, worst = 50
+PHY-1001 : End global iterations; 1.653849s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (131.3%)
+
+PHY-1001 : Congestion index: top1 = 84.20, top5 = 67.58, top10 = 58.99, top15 = 53.82.
+PHY-3001 : End congestion estimation; 1.936252s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (126.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20357 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.921716s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (98.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000114429
+PHY-3002 : Step(226): len = 652326, overlap = 260
+PHY-3002 : Step(227): len = 651759, overlap = 201.281
+PHY-3002 : Step(228): len = 646351, overlap = 180.562
+PHY-3002 : Step(229): len = 643240, overlap = 160.562
+PHY-3002 : Step(230): len = 638483, overlap = 144.469
+PHY-3002 : Step(231): len = 633990, overlap = 135.5
+PHY-3002 : Step(232): len = 629379, overlap = 128.344
+PHY-3002 : Step(233): len = 627490, overlap = 131.844
+PHY-3002 : Step(234): len = 623374, overlap = 133
+PHY-3002 : Step(235): len = 620134, overlap = 131.938
+PHY-3002 : Step(236): len = 617788, overlap = 134.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000228857
+PHY-3002 : Step(237): len = 617991, overlap = 126.438
+PHY-3002 : Step(238): len = 620152, overlap = 124.719
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000391083
+PHY-3002 : Step(239): len = 622911, overlap = 119.5
+PHY-3002 : Step(240): len = 630376, overlap = 104.094
+PHY-3002 : Step(241): len = 635685, overlap = 98.2812
+PHY-3002 : Step(242): len = 638733, overlap = 92.5938
+PHY-3002 : Step(243): len = 640930, overlap = 90.2188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83886, tnet num: 20357, tinst num: 17955, tnode num: 114123, tedge num: 133788.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.440166s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.8%)
+
+RUN-1004 : used memory is 570 MB, reserved memory is 557 MB, peak memory is 705 MB
+OPT-1001 : Total overflow 411.81 peak overflow 6.06
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 845/20535.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735216, over cnt = 3021(8%), over = 10907, worst = 28
+PHY-1001 : End global iterations; 1.196006s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (146.3%)
+
+PHY-1001 : Congestion index: top1 = 69.89, top5 = 57.17, top10 = 51.07, top15 = 47.37.
+PHY-1001 : End incremental global routing; 1.527683s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (136.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20357 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.912917s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (97.6%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17824 has valid locations, 296 needs to be replaced
+PHY-3001 : design contains 18205 instances, 7735 luts, 9249 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6055 pins
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 664360
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16893/20785.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749320, over cnt = 3059(8%), over = 10933, worst = 28
+PHY-1001 : End global iterations; 0.235438s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (99.5%)
+
+PHY-1001 : Congestion index: top1 = 70.26, top5 = 57.49, top10 = 51.28, top15 = 47.66.
+PHY-3001 : End congestion estimation; 0.491886s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (98.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84904, tnet num: 20607, tinst num: 18205, tnode num: 115635, tedge num: 135324.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.438539s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (98.8%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 608 MB, peak memory is 709 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20607 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.374998s wall, 2.296875s user + 0.062500s system = 2.359375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(244): len = 663292, overlap = 0.0625
+PHY-3002 : Step(245): len = 662780, overlap = 0.0625
+PHY-3002 : Step(246): len = 662434, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16974/20785.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 746960, over cnt = 3064(8%), over = 11017, worst = 28
+PHY-1001 : End global iterations; 0.200060s wall, 0.359375s user + 0.046875s system = 0.406250s CPU (203.1%)
+
+PHY-1001 : Congestion index: top1 = 70.58, top5 = 57.88, top10 = 51.65, top15 = 47.87.
+PHY-3001 : End congestion estimation; 0.448071s wall, 0.609375s user + 0.046875s system = 0.656250s CPU (146.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20607 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.297521s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00038556
+PHY-3002 : Step(247): len = 662198, overlap = 92.625
+PHY-3002 : Step(248): len = 662223, overlap = 92.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00077112
+PHY-3002 : Step(249): len = 662562, overlap = 92.1562
+PHY-3002 : Step(250): len = 662763, overlap = 92.3438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00154224
+PHY-3002 : Step(251): len = 663075, overlap = 91.875
+PHY-3002 : Step(252): len = 663768, overlap = 91.6875
+PHY-3001 : Final: Len = 663768, Over = 91.6875
+PHY-3001 : End incremental placement; 5.320431s wall, 5.500000s user + 0.406250s system = 5.906250s CPU (111.0%)
+
+OPT-1001 : Total overflow 417.84 peak overflow 6.06
+OPT-1001 : End high-fanout net optimization; 8.348059s wall, 9.125000s user + 0.437500s system = 9.562500s CPU (114.5%)
+
+OPT-1001 : Current memory(MB): used = 711, reserve = 703, peak = 728.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16914/20785.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 750744, over cnt = 3000(8%), over = 9994, worst = 28
+PHY-1002 : len = 802360, over cnt = 2036(5%), over = 5079, worst = 28
+PHY-1002 : len = 846728, over cnt = 744(2%), over = 1679, worst = 17
+PHY-1002 : len = 865912, over cnt = 199(0%), over = 361, worst = 14
+PHY-1002 : len = 872936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.226252s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (129.1%)
+
+PHY-1001 : Congestion index: top1 = 57.54, top5 = 50.47, top10 = 46.78, top15 = 44.51.
+OPT-1001 : End congestion update; 2.478175s wall, 3.093750s user + 0.031250s system = 3.125000s CPU (126.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20607 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.783604s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 131 cells processed and 15450 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 32 cells processed and 2650 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 21 cells processed and 2250 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 5: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 746 slack improved
+OPT-1001 : End bottleneck based optimization; 3.747023s wall, 4.359375s user + 0.031250s system = 4.390625s CPU (117.2%)
+
+OPT-1001 : Current memory(MB): used = 687, reserve = 682, peak = 728.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16961/20790.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872984, over cnt = 66(0%), over = 100, worst = 5
+PHY-1002 : len = 872816, over cnt = 47(0%), over = 60, worst = 3
+PHY-1002 : len = 873144, over cnt = 24(0%), over = 28, worst = 2
+PHY-1002 : len = 873592, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 873600, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.754717s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 57.54, top5 = 50.38, top10 = 46.74, top15 = 44.46.
+OPT-1001 : End congestion update; 1.021761s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (102.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20612 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.781270s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.0%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 14 cells processed and 5050 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.913464s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (101.3%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 691, peak = 728.
+OPT-1001 : End physical optimization; 15.751627s wall, 17.250000s user + 0.500000s system = 17.750000s CPU (112.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7735 LUT to BLE ...
+SYN-4008 : Packed 7735 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6121 remaining SEQ's ...
+SYN-4005 : Packed 3866 SEQ with LUT/SLICE
+SYN-4006 : 1031 single LUT's are left
+SYN-4006 : 2255 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9990/13825 primitive instances ...
+PHY-3001 : End packing; 1.581600s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6760 instances
+RUN-1001 : 3306 mslices, 3306 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17786 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9963 nets have 2 pins
+RUN-1001 : 6473 nets have [3 - 5] pins
+RUN-1001 : 727 nets have [6 - 10] pins
+RUN-1001 : 291 nets have [11 - 20] pins
+RUN-1001 : 300 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6758 instances, 6612 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3534 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 675551, Over = 213.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7688/17786.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826376, over cnt = 1915(5%), over = 3012, worst = 7
+PHY-1002 : len = 834536, over cnt = 1118(3%), over = 1528, worst = 7
+PHY-1002 : len = 843672, over cnt = 558(1%), over = 747, worst = 6
+PHY-1002 : len = 852304, over cnt = 170(0%), over = 205, worst = 4
+PHY-1002 : len = 856288, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.817258s wall, 2.500000s user + 0.031250s system = 2.531250s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 50.31, top10 = 46.35, top15 = 43.93.
+PHY-3001 : End congestion estimation; 2.210857s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (131.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71262, tnet num: 17608, tinst num: 6758, tnode num: 93603, tedge num: 118451.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.583457s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.7%)
+
+RUN-1004 : used memory is 607 MB, reserved memory is 612 MB, peak memory is 728 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17608 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.428888s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.29904e-05
+PHY-3002 : Step(253): len = 662411, overlap = 217
+PHY-3002 : Step(254): len = 655059, overlap = 220.25
+PHY-3002 : Step(255): len = 649849, overlap = 227.5
+PHY-3002 : Step(256): len = 645871, overlap = 230.5
+PHY-3002 : Step(257): len = 642276, overlap = 236.5
+PHY-3002 : Step(258): len = 639276, overlap = 251.5
+PHY-3002 : Step(259): len = 636708, overlap = 253.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000105981
+PHY-3002 : Step(260): len = 639425, overlap = 247.5
+PHY-3002 : Step(261): len = 645193, overlap = 243.25
+PHY-3002 : Step(262): len = 646766, overlap = 239.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000211962
+PHY-3002 : Step(263): len = 653308, overlap = 228.5
+PHY-3002 : Step(264): len = 658688, overlap = 223
+PHY-3002 : Step(265): len = 658664, overlap = 219
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.353260s wall, 0.390625s user + 0.453125s system = 0.843750s CPU (238.8%)
+
+PHY-3001 : Trial Legalized: Len = 743296
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 833/17786.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853128, over cnt = 2617(7%), over = 4325, worst = 8
+PHY-1002 : len = 868392, over cnt = 1625(4%), over = 2357, worst = 7
+PHY-1002 : len = 890424, over cnt = 468(1%), over = 667, worst = 7
+PHY-1002 : len = 900816, over cnt = 34(0%), over = 38, worst = 2
+PHY-1002 : len = 901904, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.875831s wall, 3.921875s user + 0.015625s system = 3.937500s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 53.99, top5 = 49.40, top10 = 46.62, top15 = 44.68.
+PHY-3001 : End congestion estimation; 3.339594s wall, 4.390625s user + 0.015625s system = 4.406250s CPU (131.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17608 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.888389s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000179118
+PHY-3002 : Step(266): len = 715228, overlap = 44.25
+PHY-3002 : Step(267): len = 700183, overlap = 69.75
+PHY-3002 : Step(268): len = 687428, overlap = 97
+PHY-3002 : Step(269): len = 679825, overlap = 118.75
+PHY-3002 : Step(270): len = 673507, overlap = 147
+PHY-3002 : Step(271): len = 670712, overlap = 161.75
+PHY-3002 : Step(272): len = 668773, overlap = 166.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000358235
+PHY-3002 : Step(273): len = 672488, overlap = 161.5
+PHY-3002 : Step(274): len = 677073, overlap = 149
+PHY-3002 : Step(275): len = 680650, overlap = 142
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000716471
+PHY-3002 : Step(276): len = 683265, overlap = 140.25
+PHY-3002 : Step(277): len = 689740, overlap = 136.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034025s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (91.8%)
+
+PHY-3001 : Legalized: Len = 719181, Over = 0
+PHY-3001 : Spreading special nets. 405 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.100013s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (93.7%)
+
+PHY-3001 : 586 instances has been re-located, deltaX = 180, deltaY = 337, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 728375, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71262, tnet num: 17608, tinst num: 6761, tnode num: 93603, tedge num: 118451.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.852384s wall, 1.796875s user + 0.062500s system = 1.859375s CPU (100.4%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 636 MB, peak memory is 728 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3724/17786.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 850632, over cnt = 2437(6%), over = 3891, worst = 8
+PHY-1002 : len = 863312, over cnt = 1487(4%), over = 2118, worst = 7
+PHY-1002 : len = 877728, over cnt = 693(1%), over = 949, worst = 7
+PHY-1002 : len = 891184, over cnt = 127(0%), over = 152, worst = 5
+PHY-1002 : len = 893536, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.089262s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.12, top10 = 45.25, top15 = 43.44.
+PHY-1001 : End incremental global routing; 2.480145s wall, 3.343750s user + 0.015625s system = 3.359375s CPU (135.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17608 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.844396s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.9%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6669 has valid locations, 22 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3614 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 732142
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16165/17804.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 897816, over cnt = 78(0%), over = 85, worst = 3
+PHY-1002 : len = 897904, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 897992, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 898320, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.609694s wall, 0.671875s user + 0.046875s system = 0.718750s CPU (117.9%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.11, top10 = 45.27, top15 = 43.53.
+PHY-3001 : End congestion estimation; 0.934621s wall, 1.000000s user + 0.046875s system = 1.046875s CPU (112.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71434, tnet num: 17626, tinst num: 6779, tnode num: 93819, tedge num: 118663.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.837621s wall, 1.812500s user + 0.015625s system = 1.828125s CPU (99.5%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 665 MB, peak memory is 728 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17626 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.708299s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(278): len = 730677, overlap = 0.25
+PHY-3002 : Step(279): len = 730420, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16152/17804.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 895224, over cnt = 62(0%), over = 69, worst = 3
+PHY-1002 : len = 895280, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 895424, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 895600, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.576044s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.08, top10 = 45.25, top15 = 43.49.
+PHY-3001 : End congestion estimation; 0.892510s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (101.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17626 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.852743s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00015817
+PHY-3002 : Step(280): len = 730280, overlap = 1.25
+PHY-3002 : Step(281): len = 730280, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005589s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 730350, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058305s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.4%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 0, deltaY = 9, maxDist = 1.
+PHY-3001 : Final: Len = 730528, Over = 0
+PHY-3001 : End incremental placement; 5.875956s wall, 5.984375s user + 0.109375s system = 6.093750s CPU (103.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.673981s wall, 10.750000s user + 0.125000s system = 10.875000s CPU (112.4%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 713, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16129/17804.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 895952, over cnt = 59(0%), over = 72, worst = 6
+PHY-1002 : len = 896000, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 896200, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 896432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.602756s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (103.7%)
+
+PHY-1001 : Congestion index: top1 = 53.34, top5 = 48.18, top10 = 45.35, top15 = 43.57.
+OPT-1001 : End congestion update; 0.909379s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (103.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17626 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.700714s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.3%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3614 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 736495, Over = 0
+PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063622s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.2%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 12, deltaY = 12, maxDist = 3.
+PHY-3001 : Final: Len = 737211, Over = 0
+PHY-3001 : End incremental legalization; 0.423147s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 56 cells processed and 22755 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6691 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6779 instances, 6630 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3614 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 737077, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067541s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.5%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 7, deltaY = 4, maxDist = 3.
+PHY-3001 : Final: Len = 737407, Over = 0
+PHY-3001 : End incremental legalization; 0.421059s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.2%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 21 cells processed and 1550 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3617 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 737882, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058645s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.6%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 8, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 738096, Over = 0
+PHY-3001 : End incremental legalization; 0.441358s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.7%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 9 cells processed and 1344 slack improved
+OPT-1001 : End bottleneck based optimization; 3.342316s wall, 3.406250s user + 0.015625s system = 3.421875s CPU (102.4%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 715, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15832/17808.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903760, over cnt = 129(0%), over = 174, worst = 4
+PHY-1002 : len = 904360, over cnt = 67(0%), over = 70, worst = 2
+PHY-1002 : len = 904760, over cnt = 32(0%), over = 32, worst = 1
+PHY-1002 : len = 905400, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 905544, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.835862s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.32, top10 = 45.46, top15 = 43.63.
+OPT-1001 : End congestion update; 1.159183s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (103.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.749228s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.1%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3617 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738244, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059681s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 11, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 738348, Over = 0
+PHY-3001 : End incremental legalization; 0.375476s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1400 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.406667s wall, 2.500000s user + 0.046875s system = 2.546875s CPU (105.8%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 715, peak = 733.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.699579s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16158/17808.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905248, over cnt = 43(0%), over = 44, worst = 2
+PHY-1002 : len = 905120, over cnt = 27(0%), over = 28, worst = 2
+PHY-1002 : len = 905416, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 905568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.586913s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (98.5%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.37, top10 = 45.48, top15 = 43.63.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701639s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.689655
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3617 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738348, Over = 0
+PHY-3001 : End spreading; 0.055827s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (84.0%)
+
+PHY-3001 : Final: Len = 738348, Over = 0
+PHY-3001 : End incremental legalization; 0.393716s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (95.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694323s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.3%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16189/17808.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.124148s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (100.7%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.37, top10 = 45.48, top15 = 43.63.
+OPT-1001 : End congestion update; 0.422443s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.692832s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3617 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738298, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056245s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (83.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 1, maxDist = 3.
+PHY-3001 : Final: Len = 738348, Over = 0
+PHY-3001 : End incremental legalization; 0.364075s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.7%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.585122s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.6%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 715, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16189/17808.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.125448s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.6%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.37, top10 = 45.48, top15 = 43.63.
+OPT-1001 : End congestion update; 0.425419s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.693263s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.4%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3617 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738298, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056326s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (111.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 1, maxDist = 3.
+PHY-3001 : Final: Len = 738348, Over = 0
+PHY-3001 : End incremental legalization; 0.366380s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (132.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3617 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738298, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056495s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 1, maxDist = 3.
+PHY-3001 : Final: Len = 738348, Over = 0
+PHY-3001 : End incremental legalization; 0.368588s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.7%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.127504s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (105.0%)
+
+OPT-1001 : Current memory(MB): used = 720, reserve = 715, peak = 733.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.695041s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 720, reserve = 715, peak = 733.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.732356s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.3%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16189/17808.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.125201s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.8%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.37, top10 = 45.48, top15 = 43.63.
+RUN-1001 : End congestion update; 0.430905s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.9%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.166390s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.1%)
+
+OPT-1001 : Current memory(MB): used = 720, reserve = 715, peak = 733.
+OPT-1001 : End physical optimization; 27.124482s wall, 27.953125s user + 0.250000s system = 28.203125s CPU (104.0%)
+
+RUN-1003 : finish command "place" in 70.638073s wall, 98.250000s user + 5.265625s system = 103.515625s CPU (146.5%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 634 MB, peak memory is 733 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.632230s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (174.2%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 635 MB, peak memory is 733 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6790 instances
+RUN-1001 : 3319 mslices, 3320 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17808 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9953 nets have 2 pins
+RUN-1001 : 6482 nets have [3 - 5] pins
+RUN-1001 : 736 nets have [6 - 10] pins
+RUN-1001 : 298 nets have [11 - 20] pins
+RUN-1001 : 311 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71497, tnet num: 17630, tinst num: 6788, tnode num: 93908, tedge num: 118747.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.598021s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.7%)
+
+RUN-1004 : used memory is 638 MB, reserved memory is 651 MB, peak memory is 733 MB
+PHY-1001 : 3319 mslices, 3320 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838320, over cnt = 2629(7%), over = 4226, worst = 8
+PHY-1002 : len = 856624, over cnt = 1494(4%), over = 2058, worst = 7
+PHY-1002 : len = 875008, over cnt = 538(1%), over = 682, worst = 6
+PHY-1002 : len = 886360, over cnt = 8(0%), over = 11, worst = 4
+PHY-1002 : len = 886608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.992650s wall, 3.937500s user + 0.062500s system = 4.000000s CPU (133.7%)
+
+PHY-1001 : Congestion index: top1 = 52.54, top5 = 47.81, top10 = 45.08, top15 = 43.12.
+PHY-1001 : End global routing; 3.316954s wall, 4.281250s user + 0.062500s system = 4.343750s CPU (131.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 703, reserve = 706, peak = 733.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 974, reserve = 976, peak = 974.
+PHY-1001 : End build detailed router design. 4.074871s wall, 4.015625s user + 0.062500s system = 4.078125s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 269848, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.100839s wall, 5.093750s user + 0.000000s system = 5.093750s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 269904, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.421267s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1011, reserve = 1013, peak = 1011.
+PHY-1001 : End phase 1; 5.534125s wall, 5.531250s user + 0.000000s system = 5.531250s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.25549e+06, over cnt = 1599(0%), over = 1604, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1024, peak = 1024.
+PHY-1001 : End initial routed; 23.843915s wall, 58.515625s user + 0.296875s system = 58.812500s CPU (246.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16731(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.810 | -0.810 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.829234s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1034, reserve = 1035, peak = 1034.
+PHY-1001 : End phase 2; 27.673213s wall, 62.343750s user + 0.296875s system = 62.640625s CPU (226.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135844s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.5%)
+
+PHY-1022 : len = 2.25549e+06, over cnt = 1599(0%), over = 1604, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.410682s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.23132e+06, over cnt = 681(0%), over = 681, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.884636s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (180.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.22735e+06, over cnt = 111(0%), over = 111, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.854849s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (138.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.22796e+06, over cnt = 16(0%), over = 16, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.300281s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (119.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.22812e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.204725s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.22817e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.207683s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16731(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.855046s wall, 3.843750s user + 0.000000s system = 3.843750s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 501 feed throughs used by 366 nets
+PHY-1001 : End commit to database; 2.261112s wall, 2.250000s user + 0.015625s system = 2.265625s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1137, reserve = 1141, peak = 1137.
+PHY-1001 : End phase 3; 9.374273s wall, 10.453125s user + 0.031250s system = 10.484375s CPU (111.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.131767s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.9%)
+
+PHY-1022 : len = 2.22817e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.359883s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (95.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.805ns, -0.805ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16731(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.807528s wall, 3.796875s user + 0.000000s system = 3.796875s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 501 feed throughs used by 366 nets
+PHY-1001 : End commit to database; 2.359535s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1145, reserve = 1149, peak = 1145.
+PHY-1001 : End phase 4; 6.552197s wall, 6.562500s user + 0.000000s system = 6.562500s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.22817e+06
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1151, peak = 1147.
+PHY-1001 : End export database. 0.058911s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.1%)
+
+PHY-1001 : End detail routing; 53.652759s wall, 89.328125s user + 0.390625s system = 89.718750s CPU (167.2%)
+
+RUN-1003 : finish command "route" in 59.602365s wall, 96.234375s user + 0.468750s system = 96.703125s CPU (162.2%)
+
+RUN-1004 : used memory is 1071 MB, reserved memory is 1089 MB, peak memory is 1147 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10149 out of 19600 51.78%
+#reg 9392 out of 19600 47.92%
+#le 12374
+ #lut only 2982 out of 12374 24.10%
+ #reg only 2225 out of 12374 17.98%
+ #lut® 7167 out of 12374 57.92%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1795
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1393
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1262
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 982
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 137
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_303.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg46_syn_233.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P84 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P109 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P14 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P110 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P146 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12374 |9122 |1027 |9426 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |533 |455 |23 |438 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |91 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |45 |45 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |8 |0 |0 |
+| exdev_ctl_a |exdev_ctl |752 |349 |96 |572 |0 |0 |
+| u_ADconfig |AD_config |184 |124 |25 |141 |0 |0 |
+| u_gen_sp |gen_sp |257 |142 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |737 |402 |96 |557 |0 |0 |
+| u_ADconfig |AD_config |171 |111 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |255 |159 |71 |120 |0 |0 |
+| sampling_fe_a |sampling_fe |3118 |2520 |306 |2070 |25 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |177 |99 |17 |147 |0 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_sort |sort |2910 |2398 |289 |1894 |25 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2452 |2062 |253 |1531 |22 |0 |
+| channelPart |channel_part_8478 |142 |137 |3 |134 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1964 |1648 |197 |1140 |0 |0 |
+| adc_addr_gen |adc_addr_gen |222 |195 |27 |122 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |17 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| insert |insert |916 |628 |170 |620 |0 |0 |
+| ram_switch_state |ram_switch_state |826 |825 |0 |398 |0 |0 |
+| read_ram_i |read_ram |258 |204 |44 |185 |0 |0 |
+| read_ram_addr |read_ram_addr |214 |174 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |41 |27 |4 |30 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |325 |216 |36 |271 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3119 |2390 |349 |2084 |25 |1 |
+| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_ad_sampling |ad_sampling |182 |95 |17 |153 |0 |0 |
+| u0_soft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u_sort |sort_rev |2910 |2285 |332 |1904 |25 |1 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2456 |1953 |290 |1550 |22 |1 |
+| channelPart |channel_part_8478 |133 |120 |3 |129 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1882 |1518 |197 |1138 |0 |0 |
+| adc_addr_gen |adc_addr_gen |194 |167 |27 |109 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |16 |13 |3 |8 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |5 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| insert |insert |970 |637 |170 |675 |0 |0 |
+| ram_switch_state |ram_switch_state |718 |714 |0 |354 |0 |0 |
+| read_ram_i |read_ram_rev |350 |243 |81 |208 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |289 |205 |73 |163 |0 |0 |
+| read_ram_data |read_ram_data_rev |61 |38 |8 |45 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9891
+ #2 2 4230
+ #3 3 1685
+ #4 4 564
+ #5 5-10 772
+ #6 11-50 558
+ #7 51-100 12
+ #8 >500 1
+ Average 2.73
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.018853s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (171.8%)
+
+RUN-1004 : used memory is 1073 MB, reserved memory is 1090 MB, peak memory is 1147 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71497, tnet num: 17630, tinst num: 6788, tnode num: 93908, tedge num: 118747.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.551611s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.7%)
+
+RUN-1004 : used memory is 1076 MB, reserved memory is 1093 MB, peak memory is 1147 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17630 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 2.097438s wall, 2.062500s user + 0.031250s system = 2.093750s CPU (99.8%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1100 MB, peak memory is 1147 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6788
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17808, pip num: 167214
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 501
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3253 valid insts, and 466685 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.433022s wall, 61.796875s user + 0.171875s system = 61.968750s CPU (656.9%)
+
+RUN-1004 : used memory is 1237 MB, reserved memory is 1236 MB, peak memory is 1352 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240315_163759.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_152242.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_152242.log
new file mode 100644
index 0000000..5df293b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_152242.log
@@ -0,0 +1,2239 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 15:22:42 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 59 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.201112s wall, 2.125000s user + 0.062500s system = 2.187500s CPU (99.4%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 311 MB, peak memory is 334 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2937 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17976 instances
+RUN-0007 : 7661 luts, 9092 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20554 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13083 nets have 2 pins
+RUN-1001 : 6431 nets have [3 - 5] pins
+RUN-1001 : 625 nets have [6 - 10] pins
+RUN-1001 : 178 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 793
+RUN-1001 : No | No | Yes | 2017
+RUN-1001 : No | Yes | No | 3473
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17974 instances, 7661 luts, 9092 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5943 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83919, tnet num: 20376, tinst num: 17974, tnode num: 114144, tedge num: 133816.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.150565s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (100.5%)
+
+RUN-1004 : used memory is 522 MB, reserved memory is 509 MB, peak memory is 522 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.956473s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (99.8%)
+
+PHY-3001 : Found 1251 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.06135e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17974.
+PHY-3001 : Level 1 #clusters 2076.
+PHY-3001 : End clustering; 0.122599s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (152.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32919e+06, overlap = 445.531
+PHY-3002 : Step(2): len = 1.22005e+06, overlap = 487.562
+PHY-3002 : Step(3): len = 841774, overlap = 578.125
+PHY-3002 : Step(4): len = 777474, overlap = 630.531
+PHY-3002 : Step(5): len = 622864, overlap = 768.281
+PHY-3002 : Step(6): len = 553504, overlap = 837.812
+PHY-3002 : Step(7): len = 477408, overlap = 906.562
+PHY-3002 : Step(8): len = 429964, overlap = 959.438
+PHY-3002 : Step(9): len = 387962, overlap = 1003.75
+PHY-3002 : Step(10): len = 351228, overlap = 1016.75
+PHY-3002 : Step(11): len = 326271, overlap = 1062.53
+PHY-3002 : Step(12): len = 296098, overlap = 1095.91
+PHY-3002 : Step(13): len = 271439, overlap = 1162.25
+PHY-3002 : Step(14): len = 245485, overlap = 1225.34
+PHY-3002 : Step(15): len = 229374, overlap = 1258.56
+PHY-3002 : Step(16): len = 202910, overlap = 1302.12
+PHY-3002 : Step(17): len = 187936, overlap = 1327.62
+PHY-3002 : Step(18): len = 169212, overlap = 1366.03
+PHY-3002 : Step(19): len = 161020, overlap = 1414.94
+PHY-3002 : Step(20): len = 149800, overlap = 1455.59
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.21716e-06
+PHY-3002 : Step(21): len = 152504, overlap = 1404.19
+PHY-3002 : Step(22): len = 190591, overlap = 1278.66
+PHY-3002 : Step(23): len = 197887, overlap = 1245.81
+PHY-3002 : Step(24): len = 201837, overlap = 1194.28
+PHY-3002 : Step(25): len = 201064, overlap = 1178.62
+PHY-3002 : Step(26): len = 201551, overlap = 1161.03
+PHY-3002 : Step(27): len = 197420, overlap = 1148.75
+PHY-3002 : Step(28): len = 197268, overlap = 1128.81
+PHY-3002 : Step(29): len = 194452, overlap = 1112
+PHY-3002 : Step(30): len = 192450, overlap = 1058
+PHY-3002 : Step(31): len = 189239, overlap = 1052.03
+PHY-3002 : Step(32): len = 186818, overlap = 1054.06
+PHY-3002 : Step(33): len = 184308, overlap = 1069.66
+PHY-3002 : Step(34): len = 183572, overlap = 1073.16
+PHY-3002 : Step(35): len = 181459, overlap = 1070.19
+PHY-3002 : Step(36): len = 180528, overlap = 1077.03
+PHY-3002 : Step(37): len = 178457, overlap = 1077.56
+PHY-3002 : Step(38): len = 177601, overlap = 1077.31
+PHY-3002 : Step(39): len = 176229, overlap = 1073.94
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.43432e-06
+PHY-3002 : Step(40): len = 181271, overlap = 1048.88
+PHY-3002 : Step(41): len = 191348, overlap = 1017.88
+PHY-3002 : Step(42): len = 193943, overlap = 994.406
+PHY-3002 : Step(43): len = 197544, overlap = 983.062
+PHY-3002 : Step(44): len = 199413, overlap = 961.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.86865e-06
+PHY-3002 : Step(45): len = 206533, overlap = 969.938
+PHY-3002 : Step(46): len = 226246, overlap = 900.531
+PHY-3002 : Step(47): len = 238524, overlap = 802.688
+PHY-3002 : Step(48): len = 247998, overlap = 757.031
+PHY-3002 : Step(49): len = 250327, overlap = 725.906
+PHY-3002 : Step(50): len = 249994, overlap = 730.406
+PHY-3002 : Step(51): len = 248249, overlap = 730.875
+PHY-3002 : Step(52): len = 247396, overlap = 721.469
+PHY-3002 : Step(53): len = 246378, overlap = 703.188
+PHY-3002 : Step(54): len = 246351, overlap = 695.906
+PHY-3002 : Step(55): len = 246056, overlap = 689.688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.73729e-06
+PHY-3002 : Step(56): len = 262892, overlap = 676.094
+PHY-3002 : Step(57): len = 285819, overlap = 582.625
+PHY-3002 : Step(58): len = 293390, overlap = 511.344
+PHY-3002 : Step(59): len = 298085, overlap = 479.156
+PHY-3002 : Step(60): len = 297735, overlap = 471.812
+PHY-3002 : Step(61): len = 297760, overlap = 482.5
+PHY-3002 : Step(62): len = 295918, overlap = 489.156
+PHY-3002 : Step(63): len = 295065, overlap = 487.281
+PHY-3002 : Step(64): len = 295252, overlap = 503.031
+PHY-3002 : Step(65): len = 294568, overlap = 505.125
+PHY-3002 : Step(66): len = 295186, overlap = 512.594
+PHY-3002 : Step(67): len = 295689, overlap = 499.75
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.94746e-05
+PHY-3002 : Step(68): len = 310777, overlap = 472.906
+PHY-3002 : Step(69): len = 324457, overlap = 436.031
+PHY-3002 : Step(70): len = 328003, overlap = 385
+PHY-3002 : Step(71): len = 329685, overlap = 377.594
+PHY-3002 : Step(72): len = 329290, overlap = 369.25
+PHY-3002 : Step(73): len = 330290, overlap = 361.156
+PHY-3002 : Step(74): len = 329466, overlap = 356.219
+PHY-3002 : Step(75): len = 331302, overlap = 346.375
+PHY-3002 : Step(76): len = 332816, overlap = 342.344
+PHY-3002 : Step(77): len = 333346, overlap = 344.125
+PHY-3002 : Step(78): len = 331252, overlap = 346.531
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.89492e-05
+PHY-3002 : Step(79): len = 348460, overlap = 327.781
+PHY-3002 : Step(80): len = 359142, overlap = 333.094
+PHY-3002 : Step(81): len = 360141, overlap = 331.344
+PHY-3002 : Step(82): len = 360961, overlap = 335.969
+PHY-3002 : Step(83): len = 361156, overlap = 326.062
+PHY-3002 : Step(84): len = 362882, overlap = 314.875
+PHY-3002 : Step(85): len = 362252, overlap = 325.344
+PHY-3002 : Step(86): len = 365060, overlap = 309.5
+PHY-3002 : Step(87): len = 367016, overlap = 295.781
+PHY-3002 : Step(88): len = 369421, overlap = 300.938
+PHY-3002 : Step(89): len = 368498, overlap = 304.438
+PHY-3002 : Step(90): len = 368784, overlap = 307.5
+PHY-3002 : Step(91): len = 368701, overlap = 302.25
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.78984e-05
+PHY-3002 : Step(92): len = 385958, overlap = 316.062
+PHY-3002 : Step(93): len = 397750, overlap = 307.594
+PHY-3002 : Step(94): len = 396072, overlap = 278.5
+PHY-3002 : Step(95): len = 396675, overlap = 275
+PHY-3002 : Step(96): len = 398785, overlap = 278.469
+PHY-3002 : Step(97): len = 402233, overlap = 274.281
+PHY-3002 : Step(98): len = 399925, overlap = 275
+PHY-3002 : Step(99): len = 401797, overlap = 275.281
+PHY-3002 : Step(100): len = 404660, overlap = 267.156
+PHY-3002 : Step(101): len = 406938, overlap = 270.406
+PHY-3002 : Step(102): len = 404519, overlap = 258.719
+PHY-3002 : Step(103): len = 403619, overlap = 258.688
+PHY-3002 : Step(104): len = 404470, overlap = 257.562
+PHY-3002 : Step(105): len = 406779, overlap = 248.906
+PHY-3002 : Step(106): len = 405050, overlap = 251.844
+PHY-3002 : Step(107): len = 405450, overlap = 255.125
+PHY-3002 : Step(108): len = 406346, overlap = 247.406
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000155797
+PHY-3002 : Step(109): len = 421098, overlap = 235.188
+PHY-3002 : Step(110): len = 431174, overlap = 223.031
+PHY-3002 : Step(111): len = 430658, overlap = 211.312
+PHY-3002 : Step(112): len = 433426, overlap = 200.719
+PHY-3002 : Step(113): len = 437756, overlap = 185.562
+PHY-3002 : Step(114): len = 442888, overlap = 178.844
+PHY-3002 : Step(115): len = 441256, overlap = 181.438
+PHY-3002 : Step(116): len = 440949, overlap = 176.438
+PHY-3002 : Step(117): len = 442307, overlap = 179.125
+PHY-3002 : Step(118): len = 443138, overlap = 175.094
+PHY-3002 : Step(119): len = 439711, overlap = 187.312
+PHY-3002 : Step(120): len = 438829, overlap = 185.938
+PHY-3002 : Step(121): len = 440137, overlap = 183.531
+PHY-3002 : Step(122): len = 441363, overlap = 181.188
+PHY-3002 : Step(123): len = 439760, overlap = 188.281
+PHY-3002 : Step(124): len = 439945, overlap = 184.656
+PHY-3002 : Step(125): len = 440625, overlap = 186.312
+PHY-3002 : Step(126): len = 441147, overlap = 185.344
+PHY-3002 : Step(127): len = 440118, overlap = 189.938
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000291403
+PHY-3002 : Step(128): len = 448709, overlap = 172.844
+PHY-3002 : Step(129): len = 456204, overlap = 167.406
+PHY-3002 : Step(130): len = 456756, overlap = 167.562
+PHY-3002 : Step(131): len = 457637, overlap = 163.438
+PHY-3002 : Step(132): len = 459321, overlap = 159.625
+PHY-3002 : Step(133): len = 460636, overlap = 157.594
+PHY-3002 : Step(134): len = 460172, overlap = 149.906
+PHY-3002 : Step(135): len = 460938, overlap = 156.062
+PHY-3002 : Step(136): len = 463467, overlap = 153.281
+PHY-3002 : Step(137): len = 465546, overlap = 147
+PHY-3002 : Step(138): len = 463953, overlap = 149.156
+PHY-3002 : Step(139): len = 463751, overlap = 147.031
+PHY-3002 : Step(140): len = 464668, overlap = 147.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000563732
+PHY-3002 : Step(141): len = 471538, overlap = 146.688
+PHY-3002 : Step(142): len = 481395, overlap = 136.25
+PHY-3002 : Step(143): len = 484786, overlap = 135.531
+PHY-3002 : Step(144): len = 488015, overlap = 138.062
+PHY-3002 : Step(145): len = 490442, overlap = 137.031
+PHY-3002 : Step(146): len = 491814, overlap = 131.375
+PHY-3002 : Step(147): len = 489052, overlap = 131.562
+PHY-3002 : Step(148): len = 488096, overlap = 130.031
+PHY-3002 : Step(149): len = 489585, overlap = 131.094
+PHY-3002 : Step(150): len = 490906, overlap = 133.062
+PHY-3002 : Step(151): len = 490483, overlap = 135.875
+PHY-3002 : Step(152): len = 491230, overlap = 138.156
+PHY-3002 : Step(153): len = 492463, overlap = 138.219
+PHY-3002 : Step(154): len = 493051, overlap = 140.031
+PHY-3002 : Step(155): len = 491645, overlap = 139.125
+PHY-3002 : Step(156): len = 491063, overlap = 145.219
+PHY-3002 : Step(157): len = 491758, overlap = 141.125
+PHY-3002 : Step(158): len = 492120, overlap = 146.125
+PHY-3002 : Step(159): len = 491443, overlap = 147.219
+PHY-3002 : Step(160): len = 491396, overlap = 149.094
+PHY-3002 : Step(161): len = 492205, overlap = 147
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108487
+PHY-3002 : Step(162): len = 496518, overlap = 140.438
+PHY-3002 : Step(163): len = 503813, overlap = 135.719
+PHY-3002 : Step(164): len = 505448, overlap = 132.344
+PHY-3002 : Step(165): len = 506596, overlap = 129
+PHY-3002 : Step(166): len = 507449, overlap = 130.562
+PHY-3002 : Step(167): len = 507758, overlap = 132.344
+PHY-3002 : Step(168): len = 507008, overlap = 131.156
+PHY-3002 : Step(169): len = 506829, overlap = 134.344
+PHY-3002 : Step(170): len = 507896, overlap = 131.875
+PHY-3002 : Step(171): len = 508721, overlap = 128.562
+PHY-3002 : Step(172): len = 507922, overlap = 131.312
+PHY-3002 : Step(173): len = 507663, overlap = 133.25
+PHY-3002 : Step(174): len = 508401, overlap = 130.75
+PHY-3002 : Step(175): len = 508577, overlap = 129.375
+PHY-3002 : Step(176): len = 508078, overlap = 130.281
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00177433
+PHY-3002 : Step(177): len = 510956, overlap = 128.656
+PHY-3002 : Step(178): len = 516947, overlap = 124.375
+PHY-3002 : Step(179): len = 517995, overlap = 122.75
+PHY-3002 : Step(180): len = 518794, overlap = 125.25
+PHY-3002 : Step(181): len = 520254, overlap = 120.062
+PHY-3002 : Step(182): len = 520968, overlap = 118.781
+PHY-3002 : Step(183): len = 520313, overlap = 117.469
+PHY-3002 : Step(184): len = 519988, overlap = 118.312
+PHY-3002 : Step(185): len = 521377, overlap = 113.312
+PHY-3002 : Step(186): len = 522396, overlap = 111.312
+PHY-3002 : Step(187): len = 521634, overlap = 106.812
+PHY-3002 : Step(188): len = 521432, overlap = 105.719
+PHY-3002 : Step(189): len = 522191, overlap = 108.281
+PHY-3002 : Step(190): len = 523345, overlap = 108.281
+PHY-3002 : Step(191): len = 523573, overlap = 107.344
+PHY-3002 : Step(192): len = 524172, overlap = 103.594
+PHY-3002 : Step(193): len = 525286, overlap = 106.938
+PHY-3002 : Step(194): len = 525821, overlap = 104.688
+PHY-3002 : Step(195): len = 525372, overlap = 104.094
+PHY-3002 : Step(196): len = 525259, overlap = 102.281
+PHY-3002 : Step(197): len = 525527, overlap = 106.562
+PHY-3002 : Step(198): len = 525540, overlap = 106.25
+PHY-3002 : Step(199): len = 525070, overlap = 105.719
+PHY-3002 : Step(200): len = 525070, overlap = 105.719
+PHY-3002 : Step(201): len = 525213, overlap = 103.219
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00304851
+PHY-3002 : Step(202): len = 526439, overlap = 105.5
+PHY-3002 : Step(203): len = 529948, overlap = 105.25
+PHY-3002 : Step(204): len = 531518, overlap = 104.344
+PHY-3002 : Step(205): len = 532644, overlap = 108.969
+PHY-3002 : Step(206): len = 533091, overlap = 107.25
+PHY-3002 : Step(207): len = 533451, overlap = 107.625
+PHY-3002 : Step(208): len = 534092, overlap = 107.812
+PHY-3002 : Step(209): len = 534741, overlap = 112.812
+PHY-3002 : Step(210): len = 535797, overlap = 106.875
+PHY-3002 : Step(211): len = 537561, overlap = 105.5
+PHY-3002 : Step(212): len = 538828, overlap = 103.938
+PHY-3002 : Step(213): len = 539274, overlap = 101
+PHY-3002 : Step(214): len = 539407, overlap = 103.25
+PHY-3002 : Step(215): len = 539521, overlap = 101.094
+PHY-3002 : Step(216): len = 539743, overlap = 103.281
+PHY-3002 : Step(217): len = 539810, overlap = 103.281
+PHY-3002 : Step(218): len = 539514, overlap = 105.531
+PHY-3002 : Step(219): len = 539514, overlap = 105.531
+PHY-3002 : Step(220): len = 539637, overlap = 105.531
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.021818s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (71.6%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715840, over cnt = 1628(4%), over = 7172, worst = 34
+PHY-1001 : End global iterations; 0.716522s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (128.7%)
+
+PHY-1001 : Congestion index: top1 = 79.31, top5 = 60.63, top10 = 51.74, top15 = 46.25.
+PHY-3001 : End congestion estimation; 0.961456s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (121.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.866934s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000122838
+PHY-3002 : Step(221): len = 647939, overlap = 47.4688
+PHY-3002 : Step(222): len = 653276, overlap = 47.3125
+PHY-3002 : Step(223): len = 649084, overlap = 51.125
+PHY-3002 : Step(224): len = 644668, overlap = 49.5938
+PHY-3002 : Step(225): len = 639160, overlap = 45.0938
+PHY-3002 : Step(226): len = 636263, overlap = 42.0625
+PHY-3002 : Step(227): len = 634049, overlap = 36.9062
+PHY-3002 : Step(228): len = 631104, overlap = 33.5
+PHY-3002 : Step(229): len = 627887, overlap = 25.3125
+PHY-3002 : Step(230): len = 626676, overlap = 23.3438
+PHY-3002 : Step(231): len = 625097, overlap = 22.0312
+PHY-3002 : Step(232): len = 623129, overlap = 24.5
+PHY-3002 : Step(233): len = 622458, overlap = 30.7188
+PHY-3002 : Step(234): len = 623440, overlap = 35.5
+PHY-3002 : Step(235): len = 622770, overlap = 44.4375
+PHY-3002 : Step(236): len = 622360, overlap = 50.875
+PHY-3002 : Step(237): len = 622627, overlap = 54.9062
+PHY-3002 : Step(238): len = 621030, overlap = 53.75
+PHY-3002 : Step(239): len = 619460, overlap = 54.9688
+PHY-3002 : Step(240): len = 619249, overlap = 53.3438
+PHY-3002 : Step(241): len = 617589, overlap = 54.4375
+PHY-3002 : Step(242): len = 615213, overlap = 50.9062
+PHY-3002 : Step(243): len = 613296, overlap = 48.8438
+PHY-3002 : Step(244): len = 612228, overlap = 49.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000245676
+PHY-3002 : Step(245): len = 614718, overlap = 46.75
+PHY-3002 : Step(246): len = 620720, overlap = 42.6562
+PHY-3002 : Step(247): len = 622762, overlap = 41.1562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000432693
+PHY-3002 : Step(248): len = 631539, overlap = 40.3438
+PHY-3002 : Step(249): len = 649375, overlap = 48.7188
+PHY-3002 : Step(250): len = 653698, overlap = 44.7188
+PHY-3002 : Step(251): len = 652845, overlap = 43.9062
+PHY-3002 : Step(252): len = 651837, overlap = 44.3125
+PHY-3002 : Step(253): len = 651509, overlap = 44.4062
+PHY-3002 : Step(254): len = 650075, overlap = 46.4375
+PHY-3002 : Step(255): len = 650644, overlap = 49.2188
+PHY-3002 : Step(256): len = 650870, overlap = 49.5938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000834768
+PHY-3002 : Step(257): len = 656955, overlap = 48.6875
+PHY-3002 : Step(258): len = 668970, overlap = 51.125
+PHY-3002 : Step(259): len = 671997, overlap = 59.0938
+PHY-3002 : Step(260): len = 674462, overlap = 56.2812
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 35/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 755584, over cnt = 2720(7%), over = 13210, worst = 42
+PHY-1001 : End global iterations; 1.551999s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (129.9%)
+
+PHY-1001 : Congestion index: top1 = 92.41, top5 = 71.24, top10 = 62.20, top15 = 56.62.
+PHY-3001 : End congestion estimation; 1.853179s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (125.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.880154s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000108587
+PHY-3002 : Step(261): len = 663948, overlap = 230.625
+PHY-3002 : Step(262): len = 659385, overlap = 180.375
+PHY-3002 : Step(263): len = 646714, overlap = 172.281
+PHY-3002 : Step(264): len = 639837, overlap = 156.938
+PHY-3002 : Step(265): len = 633110, overlap = 137.25
+PHY-3002 : Step(266): len = 627941, overlap = 127.125
+PHY-3002 : Step(267): len = 622688, overlap = 131
+PHY-3002 : Step(268): len = 618836, overlap = 127.031
+PHY-3002 : Step(269): len = 616733, overlap = 121.781
+PHY-3002 : Step(270): len = 612174, overlap = 120.25
+PHY-3002 : Step(271): len = 609877, overlap = 118.094
+PHY-3002 : Step(272): len = 608192, overlap = 116.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000217175
+PHY-3002 : Step(273): len = 608064, overlap = 110.031
+PHY-3002 : Step(274): len = 610644, overlap = 103.594
+PHY-3002 : Step(275): len = 612910, overlap = 99.6562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000434349
+PHY-3002 : Step(276): len = 618954, overlap = 91.3438
+PHY-3002 : Step(277): len = 627753, overlap = 83.75
+PHY-3002 : Step(278): len = 632770, overlap = 79.3125
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83919, tnet num: 20376, tinst num: 17974, tnode num: 114144, tedge num: 133816.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.516509s wall, 1.468750s user + 0.046875s system = 1.515625s CPU (99.9%)
+
+RUN-1004 : used memory is 566 MB, reserved memory is 558 MB, peak memory is 700 MB
+OPT-1001 : Total overflow 402.84 peak overflow 3.72
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 754/20554.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 729464, over cnt = 3046(8%), over = 11000, worst = 22
+PHY-1001 : End global iterations; 1.318431s wall, 1.937500s user + 0.046875s system = 1.984375s CPU (150.5%)
+
+PHY-1001 : Congestion index: top1 = 69.63, top5 = 55.98, top10 = 50.35, top15 = 46.90.
+PHY-1001 : End incremental global routing; 1.652501s wall, 2.250000s user + 0.046875s system = 2.296875s CPU (139.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20376 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.891067s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17843 has valid locations, 310 needs to be replaced
+PHY-3001 : design contains 18238 instances, 7759 luts, 9258 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6063 pins
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 656744
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17048/20818.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 745800, over cnt = 3071(8%), over = 11052, worst = 22
+PHY-1001 : End global iterations; 0.232400s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (121.0%)
+
+PHY-1001 : Congestion index: top1 = 69.44, top5 = 56.24, top10 = 50.68, top15 = 47.34.
+PHY-3001 : End congestion estimation; 0.479338s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (107.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84967, tnet num: 20640, tinst num: 18238, tnode num: 115712, tedge num: 135384.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.423318s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (101.0%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 605 MB, peak memory is 704 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20640 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.358295s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(279): len = 655744, overlap = 0.0625
+PHY-3002 : Step(280): len = 655376, overlap = 0
+PHY-3002 : Step(281): len = 655079, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17139/20818.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743784, over cnt = 3090(8%), over = 11155, worst = 22
+PHY-1001 : End global iterations; 0.196939s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (166.6%)
+
+PHY-1001 : Congestion index: top1 = 69.87, top5 = 56.64, top10 = 51.10, top15 = 47.68.
+PHY-3001 : End congestion estimation; 0.444830s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (130.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20640 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.911558s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000422287
+PHY-3002 : Step(282): len = 654720, overlap = 82.3125
+PHY-3002 : Step(283): len = 654634, overlap = 81.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000844574
+PHY-3002 : Step(284): len = 654915, overlap = 81.0938
+PHY-3002 : Step(285): len = 655387, overlap = 81.2812
+PHY-3001 : Final: Len = 655387, Over = 81.2812
+PHY-3001 : End incremental placement; 4.815765s wall, 5.187500s user + 0.218750s system = 5.406250s CPU (112.3%)
+
+OPT-1001 : Total overflow 406.62 peak overflow 3.72
+OPT-1001 : End high-fanout net optimization; 7.881397s wall, 8.937500s user + 0.265625s system = 9.203125s CPU (116.8%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 702, peak = 722.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17082/20818.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 745680, over cnt = 3013(8%), over = 10060, worst = 22
+PHY-1002 : len = 791000, over cnt = 2160(6%), over = 5628, worst = 22
+PHY-1002 : len = 835792, over cnt = 915(2%), over = 2262, worst = 15
+PHY-1002 : len = 865656, over cnt = 201(0%), over = 426, worst = 13
+PHY-1002 : len = 872496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.598437s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (150.5%)
+
+PHY-1001 : Congestion index: top1 = 58.71, top5 = 50.86, top10 = 46.93, top15 = 44.44.
+OPT-1001 : End congestion update; 1.866140s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (143.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20640 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.793035s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (100.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 119 cells processed and 20750 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 1934 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 2.960925s wall, 3.734375s user + 0.031250s system = 3.765625s CPU (127.2%)
+
+OPT-1001 : Current memory(MB): used = 685, reserve = 685, peak = 722.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17156/20820.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 873272, over cnt = 67(0%), over = 97, worst = 3
+PHY-1002 : len = 872888, over cnt = 42(0%), over = 46, worst = 3
+PHY-1002 : len = 873096, over cnt = 26(0%), over = 27, worst = 2
+PHY-1002 : len = 873504, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 873616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.683483s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (112.0%)
+
+PHY-1001 : Congestion index: top1 = 58.51, top5 = 50.65, top10 = 46.69, top15 = 44.28.
+OPT-1001 : End congestion update; 0.947538s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (108.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779908s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 4500 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.838683s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (104.5%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 690, peak = 722.
+OPT-1001 : End physical optimization; 14.498280s wall, 16.343750s user + 0.375000s system = 16.718750s CPU (115.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7759 LUT to BLE ...
+SYN-4008 : Packed 7759 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6127 remaining SEQ's ...
+SYN-4005 : Packed 3992 SEQ with LUT/SLICE
+SYN-4006 : 920 single LUT's are left
+SYN-4006 : 2135 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9894/13729 primitive instances ...
+PHY-3001 : End packing; 1.623717s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6706 instances
+RUN-1001 : 3279 mslices, 3279 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17811 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9960 nets have 2 pins
+RUN-1001 : 6479 nets have [3 - 5] pins
+RUN-1001 : 752 nets have [6 - 10] pins
+RUN-1001 : 292 nets have [11 - 20] pins
+RUN-1001 : 296 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6704 instances, 6558 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3500 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 666866, Over = 229.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7685/17811.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 820632, over cnt = 1951(5%), over = 3155, worst = 8
+PHY-1002 : len = 827248, over cnt = 1294(3%), over = 1876, worst = 8
+PHY-1002 : len = 838144, over cnt = 707(2%), over = 980, worst = 5
+PHY-1002 : len = 846352, over cnt = 328(0%), over = 444, worst = 5
+PHY-1002 : len = 852264, over cnt = 51(0%), over = 62, worst = 3
+PHY-1001 : End global iterations; 1.512215s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (135.4%)
+
+PHY-1001 : Congestion index: top1 = 58.12, top5 = 49.89, top10 = 46.04, top15 = 43.62.
+PHY-3001 : End congestion estimation; 1.892138s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (128.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71206, tnet num: 17633, tinst num: 6704, tnode num: 93421, tedge num: 118304.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.603195s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.4%)
+
+RUN-1004 : used memory is 605 MB, reserved memory is 608 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17633 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.494847s wall, 2.484375s user + 0.015625s system = 2.500000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.2664e-05
+PHY-3002 : Step(286): len = 655562, overlap = 227.25
+PHY-3002 : Step(287): len = 649141, overlap = 227
+PHY-3002 : Step(288): len = 645052, overlap = 239.25
+PHY-3002 : Step(289): len = 642567, overlap = 248.5
+PHY-3002 : Step(290): len = 639550, overlap = 250
+PHY-3002 : Step(291): len = 636620, overlap = 245
+PHY-3002 : Step(292): len = 635107, overlap = 243.25
+PHY-3002 : Step(293): len = 633064, overlap = 241
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000105328
+PHY-3002 : Step(294): len = 636479, overlap = 234.75
+PHY-3002 : Step(295): len = 641540, overlap = 221.5
+PHY-3002 : Step(296): len = 641270, overlap = 223.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000210656
+PHY-3002 : Step(297): len = 649394, overlap = 203.5
+PHY-3002 : Step(298): len = 654526, overlap = 194.5
+PHY-3002 : Step(299): len = 653441, overlap = 199
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.342500s wall, 0.343750s user + 0.562500s system = 0.906250s CPU (264.6%)
+
+PHY-3001 : Trial Legalized: Len = 736610
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 749/17811.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843680, over cnt = 2581(7%), over = 4343, worst = 8
+PHY-1002 : len = 859416, over cnt = 1560(4%), over = 2309, worst = 8
+PHY-1002 : len = 881928, over cnt = 453(1%), over = 664, worst = 8
+PHY-1002 : len = 892136, over cnt = 37(0%), over = 47, worst = 5
+PHY-1002 : len = 892952, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations; 2.367960s wall, 3.250000s user + 0.046875s system = 3.296875s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 54.96, top5 = 49.38, top10 = 46.59, top15 = 44.56.
+PHY-3001 : End congestion estimation; 2.826443s wall, 3.718750s user + 0.046875s system = 3.765625s CPU (133.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17633 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.856321s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160121
+PHY-3002 : Step(300): len = 710106, overlap = 33.75
+PHY-3002 : Step(301): len = 693964, overlap = 57.5
+PHY-3002 : Step(302): len = 682178, overlap = 84.5
+PHY-3002 : Step(303): len = 674115, overlap = 98.25
+PHY-3002 : Step(304): len = 667761, overlap = 114.25
+PHY-3002 : Step(305): len = 664653, overlap = 124.25
+PHY-3002 : Step(306): len = 662504, overlap = 135.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320241
+PHY-3002 : Step(307): len = 666705, overlap = 131.75
+PHY-3002 : Step(308): len = 671187, overlap = 135.75
+PHY-3002 : Step(309): len = 672815, overlap = 140.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000640483
+PHY-3002 : Step(310): len = 675382, overlap = 138.75
+PHY-3002 : Step(311): len = 682451, overlap = 132.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032072s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.4%)
+
+PHY-3001 : Legalized: Len = 710886, Over = 0
+PHY-3001 : Spreading special nets. 417 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.094435s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (99.3%)
+
+PHY-3001 : 608 instances has been re-located, deltaX = 194, deltaY = 351, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 720042, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71206, tnet num: 17633, tinst num: 6707, tnode num: 93421, tedge num: 118304.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.812168s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.2%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 635 MB, peak memory is 722 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4066/17811.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841200, over cnt = 2378(6%), over = 3821, worst = 7
+PHY-1002 : len = 851680, over cnt = 1548(4%), over = 2271, worst = 7
+PHY-1002 : len = 874440, over cnt = 427(1%), over = 567, worst = 5
+PHY-1002 : len = 883184, over cnt = 41(0%), over = 42, worst = 2
+PHY-1002 : len = 883904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations; 1.915535s wall, 2.796875s user + 0.015625s system = 2.812500s CPU (146.8%)
+
+PHY-1001 : Congestion index: top1 = 54.27, top5 = 48.40, top10 = 45.57, top15 = 43.58.
+PHY-1001 : End incremental global routing; 2.300381s wall, 3.171875s user + 0.031250s system = 3.203125s CPU (139.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17633 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.848923s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (101.2%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6614 has valid locations, 30 needs to be replaced
+PHY-3001 : design contains 6732 instances, 6583 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 726571
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16213/17839.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891712, over cnt = 119(0%), over = 141, worst = 7
+PHY-1002 : len = 891784, over cnt = 67(0%), over = 77, worst = 2
+PHY-1002 : len = 892336, over cnt = 20(0%), over = 21, worst = 2
+PHY-1002 : len = 892504, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 892704, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.752960s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (112.1%)
+
+PHY-1001 : Congestion index: top1 = 54.35, top5 = 48.55, top10 = 45.74, top15 = 43.81.
+PHY-3001 : End congestion estimation; 1.055845s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (109.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71450, tnet num: 17661, tinst num: 6732, tnode num: 93717, tedge num: 118621.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.815214s wall, 1.765625s user + 0.046875s system = 1.812500s CPU (99.9%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 658 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17661 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.672808s wall, 2.593750s user + 0.062500s system = 2.656250s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(312): len = 725878, overlap = 0
+PHY-3002 : Step(313): len = 725091, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16201/17839.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 890544, over cnt = 73(0%), over = 106, worst = 7
+PHY-1002 : len = 890848, over cnt = 27(0%), over = 34, worst = 4
+PHY-1002 : len = 891224, over cnt = 11(0%), over = 12, worst = 2
+PHY-1002 : len = 891376, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 891392, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.755367s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (111.7%)
+
+PHY-1001 : Congestion index: top1 = 54.33, top5 = 48.62, top10 = 45.82, top15 = 43.87.
+PHY-3001 : End congestion estimation; 1.071100s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (109.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17661 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.843691s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00045665
+PHY-3002 : Step(314): len = 724977, overlap = 0.25
+PHY-3002 : Step(315): len = 724800, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005464s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (286.0%)
+
+PHY-3001 : Legalized: Len = 724957, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058088s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.6%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 2, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 725103, Over = 0
+PHY-3001 : End incremental placement; 6.110644s wall, 6.218750s user + 0.171875s system = 6.390625s CPU (104.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.718488s wall, 10.687500s user + 0.218750s system = 10.906250s CPU (112.2%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 712, peak = 728.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16155/17839.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891168, over cnt = 96(0%), over = 142, worst = 8
+PHY-1002 : len = 891176, over cnt = 60(0%), over = 74, worst = 5
+PHY-1002 : len = 891992, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 892064, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 892136, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.792739s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (112.3%)
+
+PHY-1001 : Congestion index: top1 = 54.42, top5 = 48.63, top10 = 45.80, top15 = 43.83.
+OPT-1001 : End congestion update; 1.101623s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (107.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17661 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.690385s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.8%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6644 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6732 instances, 6583 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 734248, Over = 0
+PHY-3001 : Spreading special nets. 26 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064912s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (120.4%)
+
+PHY-3001 : 38 instances has been re-located, deltaX = 18, deltaY = 24, maxDist = 2.
+PHY-3001 : Final: Len = 734916, Over = 0
+PHY-3001 : End incremental legalization; 0.378920s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.0%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 59 cells processed and 20825 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6644 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6732 instances, 6583 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 735178, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069299s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (112.7%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 12, deltaY = 4, maxDist = 3.
+PHY-3001 : Final: Len = 735254, Over = 0
+PHY-3001 : End incremental legalization; 0.423732s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (106.9%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 29 cells processed and 2330 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6644 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6732 instances, 6583 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3568 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 735684, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058148s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.5%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 6, deltaY = 9, maxDist = 4.
+PHY-3001 : Final: Len = 735924, Over = 0
+PHY-3001 : End incremental legalization; 0.375272s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.9%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 18 cells processed and 1103 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 736121, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056266s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (83.3%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 736135, Over = 0
+PHY-3001 : End incremental legalization; 0.367412s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.8%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 409 slack improved
+OPT-1001 : End bottleneck based optimization; 3.874481s wall, 4.015625s user + 0.031250s system = 4.046875s CPU (104.4%)
+
+OPT-1001 : Current memory(MB): used = 714, reserve = 714, peak = 728.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15831/17842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902856, over cnt = 146(0%), over = 199, worst = 8
+PHY-1002 : len = 903048, over cnt = 93(0%), over = 113, worst = 5
+PHY-1002 : len = 903320, over cnt = 55(0%), over = 66, worst = 3
+PHY-1002 : len = 904032, over cnt = 21(0%), over = 24, worst = 2
+PHY-1002 : len = 904360, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.829465s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (114.9%)
+
+PHY-1001 : Congestion index: top1 = 55.02, top5 = 48.64, top10 = 45.82, top15 = 43.90.
+OPT-1001 : End congestion update; 1.155091s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (109.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.975266s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (99.3%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 735913, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057730s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.2%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 4, deltaY = 8, maxDist = 4.
+PHY-3001 : Final: Len = 736367, Over = 0
+PHY-3001 : End incremental legalization; 0.363993s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.7%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 12 cells processed and 1300 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.611724s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (104.1%)
+
+OPT-1001 : Current memory(MB): used = 714, reserve = 714, peak = 728.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.692729s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16224/17842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904400, over cnt = 23(0%), over = 26, worst = 2
+PHY-1002 : len = 904288, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 904344, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 904464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.578998s wall, 0.578125s user + 0.031250s system = 0.609375s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 48.55, top10 = 45.76, top15 = 43.86.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.688754s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (97.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.448276
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 736367, Over = 0
+PHY-3001 : End spreading; 0.056698s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.2%)
+
+PHY-3001 : Final: Len = 736367, Over = 0
+PHY-3001 : End incremental legalization; 0.361902s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.684424s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.4%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16248/17842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.158362s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.7%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 48.55, top10 = 45.76, top15 = 43.86.
+OPT-1001 : End congestion update; 0.460427s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.685296s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (98.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 736199, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057427s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 736367, Over = 0
+PHY-3001 : End incremental legalization; 0.365870s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.616920s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.5%)
+
+OPT-1001 : Current memory(MB): used = 714, reserve = 714, peak = 728.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16248/17842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.130849s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.5%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 48.55, top10 = 45.76, top15 = 43.86.
+OPT-1001 : End congestion update; 0.437927s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (103.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717634s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 736199, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056895s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 736367, Over = 0
+PHY-3001 : End incremental legalization; 0.388170s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.6%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3569 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 736199, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.055946s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (111.7%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 736367, Over = 0
+PHY-3001 : End incremental legalization; 0.365390s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.6%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.182037s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (100.3%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 714, peak = 728.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.691276s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 715, reserve = 714, peak = 728.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.691969s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.6%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16248/17842.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126815s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.6%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 48.55, top10 = 45.76, top15 = 43.86.
+RUN-1001 : End congestion update; 0.431404s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.4%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.126550s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (101.2%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 714, peak = 728.
+OPT-1001 : End physical optimization; 27.327642s wall, 28.484375s user + 0.312500s system = 28.796875s CPU (105.4%)
+
+RUN-1003 : finish command "place" in 70.273198s wall, 100.187500s user + 6.515625s system = 106.703125s CPU (151.8%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 632 MB, peak memory is 728 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.630124s wall, 2.812500s user + 0.015625s system = 2.828125s CPU (173.5%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 633 MB, peak memory is 728 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6738 instances
+RUN-1001 : 3287 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17842 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9954 nets have 2 pins
+RUN-1001 : 6476 nets have [3 - 5] pins
+RUN-1001 : 779 nets have [6 - 10] pins
+RUN-1001 : 295 nets have [11 - 20] pins
+RUN-1001 : 310 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71476, tnet num: 17664, tinst num: 6736, tnode num: 93754, tedge num: 118658.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.557441s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (98.3%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 607 MB, peak memory is 728 MB
+PHY-1001 : 3287 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 836904, over cnt = 2591(7%), over = 4262, worst = 8
+PHY-1002 : len = 854136, over cnt = 1614(4%), over = 2330, worst = 7
+PHY-1002 : len = 875808, over cnt = 510(1%), over = 728, worst = 7
+PHY-1002 : len = 885896, over cnt = 32(0%), over = 39, worst = 3
+PHY-1002 : len = 886928, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.941963s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (133.3%)
+
+PHY-1001 : Congestion index: top1 = 54.46, top5 = 48.18, top10 = 45.31, top15 = 43.40.
+PHY-1001 : End global routing; 3.259844s wall, 4.203125s user + 0.031250s system = 4.234375s CPU (129.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 695, reserve = 702, peak = 728.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 968, reserve = 975, peak = 968.
+PHY-1001 : End build detailed router design. 3.962710s wall, 3.890625s user + 0.062500s system = 3.953125s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267976, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.746379s wall, 4.750000s user + 0.000000s system = 4.750000s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 268032, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.457549s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.0%)
+
+PHY-1001 : Current memory(MB): used = 1003, reserve = 1012, peak = 1003.
+PHY-1001 : End phase 1; 5.215925s wall, 5.218750s user + 0.000000s system = 5.218750s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.22997e+06, over cnt = 1813(0%), over = 1817, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1020, reserve = 1025, peak = 1020.
+PHY-1001 : End initial routed; 27.864516s wall, 58.484375s user + 0.312500s system = 58.796875s CPU (211.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16764(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.811 | -0.811 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.992532s wall, 4.000000s user + 0.000000s system = 4.000000s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1029, reserve = 1034, peak = 1029.
+PHY-1001 : End phase 2; 31.857115s wall, 62.484375s user + 0.312500s system = 62.796875s CPU (197.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.708ns STNS -0.708ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135958s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.9%)
+
+PHY-1022 : len = 2.22998e+06, over cnt = 1814(0%), over = 1818, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.394683s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.19594e+06, over cnt = 568(0%), over = 568, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.745813s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (159.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.19509e+06, over cnt = 138(0%), over = 138, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.674415s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (127.4%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.19594e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.315183s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (119.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.19614e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.216073s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.19623e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.221917s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.19623e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.269161s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (98.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.19623e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.380874s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.6%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.19623e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.176651s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (88.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.19623e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.177573s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (105.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.19623e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.226553s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.19622e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.245503s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.19623e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.323406s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (101.5%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.19623e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.170015s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.19617e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.160156s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16764(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.708 | -0.708 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.852977s wall, 3.859375s user + 0.000000s system = 3.859375s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 544 feed throughs used by 398 nets
+PHY-1001 : End commit to database; 2.224400s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1128, reserve = 1139, peak = 1128.
+PHY-1001 : End phase 3; 12.183962s wall, 13.406250s user + 0.062500s system = 13.468750s CPU (110.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.708ns STNS -0.708ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.133992s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.3%)
+
+PHY-1022 : len = 2.19617e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.366966s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.708ns, -0.708ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16764(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.708 | -0.708 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.822160s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 544 feed throughs used by 398 nets
+PHY-1001 : End commit to database; 2.336124s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1136, reserve = 1147, peak = 1136.
+PHY-1001 : End phase 4; 6.552049s wall, 6.562500s user + 0.000000s system = 6.562500s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.19617e+06
+PHY-1001 : Current memory(MB): used = 1139, reserve = 1150, peak = 1139.
+PHY-1001 : End export database. 0.061305s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.9%)
+
+PHY-1001 : End detail routing; 60.226037s wall, 92.031250s user + 0.437500s system = 92.468750s CPU (153.5%)
+
+RUN-1003 : finish command "route" in 66.077721s wall, 98.812500s user + 0.468750s system = 99.281250s CPU (150.2%)
+
+RUN-1004 : used memory is 1065 MB, reserved memory is 1084 MB, peak memory is 1139 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10191 out of 19600 51.99%
+#reg 9402 out of 19600 47.97%
+#le 12304
+ #lut only 2902 out of 12304 23.59%
+ #reg only 2113 out of 12304 17.17%
+ #lut® 7289 out of 12304 59.24%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 17
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1773
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1400
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1264
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 956
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 133
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 74
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_261.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_242.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P84 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE NONE
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P109 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P15 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P110 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P148 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12304 |9164 |1027 |9432 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |536 |460 |23 |428 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |91 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |49 |49 |0 |23 |0 |0 |
+| U_ecc_gen |ecc_gen |8 |8 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |757 |355 |96 |577 |0 |0 |
+| u_ADconfig |AD_config |187 |120 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |258 |161 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |732 |388 |96 |556 |0 |0 |
+| u_ADconfig |AD_config |169 |123 |25 |125 |0 |0 |
+| u_gen_sp |gen_sp |247 |145 |71 |115 |0 |0 |
+| sampling_fe_a |sampling_fe |2976 |2411 |306 |2088 |25 |0 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |179 |113 |17 |149 |0 |0 |
+| u0_soft_n |cdc_sync |5 |0 |0 |5 |0 |0 |
+| u_sort |sort |2766 |2290 |289 |1908 |25 |0 |
+| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2299 |1931 |253 |1551 |22 |0 |
+| channelPart |channel_part_8478 |146 |134 |3 |142 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1802 |1504 |197 |1155 |0 |0 |
+| adc_addr_gen |adc_addr_gen |210 |183 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |13 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |19 |16 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |995 |726 |170 |685 |0 |0 |
+| ram_switch_state |ram_switch_state |597 |595 |0 |347 |0 |0 |
+| read_ram_i |read_ram |270 |225 |44 |187 |0 |0 |
+| read_ram_addr |read_ram_addr |226 |186 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |42 |37 |4 |33 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |309 |217 |36 |263 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3181 |2528 |349 |2075 |25 |1 |
+| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_ad_sampling |ad_sampling |172 |105 |17 |141 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |2978 |2395 |332 |1903 |25 |1 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2540 |2042 |290 |1558 |22 |1 |
+| channelPart |channel_part_8478 |136 |126 |3 |132 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1954 |1584 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |204 |177 |27 |98 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |10 |3 |3 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |975 |633 |170 |683 |0 |0 |
+| ram_switch_state |ram_switch_state |775 |774 |0 |370 |0 |0 |
+| read_ram_i |read_ram_rev |365 |264 |81 |205 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |309 |224 |73 |164 |0 |0 |
+| read_ram_data |read_ram_data_rev |56 |40 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9892
+ #2 2 4227
+ #3 3 1689
+ #4 4 557
+ #5 5-10 821
+ #6 11-50 550
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 1.996100s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (171.4%)
+
+RUN-1004 : used memory is 1066 MB, reserved memory is 1086 MB, peak memory is 1139 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71476, tnet num: 17664, tinst num: 6736, tnode num: 93754, tedge num: 118658.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.551212s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.7%)
+
+RUN-1004 : used memory is 1070 MB, reserved memory is 1089 MB, peak memory is 1139 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17664 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 2.080943s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (99.9%)
+
+RUN-1004 : used memory is 1078 MB, reserved memory is 1095 MB, peak memory is 1139 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6736
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17842, pip num: 166450
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 544
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 466297 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.682018s wall, 66.312500s user + 0.078125s system = 66.390625s CPU (685.7%)
+
+RUN-1004 : used memory is 1232 MB, reserved memory is 1236 MB, peak memory is 1347 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_152242.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_154955.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_154955.log
new file mode 100644
index 0000000..74907e6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_154955.log
@@ -0,0 +1,2030 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 15:49:55 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.198768s wall, 2.078125s user + 0.109375s system = 2.187500s CPU (99.5%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 315 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2224 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2064 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18021 instances
+RUN-0007 : 7676 luts, 9122 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20605 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13131 nets have 2 pins
+RUN-1001 : 6443 nets have [3 - 5] pins
+RUN-1001 : 608 nets have [6 - 10] pins
+RUN-1001 : 185 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3489
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18019 instances, 7676 luts, 9122 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5975 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84120, tnet num: 20427, tinst num: 18019, tnode num: 114459, tedge num: 134136.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.144258s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (99.7%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 514 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.907405s wall, 1.828125s user + 0.078125s system = 1.906250s CPU (99.9%)
+
+PHY-3001 : Found 1247 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.0266e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18019.
+PHY-3001 : Level 1 #clusters 2063.
+PHY-3001 : End clustering; 0.127110s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (159.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31488e+06, overlap = 442.719
+PHY-3002 : Step(2): len = 1.22753e+06, overlap = 502.031
+PHY-3002 : Step(3): len = 875003, overlap = 573.406
+PHY-3002 : Step(4): len = 780720, overlap = 612.812
+PHY-3002 : Step(5): len = 632679, overlap = 760.719
+PHY-3002 : Step(6): len = 580762, overlap = 801.156
+PHY-3002 : Step(7): len = 485750, overlap = 893.781
+PHY-3002 : Step(8): len = 436581, overlap = 929.281
+PHY-3002 : Step(9): len = 388206, overlap = 990.281
+PHY-3002 : Step(10): len = 357299, overlap = 1047.91
+PHY-3002 : Step(11): len = 323725, overlap = 1114.97
+PHY-3002 : Step(12): len = 295659, overlap = 1166.53
+PHY-3002 : Step(13): len = 275541, overlap = 1217.12
+PHY-3002 : Step(14): len = 242944, overlap = 1289.97
+PHY-3002 : Step(15): len = 223898, overlap = 1340.84
+PHY-3002 : Step(16): len = 194052, overlap = 1381.69
+PHY-3002 : Step(17): len = 180121, overlap = 1407.5
+PHY-3002 : Step(18): len = 160262, overlap = 1440.81
+PHY-3002 : Step(19): len = 152661, overlap = 1442.91
+PHY-3002 : Step(20): len = 137996, overlap = 1460.47
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.33472e-07
+PHY-3002 : Step(21): len = 139337, overlap = 1422.19
+PHY-3002 : Step(22): len = 168810, overlap = 1355.69
+PHY-3002 : Step(23): len = 178428, overlap = 1284.69
+PHY-3002 : Step(24): len = 186613, overlap = 1207.69
+PHY-3002 : Step(25): len = 186944, overlap = 1170.47
+PHY-3002 : Step(26): len = 186619, overlap = 1170.5
+PHY-3002 : Step(27): len = 183601, overlap = 1155.41
+PHY-3002 : Step(28): len = 181745, overlap = 1123.81
+PHY-3002 : Step(29): len = 179730, overlap = 1133.69
+PHY-3002 : Step(30): len = 179187, overlap = 1124.16
+PHY-3002 : Step(31): len = 178740, overlap = 1117.75
+PHY-3002 : Step(32): len = 177848, overlap = 1139.97
+PHY-3002 : Step(33): len = 175875, overlap = 1162.06
+PHY-3002 : Step(34): len = 174102, overlap = 1159.47
+PHY-3002 : Step(35): len = 171566, overlap = 1148.97
+PHY-3002 : Step(36): len = 170752, overlap = 1150.12
+PHY-3002 : Step(37): len = 168729, overlap = 1140.62
+PHY-3002 : Step(38): len = 168071, overlap = 1135.72
+PHY-3002 : Step(39): len = 166735, overlap = 1132.47
+PHY-3002 : Step(40): len = 166623, overlap = 1105.31
+PHY-3002 : Step(41): len = 165643, overlap = 1083.72
+PHY-3002 : Step(42): len = 164231, overlap = 1115.53
+PHY-3002 : Step(43): len = 163262, overlap = 1128.59
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.86694e-06
+PHY-3002 : Step(44): len = 164129, overlap = 1110.16
+PHY-3002 : Step(45): len = 174075, overlap = 1086.34
+PHY-3002 : Step(46): len = 179862, overlap = 1055.22
+PHY-3002 : Step(47): len = 186440, overlap = 1067.19
+PHY-3002 : Step(48): len = 187969, overlap = 1053.56
+PHY-3002 : Step(49): len = 189484, overlap = 1034.41
+PHY-3002 : Step(50): len = 188407, overlap = 1034.38
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.73389e-06
+PHY-3002 : Step(51): len = 196066, overlap = 1008.44
+PHY-3002 : Step(52): len = 212335, overlap = 941.5
+PHY-3002 : Step(53): len = 218191, overlap = 878
+PHY-3002 : Step(54): len = 225134, overlap = 847.156
+PHY-3002 : Step(55): len = 225575, overlap = 835.75
+PHY-3002 : Step(56): len = 227409, overlap = 829.625
+PHY-3002 : Step(57): len = 227300, overlap = 819.906
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.46778e-06
+PHY-3002 : Step(58): len = 242145, overlap = 800.438
+PHY-3002 : Step(59): len = 265821, overlap = 727.438
+PHY-3002 : Step(60): len = 278244, overlap = 676.062
+PHY-3002 : Step(61): len = 284723, overlap = 630.094
+PHY-3002 : Step(62): len = 284336, overlap = 597.562
+PHY-3002 : Step(63): len = 283825, overlap = 563.781
+PHY-3002 : Step(64): len = 281788, overlap = 566.656
+PHY-3002 : Step(65): len = 279990, overlap = 559.531
+PHY-3002 : Step(66): len = 278073, overlap = 554.562
+PHY-3002 : Step(67): len = 278173, overlap = 554.156
+PHY-3002 : Step(68): len = 276524, overlap = 564.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.49356e-05
+PHY-3002 : Step(69): len = 292425, overlap = 535.344
+PHY-3002 : Step(70): len = 311340, overlap = 512.531
+PHY-3002 : Step(71): len = 319408, overlap = 470.5
+PHY-3002 : Step(72): len = 321033, overlap = 464.188
+PHY-3002 : Step(73): len = 319271, overlap = 481.875
+PHY-3002 : Step(74): len = 318837, overlap = 455.719
+PHY-3002 : Step(75): len = 316221, overlap = 450.375
+PHY-3002 : Step(76): len = 317617, overlap = 417.25
+PHY-3002 : Step(77): len = 319477, overlap = 423.219
+PHY-3002 : Step(78): len = 321008, overlap = 413.469
+PHY-3002 : Step(79): len = 320438, overlap = 410.938
+PHY-3002 : Step(80): len = 320758, overlap = 403.719
+PHY-3002 : Step(81): len = 321824, overlap = 392.312
+PHY-3002 : Step(82): len = 322476, overlap = 376.062
+PHY-3002 : Step(83): len = 319921, overlap = 394.5
+PHY-3002 : Step(84): len = 319798, overlap = 397.375
+PHY-3002 : Step(85): len = 318807, overlap = 392.125
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.98711e-05
+PHY-3002 : Step(86): len = 334619, overlap = 377.562
+PHY-3002 : Step(87): len = 345774, overlap = 347.125
+PHY-3002 : Step(88): len = 350326, overlap = 331.969
+PHY-3002 : Step(89): len = 354729, overlap = 328.406
+PHY-3002 : Step(90): len = 353754, overlap = 324.781
+PHY-3002 : Step(91): len = 353378, overlap = 321.969
+PHY-3002 : Step(92): len = 351512, overlap = 309.219
+PHY-3002 : Step(93): len = 351355, overlap = 298.469
+PHY-3002 : Step(94): len = 352370, overlap = 283.406
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.97422e-05
+PHY-3002 : Step(95): len = 365285, overlap = 278.844
+PHY-3002 : Step(96): len = 378961, overlap = 270.469
+PHY-3002 : Step(97): len = 384784, overlap = 264.938
+PHY-3002 : Step(98): len = 388239, overlap = 250.719
+PHY-3002 : Step(99): len = 393526, overlap = 241.094
+PHY-3002 : Step(100): len = 396368, overlap = 236.25
+PHY-3002 : Step(101): len = 391416, overlap = 249.562
+PHY-3002 : Step(102): len = 391751, overlap = 244.062
+PHY-3002 : Step(103): len = 395804, overlap = 232.844
+PHY-3002 : Step(104): len = 399941, overlap = 230.562
+PHY-3002 : Step(105): len = 396512, overlap = 237.469
+PHY-3002 : Step(106): len = 397452, overlap = 240
+PHY-3002 : Step(107): len = 398162, overlap = 236.906
+PHY-3002 : Step(108): len = 400297, overlap = 221.031
+PHY-3002 : Step(109): len = 396342, overlap = 224.188
+PHY-3002 : Step(110): len = 396107, overlap = 222.688
+PHY-3002 : Step(111): len = 397061, overlap = 237.25
+PHY-3002 : Step(112): len = 398300, overlap = 234
+PHY-3002 : Step(113): len = 395428, overlap = 231.188
+PHY-3002 : Step(114): len = 395098, overlap = 229.812
+PHY-3002 : Step(115): len = 395846, overlap = 233.25
+PHY-3002 : Step(116): len = 397698, overlap = 241.438
+PHY-3002 : Step(117): len = 395358, overlap = 244.531
+PHY-3002 : Step(118): len = 395274, overlap = 238.312
+PHY-3002 : Step(119): len = 396513, overlap = 230.625
+PHY-3002 : Step(120): len = 398616, overlap = 231.5
+PHY-3002 : Step(121): len = 396567, overlap = 234.156
+PHY-3002 : Step(122): len = 397686, overlap = 224.844
+PHY-3002 : Step(123): len = 398030, overlap = 224.875
+PHY-3002 : Step(124): len = 398528, overlap = 224.812
+PHY-3002 : Step(125): len = 396800, overlap = 223.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000119484
+PHY-3002 : Step(126): len = 411144, overlap = 221.781
+PHY-3002 : Step(127): len = 420629, overlap = 216.469
+PHY-3002 : Step(128): len = 419633, overlap = 208.875
+PHY-3002 : Step(129): len = 420609, overlap = 210.5
+PHY-3002 : Step(130): len = 422921, overlap = 225.969
+PHY-3002 : Step(131): len = 425401, overlap = 226.281
+PHY-3002 : Step(132): len = 425634, overlap = 237.688
+PHY-3002 : Step(133): len = 425937, overlap = 235.344
+PHY-3002 : Step(134): len = 426538, overlap = 237.219
+PHY-3002 : Step(135): len = 427317, overlap = 237.406
+PHY-3002 : Step(136): len = 426153, overlap = 235
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000234216
+PHY-3002 : Step(137): len = 435200, overlap = 234.156
+PHY-3002 : Step(138): len = 442396, overlap = 222.875
+PHY-3002 : Step(139): len = 442891, overlap = 208.594
+PHY-3002 : Step(140): len = 443895, overlap = 208.469
+PHY-3002 : Step(141): len = 447215, overlap = 211.594
+PHY-3002 : Step(142): len = 449660, overlap = 206.406
+PHY-3002 : Step(143): len = 448690, overlap = 199.312
+PHY-3002 : Step(144): len = 449616, overlap = 191.844
+PHY-3002 : Step(145): len = 451299, overlap = 192.531
+PHY-3002 : Step(146): len = 452051, overlap = 189.656
+PHY-3002 : Step(147): len = 451128, overlap = 189.812
+PHY-3002 : Step(148): len = 451603, overlap = 177.094
+PHY-3002 : Step(149): len = 452882, overlap = 183.281
+PHY-3002 : Step(150): len = 453572, overlap = 181.844
+PHY-3002 : Step(151): len = 453323, overlap = 170.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000417233
+PHY-3002 : Step(152): len = 459237, overlap = 171.188
+PHY-3002 : Step(153): len = 466658, overlap = 166.062
+PHY-3002 : Step(154): len = 468401, overlap = 161.031
+PHY-3002 : Step(155): len = 470283, overlap = 159.469
+PHY-3002 : Step(156): len = 473248, overlap = 157.625
+PHY-3002 : Step(157): len = 475236, overlap = 158.344
+PHY-3002 : Step(158): len = 474297, overlap = 154.281
+PHY-3002 : Step(159): len = 474301, overlap = 156.875
+PHY-3002 : Step(160): len = 476113, overlap = 161.219
+PHY-3002 : Step(161): len = 477633, overlap = 159.031
+PHY-3002 : Step(162): len = 476667, overlap = 155.969
+PHY-3002 : Step(163): len = 477100, overlap = 155.875
+PHY-3002 : Step(164): len = 479330, overlap = 152.781
+PHY-3002 : Step(165): len = 479914, overlap = 152.969
+PHY-3002 : Step(166): len = 478837, overlap = 155.531
+PHY-3002 : Step(167): len = 478482, overlap = 155.094
+PHY-3002 : Step(168): len = 479571, overlap = 152.312
+PHY-3002 : Step(169): len = 480451, overlap = 150.781
+PHY-3002 : Step(170): len = 479161, overlap = 149.812
+PHY-3002 : Step(171): len = 478865, overlap = 149.906
+PHY-3002 : Step(172): len = 479754, overlap = 149.719
+PHY-3002 : Step(173): len = 480949, overlap = 150.5
+PHY-3002 : Step(174): len = 480215, overlap = 148.656
+PHY-3002 : Step(175): len = 479964, overlap = 151.094
+PHY-3002 : Step(176): len = 480407, overlap = 150.375
+PHY-3002 : Step(177): len = 480709, overlap = 151.781
+PHY-3002 : Step(178): len = 480203, overlap = 150.406
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000754792
+PHY-3002 : Step(179): len = 484755, overlap = 150.531
+PHY-3002 : Step(180): len = 490454, overlap = 145.906
+PHY-3002 : Step(181): len = 491588, overlap = 144.219
+PHY-3002 : Step(182): len = 492666, overlap = 143.75
+PHY-3002 : Step(183): len = 495483, overlap = 150.875
+PHY-3002 : Step(184): len = 496886, overlap = 149.625
+PHY-3002 : Step(185): len = 495909, overlap = 151.562
+PHY-3002 : Step(186): len = 495886, overlap = 153.5
+PHY-3002 : Step(187): len = 497908, overlap = 154.406
+PHY-3002 : Step(188): len = 498626, overlap = 155
+PHY-3002 : Step(189): len = 497697, overlap = 155.281
+PHY-3002 : Step(190): len = 497665, overlap = 157.406
+PHY-3002 : Step(191): len = 498488, overlap = 156.031
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00137159
+PHY-3002 : Step(192): len = 502544, overlap = 153.625
+PHY-3002 : Step(193): len = 510919, overlap = 150.969
+PHY-3002 : Step(194): len = 513702, overlap = 145.312
+PHY-3002 : Step(195): len = 516646, overlap = 157.812
+PHY-3002 : Step(196): len = 519245, overlap = 147.75
+PHY-3002 : Step(197): len = 520695, overlap = 149.344
+PHY-3002 : Step(198): len = 519922, overlap = 154.219
+PHY-3002 : Step(199): len = 519803, overlap = 148.75
+PHY-3002 : Step(200): len = 520673, overlap = 158.406
+PHY-3002 : Step(201): len = 521160, overlap = 156.031
+PHY-3002 : Step(202): len = 520328, overlap = 155.906
+PHY-3002 : Step(203): len = 520274, overlap = 153.656
+PHY-3002 : Step(204): len = 521097, overlap = 146.719
+PHY-3002 : Step(205): len = 521310, overlap = 152
+PHY-3002 : Step(206): len = 520789, overlap = 150.656
+PHY-3002 : Step(207): len = 520667, overlap = 150.656
+PHY-3002 : Step(208): len = 521143, overlap = 148.812
+PHY-3002 : Step(209): len = 521458, overlap = 149.688
+PHY-3002 : Step(210): len = 521054, overlap = 152.281
+PHY-3002 : Step(211): len = 520931, overlap = 151.812
+PHY-3002 : Step(212): len = 521415, overlap = 146.719
+PHY-3002 : Step(213): len = 522489, overlap = 137.875
+PHY-3002 : Step(214): len = 522024, overlap = 142.875
+PHY-3002 : Step(215): len = 522004, overlap = 144
+PHY-3002 : Step(216): len = 522094, overlap = 148.969
+PHY-3002 : Step(217): len = 522120, overlap = 149.219
+PHY-3002 : Step(218): len = 521855, overlap = 146.406
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00229114
+PHY-3002 : Step(219): len = 523328, overlap = 146.781
+PHY-3002 : Step(220): len = 526783, overlap = 136.469
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012267s wall, 0.000000s user + 0.015625s system = 0.015625s CPU (127.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 718816, over cnt = 1576(4%), over = 7392, worst = 37
+PHY-1001 : End global iterations; 0.665759s wall, 0.937500s user + 0.031250s system = 0.968750s CPU (145.5%)
+
+PHY-1001 : Congestion index: top1 = 84.14, top5 = 63.26, top10 = 53.13, top15 = 47.19.
+PHY-3001 : End congestion estimation; 0.917129s wall, 1.171875s user + 0.046875s system = 1.218750s CPU (132.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.829904s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000137567
+PHY-3002 : Step(221): len = 655586, overlap = 91.0625
+PHY-3002 : Step(222): len = 656040, overlap = 89
+PHY-3002 : Step(223): len = 649768, overlap = 92.3438
+PHY-3002 : Step(224): len = 645921, overlap = 91.4688
+PHY-3002 : Step(225): len = 644845, overlap = 83
+PHY-3002 : Step(226): len = 644605, overlap = 70.7188
+PHY-3002 : Step(227): len = 641481, overlap = 65.5
+PHY-3002 : Step(228): len = 638350, overlap = 60.25
+PHY-3002 : Step(229): len = 637797, overlap = 47.1875
+PHY-3002 : Step(230): len = 638124, overlap = 49.625
+PHY-3002 : Step(231): len = 637042, overlap = 46.1875
+PHY-3002 : Step(232): len = 636030, overlap = 45.8125
+PHY-3002 : Step(233): len = 635009, overlap = 46.25
+PHY-3002 : Step(234): len = 633929, overlap = 48.1562
+PHY-3002 : Step(235): len = 632719, overlap = 46.75
+PHY-3002 : Step(236): len = 631458, overlap = 48.1875
+PHY-3002 : Step(237): len = 630742, overlap = 50.4375
+PHY-3002 : Step(238): len = 629047, overlap = 52.5312
+PHY-3002 : Step(239): len = 627241, overlap = 52.6875
+PHY-3002 : Step(240): len = 626001, overlap = 53
+PHY-3002 : Step(241): len = 625852, overlap = 54.6875
+PHY-3002 : Step(242): len = 624346, overlap = 58.0625
+PHY-3002 : Step(243): len = 622488, overlap = 65.25
+PHY-3002 : Step(244): len = 621591, overlap = 71.7188
+PHY-3002 : Step(245): len = 620294, overlap = 73.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000275134
+PHY-3002 : Step(246): len = 623236, overlap = 71.1562
+PHY-3002 : Step(247): len = 630242, overlap = 70.0625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479156
+PHY-3002 : Step(248): len = 633137, overlap = 69.5938
+PHY-3002 : Step(249): len = 652899, overlap = 63.9062
+PHY-3002 : Step(250): len = 665502, overlap = 58.7812
+PHY-3002 : Step(251): len = 663694, overlap = 56.0312
+PHY-3002 : Step(252): len = 661990, overlap = 54.3125
+PHY-3002 : Step(253): len = 660479, overlap = 55.125
+PHY-3002 : Step(254): len = 659836, overlap = 54.2812
+PHY-3002 : Step(255): len = 661199, overlap = 51.5312
+PHY-3002 : Step(256): len = 662357, overlap = 50.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000902937
+PHY-3002 : Step(257): len = 668318, overlap = 48.25
+PHY-3002 : Step(258): len = 684505, overlap = 47.8125
+PHY-3002 : Step(259): len = 699799, overlap = 48.8125
+PHY-3002 : Step(260): len = 701058, overlap = 45.375
+PHY-3002 : Step(261): len = 698852, overlap = 46.5
+PHY-3002 : Step(262): len = 695783, overlap = 45.5625
+PHY-3002 : Step(263): len = 694479, overlap = 49.5312
+PHY-3002 : Step(264): len = 694739, overlap = 44.3438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00159413
+PHY-3002 : Step(265): len = 699260, overlap = 47.9062
+PHY-3002 : Step(266): len = 708601, overlap = 43.625
+PHY-3002 : Step(267): len = 714279, overlap = 45.0625
+PHY-3002 : Step(268): len = 720488, overlap = 49.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 46/20605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 805784, over cnt = 2783(7%), over = 13869, worst = 49
+PHY-1001 : End global iterations; 1.502968s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (134.1%)
+
+PHY-1001 : Congestion index: top1 = 105.52, top5 = 76.39, top10 = 65.56, top15 = 59.13.
+PHY-3001 : End congestion estimation; 1.767275s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (129.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.869841s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000123244
+PHY-3002 : Step(269): len = 704254, overlap = 241.156
+PHY-3002 : Step(270): len = 694006, overlap = 197.375
+PHY-3002 : Step(271): len = 680497, overlap = 182.562
+PHY-3002 : Step(272): len = 668398, overlap = 156.031
+PHY-3002 : Step(273): len = 658253, overlap = 131.562
+PHY-3002 : Step(274): len = 652492, overlap = 123.375
+PHY-3002 : Step(275): len = 645606, overlap = 115.125
+PHY-3002 : Step(276): len = 640876, overlap = 109.5
+PHY-3002 : Step(277): len = 637284, overlap = 111.281
+PHY-3002 : Step(278): len = 632682, overlap = 111.688
+PHY-3002 : Step(279): len = 628172, overlap = 107.125
+PHY-3002 : Step(280): len = 623893, overlap = 100.719
+PHY-3002 : Step(281): len = 620775, overlap = 107.812
+PHY-3002 : Step(282): len = 616260, overlap = 111.156
+PHY-3002 : Step(283): len = 612287, overlap = 114.875
+PHY-3002 : Step(284): len = 609351, overlap = 117.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000246488
+PHY-3002 : Step(285): len = 609714, overlap = 110.781
+PHY-3002 : Step(286): len = 614122, overlap = 102.344
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000492977
+PHY-3002 : Step(287): len = 617620, overlap = 96.2188
+PHY-3002 : Step(288): len = 628516, overlap = 86.8438
+PHY-3002 : Step(289): len = 634486, overlap = 80.6562
+PHY-3002 : Step(290): len = 633547, overlap = 79.5312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000985954
+PHY-3002 : Step(291): len = 635435, overlap = 72.4688
+PHY-3002 : Step(292): len = 641376, overlap = 68.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84120, tnet num: 20427, tinst num: 18019, tnode num: 114459, tedge num: 134136.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.407606s wall, 1.375000s user + 0.031250s system = 1.406250s CPU (99.9%)
+
+RUN-1004 : used memory is 572 MB, reserved memory is 563 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 376.94 peak overflow 3.72
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 400/20605.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737472, over cnt = 3092(8%), over = 10621, worst = 23
+PHY-1001 : End global iterations; 1.367026s wall, 1.859375s user + 0.046875s system = 1.906250s CPU (139.4%)
+
+PHY-1001 : Congestion index: top1 = 67.09, top5 = 56.03, top10 = 50.46, top15 = 47.12.
+PHY-1001 : End incremental global routing; 1.693968s wall, 2.187500s user + 0.046875s system = 2.234375s CPU (131.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20427 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.249006s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (100.1%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17888 has valid locations, 306 needs to be replaced
+PHY-3001 : design contains 18279 instances, 7772 luts, 9286 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6090 pins
+PHY-3001 : Found 1257 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 665161
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16971/20865.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753240, over cnt = 3157(8%), over = 10739, worst = 23
+PHY-1001 : End global iterations; 0.238805s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (150.5%)
+
+PHY-1001 : Congestion index: top1 = 67.05, top5 = 56.45, top10 = 50.93, top15 = 47.64.
+PHY-3001 : End congestion estimation; 0.484667s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (125.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85160, tnet num: 20687, tinst num: 18279, tnode num: 116013, tedge num: 135696.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.418652s wall, 1.375000s user + 0.046875s system = 1.421875s CPU (100.2%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 634 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20687 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.386672s wall, 2.328125s user + 0.062500s system = 2.390625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(293): len = 664228, overlap = 0.0625
+PHY-3002 : Step(294): len = 663851, overlap = 0.1875
+PHY-3002 : Step(295): len = 663659, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17074/20865.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751264, over cnt = 3160(8%), over = 10782, worst = 23
+PHY-1001 : End global iterations; 0.195674s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (119.8%)
+
+PHY-1001 : Congestion index: top1 = 67.89, top5 = 56.82, top10 = 51.23, top15 = 47.89.
+PHY-3001 : End congestion estimation; 0.440995s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (106.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20687 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.908995s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000355068
+PHY-3002 : Step(296): len = 663402, overlap = 71.125
+PHY-3002 : Step(297): len = 663426, overlap = 70.8438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000710136
+PHY-3002 : Step(298): len = 663678, overlap = 70.625
+PHY-3002 : Step(299): len = 664242, overlap = 70.75
+PHY-3001 : Final: Len = 664242, Over = 70.75
+PHY-3001 : End incremental placement; 4.839447s wall, 5.078125s user + 0.187500s system = 5.265625s CPU (108.8%)
+
+OPT-1001 : Total overflow 381.56 peak overflow 3.72
+OPT-1001 : End high-fanout net optimization; 8.301954s wall, 9.125000s user + 0.250000s system = 9.375000s CPU (112.9%)
+
+OPT-1001 : Current memory(MB): used = 714, reserve = 710, peak = 731.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17014/20865.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753936, over cnt = 3092(8%), over = 9716, worst = 23
+PHY-1002 : len = 803328, over cnt = 1994(5%), over = 4849, worst = 23
+PHY-1002 : len = 837944, over cnt = 924(2%), over = 2202, worst = 23
+PHY-1002 : len = 865904, over cnt = 193(0%), over = 403, worst = 18
+PHY-1002 : len = 872360, over cnt = 17(0%), over = 19, worst = 2
+PHY-1001 : End global iterations; 1.513340s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 57.72, top5 = 50.70, top10 = 47.06, top15 = 44.85.
+OPT-1001 : End congestion update; 1.764701s wall, 2.437500s user + 0.031250s system = 2.468750s CPU (139.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20687 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.782799s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.8%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 112 cells processed and 17500 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 1900 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 28 cells processed and 2250 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 200 slack improved
+OPT-0007 : Iter 5: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.033548s wall, 3.703125s user + 0.031250s system = 3.734375s CPU (123.1%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 694, peak = 731.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17044/20867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872824, over cnt = 94(0%), over = 120, worst = 4
+PHY-1002 : len = 872440, over cnt = 60(0%), over = 65, worst = 3
+PHY-1002 : len = 872816, over cnt = 27(0%), over = 27, worst = 1
+PHY-1002 : len = 873176, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 873336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.720061s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (106.3%)
+
+PHY-1001 : Congestion index: top1 = 57.41, top5 = 50.39, top10 = 46.86, top15 = 44.67.
+OPT-1001 : End congestion update; 0.977765s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (105.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.068565s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.4%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 4650 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.159551s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (102.0%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 704, peak = 731.
+OPT-1001 : End physical optimization; 15.200214s wall, 16.671875s user + 0.359375s system = 17.031250s CPU (112.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7772 LUT to BLE ...
+SYN-4008 : Packed 7772 LUT and 3141 SEQ to BLE.
+SYN-4003 : Packing 6147 remaining SEQ's ...
+SYN-4005 : Packed 3993 SEQ with LUT/SLICE
+SYN-4006 : 922 single LUT's are left
+SYN-4006 : 2154 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9926/13781 primitive instances ...
+PHY-3001 : End packing; 1.620605s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6687 instances
+RUN-1001 : 3269 mslices, 3270 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17854 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10016 nets have 2 pins
+RUN-1001 : 6493 nets have [3 - 5] pins
+RUN-1001 : 710 nets have [6 - 10] pins
+RUN-1001 : 313 nets have [11 - 20] pins
+RUN-1001 : 290 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6685 instances, 6539 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3518 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 674363, Over = 203.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7522/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 822288, over cnt = 1932(5%), over = 3018, worst = 8
+PHY-1002 : len = 828712, over cnt = 1324(3%), over = 1868, worst = 6
+PHY-1002 : len = 838904, over cnt = 708(2%), over = 974, worst = 5
+PHY-1002 : len = 848968, over cnt = 281(0%), over = 399, worst = 4
+PHY-1002 : len = 855224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.557387s wall, 2.140625s user + 0.062500s system = 2.203125s CPU (141.5%)
+
+PHY-1001 : Congestion index: top1 = 58.86, top5 = 50.58, top10 = 46.61, top15 = 44.16.
+PHY-3001 : End congestion estimation; 1.948487s wall, 2.515625s user + 0.062500s system = 2.578125s CPU (132.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71323, tnet num: 17676, tinst num: 6685, tnode num: 93607, tedge num: 118497.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.569007s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.6%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 615 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.416226s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.58902e-05
+PHY-3002 : Step(300): len = 662097, overlap = 212
+PHY-3002 : Step(301): len = 655090, overlap = 220.75
+PHY-3002 : Step(302): len = 650730, overlap = 223.75
+PHY-3002 : Step(303): len = 647911, overlap = 221.25
+PHY-3002 : Step(304): len = 645568, overlap = 225.25
+PHY-3002 : Step(305): len = 643495, overlap = 232.75
+PHY-3002 : Step(306): len = 641097, overlap = 241.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00011178
+PHY-3002 : Step(307): len = 644509, overlap = 229.75
+PHY-3002 : Step(308): len = 649180, overlap = 219.25
+PHY-3002 : Step(309): len = 649143, overlap = 221.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000223561
+PHY-3002 : Step(310): len = 658224, overlap = 209.25
+PHY-3002 : Step(311): len = 665298, overlap = 204.25
+PHY-3002 : Step(312): len = 663914, overlap = 204.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.392183s wall, 0.531250s user + 0.609375s system = 1.140625s CPU (290.8%)
+
+PHY-3001 : Trial Legalized: Len = 743072
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 921/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853592, over cnt = 2637(7%), over = 4294, worst = 8
+PHY-1002 : len = 870928, over cnt = 1513(4%), over = 2108, worst = 8
+PHY-1002 : len = 882384, over cnt = 890(2%), over = 1211, worst = 8
+PHY-1002 : len = 892456, over cnt = 414(1%), over = 572, worst = 6
+PHY-1002 : len = 903552, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.320120s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (145.5%)
+
+PHY-1001 : Congestion index: top1 = 55.78, top5 = 49.95, top10 = 46.96, top15 = 44.94.
+PHY-3001 : End congestion estimation; 2.763005s wall, 3.796875s user + 0.031250s system = 3.828125s CPU (138.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.828982s wall, 0.781250s user + 0.046875s system = 0.828125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165011
+PHY-3002 : Step(313): len = 717394, overlap = 40.5
+PHY-3002 : Step(314): len = 701481, overlap = 67
+PHY-3002 : Step(315): len = 687644, overlap = 94.5
+PHY-3002 : Step(316): len = 678382, overlap = 112
+PHY-3002 : Step(317): len = 673919, overlap = 130.5
+PHY-3002 : Step(318): len = 670795, overlap = 142.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000330021
+PHY-3002 : Step(319): len = 675750, overlap = 139.5
+PHY-3002 : Step(320): len = 680087, overlap = 139.25
+PHY-3002 : Step(321): len = 681041, overlap = 139.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000624168
+PHY-3002 : Step(322): len = 684547, overlap = 137.75
+PHY-3002 : Step(323): len = 692615, overlap = 134.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033892s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (92.2%)
+
+PHY-3001 : Legalized: Len = 720408, Over = 0
+PHY-3001 : Spreading special nets. 435 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.096906s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (96.7%)
+
+PHY-3001 : 628 instances has been re-located, deltaX = 233, deltaY = 341, maxDist = 3.
+PHY-3001 : Final: Len = 730698, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71323, tnet num: 17676, tinst num: 6688, tnode num: 93607, tedge num: 118497.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.841149s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.1%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 620 MB, peak memory is 731 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4407/17854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858328, over cnt = 2430(6%), over = 3790, worst = 7
+PHY-1002 : len = 871104, over cnt = 1345(3%), over = 1890, worst = 7
+PHY-1002 : len = 886208, over cnt = 495(1%), over = 680, worst = 5
+PHY-1002 : len = 894368, over cnt = 131(0%), over = 170, worst = 4
+PHY-1002 : len = 897232, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations; 1.991547s wall, 2.796875s user + 0.015625s system = 2.812500s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 53.88, top5 = 48.94, top10 = 45.96, top15 = 44.03.
+PHY-1001 : End incremental global routing; 2.370434s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (135.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.850098s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.3%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6594 has valid locations, 31 needs to be replaced
+PHY-3001 : design contains 6713 instances, 6564 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3580 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 736529
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16213/17884.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903840, over cnt = 109(0%), over = 134, worst = 4
+PHY-1002 : len = 904096, over cnt = 58(0%), over = 68, worst = 4
+PHY-1002 : len = 904472, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 904968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.611752s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (112.4%)
+
+PHY-1001 : Congestion index: top1 = 54.05, top5 = 49.19, top10 = 46.17, top15 = 44.25.
+PHY-3001 : End congestion estimation; 0.938806s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (108.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71581, tnet num: 17706, tinst num: 6713, tnode num: 93931, tedge num: 118840.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.817314s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (99.7%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 647 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.674018s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(324): len = 735768, overlap = 0
+PHY-3002 : Step(325): len = 735298, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16205/17884.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903640, over cnt = 68(0%), over = 81, worst = 4
+PHY-1002 : len = 903752, over cnt = 39(0%), over = 40, worst = 2
+PHY-1002 : len = 904072, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 904184, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 904200, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.790934s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 53.94, top5 = 49.10, top10 = 46.17, top15 = 44.26.
+PHY-3001 : End congestion estimation; 1.107189s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (103.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.900109s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000606445
+PHY-3002 : Step(326): len = 735102, overlap = 1
+PHY-3002 : Step(327): len = 734801, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005756s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 734838, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057663s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.3%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 2, deltaY = 10, maxDist = 1.
+PHY-3001 : Final: Len = 734930, Over = 0
+PHY-3001 : End incremental placement; 6.135950s wall, 6.328125s user + 0.093750s system = 6.421875s CPU (104.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.835444s wall, 10.953125s user + 0.109375s system = 11.062500s CPU (112.5%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 729, peak = 731.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16154/17884.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903112, over cnt = 106(0%), over = 135, worst = 6
+PHY-1002 : len = 903224, over cnt = 39(0%), over = 39, worst = 1
+PHY-1002 : len = 903472, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 903584, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 903672, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.782448s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (111.8%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 49.06, top10 = 46.13, top15 = 44.22.
+OPT-1001 : End congestion update; 1.085176s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (108.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.007475s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.8%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6625 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6713 instances, 6564 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3580 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 743228, Over = 0
+PHY-3001 : Spreading special nets. 27 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059885s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.4%)
+
+PHY-3001 : 37 instances has been re-located, deltaX = 16, deltaY = 27, maxDist = 4.
+PHY-3001 : Final: Len = 744060, Over = 0
+PHY-3001 : End incremental legalization; 0.371293s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.0%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 55 cells processed and 20138 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6625 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6713 instances, 6564 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3580 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 744712, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061219s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.1%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 14, deltaY = 17, maxDist = 4.
+PHY-3001 : Final: Len = 745122, Over = 0
+PHY-3001 : End incremental legalization; 0.370602s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (122.3%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 32 cells processed and 2804 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6625 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6713 instances, 6564 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3580 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 745548, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058978s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.5%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 7, deltaY = 21, maxDist = 4.
+PHY-3001 : Final: Len = 746140, Over = 0
+PHY-3001 : End incremental legalization; 0.366622s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.0%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 28 cells processed and 2134 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6632 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6720 instances, 6571 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 746432, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060323s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.7%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 0, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 746364, Over = 0
+PHY-3001 : End incremental legalization; 0.382348s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (94.0%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 7 cells processed and 900 slack improved
+OPT-1001 : End bottleneck based optimization; 4.174625s wall, 4.328125s user + 0.000000s system = 4.328125s CPU (103.7%)
+
+OPT-1001 : Current memory(MB): used = 727, reserve = 730, peak = 731.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15740/17884.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914400, over cnt = 200(0%), over = 274, worst = 5
+PHY-1002 : len = 914824, over cnt = 92(0%), over = 105, worst = 3
+PHY-1002 : len = 915464, over cnt = 38(0%), over = 38, worst = 1
+PHY-1002 : len = 916024, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 916128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.834910s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 53.58, top5 = 48.78, top10 = 45.98, top15 = 44.15.
+OPT-1001 : End congestion update; 1.153564s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (104.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.700461s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.4%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6632 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6720 instances, 6571 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 746434, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059081s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.8%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 6, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 746618, Over = 0
+PHY-3001 : End incremental legalization; 0.381105s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 14 cells processed and 1095 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.357827s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (102.1%)
+
+OPT-1001 : Current memory(MB): used = 727, reserve = 730, peak = 731.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.702696s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16175/17884.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 916216, over cnt = 53(0%), over = 60, worst = 3
+PHY-1002 : len = 916344, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 916408, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 916696, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 916696, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.764818s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 53.51, top5 = 48.82, top10 = 46.01, top15 = 44.17.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.713183s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.000000
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 20.958349s wall, 22.250000s user + 0.125000s system = 22.375000s CPU (106.8%)
+
+RUN-1003 : finish command "place" in 65.664370s wall, 97.046875s user + 6.406250s system = 103.453125s CPU (157.5%)
+
+RUN-1004 : used memory is 670 MB, reserved memory is 677 MB, peak memory is 731 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.686485s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (174.2%)
+
+RUN-1004 : used memory is 671 MB, reserved memory is 677 MB, peak memory is 731 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6722 instances
+RUN-1001 : 3290 mslices, 3281 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17884 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10001 nets have 2 pins
+RUN-1001 : 6498 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 304 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71654, tnet num: 17706, tinst num: 6720, tnode num: 94029, tedge num: 118947.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.562803s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.0%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 652 MB, peak memory is 731 MB
+PHY-1001 : 3290 mslices, 3281 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 848496, over cnt = 2614(7%), over = 4273, worst = 8
+PHY-1002 : len = 865224, over cnt = 1576(4%), over = 2321, worst = 7
+PHY-1002 : len = 888312, over cnt = 448(1%), over = 648, worst = 6
+PHY-1002 : len = 897480, over cnt = 31(0%), over = 44, worst = 3
+PHY-1002 : len = 898192, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.068562s wall, 3.906250s user + 0.046875s system = 3.953125s CPU (128.8%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 48.51, top10 = 45.65, top15 = 43.72.
+PHY-1001 : End global routing; 3.391408s wall, 4.234375s user + 0.046875s system = 4.281250s CPU (126.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 702, reserve = 702, peak = 731.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 972, reserve = 975, peak = 972.
+PHY-1001 : End build detailed router design. 4.105955s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273024, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.979841s wall, 4.968750s user + 0.015625s system = 4.984375s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273080, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.456981s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1007, reserve = 1012, peak = 1007.
+PHY-1001 : End phase 1; 5.448973s wall, 5.437500s user + 0.015625s system = 5.453125s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 46% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24585e+06, over cnt = 1712(0%), over = 1717, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1028, peak = 1025.
+PHY-1001 : End initial routed; 28.182364s wall, 62.187500s user + 0.234375s system = 62.421875s CPU (221.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16807(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.275573s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1037, reserve = 1040, peak = 1037.
+PHY-1001 : End phase 2; 31.458005s wall, 65.453125s user + 0.234375s system = 65.687500s CPU (208.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.133539s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.3%)
+
+PHY-1022 : len = 2.24585e+06, over cnt = 1712(0%), over = 1717, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.392122s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.21798e+06, over cnt = 767(0%), over = 769, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.417640s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (152.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.21479e+06, over cnt = 137(0%), over = 137, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.630160s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (151.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.21528e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.340415s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (133.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.21534e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.198510s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.21541e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.177923s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (96.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16807(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.430374s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (98.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 532 feed throughs used by 404 nets
+PHY-1001 : End commit to database; 2.334725s wall, 2.250000s user + 0.031250s system = 2.281250s CPU (97.7%)
+
+PHY-1001 : Current memory(MB): used = 1138, reserve = 1143, peak = 1138.
+PHY-1001 : End phase 3; 9.318185s wall, 10.375000s user + 0.046875s system = 10.421875s CPU (111.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.136530s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1022 : len = 2.21541e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.383729s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16807(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.317270s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 532 feed throughs used by 404 nets
+PHY-1001 : End commit to database; 2.259266s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1153, peak = 1146.
+PHY-1001 : End phase 4; 5.986685s wall, 6.000000s user + 0.000000s system = 6.000000s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.21541e+06
+PHY-1001 : Current memory(MB): used = 1148, reserve = 1154, peak = 1148.
+PHY-1001 : End export database. 0.060027s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.1%)
+
+PHY-1001 : End detail routing; 56.776575s wall, 91.796875s user + 0.312500s system = 92.109375s CPU (162.2%)
+
+RUN-1003 : finish command "route" in 62.761208s wall, 98.609375s user + 0.359375s system = 98.968750s CPU (157.7%)
+
+RUN-1004 : used memory is 1078 MB, reserved memory is 1083 MB, peak memory is 1148 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10204 out of 19600 52.06%
+#reg 9440 out of 19600 48.16%
+#le 12330
+ #lut only 2890 out of 12330 23.44%
+ #reg only 2126 out of 12330 17.24%
+ #lut® 7314 out of 12330 59.32%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1789
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1390
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1283
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 955
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 134
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/u_ADconfig/en_adc_cfg_d2_reg_syn_5.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_320.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P109 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P3 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P149 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P19 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12330 |9177 |1027 |9474 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |518 |438 |23 |430 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |84 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |39 |39 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |8 |8 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |759 |388 |96 |579 |0 |0 |
+| u_ADconfig |AD_config |186 |131 |25 |140 |0 |0 |
+| u_gen_sp |gen_sp |254 |150 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |739 |349 |96 |563 |0 |0 |
+| u_ADconfig |AD_config |172 |99 |25 |129 |0 |0 |
+| u_gen_sp |gen_sp |258 |138 |71 |125 |0 |0 |
+| sampling_fe_a |sampling_fe |3005 |2466 |306 |2110 |25 |0 |
+| u0_soft_n |cdc_sync |7 |1 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |185 |109 |17 |155 |0 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_sort |sort |2783 |2338 |289 |1918 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2360 |2027 |253 |1569 |22 |0 |
+| channelPart |channel_part_8478 |143 |139 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |57 |48 |9 |41 |0 |0 |
+| ram_switch |ram_switch |1841 |1571 |197 |1165 |0 |0 |
+| adc_addr_gen |adc_addr_gen |217 |190 |27 |119 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |28 |25 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| insert |insert |954 |712 |170 |647 |0 |0 |
+| ram_switch_state |ram_switch_state |670 |669 |0 |399 |0 |0 |
+| read_ram_i |read_ram |292 |245 |44 |197 |0 |0 |
+| read_ram_addr |read_ram_addr |237 |197 |40 |156 |0 |0 |
+| read_ram_data |read_ram_data |51 |45 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |227 |36 |268 |3 |0 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3182 |2479 |349 |2073 |25 |1 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |91 |17 |154 |0 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_sort |sort_rev |2964 |2374 |332 |1885 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2541 |2046 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |140 |133 |3 |130 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1949 |1581 |197 |1129 |0 |0 |
+| adc_addr_gen |adc_addr_gen |186 |159 |27 |81 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |16 |13 |3 |5 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |5 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 |
+| insert |insert |970 |632 |170 |684 |0 |0 |
+| ram_switch_state |ram_switch_state |793 |790 |0 |364 |0 |0 |
+| read_ram_i |read_ram_rev |366 |263 |81 |215 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |307 |224 |73 |170 |0 |0 |
+| read_ram_data |read_ram_data_rev |59 |39 |8 |45 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9939
+ #2 2 4252
+ #3 3 1648
+ #4 4 595
+ #5 5-10 770
+ #6 11-50 577
+ #7 51-100 7
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.029751s wall, 3.468750s user + 0.015625s system = 3.484375s CPU (171.7%)
+
+RUN-1004 : used memory is 1079 MB, reserved memory is 1084 MB, peak memory is 1148 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71654, tnet num: 17706, tinst num: 6720, tnode num: 94029, tedge num: 118947.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.588776s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.3%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1088 MB, peak memory is 1148 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17706 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.452873s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.0%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1091 MB, peak memory is 1148 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6720
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17884, pip num: 166895
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 532
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3229 valid insts, and 466583 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.039976s wall, 67.312500s user + 0.203125s system = 67.515625s CPU (672.5%)
+
+RUN-1004 : used memory is 1242 MB, reserved memory is 1245 MB, peak memory is 1357 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_154955.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_162229.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_162229.log
new file mode 100644
index 0000000..6e88e05
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_162229.log
@@ -0,0 +1,2195 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 16:22:29 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.355656s wall, 2.203125s user + 0.125000s system = 2.328125s CPU (98.8%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 316 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2227 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2067 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18014 instances
+RUN-0007 : 7663 luts, 9128 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20598 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13113 nets have 2 pins
+RUN-1001 : 6452 nets have [3 - 5] pins
+RUN-1001 : 613 nets have [6 - 10] pins
+RUN-1001 : 180 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3495
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18012 instances, 7663 luts, 9128 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 5981 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84112, tnet num: 20420, tinst num: 18012, tnode num: 114469, tedge num: 134134.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.268378s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (101.0%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 515 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.198090s wall, 2.171875s user + 0.031250s system = 2.203125s CPU (100.2%)
+
+PHY-3001 : Found 1246 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.98477e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18012.
+PHY-3001 : Level 1 #clusters 2044.
+PHY-3001 : End clustering; 0.318556s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (107.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31507e+06, overlap = 445.969
+PHY-3002 : Step(2): len = 1.22778e+06, overlap = 482.688
+PHY-3002 : Step(3): len = 856028, overlap = 564
+PHY-3002 : Step(4): len = 778641, overlap = 610.812
+PHY-3002 : Step(5): len = 617382, overlap = 762.125
+PHY-3002 : Step(6): len = 550039, overlap = 817.688
+PHY-3002 : Step(7): len = 476217, overlap = 885.969
+PHY-3002 : Step(8): len = 429303, overlap = 914.969
+PHY-3002 : Step(9): len = 389858, overlap = 974.781
+PHY-3002 : Step(10): len = 361256, overlap = 1033.28
+PHY-3002 : Step(11): len = 328398, overlap = 1077.19
+PHY-3002 : Step(12): len = 298443, overlap = 1144.34
+PHY-3002 : Step(13): len = 271647, overlap = 1208.19
+PHY-3002 : Step(14): len = 245487, overlap = 1255.69
+PHY-3002 : Step(15): len = 229343, overlap = 1325.84
+PHY-3002 : Step(16): len = 207760, overlap = 1331.12
+PHY-3002 : Step(17): len = 192101, overlap = 1348.06
+PHY-3002 : Step(18): len = 171302, overlap = 1372.38
+PHY-3002 : Step(19): len = 163716, overlap = 1410.47
+PHY-3002 : Step(20): len = 147049, overlap = 1439.09
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.08784e-06
+PHY-3002 : Step(21): len = 147374, overlap = 1404.25
+PHY-3002 : Step(22): len = 179848, overlap = 1269.28
+PHY-3002 : Step(23): len = 190628, overlap = 1175.97
+PHY-3002 : Step(24): len = 197517, overlap = 1138.38
+PHY-3002 : Step(25): len = 198246, overlap = 1068.31
+PHY-3002 : Step(26): len = 196876, overlap = 1058.88
+PHY-3002 : Step(27): len = 192906, overlap = 1068.81
+PHY-3002 : Step(28): len = 189282, overlap = 1087.09
+PHY-3002 : Step(29): len = 185687, overlap = 1070.38
+PHY-3002 : Step(30): len = 182053, overlap = 1032.31
+PHY-3002 : Step(31): len = 179500, overlap = 1040.69
+PHY-3002 : Step(32): len = 177447, overlap = 1050.91
+PHY-3002 : Step(33): len = 174777, overlap = 1061.44
+PHY-3002 : Step(34): len = 173860, overlap = 1060.5
+PHY-3002 : Step(35): len = 172461, overlap = 1055.84
+PHY-3002 : Step(36): len = 171203, overlap = 1052.59
+PHY-3002 : Step(37): len = 169124, overlap = 1051.09
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.17568e-06
+PHY-3002 : Step(38): len = 171924, overlap = 1035.38
+PHY-3002 : Step(39): len = 183706, overlap = 994.656
+PHY-3002 : Step(40): len = 188313, overlap = 1003.16
+PHY-3002 : Step(41): len = 192429, overlap = 989.344
+PHY-3002 : Step(42): len = 195054, overlap = 1003.97
+PHY-3002 : Step(43): len = 196075, overlap = 1018.78
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.35136e-06
+PHY-3002 : Step(44): len = 202007, overlap = 995.656
+PHY-3002 : Step(45): len = 218676, overlap = 895.5
+PHY-3002 : Step(46): len = 227811, overlap = 831.656
+PHY-3002 : Step(47): len = 236610, overlap = 814.281
+PHY-3002 : Step(48): len = 241511, overlap = 778.812
+PHY-3002 : Step(49): len = 243451, overlap = 739.125
+PHY-3002 : Step(50): len = 242240, overlap = 726.062
+PHY-3002 : Step(51): len = 242305, overlap = 730.281
+PHY-3002 : Step(52): len = 240052, overlap = 725.594
+PHY-3002 : Step(53): len = 240256, overlap = 724.344
+PHY-3002 : Step(54): len = 239837, overlap = 729.938
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.70272e-06
+PHY-3002 : Step(55): len = 254228, overlap = 666.781
+PHY-3002 : Step(56): len = 272848, overlap = 584.938
+PHY-3002 : Step(57): len = 280186, overlap = 528.875
+PHY-3002 : Step(58): len = 285747, overlap = 512.344
+PHY-3002 : Step(59): len = 287401, overlap = 510.312
+PHY-3002 : Step(60): len = 289657, overlap = 483.344
+PHY-3002 : Step(61): len = 288581, overlap = 479.594
+PHY-3002 : Step(62): len = 290337, overlap = 466.469
+PHY-3002 : Step(63): len = 291851, overlap = 466
+PHY-3002 : Step(64): len = 292028, overlap = 472.281
+PHY-3002 : Step(65): len = 289523, overlap = 484.719
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.74054e-05
+PHY-3002 : Step(66): len = 304647, overlap = 449.094
+PHY-3002 : Step(67): len = 319822, overlap = 405.25
+PHY-3002 : Step(68): len = 325969, overlap = 373.906
+PHY-3002 : Step(69): len = 327771, overlap = 382.031
+PHY-3002 : Step(70): len = 326393, overlap = 405.25
+PHY-3002 : Step(71): len = 326503, overlap = 420.062
+PHY-3002 : Step(72): len = 327256, overlap = 419.562
+PHY-3002 : Step(73): len = 331297, overlap = 378.5
+PHY-3002 : Step(74): len = 331916, overlap = 386.688
+PHY-3002 : Step(75): len = 331822, overlap = 378
+PHY-3002 : Step(76): len = 332012, overlap = 356.031
+PHY-3002 : Step(77): len = 333644, overlap = 354.625
+PHY-3002 : Step(78): len = 334349, overlap = 351.031
+PHY-3002 : Step(79): len = 331738, overlap = 375.094
+PHY-3002 : Step(80): len = 330964, overlap = 387.969
+PHY-3002 : Step(81): len = 331814, overlap = 389.281
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.48109e-05
+PHY-3002 : Step(82): len = 346689, overlap = 370.531
+PHY-3002 : Step(83): len = 359584, overlap = 347.062
+PHY-3002 : Step(84): len = 362779, overlap = 334.125
+PHY-3002 : Step(85): len = 363711, overlap = 335.781
+PHY-3002 : Step(86): len = 365303, overlap = 325.406
+PHY-3002 : Step(87): len = 367105, overlap = 314.375
+PHY-3002 : Step(88): len = 366884, overlap = 329.438
+PHY-3002 : Step(89): len = 365241, overlap = 331.5
+PHY-3002 : Step(90): len = 365305, overlap = 327.344
+PHY-3002 : Step(91): len = 365862, overlap = 330.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.96217e-05
+PHY-3002 : Step(92): len = 380789, overlap = 315.938
+PHY-3002 : Step(93): len = 393357, overlap = 290.562
+PHY-3002 : Step(94): len = 394589, overlap = 288
+PHY-3002 : Step(95): len = 398251, overlap = 301.75
+PHY-3002 : Step(96): len = 403684, overlap = 294.094
+PHY-3002 : Step(97): len = 406340, overlap = 283.875
+PHY-3002 : Step(98): len = 401894, overlap = 302.75
+PHY-3002 : Step(99): len = 402388, overlap = 297.781
+PHY-3002 : Step(100): len = 403322, overlap = 294.312
+PHY-3002 : Step(101): len = 405345, overlap = 282.25
+PHY-3002 : Step(102): len = 403505, overlap = 279.312
+PHY-3002 : Step(103): len = 403705, overlap = 263.688
+PHY-3002 : Step(104): len = 406270, overlap = 244.781
+PHY-3002 : Step(105): len = 408412, overlap = 234.906
+PHY-3002 : Step(106): len = 404655, overlap = 236.281
+PHY-3002 : Step(107): len = 404056, overlap = 232.719
+PHY-3002 : Step(108): len = 405042, overlap = 229.875
+PHY-3002 : Step(109): len = 406646, overlap = 241.406
+PHY-3002 : Step(110): len = 403729, overlap = 234.625
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000137196
+PHY-3002 : Step(111): len = 417153, overlap = 233.406
+PHY-3002 : Step(112): len = 426122, overlap = 216.781
+PHY-3002 : Step(113): len = 425122, overlap = 213.656
+PHY-3002 : Step(114): len = 425898, overlap = 212.469
+PHY-3002 : Step(115): len = 427951, overlap = 204.25
+PHY-3002 : Step(116): len = 430233, overlap = 205.5
+PHY-3002 : Step(117): len = 429523, overlap = 197.406
+PHY-3002 : Step(118): len = 430264, overlap = 194.656
+PHY-3002 : Step(119): len = 431847, overlap = 196.281
+PHY-3002 : Step(120): len = 433245, overlap = 204.438
+PHY-3002 : Step(121): len = 431170, overlap = 204.062
+PHY-3002 : Step(122): len = 431002, overlap = 202.938
+PHY-3002 : Step(123): len = 432209, overlap = 203.312
+PHY-3002 : Step(124): len = 432990, overlap = 199.438
+PHY-3002 : Step(125): len = 431650, overlap = 197.531
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000249287
+PHY-3002 : Step(126): len = 439400, overlap = 197.625
+PHY-3002 : Step(127): len = 446841, overlap = 190.656
+PHY-3002 : Step(128): len = 447598, overlap = 176.688
+PHY-3002 : Step(129): len = 449318, overlap = 180.094
+PHY-3002 : Step(130): len = 452921, overlap = 183.25
+PHY-3002 : Step(131): len = 455157, overlap = 182.219
+PHY-3002 : Step(132): len = 453478, overlap = 178.594
+PHY-3002 : Step(133): len = 454112, overlap = 181
+PHY-3002 : Step(134): len = 456932, overlap = 177.781
+PHY-3002 : Step(135): len = 458697, overlap = 177.312
+PHY-3002 : Step(136): len = 457443, overlap = 173.469
+PHY-3002 : Step(137): len = 458270, overlap = 170.812
+PHY-3002 : Step(138): len = 461260, overlap = 170.906
+PHY-3002 : Step(139): len = 462647, overlap = 169.719
+PHY-3002 : Step(140): len = 460384, overlap = 168.562
+PHY-3002 : Step(141): len = 459960, overlap = 169.219
+PHY-3002 : Step(142): len = 462174, overlap = 170.781
+PHY-3002 : Step(143): len = 463466, overlap = 169.25
+PHY-3002 : Step(144): len = 461725, overlap = 174.75
+PHY-3002 : Step(145): len = 461228, overlap = 174.969
+PHY-3002 : Step(146): len = 464062, overlap = 180.281
+PHY-3002 : Step(147): len = 468524, overlap = 177.844
+PHY-3002 : Step(148): len = 466247, overlap = 177.938
+PHY-3002 : Step(149): len = 465142, overlap = 178.969
+PHY-3002 : Step(150): len = 465542, overlap = 170.562
+PHY-3002 : Step(151): len = 465736, overlap = 170.281
+PHY-3002 : Step(152): len = 463459, overlap = 173.188
+PHY-3002 : Step(153): len = 463041, overlap = 173.531
+PHY-3002 : Step(154): len = 463945, overlap = 173.312
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000498573
+PHY-3002 : Step(155): len = 471754, overlap = 177
+PHY-3002 : Step(156): len = 481795, overlap = 174.719
+PHY-3002 : Step(157): len = 484614, overlap = 175.125
+PHY-3002 : Step(158): len = 486695, overlap = 166.875
+PHY-3002 : Step(159): len = 488701, overlap = 162.281
+PHY-3002 : Step(160): len = 492381, overlap = 152.594
+PHY-3002 : Step(161): len = 491773, overlap = 156.875
+PHY-3002 : Step(162): len = 491629, overlap = 151.375
+PHY-3002 : Step(163): len = 492856, overlap = 156.969
+PHY-3002 : Step(164): len = 493439, overlap = 159.406
+PHY-3002 : Step(165): len = 492130, overlap = 163.156
+PHY-3002 : Step(166): len = 491556, overlap = 165.75
+PHY-3002 : Step(167): len = 491623, overlap = 162.656
+PHY-3002 : Step(168): len = 491664, overlap = 162.375
+PHY-3002 : Step(169): len = 490655, overlap = 163.906
+PHY-3002 : Step(170): len = 490319, overlap = 163.844
+PHY-3002 : Step(171): len = 490593, overlap = 161.719
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000955965
+PHY-3002 : Step(172): len = 494237, overlap = 157.156
+PHY-3002 : Step(173): len = 498639, overlap = 157.875
+PHY-3002 : Step(174): len = 499801, overlap = 152.625
+PHY-3002 : Step(175): len = 501040, overlap = 152.469
+PHY-3002 : Step(176): len = 503146, overlap = 148.906
+PHY-3002 : Step(177): len = 504300, overlap = 149.625
+PHY-3002 : Step(178): len = 503796, overlap = 151.094
+PHY-3002 : Step(179): len = 503663, overlap = 150.281
+PHY-3002 : Step(180): len = 504531, overlap = 150.406
+PHY-3002 : Step(181): len = 504781, overlap = 148.688
+PHY-3002 : Step(182): len = 504589, overlap = 149.781
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00163413
+PHY-3002 : Step(183): len = 507921, overlap = 145.344
+PHY-3002 : Step(184): len = 513383, overlap = 143.75
+PHY-3002 : Step(185): len = 514330, overlap = 143.406
+PHY-3002 : Step(186): len = 514978, overlap = 140.781
+PHY-3002 : Step(187): len = 516224, overlap = 138.719
+PHY-3002 : Step(188): len = 516650, overlap = 138.219
+PHY-3002 : Step(189): len = 515958, overlap = 137.562
+PHY-3002 : Step(190): len = 515871, overlap = 137.75
+PHY-3002 : Step(191): len = 516361, overlap = 141.094
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00264922
+PHY-3002 : Step(192): len = 518282, overlap = 137.844
+PHY-3002 : Step(193): len = 524428, overlap = 135.781
+PHY-3002 : Step(194): len = 527329, overlap = 132.969
+PHY-3002 : Step(195): len = 530423, overlap = 136
+PHY-3002 : Step(196): len = 532499, overlap = 137.5
+PHY-3002 : Step(197): len = 533996, overlap = 138.062
+PHY-3002 : Step(198): len = 534016, overlap = 138.594
+PHY-3002 : Step(199): len = 534234, overlap = 140.531
+PHY-3002 : Step(200): len = 535041, overlap = 141.656
+PHY-3002 : Step(201): len = 535517, overlap = 144.094
+PHY-3002 : Step(202): len = 535235, overlap = 141.656
+PHY-3002 : Step(203): len = 535187, overlap = 140.75
+PHY-3002 : Step(204): len = 535426, overlap = 140.594
+PHY-3002 : Step(205): len = 535490, overlap = 140.031
+PHY-3002 : Step(206): len = 535394, overlap = 140.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.017863s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (87.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724176, over cnt = 1608(4%), over = 7564, worst = 44
+PHY-1001 : End global iterations; 0.738099s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (124.9%)
+
+PHY-1001 : Congestion index: top1 = 82.18, top5 = 62.60, top10 = 53.70, top15 = 47.73.
+PHY-3001 : End congestion estimation; 0.982287s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (119.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.925268s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000139923
+PHY-3002 : Step(207): len = 659053, overlap = 90.25
+PHY-3002 : Step(208): len = 659256, overlap = 75.8125
+PHY-3002 : Step(209): len = 654866, overlap = 77.6562
+PHY-3002 : Step(210): len = 652000, overlap = 69.3438
+PHY-3002 : Step(211): len = 648086, overlap = 73
+PHY-3002 : Step(212): len = 645995, overlap = 74.1562
+PHY-3002 : Step(213): len = 646121, overlap = 64.8125
+PHY-3002 : Step(214): len = 642625, overlap = 47.875
+PHY-3002 : Step(215): len = 639623, overlap = 41.625
+PHY-3002 : Step(216): len = 635933, overlap = 41.75
+PHY-3002 : Step(217): len = 634322, overlap = 35.0625
+PHY-3002 : Step(218): len = 633763, overlap = 36.1562
+PHY-3002 : Step(219): len = 631439, overlap = 35.25
+PHY-3002 : Step(220): len = 630193, overlap = 36.1875
+PHY-3002 : Step(221): len = 630982, overlap = 33.9062
+PHY-3002 : Step(222): len = 632224, overlap = 31.3125
+PHY-3002 : Step(223): len = 630995, overlap = 35.25
+PHY-3002 : Step(224): len = 629428, overlap = 35.7188
+PHY-3002 : Step(225): len = 629339, overlap = 38.0312
+PHY-3002 : Step(226): len = 629239, overlap = 36.1562
+PHY-3002 : Step(227): len = 628107, overlap = 34.125
+PHY-3002 : Step(228): len = 627386, overlap = 32.5938
+PHY-3002 : Step(229): len = 626156, overlap = 31.75
+PHY-3002 : Step(230): len = 625719, overlap = 30.6875
+PHY-3002 : Step(231): len = 624488, overlap = 34.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000279845
+PHY-3002 : Step(232): len = 628045, overlap = 31.4062
+PHY-3002 : Step(233): len = 632627, overlap = 29.9688
+PHY-3002 : Step(234): len = 638183, overlap = 28.6562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000553752
+PHY-3002 : Step(235): len = 648263, overlap = 27.1562
+PHY-3002 : Step(236): len = 662828, overlap = 21.9688
+PHY-3002 : Step(237): len = 667158, overlap = 21.25
+PHY-3002 : Step(238): len = 668639, overlap = 21.25
+PHY-3002 : Step(239): len = 668431, overlap = 21.4688
+PHY-3002 : Step(240): len = 669642, overlap = 18.3438
+PHY-3002 : Step(241): len = 670818, overlap = 19.5
+PHY-3002 : Step(242): len = 672420, overlap = 20.0938
+PHY-3002 : Step(243): len = 673620, overlap = 21.4688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.0011075
+PHY-3002 : Step(244): len = 680186, overlap = 22.5938
+PHY-3002 : Step(245): len = 690743, overlap = 24.4375
+PHY-3002 : Step(246): len = 695492, overlap = 23.5625
+PHY-3002 : Step(247): len = 701751, overlap = 21.1562
+PHY-3002 : Step(248): len = 706766, overlap = 19.5312
+PHY-3002 : Step(249): len = 710604, overlap = 15
+PHY-3002 : Step(250): len = 709311, overlap = 16.4062
+PHY-3002 : Step(251): len = 707604, overlap = 15.9688
+PHY-3002 : Step(252): len = 706365, overlap = 17.5625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00192397
+PHY-3002 : Step(253): len = 709133, overlap = 17.7812
+PHY-3002 : Step(254): len = 714916, overlap = 18.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 34/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 796776, over cnt = 2781(7%), over = 13271, worst = 53
+PHY-1001 : End global iterations; 1.842181s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 84.48, top5 = 70.19, top10 = 61.93, top15 = 56.65.
+PHY-3001 : End congestion estimation; 2.151678s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (132.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.981430s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012911
+PHY-3002 : Step(255): len = 702575, overlap = 215.312
+PHY-3002 : Step(256): len = 694599, overlap = 162
+PHY-3002 : Step(257): len = 679536, overlap = 145.25
+PHY-3002 : Step(258): len = 668745, overlap = 130.406
+PHY-3002 : Step(259): len = 659309, overlap = 117.5
+PHY-3002 : Step(260): len = 654101, overlap = 114.969
+PHY-3002 : Step(261): len = 647746, overlap = 118.219
+PHY-3002 : Step(262): len = 642356, overlap = 118.719
+PHY-3002 : Step(263): len = 638947, overlap = 124.344
+PHY-3002 : Step(264): len = 635915, overlap = 122.469
+PHY-3002 : Step(265): len = 632218, overlap = 115.188
+PHY-3002 : Step(266): len = 629863, overlap = 121.938
+PHY-3002 : Step(267): len = 626057, overlap = 128.094
+PHY-3002 : Step(268): len = 623166, overlap = 127.625
+PHY-3002 : Step(269): len = 620427, overlap = 122.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00025822
+PHY-3002 : Step(270): len = 622298, overlap = 120.219
+PHY-3002 : Step(271): len = 625863, overlap = 111.969
+PHY-3002 : Step(272): len = 628994, overlap = 113.281
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00051644
+PHY-3002 : Step(273): len = 632305, overlap = 110.906
+PHY-3002 : Step(274): len = 637674, overlap = 105.094
+PHY-3002 : Step(275): len = 642628, overlap = 98.1562
+PHY-3002 : Step(276): len = 643223, overlap = 92.7188
+PHY-3002 : Step(277): len = 643616, overlap = 87.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00103288
+PHY-3002 : Step(278): len = 647008, overlap = 84.9688
+PHY-3002 : Step(279): len = 651532, overlap = 84.2812
+PHY-3002 : Step(280): len = 657543, overlap = 78.9375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00193902
+PHY-3002 : Step(281): len = 658349, overlap = 79.375
+PHY-3002 : Step(282): len = 662685, overlap = 80.9062
+PHY-3002 : Step(283): len = 673708, overlap = 72.4688
+PHY-3002 : Step(284): len = 677941, overlap = 67.0938
+PHY-3002 : Step(285): len = 679645, overlap = 65.8438
+PHY-3002 : Step(286): len = 679514, overlap = 62.875
+PHY-3002 : Step(287): len = 679430, overlap = 61
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84112, tnet num: 20420, tinst num: 18012, tnode num: 114469, tedge num: 134134.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.582292s wall, 1.562500s user + 0.031250s system = 1.593750s CPU (100.7%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 564 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 378.44 peak overflow 2.59
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 562/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 778808, over cnt = 3104(8%), over = 11165, worst = 22
+PHY-1001 : End global iterations; 1.559381s wall, 2.265625s user + 0.109375s system = 2.375000s CPU (152.3%)
+
+PHY-1001 : Congestion index: top1 = 75.95, top5 = 60.55, top10 = 53.69, top15 = 49.60.
+PHY-1001 : End incremental global routing; 1.951382s wall, 2.656250s user + 0.109375s system = 2.765625s CPU (141.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.225054s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.8%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17881 has valid locations, 302 needs to be replaced
+PHY-3001 : design contains 18268 instances, 7752 luts, 9295 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6096 pins
+PHY-3001 : Found 1253 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 702799
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17354/20854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 795536, over cnt = 3120(8%), over = 11280, worst = 22
+PHY-1001 : End global iterations; 0.241607s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (155.2%)
+
+PHY-1001 : Congestion index: top1 = 75.34, top5 = 60.55, top10 = 53.90, top15 = 49.82.
+PHY-3001 : End congestion estimation; 0.523322s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (122.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85136, tnet num: 20676, tinst num: 18268, tnode num: 116013, tedge num: 135670.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.552884s wall, 1.500000s user + 0.062500s system = 1.562500s CPU (100.6%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 616 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.551567s wall, 2.468750s user + 0.078125s system = 2.546875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(288): len = 701928, overlap = 0
+PHY-3002 : Step(289): len = 701320, overlap = 0
+PHY-3002 : Step(290): len = 700932, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17435/20854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 792680, over cnt = 3121(8%), over = 11317, worst = 22
+PHY-1001 : End global iterations; 0.208908s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 75.91, top5 = 60.88, top10 = 54.10, top15 = 49.92.
+PHY-3001 : End congestion estimation; 0.492375s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (114.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.002881s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000374913
+PHY-3002 : Step(291): len = 700819, overlap = 62.875
+PHY-3002 : Step(292): len = 700870, overlap = 62.8438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000749826
+PHY-3002 : Step(293): len = 700770, overlap = 63.2188
+PHY-3002 : Step(294): len = 701306, overlap = 64.0312
+PHY-3001 : Final: Len = 701306, Over = 64.0312
+PHY-3001 : End incremental placement; 5.330202s wall, 5.656250s user + 0.343750s system = 6.000000s CPU (112.6%)
+
+OPT-1001 : Total overflow 384.16 peak overflow 2.59
+OPT-1001 : End high-fanout net optimization; 9.104367s wall, 10.234375s user + 0.453125s system = 10.687500s CPU (117.4%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 711, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17386/20854.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 794544, over cnt = 3074(8%), over = 10278, worst = 22
+PHY-1002 : len = 835960, over cnt = 2199(6%), over = 6103, worst = 22
+PHY-1002 : len = 893128, over cnt = 766(2%), over = 1842, worst = 20
+PHY-1002 : len = 908888, over cnt = 329(0%), over = 771, worst = 16
+PHY-1002 : len = 920968, over cnt = 7(0%), over = 9, worst = 2
+PHY-1001 : End global iterations; 2.149666s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (130.1%)
+
+PHY-1001 : Congestion index: top1 = 59.59, top5 = 51.70, top10 = 47.76, top15 = 45.28.
+OPT-1001 : End congestion update; 2.444931s wall, 3.062500s user + 0.015625s system = 3.078125s CPU (125.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20676 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.864567s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (101.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 125 cells processed and 18600 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 33 cells processed and 2050 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved
+OPT-1001 : End bottleneck based optimization; 3.751495s wall, 4.343750s user + 0.031250s system = 4.375000s CPU (116.6%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 694, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17452/20859.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 921312, over cnt = 69(0%), over = 90, worst = 3
+PHY-1002 : len = 921416, over cnt = 30(0%), over = 35, worst = 2
+PHY-1002 : len = 921568, over cnt = 15(0%), over = 17, worst = 2
+PHY-1002 : len = 921720, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 921944, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.991308s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (110.3%)
+
+PHY-1001 : Congestion index: top1 = 60.02, top5 = 51.75, top10 = 47.78, top15 = 45.31.
+OPT-1001 : End congestion update; 1.285532s wall, 1.375000s user + 0.015625s system = 1.390625s CPU (108.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20681 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.065961s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (101.1%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 19 cells processed and 6200 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.475072s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (104.2%)
+
+OPT-1001 : Current memory(MB): used = 707, reserve = 703, peak = 733.
+OPT-1001 : End physical optimization; 17.251626s wall, 19.140625s user + 0.531250s system = 19.671875s CPU (114.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7752 LUT to BLE ...
+SYN-4008 : Packed 7752 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6153 remaining SEQ's ...
+SYN-4005 : Packed 4141 SEQ with LUT/SLICE
+SYN-4006 : 761 single LUT's are left
+SYN-4006 : 2012 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9764/13619 primitive instances ...
+PHY-3001 : End packing; 1.848215s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (99.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6677 instances
+RUN-1001 : 3264 mslices, 3265 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17848 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10001 nets have 2 pins
+RUN-1001 : 6500 nets have [3 - 5] pins
+RUN-1001 : 727 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6675 instances, 6529 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3555 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 704024, Over = 216.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7528/17848.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856128, over cnt = 1956(5%), over = 3228, worst = 7
+PHY-1002 : len = 863432, over cnt = 1307(3%), over = 1955, worst = 7
+PHY-1002 : len = 879328, over cnt = 471(1%), over = 682, worst = 7
+PHY-1002 : len = 887704, over cnt = 109(0%), over = 133, worst = 4
+PHY-1002 : len = 890472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.865026s wall, 2.750000s user + 0.046875s system = 2.796875s CPU (150.0%)
+
+PHY-1001 : Congestion index: top1 = 57.72, top5 = 50.55, top10 = 46.64, top15 = 44.16.
+PHY-3001 : End congestion estimation; 2.313655s wall, 3.203125s user + 0.046875s system = 3.250000s CPU (140.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71360, tnet num: 17670, tinst num: 6675, tnode num: 93746, tedge num: 118612.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.884740s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (97.8%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 619 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17670 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.835291s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.81781e-05
+PHY-3002 : Step(295): len = 689285, overlap = 208.75
+PHY-3002 : Step(296): len = 681621, overlap = 214.25
+PHY-3002 : Step(297): len = 675433, overlap = 216.5
+PHY-3002 : Step(298): len = 671348, overlap = 218
+PHY-3002 : Step(299): len = 667818, overlap = 216.25
+PHY-3002 : Step(300): len = 664338, overlap = 223.5
+PHY-3002 : Step(301): len = 660522, overlap = 223.75
+PHY-3002 : Step(302): len = 657979, overlap = 212.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000116356
+PHY-3002 : Step(303): len = 660150, overlap = 201
+PHY-3002 : Step(304): len = 664393, overlap = 198.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000232712
+PHY-3002 : Step(305): len = 667150, overlap = 190.5
+PHY-3002 : Step(306): len = 674836, overlap = 175.25
+PHY-3002 : Step(307): len = 676570, overlap = 168
+PHY-3002 : Step(308): len = 677902, overlap = 162.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.427902s wall, 0.375000s user + 0.843750s system = 1.218750s CPU (284.8%)
+
+PHY-3001 : Trial Legalized: Len = 754476
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 704/17848.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865552, over cnt = 2602(7%), over = 4362, worst = 8
+PHY-1002 : len = 882576, over cnt = 1505(4%), over = 2255, worst = 7
+PHY-1002 : len = 902416, over cnt = 537(1%), over = 765, worst = 7
+PHY-1002 : len = 910448, over cnt = 184(0%), over = 272, worst = 4
+PHY-1002 : len = 914392, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.935895s wall, 4.203125s user + 0.031250s system = 4.234375s CPU (144.2%)
+
+PHY-1001 : Congestion index: top1 = 56.31, top5 = 50.41, top10 = 47.09, top15 = 44.99.
+PHY-3001 : End congestion estimation; 3.462774s wall, 4.718750s user + 0.031250s system = 4.750000s CPU (137.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17670 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.940506s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (101.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171958
+PHY-3002 : Step(309): len = 729082, overlap = 28.75
+PHY-3002 : Step(310): len = 714660, overlap = 52
+PHY-3002 : Step(311): len = 701932, overlap = 75.75
+PHY-3002 : Step(312): len = 695099, overlap = 92.25
+PHY-3002 : Step(313): len = 689739, overlap = 107.75
+PHY-3002 : Step(314): len = 686771, overlap = 117.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343916
+PHY-3002 : Step(315): len = 691103, overlap = 116.5
+PHY-3002 : Step(316): len = 694958, overlap = 115.25
+PHY-3002 : Step(317): len = 695662, overlap = 119
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000687832
+PHY-3002 : Step(318): len = 698615, overlap = 117.5
+PHY-3002 : Step(319): len = 704966, overlap = 113.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.035745s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (87.4%)
+
+PHY-3001 : Legalized: Len = 732315, Over = 0
+PHY-3001 : Spreading special nets. 481 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.113142s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (96.7%)
+
+PHY-3001 : 701 instances has been re-located, deltaX = 214, deltaY = 417, maxDist = 3.
+PHY-3001 : Final: Len = 743705, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71360, tnet num: 17670, tinst num: 6678, tnode num: 93746, tedge num: 118612.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.038412s wall, 2.000000s user + 0.031250s system = 2.031250s CPU (99.6%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 637 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4476/17848.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 870424, over cnt = 2416(6%), over = 3841, worst = 6
+PHY-1002 : len = 884136, over cnt = 1318(3%), over = 1815, worst = 5
+PHY-1002 : len = 895848, over cnt = 624(1%), over = 841, worst = 4
+PHY-1002 : len = 905744, over cnt = 187(0%), over = 234, worst = 4
+PHY-1002 : len = 909456, over cnt = 5(0%), over = 5, worst = 1
+PHY-1001 : End global iterations; 2.264256s wall, 3.312500s user + 0.031250s system = 3.343750s CPU (147.7%)
+
+PHY-1001 : Congestion index: top1 = 54.14, top5 = 48.58, top10 = 45.78, top15 = 43.93.
+PHY-1001 : End incremental global routing; 2.682841s wall, 3.734375s user + 0.031250s system = 3.765625s CPU (140.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17670 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.935262s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.2%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6586 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6695 instances, 6546 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3615 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 747394
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16284/17866.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912616, over cnt = 77(0%), over = 92, worst = 6
+PHY-1002 : len = 912752, over cnt = 35(0%), over = 40, worst = 3
+PHY-1002 : len = 913032, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 913032, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 913400, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.854386s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (109.7%)
+
+PHY-1001 : Congestion index: top1 = 54.20, top5 = 48.66, top10 = 45.87, top15 = 44.06.
+PHY-3001 : End congestion estimation; 1.196762s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (107.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71484, tnet num: 17688, tinst num: 6695, tnode num: 93891, tedge num: 118761.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.987514s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (99.8%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 657 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17688 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.948178s wall, 2.921875s user + 0.031250s system = 2.953125s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(320): len = 746354, overlap = 0
+PHY-3002 : Step(321): len = 745932, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16273/17866.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911344, over cnt = 59(0%), over = 68, worst = 4
+PHY-1002 : len = 911408, over cnt = 43(0%), over = 45, worst = 2
+PHY-1002 : len = 911760, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 911912, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.664264s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (105.9%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 48.59, top10 = 45.84, top15 = 44.03.
+PHY-3001 : End congestion estimation; 1.021492s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (102.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17688 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.916156s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000323322
+PHY-3002 : Step(322): len = 745805, overlap = 0.5
+PHY-3002 : Step(323): len = 745796, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005777s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 745833, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065287s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 745869, Over = 0
+PHY-3001 : End incremental placement; 6.612728s wall, 6.843750s user + 0.078125s system = 6.921875s CPU (104.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.759946s wall, 12.015625s user + 0.125000s system = 12.140625s CPU (112.8%)
+
+OPT-1001 : Current memory(MB): used = 728, reserve = 728, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16273/17866.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911816, over cnt = 46(0%), over = 55, worst = 4
+PHY-1002 : len = 911888, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 912088, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 912120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.632977s wall, 0.656250s user + 0.031250s system = 0.687500s CPU (108.6%)
+
+PHY-1001 : Congestion index: top1 = 54.07, top5 = 48.60, top10 = 45.83, top15 = 44.03.
+OPT-1001 : End congestion update; 0.979184s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (105.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17688 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.765618s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.0%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6607 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6695 instances, 6546 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3615 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 751470, Over = 0
+PHY-3001 : Spreading special nets. 31 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.071157s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (87.8%)
+
+PHY-3001 : 45 instances has been re-located, deltaX = 16, deltaY = 38, maxDist = 2.
+PHY-3001 : Final: Len = 752458, Over = 0
+PHY-3001 : End incremental legalization; 0.427131s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (98.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 59 cells processed and 20147 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6607 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6695 instances, 6546 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3615 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 752286, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065484s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.4%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 15, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 752900, Over = 0
+PHY-3001 : End incremental legalization; 0.415170s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (105.4%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 26 cells processed and 1854 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6614 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6702 instances, 6553 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 754265, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064347s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.1%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 7, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 754463, Over = 0
+PHY-3001 : End incremental legalization; 0.421600s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (114.9%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 7 cells processed and 1590 slack improved
+OPT-1001 : End bottleneck based optimization; 3.552001s wall, 3.609375s user + 0.062500s system = 3.671875s CPU (103.4%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15892/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 920808, over cnt = 161(0%), over = 217, worst = 9
+PHY-1002 : len = 921192, over cnt = 78(0%), over = 85, worst = 3
+PHY-1002 : len = 921768, over cnt = 30(0%), over = 32, worst = 2
+PHY-1002 : len = 922032, over cnt = 9(0%), over = 10, worst = 2
+PHY-1002 : len = 922160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.902580s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (109.1%)
+
+PHY-1001 : Congestion index: top1 = 54.46, top5 = 48.67, top10 = 45.79, top15 = 44.01.
+OPT-1001 : End congestion update; 1.253559s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (107.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.770092s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6614 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6702 instances, 6553 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 754221, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066837s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.5%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 11, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 754593, Over = 0
+PHY-3001 : End incremental legalization; 0.421841s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (122.2%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 19 cells processed and 2400 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.589133s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (106.8%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 733.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.781798s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16226/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 921960, over cnt = 42(0%), over = 45, worst = 2
+PHY-1002 : len = 921912, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 922032, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 922072, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 922120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.885652s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 54.53, top5 = 48.62, top10 = 45.79, top15 = 44.01.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.797516s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 71 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.103448
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 71ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6614 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6702 instances, 6553 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 754593, Over = 0
+PHY-3001 : End spreading; 0.065497s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.4%)
+
+PHY-3001 : Final: Len = 754593, Over = 0
+PHY-3001 : End incremental legalization; 0.429590s wall, 0.406250s user + 0.031250s system = 0.437500s CPU (101.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.769030s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.6%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16299/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.155427s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.5%)
+
+PHY-1001 : Congestion index: top1 = 54.53, top5 = 48.62, top10 = 45.79, top15 = 44.01.
+OPT-1001 : End congestion update; 0.505666s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (98.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.767055s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.8%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6614 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6702 instances, 6553 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 754559, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062721s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 754593, Over = 0
+PHY-3001 : End incremental legalization; 0.411856s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.802723s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.7%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16299/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.149249s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 54.53, top5 = 48.62, top10 = 45.79, top15 = 44.01.
+OPT-1001 : End congestion update; 0.495760s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (100.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.782674s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.8%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6614 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6702 instances, 6553 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 754559, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064800s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (120.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 754593, Over = 0
+PHY-3001 : End incremental legalization; 0.412491s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.5%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 150 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6614 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6702 instances, 6553 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 754559, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064590s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 754593, Over = 0
+PHY-3001 : End incremental legalization; 0.419658s wall, 0.390625s user + 0.046875s system = 0.437500s CPU (104.3%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.414396s wall, 2.500000s user + 0.046875s system = 2.546875s CPU (105.5%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 733.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.780282s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 733.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.806140s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (96.9%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16299/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.148012s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.0%)
+
+PHY-1001 : Congestion index: top1 = 54.53, top5 = 48.62, top10 = 45.79, top15 = 44.01.
+RUN-1001 : End congestion update; 0.503272s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (102.5%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.313519s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (98.7%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 729, peak = 733.
+OPT-1001 : End physical optimization; 29.699738s wall, 31.265625s user + 0.296875s system = 31.562500s CPU (106.3%)
+
+RUN-1003 : finish command "place" in 82.100250s wall, 120.343750s user + 7.375000s system = 127.718750s CPU (155.6%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 638 MB, peak memory is 733 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.809506s wall, 3.156250s user + 0.000000s system = 3.156250s CPU (174.4%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 639 MB, peak memory is 733 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6704 instances
+RUN-1001 : 3280 mslices, 3273 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17868 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9987 nets have 2 pins
+RUN-1001 : 6507 nets have [3 - 5] pins
+RUN-1001 : 743 nets have [6 - 10] pins
+RUN-1001 : 293 nets have [11 - 20] pins
+RUN-1001 : 310 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71547, tnet num: 17690, tinst num: 6702, tnode num: 93976, tedge num: 118847.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.748308s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.1%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 612 MB, peak memory is 733 MB
+PHY-1001 : 3280 mslices, 3273 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858736, over cnt = 2627(7%), over = 4291, worst = 8
+PHY-1002 : len = 877384, over cnt = 1538(4%), over = 2147, worst = 7
+PHY-1002 : len = 892792, over cnt = 655(1%), over = 903, worst = 7
+PHY-1002 : len = 906232, over cnt = 33(0%), over = 37, worst = 5
+PHY-1002 : len = 907184, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.423709s wall, 4.593750s user + 0.062500s system = 4.656250s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 54.87, top5 = 48.54, top10 = 45.60, top15 = 43.70.
+PHY-1001 : End global routing; 3.791210s wall, 4.968750s user + 0.062500s system = 5.031250s CPU (132.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 701, reserve = 705, peak = 733.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 974, reserve = 980, peak = 974.
+PHY-1001 : End build detailed router design. 4.450121s wall, 4.343750s user + 0.109375s system = 4.453125s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 275976, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.103226s wall, 6.078125s user + 0.015625s system = 6.093750s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 276032, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.492868s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.4%)
+
+PHY-1001 : Current memory(MB): used = 1011, reserve = 1017, peak = 1011.
+PHY-1001 : End phase 1; 6.610411s wall, 6.593750s user + 0.015625s system = 6.609375s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28306e+06, over cnt = 1679(0%), over = 1687, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1027, reserve = 1032, peak = 1027.
+PHY-1001 : End initial routed; 35.717466s wall, 74.546875s user + 0.281250s system = 74.828125s CPU (209.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16791(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.821 | -0.821 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.682321s wall, 3.640625s user + 0.015625s system = 3.656250s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1037, reserve = 1041, peak = 1037.
+PHY-1001 : End phase 2; 39.399855s wall, 78.187500s user + 0.296875s system = 78.484375s CPU (199.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.810ns STNS -0.810ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.151642s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.0%)
+
+PHY-1022 : len = 2.28306e+06, over cnt = 1680(0%), over = 1688, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.450583s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.25993e+06, over cnt = 748(0%), over = 749, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.115197s wall, 2.046875s user + 0.015625s system = 2.062500s CPU (184.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25346e+06, over cnt = 143(0%), over = 143, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.933223s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (142.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25374e+06, over cnt = 20(0%), over = 20, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.387846s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (104.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25389e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.293575s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (106.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.209352s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.0%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.25391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.279238s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.25391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.429901s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.8%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.25391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.185685s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.25384e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.185188s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (109.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16791(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.810 | -0.810 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.625186s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 524 feed throughs used by 389 nets
+PHY-1001 : End commit to database; 2.456300s wall, 2.421875s user + 0.031250s system = 2.453125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1138, reserve = 1146, peak = 1138.
+PHY-1001 : End phase 3; 11.000215s wall, 12.343750s user + 0.046875s system = 12.390625s CPU (112.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.810ns STNS -0.810ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.152243s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.6%)
+
+PHY-1022 : len = 2.25384e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.439527s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.810ns, -0.810ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16791(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.810 | -0.810 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.552646s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 524 feed throughs used by 389 nets
+PHY-1001 : End commit to database; 2.551114s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1156, peak = 1147.
+PHY-1001 : End phase 4; 6.574189s wall, 6.562500s user + 0.000000s system = 6.562500s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.25384e+06
+PHY-1001 : Current memory(MB): used = 1149, reserve = 1158, peak = 1149.
+PHY-1001 : End export database. 0.066851s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.5%)
+
+PHY-1001 : End detail routing; 68.534636s wall, 108.531250s user + 0.468750s system = 109.000000s CPU (159.0%)
+
+RUN-1003 : finish command "route" in 75.211262s wall, 116.343750s user + 0.562500s system = 116.906250s CPU (155.4%)
+
+RUN-1004 : used memory is 1144 MB, reserved memory is 1154 MB, peak memory is 1149 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10160 out of 19600 51.84%
+#reg 9441 out of 19600 48.17%
+#le 12133
+ #lut only 2692 out of 12133 22.19%
+ #reg only 1973 out of 12133 16.26%
+ #lut® 7468 out of 12133 61.55%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1775
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1387
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1292
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 981
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice a_frame_pad_d0_reg_syn_17.q0 134
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg1_syn_156.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg45_syn_201.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P165 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12133 |9133 |1027 |9475 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |549 |462 |23 |447 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |88 |4 |93 |4 |0 |
+| U_crc16_24b |crc16_24b |24 |24 |0 |14 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |752 |397 |96 |571 |0 |0 |
+| u_ADconfig |AD_config |184 |136 |25 |138 |0 |0 |
+| u_gen_sp |gen_sp |255 |136 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |730 |375 |96 |553 |0 |0 |
+| u_ADconfig |AD_config |170 |116 |25 |128 |0 |0 |
+| u_gen_sp |gen_sp |254 |165 |71 |119 |0 |0 |
+| sampling_fe_a |sampling_fe |2901 |2358 |306 |2095 |25 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |108 |17 |154 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2685 |2241 |289 |1909 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2235 |1880 |253 |1541 |22 |0 |
+| channelPart |channel_part_8478 |147 |134 |3 |142 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |47 |0 |0 |
+| ram_switch |ram_switch |1716 |1447 |197 |1131 |0 |0 |
+| adc_addr_gen |adc_addr_gen |210 |183 |27 |122 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |16 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |23 |20 |3 |10 |0 |0 |
+| insert |insert |938 |697 |170 |647 |0 |0 |
+| ram_switch_state |ram_switch_state |568 |567 |0 |362 |0 |0 |
+| read_ram_i |read_ram |277 |219 |44 |193 |0 |0 |
+| read_ram_addr |read_ram_addr |230 |190 |40 |157 |0 |0 |
+| read_ram_data |read_ram_data |44 |28 |4 |33 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |327 |245 |36 |275 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3121 |2457 |349 |2105 |25 |1 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |103 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2899 |2341 |332 |1914 |25 |1 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2490 |2021 |290 |1569 |22 |1 |
+| channelPart |channel_part_8478 |140 |124 |3 |134 |0 |0 |
+| fifo_adc |fifo_adc |55 |46 |9 |40 |0 |1 |
+| ram_switch |ram_switch |1916 |1579 |197 |1154 |0 |0 |
+| adc_addr_gen |adc_addr_gen |198 |171 |27 |100 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |18 |15 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |7 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |10 |3 |3 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| insert |insert |983 |674 |170 |696 |0 |0 |
+| ram_switch_state |ram_switch_state |735 |734 |0 |358 |0 |0 |
+| read_ram_i |read_ram_rev |348 |248 |81 |210 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |287 |210 |73 |163 |0 |0 |
+| read_ram_data |read_ram_data_rev |61 |38 |8 |47 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9925
+ #2 2 4256
+ #3 3 1688
+ #4 4 560
+ #5 5-10 780
+ #6 11-50 552
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.160351s wall, 3.765625s user + 0.031250s system = 3.796875s CPU (175.8%)
+
+RUN-1004 : used memory is 1144 MB, reserved memory is 1153 MB, peak memory is 1199 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71547, tnet num: 17690, tinst num: 6702, tnode num: 93976, tedge num: 118847.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.720024s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.9%)
+
+RUN-1004 : used memory is 1145 MB, reserved memory is 1154 MB, peak memory is 1199 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.606784s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (99.2%)
+
+RUN-1004 : used memory is 1146 MB, reserved memory is 1154 MB, peak memory is 1199 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6702
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17868, pip num: 168071
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 524
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3239 valid insts, and 468514 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.756317s wall, 69.281250s user + 0.375000s system = 69.656250s CPU (647.6%)
+
+RUN-1004 : used memory is 1247 MB, reserved memory is 1250 MB, peak memory is 1362 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_162229.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_165409.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_165409.log
new file mode 100644
index 0000000..d72e6dc
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_165409.log
@@ -0,0 +1,2180 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 16:54:09 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(855)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(864)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(888)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(890)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(896)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(899)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1070)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1159)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1460)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1471)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1489)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1671)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2067)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.228028s wall, 2.171875s user + 0.046875s system = 2.218750s CPU (99.6%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 323 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2404 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2243 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18499 instances
+RUN-0007 : 7778 luts, 9492 seqs, 708 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21105 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13395 nets have 2 pins
+RUN-1001 : 6676 nets have [3 - 5] pins
+RUN-1001 : 609 nets have [6 - 10] pins
+RUN-1001 : 185 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 803
+RUN-1001 : No | No | Yes | 2377
+RUN-1001 : No | Yes | No | 3503
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18497 instances, 7778 luts, 9492 seqs, 1081 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6334 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86164, tnet num: 20905, tinst num: 18497, tnode num: 117604, tedge num: 137258.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.149299s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (100.6%)
+
+RUN-1004 : used memory is 541 MB, reserved memory is 526 MB, peak memory is 541 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20905 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.934658s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (100.1%)
+
+PHY-3001 : Found 1253 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.06254e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18497.
+PHY-3001 : Level 1 #clusters 2088.
+PHY-3001 : End clustering; 0.127689s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (146.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29115e+06, overlap = 440.781
+PHY-3002 : Step(2): len = 1.21346e+06, overlap = 506.812
+PHY-3002 : Step(3): len = 856778, overlap = 583.562
+PHY-3002 : Step(4): len = 783511, overlap = 637.156
+PHY-3002 : Step(5): len = 625963, overlap = 755.906
+PHY-3002 : Step(6): len = 566629, overlap = 791
+PHY-3002 : Step(7): len = 482043, overlap = 891.5
+PHY-3002 : Step(8): len = 435898, overlap = 932.344
+PHY-3002 : Step(9): len = 399591, overlap = 988.281
+PHY-3002 : Step(10): len = 356666, overlap = 1048.62
+PHY-3002 : Step(11): len = 326958, overlap = 1103.06
+PHY-3002 : Step(12): len = 299194, overlap = 1156.44
+PHY-3002 : Step(13): len = 277339, overlap = 1210.34
+PHY-3002 : Step(14): len = 245801, overlap = 1263.69
+PHY-3002 : Step(15): len = 230188, overlap = 1337.03
+PHY-3002 : Step(16): len = 209809, overlap = 1358.66
+PHY-3002 : Step(17): len = 192498, overlap = 1376.19
+PHY-3002 : Step(18): len = 172803, overlap = 1434.75
+PHY-3002 : Step(19): len = 161608, overlap = 1441.25
+PHY-3002 : Step(20): len = 149993, overlap = 1455.38
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.25169e-06
+PHY-3002 : Step(21): len = 149544, overlap = 1408.12
+PHY-3002 : Step(22): len = 186924, overlap = 1307.59
+PHY-3002 : Step(23): len = 196657, overlap = 1234.81
+PHY-3002 : Step(24): len = 201662, overlap = 1173.03
+PHY-3002 : Step(25): len = 200252, overlap = 1144.47
+PHY-3002 : Step(26): len = 200277, overlap = 1126.75
+PHY-3002 : Step(27): len = 200909, overlap = 1081.31
+PHY-3002 : Step(28): len = 200627, overlap = 1084.62
+PHY-3002 : Step(29): len = 198023, overlap = 1086.78
+PHY-3002 : Step(30): len = 194982, overlap = 1049.81
+PHY-3002 : Step(31): len = 193999, overlap = 1072.16
+PHY-3002 : Step(32): len = 190950, overlap = 1078.16
+PHY-3002 : Step(33): len = 188489, overlap = 1074.28
+PHY-3002 : Step(34): len = 185500, overlap = 1065.72
+PHY-3002 : Step(35): len = 183230, overlap = 1065.19
+PHY-3002 : Step(36): len = 181772, overlap = 1057.28
+PHY-3002 : Step(37): len = 181794, overlap = 1064.59
+PHY-3002 : Step(38): len = 180942, overlap = 1073.12
+PHY-3002 : Step(39): len = 179596, overlap = 1074.31
+PHY-3002 : Step(40): len = 178731, overlap = 1078.41
+PHY-3002 : Step(41): len = 178841, overlap = 1070.62
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.50337e-06
+PHY-3002 : Step(42): len = 182125, overlap = 1044.88
+PHY-3002 : Step(43): len = 193274, overlap = 1009.53
+PHY-3002 : Step(44): len = 198014, overlap = 998.5
+PHY-3002 : Step(45): len = 202228, overlap = 975.844
+PHY-3002 : Step(46): len = 202307, overlap = 972.906
+PHY-3002 : Step(47): len = 203274, overlap = 961.219
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.00675e-06
+PHY-3002 : Step(48): len = 210969, overlap = 925.469
+PHY-3002 : Step(49): len = 228796, overlap = 898.656
+PHY-3002 : Step(50): len = 240932, overlap = 796.812
+PHY-3002 : Step(51): len = 252241, overlap = 709.281
+PHY-3002 : Step(52): len = 256538, overlap = 677.031
+PHY-3002 : Step(53): len = 258118, overlap = 653.531
+PHY-3002 : Step(54): len = 256383, overlap = 632.406
+PHY-3002 : Step(55): len = 255664, overlap = 628.438
+PHY-3002 : Step(56): len = 252475, overlap = 632.406
+PHY-3002 : Step(57): len = 251940, overlap = 635.594
+PHY-3002 : Step(58): len = 249569, overlap = 656.406
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.00135e-05
+PHY-3002 : Step(59): len = 266676, overlap = 593.312
+PHY-3002 : Step(60): len = 283222, overlap = 545.875
+PHY-3002 : Step(61): len = 290621, overlap = 517.938
+PHY-3002 : Step(62): len = 294682, overlap = 509.719
+PHY-3002 : Step(63): len = 296051, overlap = 515.25
+PHY-3002 : Step(64): len = 296871, overlap = 501.188
+PHY-3002 : Step(65): len = 294948, overlap = 490.844
+PHY-3002 : Step(66): len = 295638, overlap = 485.781
+PHY-3002 : Step(67): len = 295958, overlap = 461.188
+PHY-3002 : Step(68): len = 296737, overlap = 461.094
+PHY-3002 : Step(69): len = 295245, overlap = 477.625
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.0027e-05
+PHY-3002 : Step(70): len = 312035, overlap = 465.844
+PHY-3002 : Step(71): len = 326465, overlap = 441.969
+PHY-3002 : Step(72): len = 330847, overlap = 430
+PHY-3002 : Step(73): len = 332739, overlap = 422.781
+PHY-3002 : Step(74): len = 332047, overlap = 427.312
+PHY-3002 : Step(75): len = 333195, overlap = 419.75
+PHY-3002 : Step(76): len = 332918, overlap = 401
+PHY-3002 : Step(77): len = 334271, overlap = 398.188
+PHY-3002 : Step(78): len = 336070, overlap = 386.812
+PHY-3002 : Step(79): len = 337418, overlap = 368.469
+PHY-3002 : Step(80): len = 336616, overlap = 350.969
+PHY-3002 : Step(81): len = 335755, overlap = 357.062
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.0054e-05
+PHY-3002 : Step(82): len = 350962, overlap = 356.062
+PHY-3002 : Step(83): len = 363386, overlap = 350.281
+PHY-3002 : Step(84): len = 365574, overlap = 339.969
+PHY-3002 : Step(85): len = 368480, overlap = 328.531
+PHY-3002 : Step(86): len = 368649, overlap = 311.594
+PHY-3002 : Step(87): len = 370659, overlap = 317.344
+PHY-3002 : Step(88): len = 371032, overlap = 307.125
+PHY-3002 : Step(89): len = 374783, overlap = 286.094
+PHY-3002 : Step(90): len = 377972, overlap = 282.938
+PHY-3002 : Step(91): len = 377956, overlap = 291.188
+PHY-3002 : Step(92): len = 376542, overlap = 303.812
+PHY-3002 : Step(93): len = 374853, overlap = 305.188
+PHY-3002 : Step(94): len = 374713, overlap = 299.094
+PHY-3002 : Step(95): len = 374532, overlap = 300.188
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.0108e-05
+PHY-3002 : Step(96): len = 388389, overlap = 304.656
+PHY-3002 : Step(97): len = 400889, overlap = 289.438
+PHY-3002 : Step(98): len = 401243, overlap = 275.812
+PHY-3002 : Step(99): len = 404469, overlap = 274.875
+PHY-3002 : Step(100): len = 409657, overlap = 274.906
+PHY-3002 : Step(101): len = 413478, overlap = 266.281
+PHY-3002 : Step(102): len = 409610, overlap = 243.688
+PHY-3002 : Step(103): len = 411159, overlap = 221.031
+PHY-3002 : Step(104): len = 413257, overlap = 238.625
+PHY-3002 : Step(105): len = 416192, overlap = 226.969
+PHY-3002 : Step(106): len = 410906, overlap = 230.406
+PHY-3002 : Step(107): len = 410932, overlap = 227.938
+PHY-3002 : Step(108): len = 412089, overlap = 240.875
+PHY-3002 : Step(109): len = 413936, overlap = 238.281
+PHY-3002 : Step(110): len = 409482, overlap = 218.75
+PHY-3002 : Step(111): len = 408991, overlap = 228.344
+PHY-3002 : Step(112): len = 409497, overlap = 228.875
+PHY-3002 : Step(113): len = 410986, overlap = 223.688
+PHY-3002 : Step(114): len = 409275, overlap = 224.938
+PHY-3002 : Step(115): len = 409628, overlap = 236.594
+PHY-3002 : Step(116): len = 409661, overlap = 223.688
+PHY-3002 : Step(117): len = 410074, overlap = 228.125
+PHY-3002 : Step(118): len = 407882, overlap = 224.375
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000153135
+PHY-3002 : Step(119): len = 419224, overlap = 231.438
+PHY-3002 : Step(120): len = 428919, overlap = 228.5
+PHY-3002 : Step(121): len = 429292, overlap = 224.969
+PHY-3002 : Step(122): len = 430166, overlap = 229.938
+PHY-3002 : Step(123): len = 432096, overlap = 235.844
+PHY-3002 : Step(124): len = 433857, overlap = 232.469
+PHY-3002 : Step(125): len = 432834, overlap = 231.406
+PHY-3002 : Step(126): len = 433670, overlap = 217.562
+PHY-3002 : Step(127): len = 436050, overlap = 210.781
+PHY-3002 : Step(128): len = 438625, overlap = 205.688
+PHY-3002 : Step(129): len = 437040, overlap = 211.25
+PHY-3002 : Step(130): len = 437750, overlap = 212.344
+PHY-3002 : Step(131): len = 440371, overlap = 204.906
+PHY-3002 : Step(132): len = 442804, overlap = 200.656
+PHY-3002 : Step(133): len = 441730, overlap = 200
+PHY-3002 : Step(134): len = 441835, overlap = 198.562
+PHY-3002 : Step(135): len = 443314, overlap = 192.031
+PHY-3002 : Step(136): len = 444762, overlap = 187.625
+PHY-3002 : Step(137): len = 443062, overlap = 193.594
+PHY-3002 : Step(138): len = 442947, overlap = 200.375
+PHY-3002 : Step(139): len = 443891, overlap = 192.562
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00030627
+PHY-3002 : Step(140): len = 454445, overlap = 186.688
+PHY-3002 : Step(141): len = 463946, overlap = 193.344
+PHY-3002 : Step(142): len = 465119, overlap = 189.688
+PHY-3002 : Step(143): len = 465821, overlap = 188.594
+PHY-3002 : Step(144): len = 468832, overlap = 195.125
+PHY-3002 : Step(145): len = 471160, overlap = 194.938
+PHY-3002 : Step(146): len = 469760, overlap = 190.562
+PHY-3002 : Step(147): len = 469801, overlap = 191.438
+PHY-3002 : Step(148): len = 472086, overlap = 189.875
+PHY-3002 : Step(149): len = 475265, overlap = 188.5
+PHY-3002 : Step(150): len = 474132, overlap = 188.688
+PHY-3002 : Step(151): len = 474950, overlap = 186.5
+PHY-3002 : Step(152): len = 477870, overlap = 173.188
+PHY-3002 : Step(153): len = 478918, overlap = 170.688
+PHY-3002 : Step(154): len = 477200, overlap = 172.938
+PHY-3002 : Step(155): len = 476896, overlap = 175.625
+PHY-3002 : Step(156): len = 477945, overlap = 174.25
+PHY-3002 : Step(157): len = 478733, overlap = 173.531
+PHY-3002 : Step(158): len = 477448, overlap = 172.906
+PHY-3002 : Step(159): len = 477202, overlap = 172.969
+PHY-3002 : Step(160): len = 478445, overlap = 169.75
+PHY-3002 : Step(161): len = 478840, overlap = 169.875
+PHY-3002 : Step(162): len = 477672, overlap = 174.812
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000560138
+PHY-3002 : Step(163): len = 483646, overlap = 171.656
+PHY-3002 : Step(164): len = 488781, overlap = 165.75
+PHY-3002 : Step(165): len = 489424, overlap = 162.844
+PHY-3002 : Step(166): len = 490459, overlap = 157.031
+PHY-3002 : Step(167): len = 493183, overlap = 155.875
+PHY-3002 : Step(168): len = 494594, overlap = 156.938
+PHY-3002 : Step(169): len = 493996, overlap = 155.844
+PHY-3002 : Step(170): len = 494838, overlap = 153.062
+PHY-3002 : Step(171): len = 497353, overlap = 158.469
+PHY-3002 : Step(172): len = 498397, overlap = 149.25
+PHY-3002 : Step(173): len = 497601, overlap = 148.094
+PHY-3002 : Step(174): len = 497566, overlap = 144.969
+PHY-3002 : Step(175): len = 498309, overlap = 140.812
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109438
+PHY-3002 : Step(176): len = 503535, overlap = 136.062
+PHY-3002 : Step(177): len = 512966, overlap = 129.469
+PHY-3002 : Step(178): len = 516608, overlap = 130.906
+PHY-3002 : Step(179): len = 518873, overlap = 134.312
+PHY-3002 : Step(180): len = 520505, overlap = 132.344
+PHY-3002 : Step(181): len = 521154, overlap = 128.156
+PHY-3002 : Step(182): len = 520353, overlap = 132.656
+PHY-3002 : Step(183): len = 519977, overlap = 130.25
+PHY-3002 : Step(184): len = 520314, overlap = 125.125
+PHY-3002 : Step(185): len = 521165, overlap = 129.406
+PHY-3002 : Step(186): len = 521225, overlap = 133.656
+PHY-3002 : Step(187): len = 521401, overlap = 135.438
+PHY-3002 : Step(188): len = 521692, overlap = 135.156
+PHY-3002 : Step(189): len = 521944, overlap = 136.594
+PHY-3002 : Step(190): len = 522250, overlap = 133.406
+PHY-3002 : Step(191): len = 522714, overlap = 139.344
+PHY-3002 : Step(192): len = 522947, overlap = 137.625
+PHY-3002 : Step(193): len = 523128, overlap = 135.312
+PHY-3002 : Step(194): len = 523584, overlap = 139.094
+PHY-3002 : Step(195): len = 524158, overlap = 136.75
+PHY-3002 : Step(196): len = 524127, overlap = 136.406
+PHY-3002 : Step(197): len = 524127, overlap = 136.406
+PHY-3002 : Step(198): len = 524185, overlap = 135.312
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00196201
+PHY-3002 : Step(199): len = 527588, overlap = 131.375
+PHY-3002 : Step(200): len = 533868, overlap = 126.531
+PHY-3002 : Step(201): len = 535130, overlap = 125.531
+PHY-3002 : Step(202): len = 535877, overlap = 123.781
+PHY-3002 : Step(203): len = 537214, overlap = 119.656
+PHY-3002 : Step(204): len = 538603, overlap = 119.344
+PHY-3002 : Step(205): len = 539452, overlap = 121.281
+PHY-3002 : Step(206): len = 540261, overlap = 120.625
+PHY-3002 : Step(207): len = 541495, overlap = 124.094
+PHY-3002 : Step(208): len = 542677, overlap = 123.094
+PHY-3002 : Step(209): len = 542953, overlap = 122.438
+PHY-3002 : Step(210): len = 542992, overlap = 125.312
+PHY-3002 : Step(211): len = 543028, overlap = 123.219
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00324023
+PHY-3002 : Step(212): len = 545861, overlap = 125.688
+PHY-3002 : Step(213): len = 554149, overlap = 117.188
+PHY-3002 : Step(214): len = 557762, overlap = 110.5
+PHY-3002 : Step(215): len = 560948, overlap = 109.75
+PHY-3002 : Step(216): len = 563911, overlap = 109.688
+PHY-3002 : Step(217): len = 566248, overlap = 103.938
+PHY-3002 : Step(218): len = 566211, overlap = 102.312
+PHY-3002 : Step(219): len = 566582, overlap = 103.188
+PHY-3002 : Step(220): len = 568445, overlap = 102.188
+PHY-3002 : Step(221): len = 569431, overlap = 101.875
+PHY-3002 : Step(222): len = 569267, overlap = 104.938
+PHY-3002 : Step(223): len = 569164, overlap = 105.125
+PHY-3002 : Step(224): len = 569721, overlap = 104.344
+PHY-3002 : Step(225): len = 570241, overlap = 105.5
+PHY-3002 : Step(226): len = 569909, overlap = 106.531
+PHY-3002 : Step(227): len = 569647, overlap = 107.469
+PHY-3002 : Step(228): len = 569745, overlap = 105.281
+PHY-3002 : Step(229): len = 569726, overlap = 105.094
+PHY-3002 : Step(230): len = 569466, overlap = 105.344
+PHY-3002 : Step(231): len = 569254, overlap = 105.438
+PHY-3002 : Step(232): len = 569404, overlap = 106.938
+PHY-3002 : Step(233): len = 569522, overlap = 107.188
+PHY-3002 : Step(234): len = 569378, overlap = 104.75
+PHY-3002 : Step(235): len = 569304, overlap = 104.75
+PHY-3002 : Step(236): len = 569439, overlap = 105.375
+PHY-3002 : Step(237): len = 569600, overlap = 104.406
+PHY-3002 : Step(238): len = 569515, overlap = 101.875
+PHY-3002 : Step(239): len = 569493, overlap = 103.5
+PHY-3002 : Step(240): len = 569668, overlap = 106.344
+PHY-3002 : Step(241): len = 569774, overlap = 107.094
+PHY-3002 : Step(242): len = 569811, overlap = 105.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012709s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (122.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21105.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 739944, over cnt = 1665(4%), over = 7373, worst = 42
+PHY-1001 : End global iterations; 0.754440s wall, 1.046875s user + 0.046875s system = 1.093750s CPU (145.0%)
+
+PHY-1001 : Congestion index: top1 = 81.79, top5 = 62.79, top10 = 53.34, top15 = 47.50.
+PHY-3001 : End congestion estimation; 0.975651s wall, 1.265625s user + 0.046875s system = 1.312500s CPU (134.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20905 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.881506s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000156474
+PHY-3002 : Step(243): len = 664804, overlap = 64.25
+PHY-3002 : Step(244): len = 661633, overlap = 61.25
+PHY-3002 : Step(245): len = 654084, overlap = 68.75
+PHY-3002 : Step(246): len = 652425, overlap = 58.1562
+PHY-3002 : Step(247): len = 651512, overlap = 56.1562
+PHY-3002 : Step(248): len = 648323, overlap = 54.8438
+PHY-3002 : Step(249): len = 645219, overlap = 53.375
+PHY-3002 : Step(250): len = 641318, overlap = 49.9688
+PHY-3002 : Step(251): len = 638499, overlap = 48.2812
+PHY-3002 : Step(252): len = 635733, overlap = 56.6562
+PHY-3002 : Step(253): len = 634086, overlap = 56.9375
+PHY-3002 : Step(254): len = 631492, overlap = 55.3125
+PHY-3002 : Step(255): len = 630262, overlap = 55.1562
+PHY-3002 : Step(256): len = 628085, overlap = 55.1562
+PHY-3002 : Step(257): len = 627916, overlap = 59.8125
+PHY-3002 : Step(258): len = 625094, overlap = 57.875
+PHY-3002 : Step(259): len = 623356, overlap = 57.6562
+PHY-3002 : Step(260): len = 620291, overlap = 55.0625
+PHY-3002 : Step(261): len = 618291, overlap = 53.1875
+PHY-3002 : Step(262): len = 615685, overlap = 54.2188
+PHY-3002 : Step(263): len = 614340, overlap = 48.6562
+PHY-3002 : Step(264): len = 612522, overlap = 45.9688
+PHY-3002 : Step(265): len = 612190, overlap = 45.0625
+PHY-3002 : Step(266): len = 610337, overlap = 45.1562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000312948
+PHY-3002 : Step(267): len = 615500, overlap = 47.4375
+PHY-3002 : Step(268): len = 617145, overlap = 47.1875
+PHY-3002 : Step(269): len = 618385, overlap = 45.8125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00050635
+PHY-3002 : Step(270): len = 626608, overlap = 43.5625
+PHY-3002 : Step(271): len = 635550, overlap = 43.5312
+PHY-3002 : Step(272): len = 640866, overlap = 44.375
+PHY-3002 : Step(273): len = 647511, overlap = 40.5625
+PHY-3002 : Step(274): len = 655302, overlap = 34.6875
+PHY-3002 : Step(275): len = 655253, overlap = 34.4062
+PHY-3002 : Step(276): len = 654720, overlap = 35.875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 119/21105.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 739536, over cnt = 2816(8%), over = 12296, worst = 32
+PHY-1001 : End global iterations; 1.716866s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (130.1%)
+
+PHY-1001 : Congestion index: top1 = 83.90, top5 = 66.09, top10 = 57.58, top15 = 52.55.
+PHY-3001 : End congestion estimation; 1.997216s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (126.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20905 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.475906s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000115612
+PHY-3002 : Step(277): len = 648272, overlap = 222.688
+PHY-3002 : Step(278): len = 646205, overlap = 186.781
+PHY-3002 : Step(279): len = 634987, overlap = 172.938
+PHY-3002 : Step(280): len = 629866, overlap = 156.406
+PHY-3002 : Step(281): len = 623948, overlap = 146.094
+PHY-3002 : Step(282): len = 618369, overlap = 138.25
+PHY-3002 : Step(283): len = 614754, overlap = 130
+PHY-3002 : Step(284): len = 612121, overlap = 120.781
+PHY-3002 : Step(285): len = 608042, overlap = 120.094
+PHY-3002 : Step(286): len = 606155, overlap = 119.25
+PHY-3002 : Step(287): len = 602915, overlap = 128.312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000231223
+PHY-3002 : Step(288): len = 603640, overlap = 122.688
+PHY-3002 : Step(289): len = 605637, overlap = 121.031
+PHY-3002 : Step(290): len = 607143, overlap = 115.938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000462446
+PHY-3002 : Step(291): len = 611977, overlap = 104.844
+PHY-3002 : Step(292): len = 621717, overlap = 95.375
+PHY-3002 : Step(293): len = 626355, overlap = 86.875
+PHY-3002 : Step(294): len = 624855, overlap = 86.6875
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86164, tnet num: 20905, tinst num: 18497, tnode num: 117604, tedge num: 137258.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.467374s wall, 1.421875s user + 0.046875s system = 1.468750s CPU (100.1%)
+
+RUN-1004 : used memory is 586 MB, reserved memory is 577 MB, peak memory is 723 MB
+OPT-1001 : Total overflow 410.81 peak overflow 3.59
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 864/21105.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720368, over cnt = 2993(8%), over = 11040, worst = 24
+PHY-1001 : End global iterations; 1.209857s wall, 1.828125s user + 0.046875s system = 1.875000s CPU (155.0%)
+
+PHY-1001 : Congestion index: top1 = 72.16, top5 = 58.31, top10 = 51.56, top15 = 47.64.
+PHY-1001 : End incremental global routing; 1.580020s wall, 2.203125s user + 0.046875s system = 2.250000s CPU (142.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20905 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.978688s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (100.6%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18365 has valid locations, 310 needs to be replaced
+PHY-3001 : design contains 18760 instances, 7880 luts, 9653 seqs, 1081 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6452 pins
+PHY-3001 : Found 1262 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 647899
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17203/21368.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733872, over cnt = 3029(8%), over = 11137, worst = 24
+PHY-1001 : End global iterations; 0.228090s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (109.6%)
+
+PHY-1001 : Congestion index: top1 = 71.49, top5 = 58.39, top10 = 51.73, top15 = 47.82.
+PHY-3001 : End congestion estimation; 0.498460s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (106.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87207, tnet num: 21168, tinst num: 18760, tnode num: 119149, tedge num: 138818.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.490584s wall, 1.453125s user + 0.046875s system = 1.500000s CPU (100.6%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 626 MB, peak memory is 726 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21168 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.462904s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(295): len = 646827, overlap = 0.3125
+PHY-3002 : Step(296): len = 646422, overlap = 0.3125
+PHY-3002 : Step(297): len = 646169, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17305/21368.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731280, over cnt = 3048(8%), over = 11190, worst = 24
+PHY-1001 : End global iterations; 0.199581s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (109.6%)
+
+PHY-1001 : Congestion index: top1 = 72.09, top5 = 58.58, top10 = 51.92, top15 = 48.04.
+PHY-3001 : End congestion estimation; 0.472469s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (105.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21168 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.926691s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000403266
+PHY-3002 : Step(298): len = 645822, overlap = 88.5625
+PHY-3002 : Step(299): len = 645870, overlap = 88.1562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000806532
+PHY-3002 : Step(300): len = 646228, overlap = 88.3438
+PHY-3002 : Step(301): len = 646455, overlap = 88.0625
+PHY-3001 : Final: Len = 646455, Over = 88.0625
+PHY-3001 : End incremental placement; 5.028987s wall, 5.312500s user + 0.171875s system = 5.484375s CPU (109.1%)
+
+OPT-1001 : Total overflow 414.88 peak overflow 3.59
+OPT-1001 : End high-fanout net optimization; 8.121766s wall, 9.078125s user + 0.250000s system = 9.328125s CPU (114.9%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 726, peak = 747.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17272/21368.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 734648, over cnt = 2981(8%), over = 10237, worst = 24
+PHY-1002 : len = 786064, over cnt = 2060(5%), over = 5288, worst = 19
+PHY-1002 : len = 830832, over cnt = 954(2%), over = 1995, worst = 16
+PHY-1002 : len = 849992, over cnt = 349(0%), over = 633, worst = 12
+PHY-1002 : len = 862312, over cnt = 11(0%), over = 22, worst = 9
+PHY-1001 : End global iterations; 1.733615s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (143.3%)
+
+PHY-1001 : Congestion index: top1 = 60.02, top5 = 51.41, top10 = 47.58, top15 = 45.14.
+OPT-1001 : End congestion update; 1.992913s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (138.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21168 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.805453s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 112 cells processed and 17150 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 29 cells processed and 4200 slack improved
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 6 cells processed and 500 slack improved
+OPT-0007 : Iter 4: improved WNS 121 TNS 0 NUM_FEPS 0 with 3 cells processed and 850 slack improved
+OPT-1001 : End bottleneck based optimization; 3.205148s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (123.8%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 704, peak = 747.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17299/21374.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862720, over cnt = 86(0%), over = 129, worst = 9
+PHY-1002 : len = 862672, over cnt = 33(0%), over = 37, worst = 3
+PHY-1002 : len = 862824, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 862872, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 863088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.707536s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 60.04, top5 = 51.29, top10 = 47.48, top15 = 45.00.
+OPT-1001 : End congestion update; 0.984622s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (106.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21174 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.802064s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.4%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 13 cells processed and 3850 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.895162s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (103.1%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 715, peak = 747.
+OPT-1001 : End physical optimization; 14.995314s wall, 16.687500s user + 0.343750s system = 17.031250s CPU (113.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7880 LUT to BLE ...
+SYN-4008 : Packed 7880 LUT and 3224 SEQ to BLE.
+SYN-4003 : Packing 6435 remaining SEQ's ...
+SYN-4005 : Packed 4060 SEQ with LUT/SLICE
+SYN-4006 : 894 single LUT's are left
+SYN-4006 : 2375 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10255/14956 primitive instances ...
+PHY-3001 : End packing; 1.671672s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6913 instances
+RUN-1001 : 3382 mslices, 3383 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18285 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10191 nets have 2 pins
+RUN-1001 : 6741 nets have [3 - 5] pins
+RUN-1001 : 714 nets have [6 - 10] pins
+RUN-1001 : 302 nets have [11 - 20] pins
+RUN-1001 : 305 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6911 instances, 6765 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3741 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 658505, Over = 244.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7735/18285.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 810088, over cnt = 1921(5%), over = 3145, worst = 10
+PHY-1002 : len = 817528, over cnt = 1259(3%), over = 1830, worst = 7
+PHY-1002 : len = 836240, over cnt = 255(0%), over = 321, worst = 5
+PHY-1002 : len = 841520, over cnt = 58(0%), over = 66, worst = 3
+PHY-1002 : len = 842880, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.599744s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (134.8%)
+
+PHY-1001 : Congestion index: top1 = 59.44, top5 = 51.32, top10 = 47.18, top15 = 44.48.
+PHY-3001 : End congestion estimation; 1.987140s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (129.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73023, tnet num: 18085, tinst num: 6911, tnode num: 96144, tedge num: 121264.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.599269s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.7%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 625 MB, peak memory is 747 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18085 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.452576s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.979e-05
+PHY-3002 : Step(302): len = 648408, overlap = 240.5
+PHY-3002 : Step(303): len = 642329, overlap = 239.5
+PHY-3002 : Step(304): len = 638833, overlap = 234
+PHY-3002 : Step(305): len = 636403, overlap = 239.75
+PHY-3002 : Step(306): len = 633574, overlap = 244.75
+PHY-3002 : Step(307): len = 631122, overlap = 254
+PHY-3002 : Step(308): len = 628353, overlap = 255.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.958e-05
+PHY-3002 : Step(309): len = 630698, overlap = 245.75
+PHY-3002 : Step(310): len = 635116, overlap = 235.5
+PHY-3002 : Step(311): len = 635613, overlap = 233
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00019916
+PHY-3002 : Step(312): len = 641638, overlap = 224.25
+PHY-3002 : Step(313): len = 649307, overlap = 216
+PHY-3002 : Step(314): len = 649097, overlap = 209.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.367342s wall, 0.343750s user + 0.640625s system = 0.984375s CPU (268.0%)
+
+PHY-3001 : Trial Legalized: Len = 732034
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 944/18285.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844488, over cnt = 2724(7%), over = 4623, worst = 7
+PHY-1002 : len = 863864, over cnt = 1642(4%), over = 2322, worst = 5
+PHY-1002 : len = 879816, over cnt = 768(2%), over = 1080, worst = 5
+PHY-1002 : len = 892376, over cnt = 200(0%), over = 271, worst = 5
+PHY-1002 : len = 895888, over cnt = 48(0%), over = 70, worst = 4
+PHY-1001 : End global iterations; 2.452615s wall, 3.484375s user + 0.015625s system = 3.500000s CPU (142.7%)
+
+PHY-1001 : Congestion index: top1 = 53.02, top5 = 48.32, top10 = 45.77, top15 = 44.00.
+PHY-3001 : End congestion estimation; 2.916989s wall, 3.921875s user + 0.046875s system = 3.968750s CPU (136.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18085 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.841026s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000151197
+PHY-3002 : Step(315): len = 704579, overlap = 35.5
+PHY-3002 : Step(316): len = 687978, overlap = 62.75
+PHY-3002 : Step(317): len = 674972, overlap = 90.5
+PHY-3002 : Step(318): len = 666840, overlap = 112.75
+PHY-3002 : Step(319): len = 662093, overlap = 128.75
+PHY-3002 : Step(320): len = 658751, overlap = 145.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000302393
+PHY-3002 : Step(321): len = 663037, overlap = 144.75
+PHY-3002 : Step(322): len = 667032, overlap = 142.75
+PHY-3002 : Step(323): len = 668215, overlap = 147.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000604786
+PHY-3002 : Step(324): len = 672543, overlap = 145.5
+PHY-3002 : Step(325): len = 680159, overlap = 145.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032663s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (95.7%)
+
+PHY-3001 : Legalized: Len = 709214, Over = 0
+PHY-3001 : Spreading special nets. 442 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.101824s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (92.1%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 242, deltaY = 373, maxDist = 3.
+PHY-3001 : Final: Len = 719326, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73023, tnet num: 18085, tinst num: 6914, tnode num: 96144, tedge num: 121264.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.859874s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (99.1%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 646 MB, peak memory is 747 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4402/18285.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844800, over cnt = 2520(7%), over = 4122, worst = 8
+PHY-1002 : len = 858536, over cnt = 1536(4%), over = 2219, worst = 7
+PHY-1002 : len = 878672, over cnt = 438(1%), over = 596, worst = 7
+PHY-1002 : len = 884624, over cnt = 203(0%), over = 261, worst = 5
+PHY-1002 : len = 889360, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.905389s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (139.4%)
+
+PHY-1001 : Congestion index: top1 = 53.25, top5 = 48.11, top10 = 45.36, top15 = 43.62.
+PHY-1001 : End incremental global routing; 2.276022s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (132.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18085 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.857606s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.2%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6821 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6936 instances, 6787 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3816 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 725678
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16610/18308.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896800, over cnt = 125(0%), over = 157, worst = 6
+PHY-1002 : len = 897008, over cnt = 64(0%), over = 72, worst = 3
+PHY-1002 : len = 897472, over cnt = 16(0%), over = 17, worst = 2
+PHY-1002 : len = 897776, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 897808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.791193s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 53.38, top5 = 48.39, top10 = 45.61, top15 = 43.85.
+PHY-3001 : End congestion estimation; 1.100159s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73246, tnet num: 18108, tinst num: 6936, tnode num: 96417, tedge num: 121542.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.834701s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (99.6%)
+
+RUN-1004 : used memory is 665 MB, reserved memory is 668 MB, peak memory is 747 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18108 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.710305s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(326): len = 723439, overlap = 0
+PHY-3002 : Step(327): len = 722021, overlap = 1.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16592/18308.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892144, over cnt = 93(0%), over = 118, worst = 6
+PHY-1002 : len = 892296, over cnt = 46(0%), over = 51, worst = 3
+PHY-1002 : len = 892712, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 892784, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 892928, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.778310s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (104.4%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.27, top10 = 45.50, top15 = 43.74.
+PHY-3001 : End congestion estimation; 1.082264s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (102.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18108 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.893871s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.38885e-05
+PHY-3002 : Step(328): len = 721942, overlap = 2.75
+PHY-3002 : Step(329): len = 722192, overlap = 3.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005417s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (288.4%)
+
+PHY-3001 : Legalized: Len = 722296, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058881s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.1%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 722492, Over = 0
+PHY-3001 : End incremental placement; 6.249602s wall, 6.406250s user + 0.015625s system = 6.421875s CPU (102.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.003034s wall, 10.906250s user + 0.015625s system = 10.921875s CPU (109.2%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 744, peak = 747.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16554/18308.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 893352, over cnt = 68(0%), over = 91, worst = 5
+PHY-1002 : len = 893296, over cnt = 31(0%), over = 35, worst = 3
+PHY-1002 : len = 893640, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 893656, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 893688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.768684s wall, 0.781250s user + 0.046875s system = 0.828125s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 53.17, top5 = 48.10, top10 = 45.43, top15 = 43.71.
+OPT-1001 : End congestion update; 1.077912s wall, 1.093750s user + 0.046875s system = 1.140625s CPU (105.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18108 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.714693s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.4%)
+
+OPT-0007 : Start: WNS -129 TNS -129 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6848 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6936 instances, 6787 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3816 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 729001, Over = 0
+PHY-3001 : Spreading special nets. 32 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065599s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.3%)
+
+PHY-3001 : 49 instances has been re-located, deltaX = 39, deltaY = 35, maxDist = 4.
+PHY-3001 : Final: Len = 730491, Over = 0
+PHY-3001 : End incremental legalization; 0.389865s wall, 0.484375s user + 0.031250s system = 0.515625s CPU (132.3%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 50 cells processed and 19694 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6848 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6936 instances, 6787 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3816 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 729925, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062163s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 8, deltaY = 22, maxDist = 4.
+PHY-3001 : Final: Len = 730351, Over = 0
+PHY-3001 : End incremental legalization; 0.382260s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.2%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 28 cells processed and 2489 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6856 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6944 instances, 6795 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3816 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 731493, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057834s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.1%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 5, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 731699, Over = 0
+PHY-3001 : End incremental legalization; 0.377160s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (103.6%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 8 cells processed and 1239 slack improved
+OPT-1001 : End bottleneck based optimization; 3.404467s wall, 3.515625s user + 0.078125s system = 3.593750s CPU (105.6%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 745, peak = 747.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16233/18310.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902880, over cnt = 162(0%), over = 198, worst = 8
+PHY-1002 : len = 903112, over cnt = 76(0%), over = 79, worst = 2
+PHY-1002 : len = 903704, over cnt = 25(0%), over = 26, worst = 2
+PHY-1002 : len = 903888, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 904080, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations; 0.792304s wall, 0.828125s user + 0.046875s system = 0.875000s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 53.02, top5 = 47.99, top10 = 45.36, top15 = 43.69.
+OPT-1001 : End congestion update; 1.103728s wall, 1.125000s user + 0.046875s system = 1.171875s CPU (106.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.721427s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6856 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6944 instances, 6795 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3816 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 731537, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061432s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 14, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 731905, Over = 0
+PHY-3001 : End incremental legalization; 0.418500s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.369286s wall, 2.390625s user + 0.046875s system = 2.437500s CPU (102.9%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 745, peak = 747.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.715325s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16568/18310.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904064, over cnt = 37(0%), over = 43, worst = 3
+PHY-1002 : len = 904120, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 904272, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 904320, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 904472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.738498s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (103.7%)
+
+PHY-1001 : Congestion index: top1 = 53.15, top5 = 48.03, top10 = 45.37, top15 = 43.69.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.714229s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 71 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.724138
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 71ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6856 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6944 instances, 6795 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3816 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 731905, Over = 0
+PHY-3001 : End spreading; 0.058833s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.2%)
+
+PHY-3001 : Final: Len = 731905, Over = 0
+PHY-3001 : End incremental legalization; 0.416648s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.736661s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.7%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16634/18310.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.132703s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.0%)
+
+PHY-1001 : Congestion index: top1 = 53.15, top5 = 48.03, top10 = 45.37, top15 = 43.69.
+OPT-1001 : End congestion update; 0.451189s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717685s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6856 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6944 instances, 6795 slices, 224 macros(1081 instances: 708 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3816 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 731923, Over = 0
+PHY-3001 : End spreading; 0.058749s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.4%)
+
+PHY-3001 : Final: Len = 731923, Over = 0
+PHY-3001 : End incremental legalization; 0.375258s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (129.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.653282s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (105.9%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 745, peak = 747.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16632/18310.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904488, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127611s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.0%)
+
+PHY-1001 : Congestion index: top1 = 53.15, top5 = 48.03, top10 = 45.37, top15 = 43.69.
+OPT-1001 : End congestion update; 0.430699s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.713993s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.7%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.303794s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (99.5%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 745, peak = 747.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.713678s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 742, reserve = 745, peak = 747.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.711204s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.9%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16634/18310.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904488, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.129801s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.3%)
+
+PHY-1001 : Congestion index: top1 = 53.15, top5 = 48.03, top10 = 45.37, top15 = 43.69.
+RUN-1001 : End congestion update; 0.435350s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (96.9%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.149697s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.2%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 745, peak = 747.
+OPT-1001 : End physical optimization; 26.482434s wall, 27.593750s user + 0.171875s system = 27.765625s CPU (104.8%)
+
+RUN-1003 : finish command "place" in 70.007105s wall, 98.031250s user + 6.078125s system = 104.109375s CPU (148.7%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 656 MB, peak memory is 747 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.683957s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (175.4%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 657 MB, peak memory is 747 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6946 instances
+RUN-1001 : 3397 mslices, 3398 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18310 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10179 nets have 2 pins
+RUN-1001 : 6748 nets have [3 - 5] pins
+RUN-1001 : 729 nets have [6 - 10] pins
+RUN-1001 : 310 nets have [11 - 20] pins
+RUN-1001 : 316 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73317, tnet num: 18110, tinst num: 6944, tnode num: 96514, tedge num: 121632.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.587240s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.4%)
+
+RUN-1004 : used memory is 630 MB, reserved memory is 626 MB, peak memory is 747 MB
+PHY-1001 : 3397 mslices, 3398 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18110 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 832584, over cnt = 2721(7%), over = 4572, worst = 9
+PHY-1002 : len = 851760, over cnt = 1565(4%), over = 2308, worst = 6
+PHY-1002 : len = 866952, over cnt = 755(2%), over = 1126, worst = 6
+PHY-1002 : len = 885136, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 885264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.923275s wall, 4.062500s user + 0.031250s system = 4.093750s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 52.67, top5 = 47.92, top10 = 45.23, top15 = 43.43.
+PHY-1001 : End global routing; 3.246691s wall, 4.375000s user + 0.031250s system = 4.406250s CPU (135.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 719, reserve = 724, peak = 747.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 993, reserve = 1000, peak = 993.
+PHY-1001 : End build detailed router design. 3.979416s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 264352, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.348766s wall, 5.359375s user + 0.000000s system = 5.359375s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 264408, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.409841s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.1%)
+
+PHY-1001 : Current memory(MB): used = 1028, reserve = 1036, peak = 1028.
+PHY-1001 : End phase 1; 5.771073s wall, 5.781250s user + 0.000000s system = 5.781250s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.25218e+06, over cnt = 1720(0%), over = 1727, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1051, peak = 1046.
+PHY-1001 : End initial routed; 25.318209s wall, 58.531250s user + 0.250000s system = 58.781250s CPU (232.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 3/17211(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.706 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.320912s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1058, reserve = 1063, peak = 1058.
+PHY-1001 : End phase 2; 28.639184s wall, 61.843750s user + 0.250000s system = 62.093750s CPU (216.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.141830s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.2%)
+
+PHY-1022 : len = 2.25221e+06, over cnt = 1721(0%), over = 1728, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.422175s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.22214e+06, over cnt = 557(0%), over = 558, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.473597s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (171.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.22127e+06, over cnt = 94(0%), over = 94, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.717611s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (143.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.22209e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.309701s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (105.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2224e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.233695s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.22252e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.219663s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (106.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.22252e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.246668s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.22252e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.405781s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.22254e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.165858s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.22252e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.167147s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.22252e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.181524s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.22252e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.308513s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.22252e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.303744s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.9%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.22253e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.178864s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.22258e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.164400s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/17211(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.381610s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 493 feed throughs used by 389 nets
+PHY-1001 : End commit to database; 2.271829s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (99.0%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1169, peak = 1160.
+PHY-1001 : End phase 3; 11.580908s wall, 12.906250s user + 0.046875s system = 12.953125s CPU (111.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.137276s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.4%)
+
+PHY-1022 : len = 2.22258e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.386763s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/17211(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.282584s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 493 feed throughs used by 389 nets
+PHY-1001 : End commit to database; 2.319381s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1178, peak = 1168.
+PHY-1001 : End phase 4; 6.017357s wall, 6.015625s user + 0.000000s system = 6.015625s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.22258e+06
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1180, peak = 1170.
+PHY-1001 : End export database. 0.061415s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (76.3%)
+
+PHY-1001 : End detail routing; 56.443745s wall, 90.968750s user + 0.312500s system = 91.281250s CPU (161.7%)
+
+RUN-1003 : finish command "route" in 62.331417s wall, 97.984375s user + 0.343750s system = 98.328125s CPU (157.8%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1102 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10328 out of 19600 52.69%
+#reg 9798 out of 19600 49.99%
+#le 12668
+ #lut only 2870 out of 12668 22.66%
+ #reg only 2340 out of 12668 18.47%
+ #lut® 7458 out of 12668 58.87%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 22
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1789
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1506
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1379
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 962
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 137
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 73
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/en_adc_cfg_all_d0_reg_syn_5.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg11_syn_155.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE OREG
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P104 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P2 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P149 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P19 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12668 |9301 |1027 |9833 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |554 |488 |23 |448 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |107 |95 |4 |96 |4 |0 |
+| U_crc16_24b |crc16_24b |44 |44 |0 |23 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |8 |0 |0 |
+| exdev_ctl_a |exdev_ctl |767 |390 |96 |586 |0 |0 |
+| u_ADconfig |AD_config |188 |128 |25 |141 |0 |0 |
+| u_gen_sp |gen_sp |257 |150 |71 |123 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |367 |96 |562 |0 |0 |
+| u_ADconfig |AD_config |176 |108 |25 |128 |0 |0 |
+| u_gen_sp |gen_sp |259 |168 |71 |120 |0 |0 |
+| sampling_fe_a |sampling_fe |2957 |2318 |306 |2089 |25 |0 |
+| u0_soft_n |cdc_sync |6 |1 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |191 |100 |17 |161 |0 |0 |
+| u0_soft_n |cdc_sync |7 |3 |0 |7 |0 |0 |
+| u_sort |sort |2731 |2209 |289 |1893 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |1 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |0 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2290 |1901 |253 |1526 |22 |0 |
+| channelPart |channel_part_8478 |124 |110 |3 |120 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1801 |1491 |197 |1148 |0 |0 |
+| adc_addr_gen |adc_addr_gen |225 |198 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |17 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| insert |insert |961 |680 |170 |661 |0 |0 |
+| ram_switch_state |ram_switch_state |615 |613 |0 |364 |0 |0 |
+| read_ram_i |read_ram |279 |226 |44 |191 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |154 |0 |0 |
+| read_ram_data |read_ram_data |47 |36 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |325 |218 |36 |278 |3 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3195 |2529 |349 |2127 |25 |1 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |191 |104 |17 |162 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |2974 |2407 |332 |1935 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2551 |2075 |290 |1583 |22 |1 |
+| channelPart |channel_part_8478 |146 |131 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |64 |55 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1943 |1605 |197 |1158 |0 |0 |
+| adc_addr_gen |adc_addr_gen |196 |169 |27 |103 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |8 |5 |3 |2 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |10 |3 |3 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| insert |insert |988 |677 |170 |687 |0 |0 |
+| ram_switch_state |ram_switch_state |759 |759 |0 |368 |0 |0 |
+| read_ram_i |read_ram_rev |363 |257 |81 |211 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |303 |225 |73 |167 |0 |0 |
+| read_ram_data |read_ram_data_rev |60 |32 |8 |44 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10117
+ #2 2 4445
+ #3 3 1708
+ #4 4 592
+ #5 5-10 769
+ #6 11-50 575
+ #7 51-100 8
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.076634s wall, 3.546875s user + 0.031250s system = 3.578125s CPU (172.3%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1103 MB, peak memory is 1170 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73317, tnet num: 18110, tinst num: 6944, tnode num: 96514, tedge num: 121632.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.612097s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.8%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1108 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18110 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.474774s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (100.7%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1110 MB, peak memory is 1170 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6944
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18310, pip num: 169941
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 493
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3244 valid insts, and 474518 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.427794s wall, 61.250000s user + 0.171875s system = 61.421875s CPU (651.5%)
+
+RUN-1004 : used memory is 1262 MB, reserved memory is 1266 MB, peak memory is 1377 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_165409.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_171046.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_171046.log
new file mode 100644
index 0000000..e3eb952
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_171046.log
@@ -0,0 +1,2082 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 17:10:46 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(886)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(895)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(919)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(921)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(927)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(930)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1101)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1190)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1491)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1502)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1520)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2098)
+HDL-5007 WARNING: identifier 'a_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'b_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.208643s wall, 2.093750s user + 0.109375s system = 2.203125s CPU (99.8%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 316 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2247 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2068 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18042 instances
+RUN-0007 : 7670 luts, 9149 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20619 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13119 nets have 2 pins
+RUN-1001 : 6460 nets have [3 - 5] pins
+RUN-1001 : 618 nets have [6 - 10] pins
+RUN-1001 : 184 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3516
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18040 instances, 7670 luts, 9149 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6002 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84207, tnet num: 20441, tinst num: 18040, tnode num: 114626, tedge num: 134260.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.172582s wall, 1.125000s user + 0.046875s system = 1.171875s CPU (99.9%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 516 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20441 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.941227s wall, 1.875000s user + 0.062500s system = 1.937500s CPU (99.8%)
+
+PHY-3001 : Found 1250 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.95932e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18040.
+PHY-3001 : Level 1 #clusters 2028.
+PHY-3001 : End clustering; 0.127128s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31927e+06, overlap = 441.625
+PHY-3002 : Step(2): len = 1.21921e+06, overlap = 477.031
+PHY-3002 : Step(3): len = 850747, overlap = 560.594
+PHY-3002 : Step(4): len = 782681, overlap = 613.219
+PHY-3002 : Step(5): len = 614794, overlap = 718
+PHY-3002 : Step(6): len = 549461, overlap = 816.406
+PHY-3002 : Step(7): len = 465034, overlap = 891.281
+PHY-3002 : Step(8): len = 417667, overlap = 961.031
+PHY-3002 : Step(9): len = 375164, overlap = 1019.19
+PHY-3002 : Step(10): len = 346136, overlap = 1070.16
+PHY-3002 : Step(11): len = 308220, overlap = 1133.12
+PHY-3002 : Step(12): len = 284118, overlap = 1166.53
+PHY-3002 : Step(13): len = 263724, overlap = 1219.09
+PHY-3002 : Step(14): len = 240849, overlap = 1311.06
+PHY-3002 : Step(15): len = 221518, overlap = 1332.78
+PHY-3002 : Step(16): len = 208833, overlap = 1350.31
+PHY-3002 : Step(17): len = 181684, overlap = 1385.41
+PHY-3002 : Step(18): len = 169599, overlap = 1426.03
+PHY-3002 : Step(19): len = 154962, overlap = 1450.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.27107e-06
+PHY-3002 : Step(20): len = 156861, overlap = 1414.31
+PHY-3002 : Step(21): len = 193279, overlap = 1285.16
+PHY-3002 : Step(22): len = 204619, overlap = 1209.5
+PHY-3002 : Step(23): len = 210878, overlap = 1158.53
+PHY-3002 : Step(24): len = 208255, overlap = 1098
+PHY-3002 : Step(25): len = 205781, overlap = 1102.91
+PHY-3002 : Step(26): len = 203122, overlap = 1089.28
+PHY-3002 : Step(27): len = 201209, overlap = 1090.84
+PHY-3002 : Step(28): len = 199353, overlap = 1090.91
+PHY-3002 : Step(29): len = 197817, overlap = 1068.97
+PHY-3002 : Step(30): len = 196580, overlap = 1080.06
+PHY-3002 : Step(31): len = 195024, overlap = 1089.78
+PHY-3002 : Step(32): len = 193521, overlap = 1076.78
+PHY-3002 : Step(33): len = 191638, overlap = 1066
+PHY-3002 : Step(34): len = 191214, overlap = 1048.75
+PHY-3002 : Step(35): len = 191204, overlap = 1056.47
+PHY-3002 : Step(36): len = 190449, overlap = 1040.75
+PHY-3002 : Step(37): len = 189831, overlap = 1047.72
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.54215e-06
+PHY-3002 : Step(38): len = 195115, overlap = 1016.53
+PHY-3002 : Step(39): len = 209427, overlap = 983.219
+PHY-3002 : Step(40): len = 214823, overlap = 947.781
+PHY-3002 : Step(41): len = 219252, overlap = 920.719
+PHY-3002 : Step(42): len = 221455, overlap = 900.281
+PHY-3002 : Step(43): len = 224560, overlap = 877.594
+PHY-3002 : Step(44): len = 223776, overlap = 881.656
+PHY-3002 : Step(45): len = 223533, overlap = 903.812
+PHY-3002 : Step(46): len = 222029, overlap = 920.375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.0843e-06
+PHY-3002 : Step(47): len = 231995, overlap = 892.562
+PHY-3002 : Step(48): len = 250262, overlap = 847.406
+PHY-3002 : Step(49): len = 262393, overlap = 800.344
+PHY-3002 : Step(50): len = 271361, overlap = 762.719
+PHY-3002 : Step(51): len = 275358, overlap = 727.719
+PHY-3002 : Step(52): len = 277892, overlap = 668.094
+PHY-3002 : Step(53): len = 276979, overlap = 633.812
+PHY-3002 : Step(54): len = 275995, overlap = 631.562
+PHY-3002 : Step(55): len = 274623, overlap = 632.438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.01686e-05
+PHY-3002 : Step(56): len = 290840, overlap = 595.625
+PHY-3002 : Step(57): len = 310655, overlap = 551.562
+PHY-3002 : Step(58): len = 319199, overlap = 498.031
+PHY-3002 : Step(59): len = 322767, overlap = 502.156
+PHY-3002 : Step(60): len = 321681, overlap = 510.938
+PHY-3002 : Step(61): len = 321494, overlap = 506.031
+PHY-3002 : Step(62): len = 319187, overlap = 490.406
+PHY-3002 : Step(63): len = 318871, overlap = 496.625
+PHY-3002 : Step(64): len = 318546, overlap = 465.812
+PHY-3002 : Step(65): len = 319352, overlap = 480.469
+PHY-3002 : Step(66): len = 318883, overlap = 483.406
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.03372e-05
+PHY-3002 : Step(67): len = 335205, overlap = 412.906
+PHY-3002 : Step(68): len = 349725, overlap = 382.531
+PHY-3002 : Step(69): len = 354391, overlap = 376.531
+PHY-3002 : Step(70): len = 358676, overlap = 342.031
+PHY-3002 : Step(71): len = 357930, overlap = 343.188
+PHY-3002 : Step(72): len = 358898, overlap = 348.656
+PHY-3002 : Step(73): len = 357442, overlap = 340.031
+PHY-3002 : Step(74): len = 358106, overlap = 337.438
+PHY-3002 : Step(75): len = 357888, overlap = 339.969
+PHY-3002 : Step(76): len = 358062, overlap = 343.219
+PHY-3002 : Step(77): len = 356806, overlap = 347.156
+PHY-3002 : Step(78): len = 357040, overlap = 337.75
+PHY-3002 : Step(79): len = 356360, overlap = 344.906
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.06744e-05
+PHY-3002 : Step(80): len = 374819, overlap = 311.688
+PHY-3002 : Step(81): len = 387613, overlap = 296.031
+PHY-3002 : Step(82): len = 390156, overlap = 308.906
+PHY-3002 : Step(83): len = 390310, overlap = 313.281
+PHY-3002 : Step(84): len = 391435, overlap = 317.031
+PHY-3002 : Step(85): len = 393932, overlap = 284.156
+PHY-3002 : Step(86): len = 394275, overlap = 272.938
+PHY-3002 : Step(87): len = 395082, overlap = 281.469
+PHY-3002 : Step(88): len = 396042, overlap = 269.281
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.13487e-05
+PHY-3002 : Step(89): len = 412028, overlap = 254.75
+PHY-3002 : Step(90): len = 421193, overlap = 249.25
+PHY-3002 : Step(91): len = 419326, overlap = 250.469
+PHY-3002 : Step(92): len = 420411, overlap = 244.219
+PHY-3002 : Step(93): len = 421903, overlap = 229.781
+PHY-3002 : Step(94): len = 425091, overlap = 227.25
+PHY-3002 : Step(95): len = 423171, overlap = 239.406
+PHY-3002 : Step(96): len = 423968, overlap = 238.438
+PHY-3002 : Step(97): len = 424394, overlap = 228.938
+PHY-3002 : Step(98): len = 425461, overlap = 231.594
+PHY-3002 : Step(99): len = 423356, overlap = 227.719
+PHY-3002 : Step(100): len = 423428, overlap = 227.75
+PHY-3002 : Step(101): len = 424761, overlap = 225.625
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000162697
+PHY-3002 : Step(102): len = 438002, overlap = 223.469
+PHY-3002 : Step(103): len = 446351, overlap = 212.25
+PHY-3002 : Step(104): len = 445493, overlap = 204.938
+PHY-3002 : Step(105): len = 446153, overlap = 199.938
+PHY-3002 : Step(106): len = 449127, overlap = 191.656
+PHY-3002 : Step(107): len = 452723, overlap = 190.5
+PHY-3002 : Step(108): len = 451435, overlap = 204.25
+PHY-3002 : Step(109): len = 451531, overlap = 201.25
+PHY-3002 : Step(110): len = 452420, overlap = 202.531
+PHY-3002 : Step(111): len = 453304, overlap = 204.156
+PHY-3002 : Step(112): len = 451738, overlap = 201.969
+PHY-3002 : Step(113): len = 451545, overlap = 200.844
+PHY-3002 : Step(114): len = 452299, overlap = 197.781
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000325395
+PHY-3002 : Step(115): len = 459440, overlap = 199.625
+PHY-3002 : Step(116): len = 468608, overlap = 194.125
+PHY-3002 : Step(117): len = 471066, overlap = 174.312
+PHY-3002 : Step(118): len = 473163, overlap = 171.469
+PHY-3002 : Step(119): len = 474930, overlap = 166.094
+PHY-3002 : Step(120): len = 477182, overlap = 170.906
+PHY-3002 : Step(121): len = 476399, overlap = 174.469
+PHY-3002 : Step(122): len = 477179, overlap = 171.5
+PHY-3002 : Step(123): len = 479282, overlap = 176.594
+PHY-3002 : Step(124): len = 480829, overlap = 174.75
+PHY-3002 : Step(125): len = 479821, overlap = 182.219
+PHY-3002 : Step(126): len = 480321, overlap = 170.656
+PHY-3002 : Step(127): len = 482071, overlap = 170.844
+PHY-3002 : Step(128): len = 484038, overlap = 174
+PHY-3002 : Step(129): len = 483252, overlap = 172.812
+PHY-3002 : Step(130): len = 483304, overlap = 173.156
+PHY-3002 : Step(131): len = 484248, overlap = 176.281
+PHY-3002 : Step(132): len = 484580, overlap = 176.906
+PHY-3002 : Step(133): len = 483991, overlap = 174.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000581465
+PHY-3002 : Step(134): len = 487852, overlap = 175.25
+PHY-3002 : Step(135): len = 491454, overlap = 173.438
+PHY-3002 : Step(136): len = 492646, overlap = 165.281
+PHY-3002 : Step(137): len = 494068, overlap = 155.938
+PHY-3002 : Step(138): len = 495698, overlap = 155.938
+PHY-3002 : Step(139): len = 496607, overlap = 154.531
+PHY-3002 : Step(140): len = 496488, overlap = 154.812
+PHY-3002 : Step(141): len = 497035, overlap = 153.281
+PHY-3002 : Step(142): len = 498936, overlap = 152.719
+PHY-3002 : Step(143): len = 500490, overlap = 150.625
+PHY-3002 : Step(144): len = 500451, overlap = 151.688
+PHY-3002 : Step(145): len = 500771, overlap = 153
+PHY-3002 : Step(146): len = 502186, overlap = 148.625
+PHY-3002 : Step(147): len = 503136, overlap = 148.062
+PHY-3002 : Step(148): len = 502560, overlap = 146.188
+PHY-3002 : Step(149): len = 502523, overlap = 146.188
+PHY-3002 : Step(150): len = 503227, overlap = 145.062
+PHY-3002 : Step(151): len = 504068, overlap = 141.844
+PHY-3002 : Step(152): len = 503657, overlap = 144
+PHY-3002 : Step(153): len = 503620, overlap = 146.656
+PHY-3002 : Step(154): len = 504552, overlap = 150.75
+PHY-3002 : Step(155): len = 505526, overlap = 153.219
+PHY-3002 : Step(156): len = 504923, overlap = 152.219
+PHY-3002 : Step(157): len = 504841, overlap = 151.594
+PHY-3002 : Step(158): len = 505359, overlap = 153.781
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00105637
+PHY-3002 : Step(159): len = 508789, overlap = 153.938
+PHY-3002 : Step(160): len = 514562, overlap = 154.781
+PHY-3002 : Step(161): len = 515805, overlap = 150.406
+PHY-3002 : Step(162): len = 516767, overlap = 147.188
+PHY-3002 : Step(163): len = 518707, overlap = 147
+PHY-3002 : Step(164): len = 520176, overlap = 142.531
+PHY-3002 : Step(165): len = 519893, overlap = 138.031
+PHY-3002 : Step(166): len = 519864, overlap = 136.625
+PHY-3002 : Step(167): len = 520710, overlap = 140.906
+PHY-3002 : Step(168): len = 521585, overlap = 135.188
+PHY-3002 : Step(169): len = 521375, overlap = 126.219
+PHY-3002 : Step(170): len = 521261, overlap = 127.594
+PHY-3002 : Step(171): len = 521594, overlap = 128.188
+PHY-3002 : Step(172): len = 521861, overlap = 129.062
+PHY-3002 : Step(173): len = 521849, overlap = 120.75
+PHY-3002 : Step(174): len = 521972, overlap = 122.375
+PHY-3002 : Step(175): len = 522173, overlap = 128.688
+PHY-3002 : Step(176): len = 522173, overlap = 128.688
+PHY-3002 : Step(177): len = 522132, overlap = 122.5
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00174109
+PHY-3002 : Step(178): len = 523828, overlap = 126.938
+PHY-3002 : Step(179): len = 527389, overlap = 121.188
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.016733s wall, 0.031250s user + 0.046875s system = 0.078125s CPU (466.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20619.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 684344, over cnt = 1487(4%), over = 7446, worst = 37
+PHY-1001 : End global iterations; 0.657362s wall, 0.890625s user + 0.062500s system = 0.953125s CPU (145.0%)
+
+PHY-1001 : Congestion index: top1 = 87.76, top5 = 62.90, top10 = 52.60, top15 = 46.64.
+PHY-3001 : End congestion estimation; 0.900140s wall, 1.125000s user + 0.062500s system = 1.187500s CPU (131.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20441 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.838002s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000141996
+PHY-3002 : Step(180): len = 621393, overlap = 57.5
+PHY-3002 : Step(181): len = 622829, overlap = 51.75
+PHY-3002 : Step(182): len = 618329, overlap = 55.625
+PHY-3002 : Step(183): len = 615265, overlap = 54.2812
+PHY-3002 : Step(184): len = 613636, overlap = 49.875
+PHY-3002 : Step(185): len = 613718, overlap = 46.9688
+PHY-3002 : Step(186): len = 614090, overlap = 42.8125
+PHY-3002 : Step(187): len = 614963, overlap = 43.75
+PHY-3002 : Step(188): len = 614394, overlap = 43.1562
+PHY-3002 : Step(189): len = 612342, overlap = 43.1875
+PHY-3002 : Step(190): len = 611342, overlap = 42.9375
+PHY-3002 : Step(191): len = 610771, overlap = 39.2812
+PHY-3002 : Step(192): len = 608875, overlap = 36.5938
+PHY-3002 : Step(193): len = 608117, overlap = 34.1875
+PHY-3002 : Step(194): len = 606077, overlap = 32
+PHY-3002 : Step(195): len = 604667, overlap = 31.375
+PHY-3002 : Step(196): len = 603811, overlap = 32.6875
+PHY-3002 : Step(197): len = 601942, overlap = 33.4688
+PHY-3002 : Step(198): len = 601286, overlap = 33.7188
+PHY-3002 : Step(199): len = 599801, overlap = 33.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000283992
+PHY-3002 : Step(200): len = 602542, overlap = 32.3438
+PHY-3002 : Step(201): len = 607233, overlap = 30.4062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000513994
+PHY-3002 : Step(202): len = 612472, overlap = 28.875
+PHY-3002 : Step(203): len = 624906, overlap = 29.8125
+PHY-3002 : Step(204): len = 634782, overlap = 27.9375
+PHY-3002 : Step(205): len = 634876, overlap = 28.1875
+PHY-3002 : Step(206): len = 634830, overlap = 27.5312
+PHY-3002 : Step(207): len = 635271, overlap = 28
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 90/20619.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 716360, over cnt = 2679(7%), over = 12200, worst = 48
+PHY-1001 : End global iterations; 1.568455s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (134.5%)
+
+PHY-1001 : Congestion index: top1 = 84.25, top5 = 67.84, top10 = 58.86, top15 = 53.10.
+PHY-3001 : End congestion estimation; 1.846530s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20441 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.908937s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000118827
+PHY-3002 : Step(208): len = 630786, overlap = 226
+PHY-3002 : Step(209): len = 631703, overlap = 175.906
+PHY-3002 : Step(210): len = 624356, overlap = 158.906
+PHY-3002 : Step(211): len = 620790, overlap = 151.875
+PHY-3002 : Step(212): len = 617569, overlap = 137.844
+PHY-3002 : Step(213): len = 615692, overlap = 132.719
+PHY-3002 : Step(214): len = 613782, overlap = 133.188
+PHY-3002 : Step(215): len = 611846, overlap = 128.438
+PHY-3002 : Step(216): len = 611471, overlap = 128.188
+PHY-3002 : Step(217): len = 608288, overlap = 130.156
+PHY-3002 : Step(218): len = 605530, overlap = 133.656
+PHY-3002 : Step(219): len = 604250, overlap = 136.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000237653
+PHY-3002 : Step(220): len = 606122, overlap = 128.219
+PHY-3002 : Step(221): len = 607476, overlap = 127.469
+PHY-3002 : Step(222): len = 612423, overlap = 120.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000475307
+PHY-3002 : Step(223): len = 618157, overlap = 116.188
+PHY-3002 : Step(224): len = 621654, overlap = 110.094
+PHY-3002 : Step(225): len = 625395, overlap = 101
+PHY-3002 : Step(226): len = 629488, overlap = 91.8438
+PHY-3002 : Step(227): len = 632205, overlap = 87.6562
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84207, tnet num: 20441, tinst num: 18040, tnode num: 114626, tedge num: 134260.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.449704s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (100.2%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 563 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 425.88 peak overflow 6.38
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 894/20619.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724696, over cnt = 3066(8%), over = 11189, worst = 27
+PHY-1001 : End global iterations; 1.297121s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (133.7%)
+
+PHY-1001 : Congestion index: top1 = 72.89, top5 = 58.79, top10 = 51.77, top15 = 47.81.
+PHY-1001 : End incremental global routing; 1.628636s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (126.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20441 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.917517s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.5%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17907 has valid locations, 310 needs to be replaced
+PHY-3001 : design contains 18302 instances, 7770 luts, 9311 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6113 pins
+PHY-3001 : Found 1256 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 654161
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17024/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737328, over cnt = 3099(8%), over = 11122, worst = 26
+PHY-1001 : End global iterations; 0.220977s wall, 0.328125s user + 0.031250s system = 0.359375s CPU (162.6%)
+
+PHY-1001 : Congestion index: top1 = 72.91, top5 = 58.95, top10 = 52.08, top15 = 48.16.
+PHY-3001 : End congestion estimation; 0.471009s wall, 0.562500s user + 0.046875s system = 0.609375s CPU (129.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85249, tnet num: 20703, tinst num: 18302, tnode num: 116170, tedge num: 135820.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.428735s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (99.5%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 613 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.364192s wall, 2.328125s user + 0.031250s system = 2.359375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(228): len = 653369, overlap = 0.90625
+PHY-3002 : Step(229): len = 652917, overlap = 0.75
+PHY-3002 : Step(230): len = 652510, overlap = 0.375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17107/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735248, over cnt = 3078(8%), over = 11197, worst = 26
+PHY-1001 : End global iterations; 0.212503s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (117.6%)
+
+PHY-1001 : Congestion index: top1 = 73.77, top5 = 59.34, top10 = 52.29, top15 = 48.31.
+PHY-3001 : End congestion estimation; 0.472347s wall, 0.515625s user + 0.015625s system = 0.531250s CPU (112.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.272653s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000389329
+PHY-3002 : Step(231): len = 652316, overlap = 90.6562
+PHY-3002 : Step(232): len = 652479, overlap = 90.1562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000778658
+PHY-3002 : Step(233): len = 652767, overlap = 89.5938
+PHY-3002 : Step(234): len = 653162, overlap = 90.1875
+PHY-3001 : Final: Len = 653162, Over = 90.1875
+PHY-3001 : End incremental placement; 5.200590s wall, 5.453125s user + 0.250000s system = 5.703125s CPU (109.7%)
+
+OPT-1001 : Total overflow 431.31 peak overflow 6.38
+OPT-1001 : End high-fanout net optimization; 8.286630s wall, 9.078125s user + 0.250000s system = 9.328125s CPU (112.6%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 731.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17068/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737416, over cnt = 3019(8%), over = 10163, worst = 26
+PHY-1002 : len = 782448, over cnt = 2218(6%), over = 5911, worst = 21
+PHY-1002 : len = 820712, over cnt = 1166(3%), over = 2982, worst = 19
+PHY-1002 : len = 849296, over cnt = 466(1%), over = 1042, worst = 18
+PHY-1002 : len = 866008, over cnt = 10(0%), over = 35, worst = 9
+PHY-1001 : End global iterations; 1.697812s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (139.9%)
+
+PHY-1001 : Congestion index: top1 = 60.71, top5 = 51.65, top10 = 47.46, top15 = 44.91.
+OPT-1001 : End congestion update; 1.953607s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (134.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.781676s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 105 cells processed and 20300 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 32 cells processed and 2900 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 24 cells processed and 800 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 600 slack improved
+OPT-1001 : End bottleneck based optimization; 3.140619s wall, 3.812500s user + 0.000000s system = 3.812500s CPU (121.4%)
+
+OPT-1001 : Current memory(MB): used = 711, reserve = 706, peak = 731.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17095/20886.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 866560, over cnt = 121(0%), over = 188, worst = 9
+PHY-1002 : len = 866424, over cnt = 71(0%), over = 106, worst = 9
+PHY-1002 : len = 867312, over cnt = 32(0%), over = 38, worst = 3
+PHY-1002 : len = 867688, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 867704, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.753746s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (103.6%)
+
+PHY-1001 : Congestion index: top1 = 60.34, top5 = 51.48, top10 = 47.42, top15 = 44.88.
+OPT-1001 : End congestion update; 1.025178s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (102.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20708 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779074s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.3%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 23 cells processed and 3700 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 150 slack improved
+OPT-1001 : End path based optimization; 2.018309s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (100.6%)
+
+OPT-1001 : Current memory(MB): used = 711, reserve = 707, peak = 731.
+OPT-1001 : End physical optimization; 15.191056s wall, 16.687500s user + 0.343750s system = 17.031250s CPU (112.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7770 LUT to BLE ...
+SYN-4008 : Packed 7770 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6169 remaining SEQ's ...
+SYN-4005 : Packed 3970 SEQ with LUT/SLICE
+SYN-4006 : 938 single LUT's are left
+SYN-4006 : 2199 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9969/13824 primitive instances ...
+PHY-3001 : End packing; 1.632289s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6759 instances
+RUN-1001 : 3305 mslices, 3306 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17876 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10019 nets have 2 pins
+RUN-1001 : 6488 nets have [3 - 5] pins
+RUN-1001 : 732 nets have [6 - 10] pins
+RUN-1001 : 301 nets have [11 - 20] pins
+RUN-1001 : 305 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6757 instances, 6611 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3549 pins
+PHY-3001 : Found 468 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 662493, Over = 223
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7767/17876.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 815592, over cnt = 1985(5%), over = 3101, worst = 7
+PHY-1002 : len = 822256, over cnt = 1221(3%), over = 1663, worst = 6
+PHY-1002 : len = 837328, over cnt = 324(0%), over = 404, worst = 5
+PHY-1002 : len = 843296, over cnt = 73(0%), over = 80, worst = 4
+PHY-1002 : len = 845704, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.642758s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (145.5%)
+
+PHY-1001 : Congestion index: top1 = 59.78, top5 = 50.93, top10 = 46.89, top15 = 44.32.
+PHY-3001 : End congestion estimation; 2.030343s wall, 2.750000s user + 0.031250s system = 2.781250s CPU (137.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71430, tnet num: 17698, tinst num: 6757, tnode num: 93844, tedge num: 118686.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.570812s wall, 1.546875s user + 0.031250s system = 1.578125s CPU (100.5%)
+
+RUN-1004 : used memory is 607 MB, reserved memory is 609 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17698 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.411095s wall, 2.359375s user + 0.062500s system = 2.421875s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.65877e-05
+PHY-3002 : Step(235): len = 650759, overlap = 225.25
+PHY-3002 : Step(236): len = 643992, overlap = 234.75
+PHY-3002 : Step(237): len = 639097, overlap = 241
+PHY-3002 : Step(238): len = 635207, overlap = 248
+PHY-3002 : Step(239): len = 632273, overlap = 251.25
+PHY-3002 : Step(240): len = 629595, overlap = 255.5
+PHY-3002 : Step(241): len = 627425, overlap = 253.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000113175
+PHY-3002 : Step(242): len = 631165, overlap = 247.75
+PHY-3002 : Step(243): len = 633234, overlap = 245
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000226351
+PHY-3002 : Step(244): len = 637772, overlap = 234.25
+PHY-3002 : Step(245): len = 647737, overlap = 219
+PHY-3002 : Step(246): len = 648293, overlap = 214.75
+PHY-3002 : Step(247): len = 648291, overlap = 214
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.387226s wall, 0.359375s user + 0.609375s system = 0.968750s CPU (250.2%)
+
+PHY-3001 : Trial Legalized: Len = 734871
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1091/17876.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 845248, over cnt = 2638(7%), over = 4447, worst = 8
+PHY-1002 : len = 860568, over cnt = 1775(5%), over = 2637, worst = 7
+PHY-1002 : len = 873760, over cnt = 1035(2%), over = 1529, worst = 6
+PHY-1002 : len = 892792, over cnt = 322(0%), over = 467, worst = 5
+PHY-1002 : len = 900376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.437153s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (136.6%)
+
+PHY-1001 : Congestion index: top1 = 56.31, top5 = 51.45, top10 = 48.14, top15 = 45.87.
+PHY-3001 : End congestion estimation; 2.896184s wall, 3.750000s user + 0.031250s system = 3.781250s CPU (130.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17698 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.200917s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000181712
+PHY-3002 : Step(248): len = 706653, overlap = 38.5
+PHY-3002 : Step(249): len = 690394, overlap = 59.25
+PHY-3002 : Step(250): len = 677000, overlap = 87.5
+PHY-3002 : Step(251): len = 667715, overlap = 113
+PHY-3002 : Step(252): len = 662673, overlap = 128.5
+PHY-3002 : Step(253): len = 659643, overlap = 139.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000363423
+PHY-3002 : Step(254): len = 664094, overlap = 132.75
+PHY-3002 : Step(255): len = 668136, overlap = 134.75
+PHY-3002 : Step(256): len = 667965, overlap = 133.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000726847
+PHY-3002 : Step(257): len = 671133, overlap = 129.25
+PHY-3002 : Step(258): len = 678625, overlap = 125.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033346s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (93.7%)
+
+PHY-3001 : Legalized: Len = 706593, Over = 0
+PHY-3001 : Spreading special nets. 486 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.105590s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (103.6%)
+
+PHY-3001 : 711 instances has been re-located, deltaX = 207, deltaY = 429, maxDist = 3.
+PHY-3001 : Final: Len = 718411, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71430, tnet num: 17698, tinst num: 6760, tnode num: 93844, tedge num: 118686.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.817091s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (99.7%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 632 MB, peak memory is 731 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4208/17876.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843928, over cnt = 2502(7%), over = 4155, worst = 9
+PHY-1002 : len = 857912, over cnt = 1594(4%), over = 2312, worst = 6
+PHY-1002 : len = 878224, over cnt = 514(1%), over = 698, worst = 6
+PHY-1002 : len = 888448, over cnt = 76(0%), over = 93, worst = 6
+PHY-1002 : len = 890264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.953396s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (138.4%)
+
+PHY-1001 : Congestion index: top1 = 56.31, top5 = 50.11, top10 = 46.79, top15 = 44.76.
+PHY-1001 : End incremental global routing; 2.315712s wall, 3.046875s user + 0.031250s system = 3.078125s CPU (132.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17698 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.840217s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.4%)
+
+OPT-1001 : 3 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6669 has valid locations, 17 needs to be replaced
+PHY-3001 : design contains 6774 instances, 6625 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3611 pins
+PHY-3001 : Found 468 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 720506
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16279/17891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892760, over cnt = 75(0%), over = 83, worst = 2
+PHY-1002 : len = 892776, over cnt = 31(0%), over = 34, worst = 2
+PHY-1002 : len = 893080, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 893112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.584031s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 56.31, top5 = 50.14, top10 = 46.80, top15 = 44.79.
+PHY-3001 : End congestion estimation; 0.906831s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (103.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71557, tnet num: 17713, tinst num: 6774, tnode num: 93995, tedge num: 118840.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.793337s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.2%)
+
+RUN-1004 : used memory is 676 MB, reserved memory is 672 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.652358s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(259): len = 720506, overlap = 0
+PHY-3002 : Step(260): len = 720506, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16294/17891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 893112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127560s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (110.2%)
+
+PHY-1001 : Congestion index: top1 = 56.31, top5 = 50.14, top10 = 46.80, top15 = 44.79.
+PHY-3001 : End congestion estimation; 0.432921s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.830605s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000753838
+PHY-3002 : Step(261): len = 720269, overlap = 0.25
+PHY-3002 : Step(262): len = 720383, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005672s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 720415, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056778s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 720421, Over = 0
+PHY-3001 : End incremental placement; 5.301862s wall, 5.484375s user + 0.062500s system = 5.546875s CPU (104.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 8.921635s wall, 9.953125s user + 0.093750s system = 10.046875s CPU (112.6%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 729, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16274/17891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892928, over cnt = 37(0%), over = 45, worst = 3
+PHY-1002 : len = 892976, over cnt = 21(0%), over = 26, worst = 3
+PHY-1002 : len = 893288, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 893344, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.577441s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 56.36, top5 = 50.16, top10 = 46.80, top15 = 44.76.
+OPT-1001 : End congestion update; 0.882922s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.718859s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.0%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6774 instances, 6625 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3611 pins
+PHY-3001 : Found 468 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 727923, Over = 0
+PHY-3001 : Spreading special nets. 24 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060324s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.6%)
+
+PHY-3001 : 37 instances has been re-located, deltaX = 33, deltaY = 25, maxDist = 3.
+PHY-3001 : Final: Len = 728823, Over = 0
+PHY-3001 : End incremental legalization; 0.374067s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.2%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 53 cells processed and 17768 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6774 instances, 6625 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3611 pins
+PHY-3001 : Found 468 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 729261, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057225s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.2%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 7, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 729395, Over = 0
+PHY-3001 : End incremental legalization; 0.365901s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (128.1%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 16 cells processed and 1825 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6774 instances, 6625 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3611 pins
+PHY-3001 : Found 468 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 729699, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058602s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 1, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 729679, Over = 0
+PHY-3001 : End incremental legalization; 0.370974s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (122.1%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 19 cells processed and 1466 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6690 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6778 instances, 6629 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3614 pins
+PHY-3001 : Found 470 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730541, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057453s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.8%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 3, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 730613, Over = 0
+PHY-3001 : End incremental legalization; 0.369766s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.4%)
+
+OPT-0007 : Iter 4: improved WNS 121 TNS 0 NUM_FEPS 0 with 4 cells processed and 1250 slack improved
+OPT-1001 : End bottleneck based optimization; 3.639323s wall, 3.796875s user + 0.015625s system = 3.812500s CPU (104.8%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15892/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902872, over cnt = 169(0%), over = 203, worst = 5
+PHY-1002 : len = 902824, over cnt = 90(0%), over = 97, worst = 3
+PHY-1002 : len = 903528, over cnt = 39(0%), over = 40, worst = 2
+PHY-1002 : len = 904096, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 904304, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.844487s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (109.2%)
+
+PHY-1001 : Congestion index: top1 = 55.75, top5 = 49.81, top10 = 46.67, top15 = 44.69.
+OPT-1001 : End congestion update; 1.160678s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (106.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.731919s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.3%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6690 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6778 instances, 6629 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3614 pins
+PHY-3001 : Found 470 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730649, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058985s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.0%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 1, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 730721, Over = 0
+PHY-3001 : End incremental legalization; 0.407705s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (103.5%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 11 cells processed and 1100 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.425885s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (103.1%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 730, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.699146s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16257/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904360, over cnt = 33(0%), over = 39, worst = 4
+PHY-1002 : len = 904312, over cnt = 12(0%), over = 13, worst = 2
+PHY-1002 : len = 904416, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 904432, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 904448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.754285s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (103.6%)
+
+PHY-1001 : Congestion index: top1 = 55.69, top5 = 49.77, top10 = 46.62, top15 = 44.66.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.696253s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.344828
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6690 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6778 instances, 6629 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3614 pins
+PHY-3001 : Found 470 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730721, Over = 0
+PHY-3001 : End spreading; 0.057619s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.4%)
+
+PHY-3001 : Final: Len = 730721, Over = 0
+PHY-3001 : End incremental legalization; 0.372620s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.696582s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.7%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16286/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.125909s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.3%)
+
+PHY-1001 : Congestion index: top1 = 55.69, top5 = 49.77, top10 = 46.62, top15 = 44.66.
+OPT-1001 : End congestion update; 0.435535s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694159s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.3%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.141505s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.9%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 731, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16286/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.124544s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (100.4%)
+
+PHY-1001 : Congestion index: top1 = 55.69, top5 = 49.77, top10 = 46.62, top15 = 44.66.
+OPT-1001 : End congestion update; 0.425513s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.706558s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.289481s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.6%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 731, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.702280s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 731, reserve = 731, peak = 735.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.707299s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.4%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16286/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127198s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.3%)
+
+PHY-1001 : Congestion index: top1 = 55.69, top5 = 49.77, top10 = 46.62, top15 = 44.66.
+RUN-1001 : End congestion update; 0.432470s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.2%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.143169s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.8%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 731, peak = 735.
+OPT-1001 : End physical optimization; 24.981239s wall, 26.359375s user + 0.125000s system = 26.484375s CPU (106.0%)
+
+RUN-1003 : finish command "place" in 67.998891s wall, 92.937500s user + 6.234375s system = 99.171875s CPU (145.8%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 681 MB, peak memory is 735 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.668340s wall, 2.890625s user + 0.015625s system = 2.906250s CPU (174.2%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 682 MB, peak memory is 735 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6780 instances
+RUN-1001 : 3316 mslices, 3313 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17892 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10018 nets have 2 pins
+RUN-1001 : 6491 nets have [3 - 5] pins
+RUN-1001 : 733 nets have [6 - 10] pins
+RUN-1001 : 310 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71587, tnet num: 17714, tinst num: 6778, tnode num: 94038, tedge num: 118884.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.556202s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.4%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 659 MB, peak memory is 735 MB
+PHY-1001 : 3316 mslices, 3313 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 831832, over cnt = 2710(7%), over = 4574, worst = 9
+PHY-1002 : len = 851944, over cnt = 1663(4%), over = 2341, worst = 6
+PHY-1002 : len = 872864, over cnt = 578(1%), over = 774, worst = 5
+PHY-1002 : len = 885400, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 885752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.011996s wall, 3.859375s user + 0.031250s system = 3.890625s CPU (129.2%)
+
+PHY-1001 : Congestion index: top1 = 55.47, top5 = 49.34, top10 = 46.22, top15 = 44.32.
+PHY-1001 : End global routing; 3.328112s wall, 4.171875s user + 0.031250s system = 4.203125s CPU (126.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 706, reserve = 705, peak = 735.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 977, reserve = 979, peak = 977.
+PHY-1001 : End build detailed router design. 3.956166s wall, 3.968750s user + 0.000000s system = 3.968750s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267672, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.007691s wall, 4.984375s user + 0.000000s system = 4.984375s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267728, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.419129s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.7%)
+
+PHY-1001 : Current memory(MB): used = 1013, reserve = 1015, peak = 1013.
+PHY-1001 : End phase 1; 5.438420s wall, 5.421875s user + 0.000000s system = 5.421875s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 46% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.26206e+06, over cnt = 1733(0%), over = 1737, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1027, reserve = 1030, peak = 1027.
+PHY-1001 : End initial routed; 28.568595s wall, 56.015625s user + 0.375000s system = 56.390625s CPU (197.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16815(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.186507s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1039, peak = 1036.
+PHY-1001 : End phase 2; 31.755169s wall, 59.203125s user + 0.375000s system = 59.578125s CPU (187.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.127935s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.7%)
+
+PHY-1022 : len = 2.26206e+06, over cnt = 1734(0%), over = 1738, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.382883s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.23331e+06, over cnt = 692(0%), over = 694, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.265097s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (191.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2297e+06, over cnt = 105(0%), over = 105, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.856239s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (140.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.23032e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.281031s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (116.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.23078e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.271771s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (103.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.23084e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.180299s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16815(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.163635s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 520 feed throughs used by 402 nets
+PHY-1001 : End commit to database; 2.175292s wall, 2.140625s user + 0.031250s system = 2.171875s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1138, reserve = 1145, peak = 1138.
+PHY-1001 : End phase 3; 8.966045s wall, 10.500000s user + 0.031250s system = 10.531250s CPU (117.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.128731s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.1%)
+
+PHY-1022 : len = 2.23084e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.371933s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16815(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.199768s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 520 feed throughs used by 402 nets
+PHY-1001 : End commit to database; 2.263273s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1154, peak = 1147.
+PHY-1001 : End phase 4; 5.860528s wall, 5.859375s user + 0.000000s system = 5.859375s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.23084e+06
+PHY-1001 : Current memory(MB): used = 1149, reserve = 1157, peak = 1149.
+PHY-1001 : End export database. 0.058962s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.0%)
+
+PHY-1001 : End detail routing; 56.419729s wall, 85.390625s user + 0.406250s system = 85.796875s CPU (152.1%)
+
+RUN-1003 : finish command "route" in 62.321808s wall, 92.093750s user + 0.468750s system = 92.562500s CPU (148.5%)
+
+RUN-1004 : used memory is 1078 MB, reserved memory is 1081 MB, peak memory is 1149 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10164 out of 19600 51.86%
+#reg 9456 out of 19600 48.24%
+#le 12330
+ #lut only 2874 out of 12330 23.31%
+ #reg only 2166 out of 12330 17.57%
+ #lut® 7290 out of 12330 59.12%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1772
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1416
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1273
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 978
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 135
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u0_test_en/reg0_syn_29.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg48_syn_196.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P166 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P141 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P83 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P140 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P150 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P68 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P16 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P152 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12330 |9137 |1027 |9490 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |516 |426 |23 |433 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |92 |4 |86 |4 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |16 |0 |0 |
+| exdev_ctl_a |exdev_ctl |763 |346 |96 |586 |0 |0 |
+| u_ADconfig |AD_config |187 |124 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |260 |142 |71 |126 |0 |0 |
+| exdev_ctl_b |exdev_ctl |718 |385 |96 |542 |0 |0 |
+| u_ADconfig |AD_config |169 |123 |25 |127 |0 |0 |
+| u_gen_sp |gen_sp |251 |157 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |3017 |2439 |306 |2090 |25 |0 |
+| u0_soft_n |cdc_sync |7 |5 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |174 |119 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort |2807 |2305 |289 |1910 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |3 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2386 |1976 |253 |1559 |22 |0 |
+| channelPart |channel_part_8478 |145 |140 |3 |130 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1870 |1534 |197 |1165 |0 |0 |
+| adc_addr_gen |adc_addr_gen |218 |191 |27 |99 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |9 |0 |0 |
+| insert |insert |985 |676 |170 |696 |0 |0 |
+| ram_switch_state |ram_switch_state |667 |667 |0 |370 |0 |0 |
+| read_ram_i |read_ram |281 |225 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |231 |191 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |47 |32 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |232 |36 |272 |3 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3187 |2485 |349 |2099 |25 |1 |
+| u0_soft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |192 |96 |17 |162 |0 |0 |
+| u0_soft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u_sort |sort_rev |2959 |2368 |332 |1901 |25 |1 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2529 |2038 |290 |1544 |22 |1 |
+| channelPart |channel_part_8478 |146 |133 |3 |141 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1942 |1577 |197 |1125 |0 |0 |
+| adc_addr_gen |adc_addr_gen |196 |169 |27 |93 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |19 |16 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| insert |insert |964 |630 |170 |681 |0 |0 |
+| ram_switch_state |ram_switch_state |782 |778 |0 |351 |0 |0 |
+| read_ram_i |read_ram_rev |355 |254 |81 |208 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |214 |73 |161 |0 |0 |
+| read_ram_data |read_ram_data_rev |64 |40 |8 |47 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9956
+ #2 2 4267
+ #3 3 1673
+ #4 4 548
+ #5 5-10 773
+ #6 11-50 569
+ #7 51-100 10
+ #8 >500 1
+ Average 2.71
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.034038s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (172.1%)
+
+RUN-1004 : used memory is 1079 MB, reserved memory is 1082 MB, peak memory is 1149 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71587, tnet num: 17714, tinst num: 6778, tnode num: 94038, tedge num: 118884.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.555986s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.4%)
+
+RUN-1004 : used memory is 1083 MB, reserved memory is 1086 MB, peak memory is 1149 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.405012s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.0%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1089 MB, peak memory is 1149 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6778
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17892, pip num: 167265
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 520
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3244 valid insts, and 467082 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.769036s wall, 65.359375s user + 0.203125s system = 65.562500s CPU (671.1%)
+
+RUN-1004 : used memory is 1239 MB, reserved memory is 1242 MB, peak memory is 1355 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_171046.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_171947.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_171947.log
new file mode 100644
index 0000000..4a5af02
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_171947.log
@@ -0,0 +1,1983 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 17:19:47 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(886)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(895)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(919)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(921)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(927)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(930)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1101)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1190)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1491)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1502)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1520)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2098)
+HDL-5007 WARNING: identifier 'a_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'b_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.256906s wall, 2.140625s user + 0.109375s system = 2.250000s CPU (99.7%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 317 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2321 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2068 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18123 instances
+RUN-0007 : 7697 luts, 9203 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20700 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13220 nets have 2 pins
+RUN-1001 : 6400 nets have [3 - 5] pins
+RUN-1001 : 658 nets have [6 - 10] pins
+RUN-1001 : 173 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18121 instances, 7697 luts, 9203 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6076 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84918, tnet num: 20522, tinst num: 18121, tnode num: 115581, tedge num: 135542.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.140491s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (100.0%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 518 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.933683s wall, 1.875000s user + 0.062500s system = 1.937500s CPU (100.2%)
+
+PHY-3001 : Found 1243 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.10846e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18121.
+PHY-3001 : Level 1 #clusters 1970.
+PHY-3001 : End clustering; 0.128803s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (109.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28126e+06, overlap = 455.5
+PHY-3002 : Step(2): len = 1.21258e+06, overlap = 527.062
+PHY-3002 : Step(3): len = 828799, overlap = 622.062
+PHY-3002 : Step(4): len = 751012, overlap = 677.031
+PHY-3002 : Step(5): len = 592373, overlap = 804.531
+PHY-3002 : Step(6): len = 522733, overlap = 899.531
+PHY-3002 : Step(7): len = 450783, overlap = 987.719
+PHY-3002 : Step(8): len = 405287, overlap = 1053.5
+PHY-3002 : Step(9): len = 375564, overlap = 1122.94
+PHY-3002 : Step(10): len = 340824, overlap = 1155.88
+PHY-3002 : Step(11): len = 312373, overlap = 1187.84
+PHY-3002 : Step(12): len = 285810, overlap = 1217.56
+PHY-3002 : Step(13): len = 268535, overlap = 1247.44
+PHY-3002 : Step(14): len = 247404, overlap = 1305.88
+PHY-3002 : Step(15): len = 234630, overlap = 1352.47
+PHY-3002 : Step(16): len = 216453, overlap = 1402.72
+PHY-3002 : Step(17): len = 203726, overlap = 1396
+PHY-3002 : Step(18): len = 180348, overlap = 1404.66
+PHY-3002 : Step(19): len = 165755, overlap = 1440.31
+PHY-3002 : Step(20): len = 156116, overlap = 1463.88
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.71635e-07
+PHY-3002 : Step(21): len = 159489, overlap = 1422.16
+PHY-3002 : Step(22): len = 194400, overlap = 1291.78
+PHY-3002 : Step(23): len = 199072, overlap = 1225.56
+PHY-3002 : Step(24): len = 203033, overlap = 1198.53
+PHY-3002 : Step(25): len = 198361, overlap = 1186.25
+PHY-3002 : Step(26): len = 196444, overlap = 1192.66
+PHY-3002 : Step(27): len = 195765, overlap = 1174.44
+PHY-3002 : Step(28): len = 193685, overlap = 1135.25
+PHY-3002 : Step(29): len = 190761, overlap = 1128.22
+PHY-3002 : Step(30): len = 188338, overlap = 1119.69
+PHY-3002 : Step(31): len = 186159, overlap = 1113.41
+PHY-3002 : Step(32): len = 184095, overlap = 1103.16
+PHY-3002 : Step(33): len = 182365, overlap = 1104.5
+PHY-3002 : Step(34): len = 181317, overlap = 1078.56
+PHY-3002 : Step(35): len = 179646, overlap = 1074.78
+PHY-3002 : Step(36): len = 178481, overlap = 1058.94
+PHY-3002 : Step(37): len = 176711, overlap = 1055.81
+PHY-3002 : Step(38): len = 176252, overlap = 1035.38
+PHY-3002 : Step(39): len = 174538, overlap = 1053.19
+PHY-3002 : Step(40): len = 174445, overlap = 1060.56
+PHY-3002 : Step(41): len = 172294, overlap = 1087.38
+PHY-3002 : Step(42): len = 171096, overlap = 1095.59
+PHY-3002 : Step(43): len = 169188, overlap = 1099.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.94327e-06
+PHY-3002 : Step(44): len = 172100, overlap = 1070.81
+PHY-3002 : Step(45): len = 182550, overlap = 1024.69
+PHY-3002 : Step(46): len = 186385, overlap = 961.25
+PHY-3002 : Step(47): len = 192296, overlap = 964.938
+PHY-3002 : Step(48): len = 193632, overlap = 965
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.88654e-06
+PHY-3002 : Step(49): len = 200298, overlap = 966.75
+PHY-3002 : Step(50): len = 220619, overlap = 900.156
+PHY-3002 : Step(51): len = 229464, overlap = 851.625
+PHY-3002 : Step(52): len = 234556, overlap = 836.781
+PHY-3002 : Step(53): len = 235853, overlap = 812.625
+PHY-3002 : Step(54): len = 237291, overlap = 781.594
+PHY-3002 : Step(55): len = 237633, overlap = 780.719
+PHY-3002 : Step(56): len = 236728, overlap = 777.406
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.77308e-06
+PHY-3002 : Step(57): len = 247469, overlap = 736.438
+PHY-3002 : Step(58): len = 266933, overlap = 663.156
+PHY-3002 : Step(59): len = 276235, overlap = 622.406
+PHY-3002 : Step(60): len = 284677, overlap = 578.125
+PHY-3002 : Step(61): len = 287727, overlap = 560.75
+PHY-3002 : Step(62): len = 288346, overlap = 560.531
+PHY-3002 : Step(63): len = 286144, overlap = 575.719
+PHY-3002 : Step(64): len = 286002, overlap = 582.75
+PHY-3002 : Step(65): len = 285774, overlap = 568.25
+PHY-3002 : Step(66): len = 285220, overlap = 577.375
+PHY-3002 : Step(67): len = 284472, overlap = 576.5
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.55462e-05
+PHY-3002 : Step(68): len = 298844, overlap = 523.062
+PHY-3002 : Step(69): len = 313193, overlap = 451.969
+PHY-3002 : Step(70): len = 320956, overlap = 423.031
+PHY-3002 : Step(71): len = 325041, overlap = 416.844
+PHY-3002 : Step(72): len = 325144, overlap = 406.969
+PHY-3002 : Step(73): len = 326145, overlap = 398.062
+PHY-3002 : Step(74): len = 325869, overlap = 393.219
+PHY-3002 : Step(75): len = 325896, overlap = 374.125
+PHY-3002 : Step(76): len = 326258, overlap = 362.656
+PHY-3002 : Step(77): len = 325800, overlap = 366.125
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.10923e-05
+PHY-3002 : Step(78): len = 341044, overlap = 351.125
+PHY-3002 : Step(79): len = 351552, overlap = 324
+PHY-3002 : Step(80): len = 353321, overlap = 338.125
+PHY-3002 : Step(81): len = 356468, overlap = 323.156
+PHY-3002 : Step(82): len = 358270, overlap = 321.125
+PHY-3002 : Step(83): len = 362098, overlap = 309.906
+PHY-3002 : Step(84): len = 360040, overlap = 325.219
+PHY-3002 : Step(85): len = 361464, overlap = 320.812
+PHY-3002 : Step(86): len = 362748, overlap = 327.75
+PHY-3002 : Step(87): len = 363942, overlap = 331.75
+PHY-3002 : Step(88): len = 362289, overlap = 329.406
+PHY-3002 : Step(89): len = 362718, overlap = 323.375
+PHY-3002 : Step(90): len = 365488, overlap = 320.625
+PHY-3002 : Step(91): len = 367395, overlap = 295.531
+PHY-3002 : Step(92): len = 365025, overlap = 295.656
+PHY-3002 : Step(93): len = 366499, overlap = 305.125
+PHY-3002 : Step(94): len = 365852, overlap = 288.688
+PHY-3002 : Step(95): len = 365759, overlap = 288.531
+PHY-3002 : Step(96): len = 363990, overlap = 293.625
+PHY-3002 : Step(97): len = 363943, overlap = 297.812
+PHY-3002 : Step(98): len = 363736, overlap = 281.438
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.21847e-05
+PHY-3002 : Step(99): len = 380372, overlap = 269.188
+PHY-3002 : Step(100): len = 389555, overlap = 260.688
+PHY-3002 : Step(101): len = 387138, overlap = 255.312
+PHY-3002 : Step(102): len = 389682, overlap = 246.344
+PHY-3002 : Step(103): len = 394813, overlap = 247.969
+PHY-3002 : Step(104): len = 398204, overlap = 247.812
+PHY-3002 : Step(105): len = 394233, overlap = 246.438
+PHY-3002 : Step(106): len = 394197, overlap = 249.344
+PHY-3002 : Step(107): len = 397127, overlap = 245.312
+PHY-3002 : Step(108): len = 399426, overlap = 240.844
+PHY-3002 : Step(109): len = 395401, overlap = 244.094
+PHY-3002 : Step(110): len = 394991, overlap = 238.219
+PHY-3002 : Step(111): len = 396693, overlap = 240.594
+PHY-3002 : Step(112): len = 397717, overlap = 243.438
+PHY-3002 : Step(113): len = 394838, overlap = 252.156
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00011932
+PHY-3002 : Step(114): len = 408103, overlap = 243.812
+PHY-3002 : Step(115): len = 417968, overlap = 221.844
+PHY-3002 : Step(116): len = 417070, overlap = 217.906
+PHY-3002 : Step(117): len = 418356, overlap = 220.469
+PHY-3002 : Step(118): len = 421397, overlap = 206.812
+PHY-3002 : Step(119): len = 423658, overlap = 208.094
+PHY-3002 : Step(120): len = 421991, overlap = 214.188
+PHY-3002 : Step(121): len = 422712, overlap = 219.125
+PHY-3002 : Step(122): len = 424410, overlap = 224.188
+PHY-3002 : Step(123): len = 425970, overlap = 226.438
+PHY-3002 : Step(124): len = 424025, overlap = 223.031
+PHY-3002 : Step(125): len = 423752, overlap = 221.906
+PHY-3002 : Step(126): len = 425175, overlap = 220.438
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00023864
+PHY-3002 : Step(127): len = 435786, overlap = 220.062
+PHY-3002 : Step(128): len = 444538, overlap = 216.625
+PHY-3002 : Step(129): len = 445689, overlap = 196.875
+PHY-3002 : Step(130): len = 447701, overlap = 180.5
+PHY-3002 : Step(131): len = 451368, overlap = 182.438
+PHY-3002 : Step(132): len = 453441, overlap = 183.625
+PHY-3002 : Step(133): len = 451688, overlap = 175.688
+PHY-3002 : Step(134): len = 451944, overlap = 184.531
+PHY-3002 : Step(135): len = 454474, overlap = 194.562
+PHY-3002 : Step(136): len = 455652, overlap = 197.688
+PHY-3002 : Step(137): len = 455928, overlap = 195.188
+PHY-3002 : Step(138): len = 458250, overlap = 201.062
+PHY-3002 : Step(139): len = 460727, overlap = 208.844
+PHY-3002 : Step(140): len = 460501, overlap = 207.625
+PHY-3002 : Step(141): len = 461273, overlap = 197.875
+PHY-3002 : Step(142): len = 461359, overlap = 198.031
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00047728
+PHY-3002 : Step(143): len = 467479, overlap = 194.594
+PHY-3002 : Step(144): len = 473562, overlap = 198.25
+PHY-3002 : Step(145): len = 474991, overlap = 185.219
+PHY-3002 : Step(146): len = 476404, overlap = 184.188
+PHY-3002 : Step(147): len = 478550, overlap = 184.562
+PHY-3002 : Step(148): len = 480503, overlap = 178.781
+PHY-3002 : Step(149): len = 480358, overlap = 180.938
+PHY-3002 : Step(150): len = 481690, overlap = 173.094
+PHY-3002 : Step(151): len = 484379, overlap = 168.125
+PHY-3002 : Step(152): len = 485980, overlap = 162.375
+PHY-3002 : Step(153): len = 485042, overlap = 159.125
+PHY-3002 : Step(154): len = 485040, overlap = 159.531
+PHY-3002 : Step(155): len = 486422, overlap = 153.812
+PHY-3002 : Step(156): len = 487358, overlap = 148.75
+PHY-3002 : Step(157): len = 486318, overlap = 142.031
+PHY-3002 : Step(158): len = 486025, overlap = 142.812
+PHY-3002 : Step(159): len = 486471, overlap = 141.25
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000903303
+PHY-3002 : Step(160): len = 491003, overlap = 141.156
+PHY-3002 : Step(161): len = 497873, overlap = 133.875
+PHY-3002 : Step(162): len = 499838, overlap = 133.844
+PHY-3002 : Step(163): len = 501251, overlap = 135.219
+PHY-3002 : Step(164): len = 503100, overlap = 128.688
+PHY-3002 : Step(165): len = 504066, overlap = 126
+PHY-3002 : Step(166): len = 503336, overlap = 129.25
+PHY-3002 : Step(167): len = 503129, overlap = 130.562
+PHY-3002 : Step(168): len = 504032, overlap = 128.875
+PHY-3002 : Step(169): len = 505059, overlap = 127.125
+PHY-3002 : Step(170): len = 504910, overlap = 128.406
+PHY-3002 : Step(171): len = 504855, overlap = 126.719
+PHY-3002 : Step(172): len = 505009, overlap = 124.594
+PHY-3002 : Step(173): len = 505074, overlap = 124.844
+PHY-3002 : Step(174): len = 505086, overlap = 124.344
+PHY-3002 : Step(175): len = 505086, overlap = 124.344
+PHY-3002 : Step(176): len = 505022, overlap = 125.031
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0015089
+PHY-3002 : Step(177): len = 508330, overlap = 124.844
+PHY-3002 : Step(178): len = 516536, overlap = 123.5
+PHY-3002 : Step(179): len = 519879, overlap = 119.281
+PHY-3002 : Step(180): len = 522470, overlap = 118.844
+PHY-3002 : Step(181): len = 524008, overlap = 117.375
+PHY-3002 : Step(182): len = 524355, overlap = 116
+PHY-3002 : Step(183): len = 523250, overlap = 116.062
+PHY-3002 : Step(184): len = 522793, overlap = 115.875
+PHY-3002 : Step(185): len = 523452, overlap = 115
+PHY-3002 : Step(186): len = 523872, overlap = 115.938
+PHY-3002 : Step(187): len = 523625, overlap = 118.562
+PHY-3002 : Step(188): len = 523558, overlap = 118.062
+PHY-3002 : Step(189): len = 523967, overlap = 115.562
+PHY-3002 : Step(190): len = 523967, overlap = 115.562
+PHY-3002 : Step(191): len = 523981, overlap = 115.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013078s wall, 0.000000s user + 0.031250s system = 0.031250s CPU (238.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 703744, over cnt = 1591(4%), over = 7097, worst = 36
+PHY-1001 : End global iterations; 0.725531s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 77.56, top5 = 61.17, top10 = 52.30, top15 = 46.86.
+PHY-3001 : End congestion estimation; 0.957463s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (132.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.865699s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155078
+PHY-3002 : Step(192): len = 638501, overlap = 64.1562
+PHY-3002 : Step(193): len = 639105, overlap = 62.6562
+PHY-3002 : Step(194): len = 636144, overlap = 58.5938
+PHY-3002 : Step(195): len = 635791, overlap = 50.75
+PHY-3002 : Step(196): len = 635459, overlap = 48.75
+PHY-3002 : Step(197): len = 631947, overlap = 46.7812
+PHY-3002 : Step(198): len = 628200, overlap = 48.0938
+PHY-3002 : Step(199): len = 625743, overlap = 39.7812
+PHY-3002 : Step(200): len = 623645, overlap = 37.625
+PHY-3002 : Step(201): len = 622338, overlap = 38.5
+PHY-3002 : Step(202): len = 620646, overlap = 39.25
+PHY-3002 : Step(203): len = 619801, overlap = 37.7812
+PHY-3002 : Step(204): len = 618192, overlap = 35.7188
+PHY-3002 : Step(205): len = 617494, overlap = 32.6562
+PHY-3002 : Step(206): len = 616945, overlap = 29.7188
+PHY-3002 : Step(207): len = 615911, overlap = 33.0625
+PHY-3002 : Step(208): len = 616169, overlap = 33.8438
+PHY-3002 : Step(209): len = 613719, overlap = 34.4375
+PHY-3002 : Step(210): len = 612690, overlap = 35.3438
+PHY-3002 : Step(211): len = 610896, overlap = 36.1562
+PHY-3002 : Step(212): len = 609652, overlap = 37.1562
+PHY-3002 : Step(213): len = 608859, overlap = 38.1875
+PHY-3002 : Step(214): len = 608544, overlap = 36
+PHY-3002 : Step(215): len = 606543, overlap = 36.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000310156
+PHY-3002 : Step(216): len = 609373, overlap = 35.2812
+PHY-3002 : Step(217): len = 612184, overlap = 34.4375
+PHY-3002 : Step(218): len = 619233, overlap = 31.3438
+PHY-3002 : Step(219): len = 624360, overlap = 31.4375
+PHY-3002 : Step(220): len = 627930, overlap = 30.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000620311
+PHY-3002 : Step(221): len = 629160, overlap = 30.4375
+PHY-3002 : Step(222): len = 631905, overlap = 29.5
+PHY-3002 : Step(223): len = 638225, overlap = 26.9062
+PHY-3002 : Step(224): len = 645218, overlap = 25.2188
+PHY-3002 : Step(225): len = 651564, overlap = 27.4062
+PHY-3002 : Step(226): len = 652655, overlap = 26.5625
+PHY-3002 : Step(227): len = 652831, overlap = 28.4062
+PHY-3002 : Step(228): len = 650832, overlap = 29
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 85/20700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740616, over cnt = 2716(7%), over = 12223, worst = 43
+PHY-1001 : End global iterations; 1.757325s wall, 2.265625s user + 0.046875s system = 2.312500s CPU (131.6%)
+
+PHY-1001 : Congestion index: top1 = 83.12, top5 = 65.87, top10 = 57.72, top15 = 52.81.
+PHY-3001 : End congestion estimation; 2.095389s wall, 2.593750s user + 0.046875s system = 2.640625s CPU (126.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.894359s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (101.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001331
+PHY-3002 : Step(229): len = 646167, overlap = 230.094
+PHY-3002 : Step(230): len = 647527, overlap = 173.438
+PHY-3002 : Step(231): len = 637491, overlap = 162.219
+PHY-3002 : Step(232): len = 633727, overlap = 159.531
+PHY-3002 : Step(233): len = 627747, overlap = 149
+PHY-3002 : Step(234): len = 624949, overlap = 143.125
+PHY-3002 : Step(235): len = 621457, overlap = 128.281
+PHY-3002 : Step(236): len = 617427, overlap = 119.438
+PHY-3002 : Step(237): len = 613767, overlap = 116.562
+PHY-3002 : Step(238): len = 611717, overlap = 112.844
+PHY-3002 : Step(239): len = 609684, overlap = 106.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000266199
+PHY-3002 : Step(240): len = 609855, overlap = 101.375
+PHY-3002 : Step(241): len = 611629, overlap = 102.969
+PHY-3002 : Step(242): len = 614270, overlap = 96.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000532399
+PHY-3002 : Step(243): len = 618287, overlap = 89.875
+PHY-3002 : Step(244): len = 625165, overlap = 83.75
+PHY-3002 : Step(245): len = 631337, overlap = 75.5938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.0010648
+PHY-3002 : Step(246): len = 633328, overlap = 74.9375
+PHY-3002 : Step(247): len = 637004, overlap = 70.8125
+PHY-3002 : Step(248): len = 642749, overlap = 68.6562
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84918, tnet num: 20522, tinst num: 18121, tnode num: 115581, tedge num: 135542.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.470420s wall, 1.421875s user + 0.046875s system = 1.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 567 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 404.88 peak overflow 4.19
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1069/20700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743080, over cnt = 3135(8%), over = 11081, worst = 28
+PHY-1001 : End global iterations; 1.214812s wall, 1.750000s user + 0.062500s system = 1.812500s CPU (149.2%)
+
+PHY-1001 : Congestion index: top1 = 70.52, top5 = 57.08, top10 = 51.40, top15 = 47.94.
+PHY-1001 : End incremental global routing; 1.544766s wall, 2.078125s user + 0.062500s system = 2.140625s CPU (138.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.907814s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (99.8%)
+
+OPT-1001 : 45 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17991 has valid locations, 299 needs to be replaced
+PHY-3001 : design contains 18375 instances, 7789 luts, 9365 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6181 pins
+PHY-3001 : Found 1253 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 665818
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17118/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 756032, over cnt = 3149(8%), over = 11066, worst = 28
+PHY-1001 : End global iterations; 0.240299s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (130.0%)
+
+PHY-1001 : Congestion index: top1 = 70.02, top5 = 57.10, top10 = 51.47, top15 = 47.95.
+PHY-3001 : End congestion estimation; 0.502940s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (114.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85938, tnet num: 20776, tinst num: 18375, tnode num: 117110, tedge num: 137074.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.449531s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (100.2%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 616 MB, peak memory is 717 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.463893s wall, 2.375000s user + 0.078125s system = 2.453125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(249): len = 664885, overlap = 0.25
+PHY-3002 : Step(250): len = 664511, overlap = 0.25
+PHY-3002 : Step(251): len = 664117, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17210/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753936, over cnt = 3158(8%), over = 11137, worst = 28
+PHY-1001 : End global iterations; 0.207889s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 70.52, top5 = 57.54, top10 = 51.85, top15 = 48.33.
+PHY-3001 : End congestion estimation; 0.481946s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (103.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.947548s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000577709
+PHY-3002 : Step(252): len = 663855, overlap = 70.8438
+PHY-3002 : Step(253): len = 664105, overlap = 70.6562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00115542
+PHY-3002 : Step(254): len = 664480, overlap = 71.0938
+PHY-3002 : Step(255): len = 665092, overlap = 71.3125
+PHY-3001 : Final: Len = 665092, Over = 71.3125
+PHY-3001 : End incremental placement; 5.041716s wall, 5.109375s user + 0.265625s system = 5.375000s CPU (106.6%)
+
+OPT-1001 : Total overflow 410.88 peak overflow 4.19
+OPT-1001 : End high-fanout net optimization; 8.041953s wall, 8.687500s user + 0.375000s system = 9.062500s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 714, peak = 736.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17143/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 756992, over cnt = 3116(8%), over = 10091, worst = 28
+PHY-1002 : len = 811720, over cnt = 1939(5%), over = 4663, worst = 18
+PHY-1002 : len = 854032, over cnt = 726(2%), over = 1498, worst = 17
+PHY-1002 : len = 871464, over cnt = 132(0%), over = 192, worst = 9
+PHY-1002 : len = 874056, over cnt = 28(0%), over = 35, worst = 4
+PHY-1001 : End global iterations; 2.122992s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (134.7%)
+
+PHY-1001 : Congestion index: top1 = 58.08, top5 = 49.97, top10 = 46.50, top15 = 44.29.
+OPT-1001 : End congestion update; 2.404763s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (130.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804791s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (101.0%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 108 cells processed and 15850 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 30 cells processed and 2300 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 1550 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 550 slack improved
+OPT-1001 : End bottleneck based optimization; 3.630801s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (120.1%)
+
+OPT-1001 : Current memory(MB): used = 697, reserve = 698, peak = 736.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17210/20959.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874240, over cnt = 117(0%), over = 147, worst = 4
+PHY-1002 : len = 873976, over cnt = 70(0%), over = 76, worst = 3
+PHY-1002 : len = 874024, over cnt = 18(0%), over = 19, worst = 2
+PHY-1002 : len = 874328, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 874464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.783365s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (103.7%)
+
+PHY-1001 : Congestion index: top1 = 57.52, top5 = 49.80, top10 = 46.35, top15 = 44.17.
+OPT-1001 : End congestion update; 1.054087s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (102.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20781 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.798170s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.8%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4700 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 63 slack improved
+OPT-1001 : End path based optimization; 2.068292s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (101.2%)
+
+OPT-1001 : Current memory(MB): used = 706, reserve = 702, peak = 736.
+OPT-1001 : End physical optimization; 15.652937s wall, 17.046875s user + 0.468750s system = 17.515625s CPU (111.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7789 LUT to BLE ...
+SYN-4008 : Packed 7789 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6223 remaining SEQ's ...
+SYN-4005 : Packed 4112 SEQ with LUT/SLICE
+SYN-4006 : 824 single LUT's are left
+SYN-4006 : 2111 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9900/13755 primitive instances ...
+PHY-3001 : End packing; 1.712557s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6745 instances
+RUN-1001 : 3299 mslices, 3298 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17951 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10060 nets have 2 pins
+RUN-1001 : 6489 nets have [3 - 5] pins
+RUN-1001 : 782 nets have [6 - 10] pins
+RUN-1001 : 285 nets have [11 - 20] pins
+RUN-1001 : 303 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6743 instances, 6597 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3579 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 676330, Over = 227.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7729/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826624, over cnt = 1974(5%), over = 3181, worst = 8
+PHY-1002 : len = 833840, over cnt = 1341(3%), over = 1930, worst = 7
+PHY-1002 : len = 848464, over cnt = 547(1%), over = 754, worst = 7
+PHY-1002 : len = 853768, over cnt = 318(0%), over = 423, worst = 5
+PHY-1002 : len = 861968, over cnt = 19(0%), over = 34, worst = 5
+PHY-1001 : End global iterations; 1.643462s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 57.74, top5 = 50.02, top10 = 46.45, top15 = 44.07.
+PHY-3001 : End congestion estimation; 2.080590s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (129.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72160, tnet num: 17773, tinst num: 6743, tnode num: 94719, tedge num: 120097.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.664303s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (100.5%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 620 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.517970s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.59282e-05
+PHY-3002 : Step(256): len = 661157, overlap = 212.25
+PHY-3002 : Step(257): len = 653259, overlap = 212
+PHY-3002 : Step(258): len = 647831, overlap = 216
+PHY-3002 : Step(259): len = 644243, overlap = 218.5
+PHY-3002 : Step(260): len = 640784, overlap = 227.5
+PHY-3002 : Step(261): len = 637566, overlap = 234.75
+PHY-3002 : Step(262): len = 635341, overlap = 238.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000111856
+PHY-3002 : Step(263): len = 637817, overlap = 232
+PHY-3002 : Step(264): len = 642087, overlap = 224.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000223713
+PHY-3002 : Step(265): len = 646433, overlap = 212.25
+PHY-3002 : Step(266): len = 653526, overlap = 202.25
+PHY-3002 : Step(267): len = 654260, overlap = 196.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.368616s wall, 0.328125s user + 0.515625s system = 0.843750s CPU (228.9%)
+
+PHY-3001 : Trial Legalized: Len = 732954
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 957/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844528, over cnt = 2632(7%), over = 4404, worst = 7
+PHY-1002 : len = 861528, over cnt = 1524(4%), over = 2220, worst = 6
+PHY-1002 : len = 876488, over cnt = 725(2%), over = 1063, worst = 5
+PHY-1002 : len = 887160, over cnt = 279(0%), over = 406, worst = 5
+PHY-1002 : len = 895408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.523200s wall, 3.531250s user + 0.031250s system = 3.562500s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.43, top10 = 45.89, top15 = 44.05.
+PHY-3001 : End congestion estimation; 3.009724s wall, 4.015625s user + 0.031250s system = 4.046875s CPU (134.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.895959s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160448
+PHY-3002 : Step(268): len = 706719, overlap = 36.25
+PHY-3002 : Step(269): len = 691889, overlap = 57
+PHY-3002 : Step(270): len = 678416, overlap = 81.5
+PHY-3002 : Step(271): len = 670578, overlap = 102.25
+PHY-3002 : Step(272): len = 665778, overlap = 117.75
+PHY-3002 : Step(273): len = 662834, overlap = 126.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320895
+PHY-3002 : Step(274): len = 666942, overlap = 120.75
+PHY-3002 : Step(275): len = 670775, overlap = 117.5
+PHY-3002 : Step(276): len = 671186, overlap = 120.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00064179
+PHY-3002 : Step(277): len = 674125, overlap = 121
+PHY-3002 : Step(278): len = 680612, overlap = 121.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.031338s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (99.7%)
+
+PHY-3001 : Legalized: Len = 706194, Over = 0
+PHY-3001 : Spreading special nets. 489 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.108389s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.9%)
+
+PHY-3001 : 726 instances has been re-located, deltaX = 243, deltaY = 435, maxDist = 4.
+PHY-3001 : Final: Len = 718332, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72160, tnet num: 17773, tinst num: 6746, tnode num: 94719, tedge num: 120097.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.952868s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (100.0%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 631 MB, peak memory is 736 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4363/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 845120, over cnt = 2431(6%), over = 3852, worst = 7
+PHY-1002 : len = 858808, over cnt = 1389(3%), over = 1932, worst = 7
+PHY-1002 : len = 874832, over cnt = 495(1%), over = 638, worst = 5
+PHY-1002 : len = 878200, over cnt = 364(1%), over = 481, worst = 4
+PHY-1002 : len = 885616, over cnt = 21(0%), over = 23, worst = 2
+PHY-1001 : End global iterations; 2.176708s wall, 3.046875s user + 0.046875s system = 3.093750s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 52.59, top5 = 47.22, top10 = 44.53, top15 = 42.73.
+PHY-1001 : End incremental global routing; 2.582740s wall, 3.437500s user + 0.062500s system = 3.500000s CPU (135.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.905254s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (100.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6654 has valid locations, 24 needs to be replaced
+PHY-3001 : design contains 6766 instances, 6617 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3651 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 723008
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16334/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891088, over cnt = 103(0%), over = 115, worst = 4
+PHY-1002 : len = 891072, over cnt = 55(0%), over = 55, worst = 1
+PHY-1002 : len = 891472, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 891712, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 891744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.877849s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 52.67, top5 = 47.32, top10 = 44.65, top15 = 42.83.
+PHY-3001 : End congestion estimation; 1.217668s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (103.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72378, tnet num: 17805, tinst num: 6766, tnode num: 94993, tedge num: 120385.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.813946s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (99.9%)
+
+RUN-1004 : used memory is 687 MB, reserved memory is 686 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.313748s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (80.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(279): len = 721495, overlap = 0
+PHY-3002 : Step(280): len = 720599, overlap = 1
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16323/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 887752, over cnt = 57(0%), over = 70, worst = 5
+PHY-1002 : len = 887936, over cnt = 31(0%), over = 32, worst = 2
+PHY-1002 : len = 888152, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 888328, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 888344, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.857302s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 52.80, top5 = 47.38, top10 = 44.64, top15 = 42.83.
+PHY-3001 : End congestion estimation; 1.217130s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (105.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.890833s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.0366e-05
+PHY-3002 : Step(281): len = 720699, overlap = 2
+PHY-3002 : Step(282): len = 720699, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005991s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 720726, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.078883s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (99.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 8, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 721018, Over = 0
+PHY-3001 : End incremental placement; 7.199955s wall, 6.796875s user + 0.109375s system = 6.906250s CPU (95.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.247844s wall, 11.734375s user + 0.218750s system = 11.953125s CPU (106.3%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 740, peak = 742.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16286/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 888768, over cnt = 64(0%), over = 74, worst = 3
+PHY-1002 : len = 888880, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 889080, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 889080, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.605891s wall, 0.718750s user + 0.015625s system = 0.734375s CPU (121.2%)
+
+PHY-1001 : Congestion index: top1 = 52.74, top5 = 47.30, top10 = 44.56, top15 = 42.76.
+OPT-1001 : End congestion update; 0.943466s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (112.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.716608s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.3%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6678 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6766 instances, 6617 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3651 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 727368, Over = 0
+PHY-3001 : Spreading special nets. 24 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059169s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.6%)
+
+PHY-3001 : 33 instances has been re-located, deltaX = 16, deltaY = 23, maxDist = 3.
+PHY-3001 : Final: Len = 727692, Over = 0
+PHY-3001 : End incremental legalization; 0.368770s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.7%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 57 cells processed and 19318 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6678 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6766 instances, 6617 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3651 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 728080, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057061s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.5%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 10, deltaY = 11, maxDist = 4.
+PHY-3001 : Final: Len = 728434, Over = 0
+PHY-3001 : End incremental legalization; 0.363871s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (103.1%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 21 cells processed and 1770 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6687 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6775 instances, 6626 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3652 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 729087, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057737s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 8, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 729311, Over = 0
+PHY-3001 : End incremental legalization; 0.367995s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.9%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 1242 slack improved
+OPT-1001 : End bottleneck based optimization; 3.223072s wall, 3.421875s user + 0.031250s system = 3.453125s CPU (107.1%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 741, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15945/17986.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 897272, over cnt = 186(0%), over = 245, worst = 5
+PHY-1002 : len = 897536, over cnt = 102(0%), over = 117, worst = 4
+PHY-1002 : len = 898440, over cnt = 41(0%), over = 45, worst = 3
+PHY-1002 : len = 898800, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 899168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.838902s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (106.2%)
+
+PHY-1001 : Congestion index: top1 = 52.46, top5 = 47.18, top10 = 44.51, top15 = 42.71.
+OPT-1001 : End congestion update; 1.148860s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (104.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17808 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701233s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.3%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6687 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6775 instances, 6626 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3652 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 729869, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057404s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.7%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 7, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 730205, Over = 0
+PHY-3001 : End incremental legalization; 0.367215s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.1%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 1900 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.341103s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (102.1%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 741, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17808 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.698035s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16253/17986.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899752, over cnt = 38(0%), over = 40, worst = 3
+PHY-1002 : len = 899768, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 899928, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 899976, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 900056, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.760397s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 52.56, top5 = 47.26, top10 = 44.51, top15 = 42.71.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17808 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.700665s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.137931
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 21.465488s wall, 22.218750s user + 0.265625s system = 22.484375s CPU (104.7%)
+
+RUN-1003 : finish command "place" in 65.842540s wall, 92.000000s user + 6.421875s system = 98.421875s CPU (149.5%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 640 MB, peak memory is 743 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.664558s wall, 2.890625s user + 0.015625s system = 2.906250s CPU (174.6%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 642 MB, peak memory is 743 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6777 instances
+RUN-1001 : 3318 mslices, 3308 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17986 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10055 nets have 2 pins
+RUN-1001 : 6498 nets have [3 - 5] pins
+RUN-1001 : 795 nets have [6 - 10] pins
+RUN-1001 : 292 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72461, tnet num: 17808, tinst num: 6775, tnode num: 95104, tedge num: 120498.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.576153s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.1%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 664 MB, peak memory is 743 MB
+PHY-1001 : 3318 mslices, 3308 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17808 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 831368, over cnt = 2648(7%), over = 4253, worst = 9
+PHY-1002 : len = 848504, over cnt = 1608(4%), over = 2270, worst = 6
+PHY-1002 : len = 867720, over cnt = 574(1%), over = 795, worst = 5
+PHY-1002 : len = 881296, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 881392, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.070379s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (132.8%)
+
+PHY-1001 : Congestion index: top1 = 52.93, top5 = 47.26, top10 = 44.42, top15 = 42.62.
+PHY-1001 : End global routing; 3.392329s wall, 4.390625s user + 0.015625s system = 4.406250s CPU (129.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 716, reserve = 723, peak = 743.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 991, peak = 988.
+PHY-1001 : End build detailed router design. 4.000247s wall, 3.968750s user + 0.031250s system = 4.000000s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273176, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.852606s wall, 4.828125s user + 0.015625s system = 4.843750s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273232, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.411430s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.7%)
+
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1028, peak = 1024.
+PHY-1001 : End phase 1; 5.275713s wall, 5.250000s user + 0.015625s system = 5.265625s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.31188e+06, over cnt = 1702(0%), over = 1706, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1044, peak = 1040.
+PHY-1001 : End initial routed; 25.128412s wall, 57.375000s user + 0.156250s system = 57.531250s CPU (228.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16908(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.176570s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1057, peak = 1052.
+PHY-1001 : End phase 2; 28.305043s wall, 60.546875s user + 0.156250s system = 60.703125s CPU (214.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.133781s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.1%)
+
+PHY-1022 : len = 2.31188e+06, over cnt = 1702(0%), over = 1706, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.393875s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.28875e+06, over cnt = 621(0%), over = 622, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.304767s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (171.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.28597e+06, over cnt = 123(0%), over = 123, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.663866s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (134.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28674e+06, over cnt = 17(0%), over = 17, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.358156s wall, 0.453125s user + 0.031250s system = 0.484375s CPU (135.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28709e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.217883s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28725e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.190088s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16908(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.226462s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 485 feed throughs used by 372 nets
+PHY-1001 : End commit to database; 2.185374s wall, 2.156250s user + 0.031250s system = 2.187500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1150, reserve = 1158, peak = 1150.
+PHY-1001 : End phase 3; 8.928701s wall, 10.140625s user + 0.078125s system = 10.218750s CPU (114.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.136588s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1022 : len = 2.28725e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.375706s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16908(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.145162s wall, 3.156250s user + 0.000000s system = 3.156250s CPU (100.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 485 feed throughs used by 372 nets
+PHY-1001 : End commit to database; 2.269766s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1167, peak = 1159.
+PHY-1001 : End phase 4; 5.817067s wall, 5.812500s user + 0.000000s system = 5.812500s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.28725e+06
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1169, peak = 1161.
+PHY-1001 : End export database. 0.058654s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.9%)
+
+PHY-1001 : End detail routing; 52.776606s wall, 86.171875s user + 0.281250s system = 86.453125s CPU (163.8%)
+
+RUN-1003 : finish command "route" in 58.783757s wall, 93.171875s user + 0.296875s system = 93.468750s CPU (159.0%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1093 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10241 out of 19600 52.25%
+#reg 9565 out of 19600 48.80%
+#le 12311
+ #lut only 2746 out of 12311 22.31%
+ #reg only 2070 out of 12311 16.81%
+ #lut® 7495 out of 12311 60.88%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1774
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1455
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1280
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 973
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 134
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg19_syn_82.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg45_syn_215.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P147 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P110 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P106 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P146 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P82 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P143 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P107 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12311 |9214 |1027 |9599 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |533 |437 |23 |437 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |82 |4 |88 |4 |0 |
+| U_crc16_24b |crc16_24b |36 |36 |0 |20 |0 |0 |
+| U_ecc_gen |ecc_gen |6 |6 |0 |5 |0 |0 |
+| exdev_ctl_a |exdev_ctl |755 |350 |96 |576 |0 |0 |
+| u_ADconfig |AD_config |190 |115 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |254 |149 |71 |121 |0 |0 |
+| exdev_ctl_b |exdev_ctl |720 |359 |96 |545 |0 |0 |
+| u_ADconfig |AD_config |167 |106 |25 |125 |0 |0 |
+| u_gen_sp |gen_sp |248 |165 |71 |115 |0 |0 |
+| sampling_fe_a |sampling_fe |2920 |2347 |306 |2100 |25 |0 |
+| u0_soft_n |cdc_sync |7 |4 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |188 |117 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_sort |sort |2695 |2211 |289 |1905 |25 |0 |
+| rddpram_ctl |rddpram_ctl |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |1 |0 |7 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2238 |1862 |253 |1543 |22 |0 |
+| channelPart |channel_part_8478 |148 |143 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1737 |1437 |197 |1142 |0 |0 |
+| adc_addr_gen |adc_addr_gen |214 |187 |27 |126 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |12 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |18 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |17 |14 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |947 |675 |170 |655 |0 |0 |
+| ram_switch_state |ram_switch_state |576 |575 |0 |361 |0 |0 |
+| read_ram_i |read_ram |260 |207 |44 |187 |0 |0 |
+| read_ram_addr |read_ram_addr |211 |171 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |45 |32 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |345 |254 |36 |281 |3 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3156 |2477 |349 |2093 |25 |1 |
+| u0_soft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |195 |122 |17 |166 |0 |0 |
+| u0_soft_n |cdc_sync |7 |5 |0 |7 |0 |0 |
+| u_sort |sort_rev |2927 |2341 |332 |1893 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2504 |2009 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |152 |141 |3 |144 |0 |0 |
+| fifo_adc |fifo_adc |56 |47 |9 |41 |0 |1 |
+| ram_switch |ram_switch |1923 |1548 |197 |1134 |0 |0 |
+| adc_addr_gen |adc_addr_gen |207 |180 |27 |104 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| insert |insert |978 |630 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |738 |738 |0 |351 |0 |0 |
+| read_ram_i |read_ram_rev |346 |249 |81 |200 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |289 |207 |73 |158 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |42 |8 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9993
+ #2 2 4330
+ #3 3 1657
+ #4 4 508
+ #5 5-10 827
+ #6 11-50 564
+ #7 51-100 11
+ #8 >500 1
+ Average 2.74
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.045329s wall, 3.546875s user + 0.015625s system = 3.562500s CPU (174.2%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1094 MB, peak memory is 1161 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72461, tnet num: 17808, tinst num: 6775, tnode num: 95104, tedge num: 120498.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.549127s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.9%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1099 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17808 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.418774s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (100.2%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1105 MB, peak memory is 1161 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6775
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17986, pip num: 170007
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 485
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3255 valid insts, and 473282 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.163989s wall, 63.531250s user + 0.109375s system = 63.640625s CPU (694.5%)
+
+RUN-1004 : used memory is 1251 MB, reserved memory is 1254 MB, peak memory is 1366 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_171947.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_172934.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_172934.log
new file mode 100644
index 0000000..f56c621
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_172934.log
@@ -0,0 +1,2190 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 17:29:34 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(886)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(895)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(919)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(921)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(927)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(930)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1101)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1190)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1491)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1502)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1520)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2098)
+HDL-5007 WARNING: identifier 'a_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'b_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.185963s wall, 2.093750s user + 0.093750s system = 2.187500s CPU (100.1%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 317 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18123 instances
+RUN-0007 : 7697 luts, 9203 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20700 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13220 nets have 2 pins
+RUN-1001 : 6400 nets have [3 - 5] pins
+RUN-1001 : 658 nets have [6 - 10] pins
+RUN-1001 : 173 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18121 instances, 7697 luts, 9203 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6076 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84918, tnet num: 20522, tinst num: 18121, tnode num: 115581, tedge num: 135542.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.196899s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (99.2%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 518 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.984266s wall, 1.906250s user + 0.046875s system = 1.953125s CPU (98.4%)
+
+PHY-3001 : Found 1243 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.10846e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18121.
+PHY-3001 : Level 1 #clusters 1970.
+PHY-3001 : End clustering; 0.137915s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28126e+06, overlap = 455.5
+PHY-3002 : Step(2): len = 1.21258e+06, overlap = 527.062
+PHY-3002 : Step(3): len = 828799, overlap = 622.062
+PHY-3002 : Step(4): len = 751012, overlap = 677.031
+PHY-3002 : Step(5): len = 592373, overlap = 804.531
+PHY-3002 : Step(6): len = 522733, overlap = 899.531
+PHY-3002 : Step(7): len = 450783, overlap = 987.719
+PHY-3002 : Step(8): len = 405287, overlap = 1053.5
+PHY-3002 : Step(9): len = 375564, overlap = 1122.94
+PHY-3002 : Step(10): len = 340824, overlap = 1155.88
+PHY-3002 : Step(11): len = 312373, overlap = 1187.84
+PHY-3002 : Step(12): len = 285810, overlap = 1217.56
+PHY-3002 : Step(13): len = 268535, overlap = 1247.44
+PHY-3002 : Step(14): len = 247404, overlap = 1305.88
+PHY-3002 : Step(15): len = 234630, overlap = 1352.47
+PHY-3002 : Step(16): len = 216453, overlap = 1402.72
+PHY-3002 : Step(17): len = 203726, overlap = 1396
+PHY-3002 : Step(18): len = 180348, overlap = 1404.66
+PHY-3002 : Step(19): len = 165755, overlap = 1440.31
+PHY-3002 : Step(20): len = 156116, overlap = 1463.88
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.71635e-07
+PHY-3002 : Step(21): len = 159489, overlap = 1422.16
+PHY-3002 : Step(22): len = 194400, overlap = 1291.78
+PHY-3002 : Step(23): len = 199072, overlap = 1225.56
+PHY-3002 : Step(24): len = 203033, overlap = 1198.53
+PHY-3002 : Step(25): len = 198361, overlap = 1186.25
+PHY-3002 : Step(26): len = 196444, overlap = 1192.66
+PHY-3002 : Step(27): len = 195765, overlap = 1174.44
+PHY-3002 : Step(28): len = 193685, overlap = 1135.25
+PHY-3002 : Step(29): len = 190761, overlap = 1128.22
+PHY-3002 : Step(30): len = 188338, overlap = 1119.69
+PHY-3002 : Step(31): len = 186159, overlap = 1113.41
+PHY-3002 : Step(32): len = 184095, overlap = 1103.16
+PHY-3002 : Step(33): len = 182365, overlap = 1104.5
+PHY-3002 : Step(34): len = 181317, overlap = 1078.56
+PHY-3002 : Step(35): len = 179646, overlap = 1074.78
+PHY-3002 : Step(36): len = 178481, overlap = 1058.94
+PHY-3002 : Step(37): len = 176711, overlap = 1055.81
+PHY-3002 : Step(38): len = 176252, overlap = 1035.38
+PHY-3002 : Step(39): len = 174538, overlap = 1053.19
+PHY-3002 : Step(40): len = 174445, overlap = 1060.56
+PHY-3002 : Step(41): len = 172294, overlap = 1087.38
+PHY-3002 : Step(42): len = 171096, overlap = 1095.59
+PHY-3002 : Step(43): len = 169188, overlap = 1099.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.94327e-06
+PHY-3002 : Step(44): len = 172100, overlap = 1070.81
+PHY-3002 : Step(45): len = 182550, overlap = 1024.69
+PHY-3002 : Step(46): len = 186385, overlap = 961.25
+PHY-3002 : Step(47): len = 192296, overlap = 964.938
+PHY-3002 : Step(48): len = 193632, overlap = 965
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.88654e-06
+PHY-3002 : Step(49): len = 200298, overlap = 966.75
+PHY-3002 : Step(50): len = 220619, overlap = 900.156
+PHY-3002 : Step(51): len = 229464, overlap = 851.625
+PHY-3002 : Step(52): len = 234556, overlap = 836.781
+PHY-3002 : Step(53): len = 235853, overlap = 812.625
+PHY-3002 : Step(54): len = 237291, overlap = 781.594
+PHY-3002 : Step(55): len = 237633, overlap = 780.719
+PHY-3002 : Step(56): len = 236728, overlap = 777.406
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.77308e-06
+PHY-3002 : Step(57): len = 247469, overlap = 736.438
+PHY-3002 : Step(58): len = 266933, overlap = 663.156
+PHY-3002 : Step(59): len = 276235, overlap = 622.406
+PHY-3002 : Step(60): len = 284677, overlap = 578.125
+PHY-3002 : Step(61): len = 287727, overlap = 560.75
+PHY-3002 : Step(62): len = 288346, overlap = 560.531
+PHY-3002 : Step(63): len = 286144, overlap = 575.719
+PHY-3002 : Step(64): len = 286002, overlap = 582.75
+PHY-3002 : Step(65): len = 285774, overlap = 568.25
+PHY-3002 : Step(66): len = 285220, overlap = 577.375
+PHY-3002 : Step(67): len = 284472, overlap = 576.5
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.55462e-05
+PHY-3002 : Step(68): len = 298844, overlap = 523.062
+PHY-3002 : Step(69): len = 313193, overlap = 451.969
+PHY-3002 : Step(70): len = 320956, overlap = 423.031
+PHY-3002 : Step(71): len = 325041, overlap = 416.844
+PHY-3002 : Step(72): len = 325144, overlap = 406.969
+PHY-3002 : Step(73): len = 326145, overlap = 398.062
+PHY-3002 : Step(74): len = 325869, overlap = 393.219
+PHY-3002 : Step(75): len = 325896, overlap = 374.125
+PHY-3002 : Step(76): len = 326258, overlap = 362.656
+PHY-3002 : Step(77): len = 325800, overlap = 366.125
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.10923e-05
+PHY-3002 : Step(78): len = 341044, overlap = 351.125
+PHY-3002 : Step(79): len = 351552, overlap = 324
+PHY-3002 : Step(80): len = 353321, overlap = 338.125
+PHY-3002 : Step(81): len = 356468, overlap = 323.156
+PHY-3002 : Step(82): len = 358270, overlap = 321.125
+PHY-3002 : Step(83): len = 362098, overlap = 309.906
+PHY-3002 : Step(84): len = 360040, overlap = 325.219
+PHY-3002 : Step(85): len = 361464, overlap = 320.812
+PHY-3002 : Step(86): len = 362748, overlap = 327.75
+PHY-3002 : Step(87): len = 363942, overlap = 331.75
+PHY-3002 : Step(88): len = 362289, overlap = 329.406
+PHY-3002 : Step(89): len = 362718, overlap = 323.375
+PHY-3002 : Step(90): len = 365488, overlap = 320.625
+PHY-3002 : Step(91): len = 367395, overlap = 295.531
+PHY-3002 : Step(92): len = 365025, overlap = 295.656
+PHY-3002 : Step(93): len = 366499, overlap = 305.125
+PHY-3002 : Step(94): len = 365852, overlap = 288.688
+PHY-3002 : Step(95): len = 365759, overlap = 288.531
+PHY-3002 : Step(96): len = 363990, overlap = 293.625
+PHY-3002 : Step(97): len = 363943, overlap = 297.812
+PHY-3002 : Step(98): len = 363736, overlap = 281.438
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.21847e-05
+PHY-3002 : Step(99): len = 380372, overlap = 269.188
+PHY-3002 : Step(100): len = 389555, overlap = 260.688
+PHY-3002 : Step(101): len = 387138, overlap = 255.312
+PHY-3002 : Step(102): len = 389682, overlap = 246.344
+PHY-3002 : Step(103): len = 394813, overlap = 247.969
+PHY-3002 : Step(104): len = 398204, overlap = 247.812
+PHY-3002 : Step(105): len = 394233, overlap = 246.438
+PHY-3002 : Step(106): len = 394197, overlap = 249.344
+PHY-3002 : Step(107): len = 397127, overlap = 245.312
+PHY-3002 : Step(108): len = 399426, overlap = 240.844
+PHY-3002 : Step(109): len = 395401, overlap = 244.094
+PHY-3002 : Step(110): len = 394991, overlap = 238.219
+PHY-3002 : Step(111): len = 396693, overlap = 240.594
+PHY-3002 : Step(112): len = 397717, overlap = 243.438
+PHY-3002 : Step(113): len = 394838, overlap = 252.156
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00011932
+PHY-3002 : Step(114): len = 408103, overlap = 243.812
+PHY-3002 : Step(115): len = 417968, overlap = 221.844
+PHY-3002 : Step(116): len = 417070, overlap = 217.906
+PHY-3002 : Step(117): len = 418356, overlap = 220.469
+PHY-3002 : Step(118): len = 421397, overlap = 206.812
+PHY-3002 : Step(119): len = 423658, overlap = 208.094
+PHY-3002 : Step(120): len = 421991, overlap = 214.188
+PHY-3002 : Step(121): len = 422712, overlap = 219.125
+PHY-3002 : Step(122): len = 424410, overlap = 224.188
+PHY-3002 : Step(123): len = 425970, overlap = 226.438
+PHY-3002 : Step(124): len = 424025, overlap = 223.031
+PHY-3002 : Step(125): len = 423752, overlap = 221.906
+PHY-3002 : Step(126): len = 425175, overlap = 220.438
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00023864
+PHY-3002 : Step(127): len = 435786, overlap = 220.062
+PHY-3002 : Step(128): len = 444538, overlap = 216.625
+PHY-3002 : Step(129): len = 445689, overlap = 196.875
+PHY-3002 : Step(130): len = 447701, overlap = 180.5
+PHY-3002 : Step(131): len = 451368, overlap = 182.438
+PHY-3002 : Step(132): len = 453441, overlap = 183.625
+PHY-3002 : Step(133): len = 451688, overlap = 175.688
+PHY-3002 : Step(134): len = 451944, overlap = 184.531
+PHY-3002 : Step(135): len = 454474, overlap = 194.562
+PHY-3002 : Step(136): len = 455652, overlap = 197.688
+PHY-3002 : Step(137): len = 455928, overlap = 195.188
+PHY-3002 : Step(138): len = 458250, overlap = 201.062
+PHY-3002 : Step(139): len = 460727, overlap = 208.844
+PHY-3002 : Step(140): len = 460501, overlap = 207.625
+PHY-3002 : Step(141): len = 461273, overlap = 197.875
+PHY-3002 : Step(142): len = 461359, overlap = 198.031
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00047728
+PHY-3002 : Step(143): len = 467479, overlap = 194.594
+PHY-3002 : Step(144): len = 473562, overlap = 198.25
+PHY-3002 : Step(145): len = 474991, overlap = 185.219
+PHY-3002 : Step(146): len = 476404, overlap = 184.188
+PHY-3002 : Step(147): len = 478550, overlap = 184.562
+PHY-3002 : Step(148): len = 480503, overlap = 178.781
+PHY-3002 : Step(149): len = 480358, overlap = 180.938
+PHY-3002 : Step(150): len = 481690, overlap = 173.094
+PHY-3002 : Step(151): len = 484379, overlap = 168.125
+PHY-3002 : Step(152): len = 485980, overlap = 162.375
+PHY-3002 : Step(153): len = 485042, overlap = 159.125
+PHY-3002 : Step(154): len = 485040, overlap = 159.531
+PHY-3002 : Step(155): len = 486422, overlap = 153.812
+PHY-3002 : Step(156): len = 487358, overlap = 148.75
+PHY-3002 : Step(157): len = 486318, overlap = 142.031
+PHY-3002 : Step(158): len = 486025, overlap = 142.812
+PHY-3002 : Step(159): len = 486471, overlap = 141.25
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000903303
+PHY-3002 : Step(160): len = 491003, overlap = 141.156
+PHY-3002 : Step(161): len = 497873, overlap = 133.875
+PHY-3002 : Step(162): len = 499838, overlap = 133.844
+PHY-3002 : Step(163): len = 501251, overlap = 135.219
+PHY-3002 : Step(164): len = 503100, overlap = 128.688
+PHY-3002 : Step(165): len = 504066, overlap = 126
+PHY-3002 : Step(166): len = 503336, overlap = 129.25
+PHY-3002 : Step(167): len = 503129, overlap = 130.562
+PHY-3002 : Step(168): len = 504032, overlap = 128.875
+PHY-3002 : Step(169): len = 505059, overlap = 127.125
+PHY-3002 : Step(170): len = 504910, overlap = 128.406
+PHY-3002 : Step(171): len = 504855, overlap = 126.719
+PHY-3002 : Step(172): len = 505009, overlap = 124.594
+PHY-3002 : Step(173): len = 505074, overlap = 124.844
+PHY-3002 : Step(174): len = 505086, overlap = 124.344
+PHY-3002 : Step(175): len = 505086, overlap = 124.344
+PHY-3002 : Step(176): len = 505022, overlap = 125.031
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0015089
+PHY-3002 : Step(177): len = 508330, overlap = 124.844
+PHY-3002 : Step(178): len = 516536, overlap = 123.5
+PHY-3002 : Step(179): len = 519879, overlap = 119.281
+PHY-3002 : Step(180): len = 522470, overlap = 118.844
+PHY-3002 : Step(181): len = 524008, overlap = 117.375
+PHY-3002 : Step(182): len = 524355, overlap = 116
+PHY-3002 : Step(183): len = 523250, overlap = 116.062
+PHY-3002 : Step(184): len = 522793, overlap = 115.875
+PHY-3002 : Step(185): len = 523452, overlap = 115
+PHY-3002 : Step(186): len = 523872, overlap = 115.938
+PHY-3002 : Step(187): len = 523625, overlap = 118.562
+PHY-3002 : Step(188): len = 523558, overlap = 118.062
+PHY-3002 : Step(189): len = 523967, overlap = 115.562
+PHY-3002 : Step(190): len = 523967, overlap = 115.562
+PHY-3002 : Step(191): len = 523981, overlap = 115.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.011928s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (131.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 703744, over cnt = 1591(4%), over = 7097, worst = 36
+PHY-1001 : End global iterations; 0.726948s wall, 0.921875s user + 0.046875s system = 0.968750s CPU (133.3%)
+
+PHY-1001 : Congestion index: top1 = 77.56, top5 = 61.17, top10 = 52.30, top15 = 46.86.
+PHY-3001 : End congestion estimation; 0.956789s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (124.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.856968s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155078
+PHY-3002 : Step(192): len = 638501, overlap = 64.1562
+PHY-3002 : Step(193): len = 639105, overlap = 62.6562
+PHY-3002 : Step(194): len = 636144, overlap = 58.5938
+PHY-3002 : Step(195): len = 635791, overlap = 50.75
+PHY-3002 : Step(196): len = 635459, overlap = 48.75
+PHY-3002 : Step(197): len = 631947, overlap = 46.7812
+PHY-3002 : Step(198): len = 628200, overlap = 48.0938
+PHY-3002 : Step(199): len = 625743, overlap = 39.7812
+PHY-3002 : Step(200): len = 623645, overlap = 37.625
+PHY-3002 : Step(201): len = 622338, overlap = 38.5
+PHY-3002 : Step(202): len = 620646, overlap = 39.25
+PHY-3002 : Step(203): len = 619801, overlap = 37.7812
+PHY-3002 : Step(204): len = 618192, overlap = 35.7188
+PHY-3002 : Step(205): len = 617494, overlap = 32.6562
+PHY-3002 : Step(206): len = 616945, overlap = 29.7188
+PHY-3002 : Step(207): len = 615911, overlap = 33.0625
+PHY-3002 : Step(208): len = 616169, overlap = 33.8438
+PHY-3002 : Step(209): len = 613719, overlap = 34.4375
+PHY-3002 : Step(210): len = 612690, overlap = 35.3438
+PHY-3002 : Step(211): len = 610896, overlap = 36.1562
+PHY-3002 : Step(212): len = 609652, overlap = 37.1562
+PHY-3002 : Step(213): len = 608859, overlap = 38.1875
+PHY-3002 : Step(214): len = 608544, overlap = 36
+PHY-3002 : Step(215): len = 606543, overlap = 36.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000310156
+PHY-3002 : Step(216): len = 609373, overlap = 35.2812
+PHY-3002 : Step(217): len = 612184, overlap = 34.4375
+PHY-3002 : Step(218): len = 619233, overlap = 31.3438
+PHY-3002 : Step(219): len = 624360, overlap = 31.4375
+PHY-3002 : Step(220): len = 627930, overlap = 30.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000620311
+PHY-3002 : Step(221): len = 629160, overlap = 30.4375
+PHY-3002 : Step(222): len = 631905, overlap = 29.5
+PHY-3002 : Step(223): len = 638225, overlap = 26.9062
+PHY-3002 : Step(224): len = 645218, overlap = 25.2188
+PHY-3002 : Step(225): len = 651564, overlap = 27.4062
+PHY-3002 : Step(226): len = 652655, overlap = 26.5625
+PHY-3002 : Step(227): len = 652831, overlap = 28.4062
+PHY-3002 : Step(228): len = 650832, overlap = 29
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 85/20700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740616, over cnt = 2716(7%), over = 12223, worst = 43
+PHY-1001 : End global iterations; 1.743800s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (132.6%)
+
+PHY-1001 : Congestion index: top1 = 83.12, top5 = 65.87, top10 = 57.72, top15 = 52.81.
+PHY-3001 : End congestion estimation; 2.086471s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (127.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.877415s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001331
+PHY-3002 : Step(229): len = 646167, overlap = 230.094
+PHY-3002 : Step(230): len = 647527, overlap = 173.438
+PHY-3002 : Step(231): len = 637491, overlap = 162.219
+PHY-3002 : Step(232): len = 633727, overlap = 159.531
+PHY-3002 : Step(233): len = 627747, overlap = 149
+PHY-3002 : Step(234): len = 624949, overlap = 143.125
+PHY-3002 : Step(235): len = 621457, overlap = 128.281
+PHY-3002 : Step(236): len = 617427, overlap = 119.438
+PHY-3002 : Step(237): len = 613767, overlap = 116.562
+PHY-3002 : Step(238): len = 611717, overlap = 112.844
+PHY-3002 : Step(239): len = 609684, overlap = 106.438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000266199
+PHY-3002 : Step(240): len = 609855, overlap = 101.375
+PHY-3002 : Step(241): len = 611629, overlap = 102.969
+PHY-3002 : Step(242): len = 614270, overlap = 96.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000532399
+PHY-3002 : Step(243): len = 618287, overlap = 89.875
+PHY-3002 : Step(244): len = 625165, overlap = 83.75
+PHY-3002 : Step(245): len = 631337, overlap = 75.5938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.0010648
+PHY-3002 : Step(246): len = 633328, overlap = 74.9375
+PHY-3002 : Step(247): len = 637004, overlap = 70.8125
+PHY-3002 : Step(248): len = 642749, overlap = 68.6562
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84918, tnet num: 20522, tinst num: 18121, tnode num: 115581, tedge num: 135542.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.411608s wall, 1.359375s user + 0.046875s system = 1.406250s CPU (99.6%)
+
+RUN-1004 : used memory is 578 MB, reserved memory is 568 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 404.88 peak overflow 4.19
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1069/20700.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743080, over cnt = 3135(8%), over = 11081, worst = 28
+PHY-1001 : End global iterations; 1.213903s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (139.0%)
+
+PHY-1001 : Congestion index: top1 = 70.52, top5 = 57.08, top10 = 51.40, top15 = 47.94.
+PHY-1001 : End incremental global routing; 1.542423s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (131.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20522 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.939544s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (98.1%)
+
+OPT-1001 : 45 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17991 has valid locations, 299 needs to be replaced
+PHY-3001 : design contains 18375 instances, 7789 luts, 9365 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6181 pins
+PHY-3001 : Found 1253 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 665818
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17118/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 756032, over cnt = 3149(8%), over = 11066, worst = 28
+PHY-1001 : End global iterations; 0.242035s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (122.7%)
+
+PHY-1001 : Congestion index: top1 = 70.02, top5 = 57.10, top10 = 51.47, top15 = 47.95.
+PHY-3001 : End congestion estimation; 0.509742s wall, 0.546875s user + 0.015625s system = 0.562500s CPU (110.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85938, tnet num: 20776, tinst num: 18375, tnode num: 117110, tedge num: 137074.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.458495s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.7%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 618 MB, peak memory is 718 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.389788s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(249): len = 664885, overlap = 0.25
+PHY-3002 : Step(250): len = 664511, overlap = 0.25
+PHY-3002 : Step(251): len = 664117, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17210/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753936, over cnt = 3158(8%), over = 11137, worst = 28
+PHY-1001 : End global iterations; 0.187085s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (133.6%)
+
+PHY-1001 : Congestion index: top1 = 70.52, top5 = 57.54, top10 = 51.85, top15 = 48.33.
+PHY-3001 : End congestion estimation; 0.438236s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (117.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.267015s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000577709
+PHY-3002 : Step(252): len = 663855, overlap = 70.8438
+PHY-3002 : Step(253): len = 664105, overlap = 70.6562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00115542
+PHY-3002 : Step(254): len = 664480, overlap = 71.0938
+PHY-3002 : Step(255): len = 665092, overlap = 71.3125
+PHY-3001 : Final: Len = 665092, Over = 71.3125
+PHY-3001 : End incremental placement; 5.278422s wall, 5.640625s user + 0.218750s system = 5.859375s CPU (111.0%)
+
+OPT-1001 : Total overflow 410.88 peak overflow 4.19
+OPT-1001 : End high-fanout net optimization; 8.388412s wall, 9.281250s user + 0.250000s system = 9.531250s CPU (113.6%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 715, peak = 736.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17143/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 756992, over cnt = 3116(8%), over = 10091, worst = 28
+PHY-1002 : len = 811720, over cnt = 1939(5%), over = 4663, worst = 18
+PHY-1002 : len = 854032, over cnt = 726(2%), over = 1498, worst = 17
+PHY-1002 : len = 871464, over cnt = 132(0%), over = 192, worst = 9
+PHY-1002 : len = 874056, over cnt = 28(0%), over = 35, worst = 4
+PHY-1001 : End global iterations; 1.978930s wall, 2.734375s user + 0.062500s system = 2.796875s CPU (141.3%)
+
+PHY-1001 : Congestion index: top1 = 58.08, top5 = 49.97, top10 = 46.50, top15 = 44.29.
+OPT-1001 : End congestion update; 2.237729s wall, 2.984375s user + 0.062500s system = 3.046875s CPU (136.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.786530s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (101.3%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 108 cells processed and 15850 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 30 cells processed and 2300 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 1550 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 550 slack improved
+OPT-1001 : End bottleneck based optimization; 3.418588s wall, 4.171875s user + 0.062500s system = 4.234375s CPU (123.9%)
+
+OPT-1001 : Current memory(MB): used = 697, reserve = 695, peak = 736.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17210/20959.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874240, over cnt = 117(0%), over = 147, worst = 4
+PHY-1002 : len = 873976, over cnt = 70(0%), over = 76, worst = 3
+PHY-1002 : len = 874024, over cnt = 18(0%), over = 19, worst = 2
+PHY-1002 : len = 874328, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 874464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.752068s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (106.0%)
+
+PHY-1001 : Congestion index: top1 = 57.52, top5 = 49.80, top10 = 46.35, top15 = 44.17.
+OPT-1001 : End congestion update; 1.015196s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (104.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20781 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.809336s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (100.4%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 4700 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 63 slack improved
+OPT-1001 : End path based optimization; 2.035213s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (102.1%)
+
+OPT-1001 : Current memory(MB): used = 710, reserve = 705, peak = 736.
+OPT-1001 : End physical optimization; 15.554939s wall, 17.250000s user + 0.406250s system = 17.656250s CPU (113.5%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7789 LUT to BLE ...
+SYN-4008 : Packed 7789 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6223 remaining SEQ's ...
+SYN-4005 : Packed 4112 SEQ with LUT/SLICE
+SYN-4006 : 824 single LUT's are left
+SYN-4006 : 2111 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9900/13755 primitive instances ...
+PHY-3001 : End packing; 1.612273s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6751 instances
+RUN-1001 : 3301 mslices, 3302 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17951 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10065 nets have 2 pins
+RUN-1001 : 6482 nets have [3 - 5] pins
+RUN-1001 : 783 nets have [6 - 10] pins
+RUN-1001 : 286 nets have [11 - 20] pins
+RUN-1001 : 303 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6749 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3581 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 676123, Over = 222.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7722/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826184, over cnt = 1980(5%), over = 3187, worst = 8
+PHY-1002 : len = 833656, over cnt = 1283(3%), over = 1888, worst = 8
+PHY-1002 : len = 849968, over cnt = 403(1%), over = 536, worst = 6
+PHY-1002 : len = 856736, over cnt = 121(0%), over = 144, worst = 4
+PHY-1002 : len = 858896, over cnt = 11(0%), over = 12, worst = 2
+PHY-1001 : End global iterations; 1.627260s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (140.2%)
+
+PHY-1001 : Congestion index: top1 = 57.33, top5 = 49.88, top10 = 46.35, top15 = 44.03.
+PHY-3001 : End congestion estimation; 2.017391s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (132.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72175, tnet num: 17773, tinst num: 6749, tnode num: 94737, tedge num: 120127.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.575754s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.2%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 617 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.419870s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.85167e-05
+PHY-3002 : Step(256): len = 661209, overlap = 215.75
+PHY-3002 : Step(257): len = 653210, overlap = 210
+PHY-3002 : Step(258): len = 648093, overlap = 214.25
+PHY-3002 : Step(259): len = 644847, overlap = 214.75
+PHY-3002 : Step(260): len = 641259, overlap = 223.25
+PHY-3002 : Step(261): len = 638786, overlap = 226.25
+PHY-3002 : Step(262): len = 636740, overlap = 230.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000117033
+PHY-3002 : Step(263): len = 639337, overlap = 221
+PHY-3002 : Step(264): len = 643759, overlap = 219.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000234067
+PHY-3002 : Step(265): len = 648137, overlap = 216.5
+PHY-3002 : Step(266): len = 655485, overlap = 197.25
+PHY-3002 : Step(267): len = 656399, overlap = 196.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.374976s wall, 0.343750s user + 0.593750s system = 0.937500s CPU (250.0%)
+
+PHY-3001 : Trial Legalized: Len = 738857
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 963/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853576, over cnt = 2697(7%), over = 4444, worst = 7
+PHY-1002 : len = 869760, over cnt = 1610(4%), over = 2355, worst = 7
+PHY-1002 : len = 887200, over cnt = 658(1%), over = 968, worst = 7
+PHY-1002 : len = 902328, over cnt = 61(0%), over = 77, worst = 4
+PHY-1002 : len = 903712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.344529s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (146.0%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.24, top10 = 46.38, top15 = 44.48.
+PHY-3001 : End congestion estimation; 2.797071s wall, 3.875000s user + 0.000000s system = 3.875000s CPU (138.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.821178s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000169164
+PHY-3002 : Step(268): len = 709692, overlap = 36.75
+PHY-3002 : Step(269): len = 694843, overlap = 53.5
+PHY-3002 : Step(270): len = 681230, overlap = 73
+PHY-3002 : Step(271): len = 672775, overlap = 96.75
+PHY-3002 : Step(272): len = 668449, overlap = 110
+PHY-3002 : Step(273): len = 664866, overlap = 121.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000338327
+PHY-3002 : Step(274): len = 669510, overlap = 112
+PHY-3002 : Step(275): len = 673397, overlap = 109.25
+PHY-3002 : Step(276): len = 673572, overlap = 112.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000676654
+PHY-3002 : Step(277): len = 675629, overlap = 113.75
+PHY-3002 : Step(278): len = 681238, overlap = 117.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032615s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (95.8%)
+
+PHY-3001 : Legalized: Len = 708362, Over = 0
+PHY-3001 : Spreading special nets. 496 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.097986s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (95.7%)
+
+PHY-3001 : 713 instances has been re-located, deltaX = 232, deltaY = 407, maxDist = 2.
+PHY-3001 : Final: Len = 720222, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72175, tnet num: 17773, tinst num: 6752, tnode num: 94737, tedge num: 120127.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.800665s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (99.8%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 686 MB, peak memory is 736 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4558/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847992, over cnt = 2498(7%), over = 3977, worst = 8
+PHY-1002 : len = 860896, over cnt = 1488(4%), over = 2117, worst = 7
+PHY-1002 : len = 873064, over cnt = 839(2%), over = 1141, worst = 6
+PHY-1002 : len = 886488, over cnt = 208(0%), over = 263, worst = 4
+PHY-1002 : len = 891152, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.900885s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (152.9%)
+
+PHY-1001 : Congestion index: top1 = 52.46, top5 = 47.56, top10 = 44.90, top15 = 43.14.
+PHY-1001 : End incremental global routing; 2.274437s wall, 3.234375s user + 0.031250s system = 3.265625s CPU (143.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.823999s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.5%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 24 needs to be replaced
+PHY-3001 : design contains 6772 instances, 6623 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3652 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 724875
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16315/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896816, over cnt = 84(0%), over = 95, worst = 4
+PHY-1002 : len = 896880, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 897336, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 897352, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.688174s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (109.0%)
+
+PHY-1001 : Congestion index: top1 = 52.44, top5 = 47.59, top10 = 44.95, top15 = 43.23.
+PHY-3001 : End congestion estimation; 0.992830s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (107.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72390, tnet num: 17804, tinst num: 6772, tnode num: 95007, tedge num: 120411.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.821371s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.4%)
+
+RUN-1004 : used memory is 724 MB, reserved memory is 721 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.666422s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(279): len = 723251, overlap = 0
+PHY-3002 : Step(280): len = 722401, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16305/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 893320, over cnt = 51(0%), over = 63, worst = 3
+PHY-1002 : len = 893424, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 893592, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 893656, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.571590s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.64, top10 = 44.99, top15 = 43.23.
+PHY-3001 : End congestion estimation; 0.875169s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (103.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.830547s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000214149
+PHY-3002 : Step(281): len = 722285, overlap = 1.5
+PHY-3002 : Step(282): len = 722285, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005370s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (291.0%)
+
+PHY-3001 : Legalized: Len = 722376, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058783s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 722514, Over = 0
+PHY-3001 : End incremental placement; 5.818125s wall, 5.906250s user + 0.062500s system = 5.968750s CPU (102.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.383958s wall, 10.421875s user + 0.093750s system = 10.515625s CPU (112.1%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 735, peak = 741.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16280/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 893736, over cnt = 44(0%), over = 61, worst = 5
+PHY-1002 : len = 893744, over cnt = 18(0%), over = 23, worst = 4
+PHY-1002 : len = 893968, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 893984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.561198s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (100.2%)
+
+PHY-1001 : Congestion index: top1 = 52.46, top5 = 47.57, top10 = 44.91, top15 = 43.18.
+OPT-1001 : End congestion update; 0.865603s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.698268s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.5%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6684 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6772 instances, 6623 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3652 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 730023, Over = 0
+PHY-3001 : Spreading special nets. 27 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060550s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.2%)
+
+PHY-3001 : 36 instances has been re-located, deltaX = 32, deltaY = 21, maxDist = 3.
+PHY-3001 : Final: Len = 730807, Over = 0
+PHY-3001 : End incremental legalization; 0.375335s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 51 cells processed and 17808 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6684 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6772 instances, 6623 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3652 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 731225, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061004s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.5%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 15, deltaY = 16, maxDist = 4.
+PHY-3001 : Final: Len = 731867, Over = 0
+PHY-3001 : End incremental legalization; 0.379071s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (127.8%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 2100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6684 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6772 instances, 6623 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3652 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 731961, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058111s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.6%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 11, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 732531, Over = 0
+PHY-3001 : End incremental legalization; 0.371274s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.0%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 19 cells processed and 754 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6689 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6777 instances, 6628 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3653 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 732893, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059118s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.7%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 733005, Over = 0
+PHY-3001 : End incremental legalization; 0.375446s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (95.7%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 5 cells processed and 804 slack improved
+OPT-1001 : End bottleneck based optimization; 3.624343s wall, 3.937500s user + 0.000000s system = 3.937500s CPU (108.6%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 737, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15857/17985.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904352, over cnt = 230(0%), over = 299, worst = 6
+PHY-1002 : len = 904800, over cnt = 112(0%), over = 124, worst = 3
+PHY-1002 : len = 905800, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 906008, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 906240, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.839761s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (106.1%)
+
+PHY-1001 : Congestion index: top1 = 52.89, top5 = 47.75, top10 = 45.00, top15 = 43.21.
+OPT-1001 : End congestion update; 1.152088s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (104.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.703488s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.9%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6689 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6777 instances, 6628 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3653 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 733289, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057334s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.0%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 3, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 733411, Over = 0
+PHY-3001 : End incremental legalization; 0.405565s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.2%)
+
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 15 cells processed and 2450 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.385735s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (102.2%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 738, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.725799s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16280/17985.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906320, over cnt = 46(0%), over = 54, worst = 3
+PHY-1002 : len = 906200, over cnt = 25(0%), over = 25, worst = 1
+PHY-1002 : len = 906384, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 906576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.613081s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (101.9%)
+
+PHY-1001 : Congestion index: top1 = 52.67, top5 = 47.76, top10 = 45.04, top15 = 43.23.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.698085s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 21 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.241379
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 21ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6689 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6777 instances, 6628 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3653 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 733411, Over = 0
+PHY-3001 : End spreading; 0.057705s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.3%)
+
+PHY-3001 : Final: Len = 733411, Over = 0
+PHY-3001 : End incremental legalization; 0.370024s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701383s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16336/17985.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126775s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.6%)
+
+PHY-1001 : Congestion index: top1 = 52.67, top5 = 47.76, top10 = 45.04, top15 = 43.23.
+OPT-1001 : End congestion update; 0.430179s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.698349s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.4%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6689 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6777 instances, 6628 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3653 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 733401, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058039s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.7%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 733411, Over = 0
+PHY-3001 : End incremental legalization; 0.369325s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (131.2%)
+
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.606014s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (107.0%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 738, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16336/17985.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127350s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.2%)
+
+PHY-1001 : Congestion index: top1 = 52.67, top5 = 47.76, top10 = 45.04, top15 = 43.23.
+OPT-1001 : End congestion update; 0.434557s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701792s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6689 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6777 instances, 6628 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3653 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 733401, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056801s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.5%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 733411, Over = 0
+PHY-3001 : End incremental legalization; 0.367811s wall, 0.421875s user + 0.031250s system = 0.453125s CPU (123.2%)
+
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6689 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6777 instances, 6628 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3653 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 733401, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058214s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.5%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 733411, Over = 0
+PHY-3001 : End incremental legalization; 0.370565s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.2%)
+
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.150544s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (103.9%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 738, peak = 743.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.697187s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 740, reserve = 738, peak = 743.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.697343s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.8%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16336/17985.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127895s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.7%)
+
+PHY-1001 : Congestion index: top1 = 52.67, top5 = 47.76, top10 = 45.04, top15 = 43.23.
+RUN-1001 : End congestion update; 0.432011s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.3%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.132484s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.7%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 738, peak = 743.
+OPT-1001 : End physical optimization; 26.581778s wall, 28.171875s user + 0.156250s system = 28.328125s CPU (106.6%)
+
+RUN-1003 : finish command "place" in 70.106216s wall, 98.640625s user + 5.750000s system = 104.390625s CPU (148.9%)
+
+RUN-1004 : used memory is 681 MB, reserved memory is 679 MB, peak memory is 743 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.684552s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (175.3%)
+
+RUN-1004 : used memory is 681 MB, reserved memory is 681 MB, peak memory is 743 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6779 instances
+RUN-1001 : 3309 mslices, 3319 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17985 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10076 nets have 2 pins
+RUN-1001 : 6475 nets have [3 - 5] pins
+RUN-1001 : 798 nets have [6 - 10] pins
+RUN-1001 : 294 nets have [11 - 20] pins
+RUN-1001 : 314 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72430, tnet num: 17807, tinst num: 6777, tnode num: 95060, tedge num: 120465.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.567014s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (98.7%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 657 MB, peak memory is 743 MB
+PHY-1001 : 3309 mslices, 3319 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 836448, over cnt = 2694(7%), over = 4371, worst = 7
+PHY-1002 : len = 854064, over cnt = 1606(4%), over = 2308, worst = 6
+PHY-1002 : len = 873040, over cnt = 581(1%), over = 846, worst = 6
+PHY-1002 : len = 886496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.926539s wall, 3.750000s user + 0.046875s system = 3.796875s CPU (129.7%)
+
+PHY-1001 : Congestion index: top1 = 52.67, top5 = 47.25, top10 = 44.47, top15 = 42.64.
+PHY-1001 : End global routing; 3.243345s wall, 4.078125s user + 0.046875s system = 4.125000s CPU (127.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 708, reserve = 708, peak = 743.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 985, peak = 982.
+PHY-1001 : End build detailed router design. 3.943752s wall, 3.890625s user + 0.046875s system = 3.937500s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 272920, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.898755s wall, 4.890625s user + 0.015625s system = 4.906250s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 272976, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.416146s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.6%)
+
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1021, peak = 1017.
+PHY-1001 : End phase 1; 5.326727s wall, 5.312500s user + 0.015625s system = 5.328125s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.30745e+06, over cnt = 1580(0%), over = 1582, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1037, peak = 1033.
+PHY-1001 : End initial routed; 22.140859s wall, 53.281250s user + 0.281250s system = 53.562500s CPU (241.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16907(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.968 | -0.968 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.197491s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1050, peak = 1046.
+PHY-1001 : End phase 2; 25.338419s wall, 56.484375s user + 0.281250s system = 56.765625s CPU (224.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.857ns STNS -0.857ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135783s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%)
+
+PHY-1022 : len = 2.30745e+06, over cnt = 1581(0%), over = 1583, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.390180s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.28752e+06, over cnt = 591(0%), over = 591, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.097963s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (175.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.28515e+06, over cnt = 169(0%), over = 169, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.537089s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (130.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28501e+06, over cnt = 21(0%), over = 21, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.405841s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (123.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28531e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.271485s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (109.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28534e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.232674s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.28542e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.353868s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.28554e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.361615s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.28556e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.163766s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.4%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.28557e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.158777s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (127.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16907(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.857 | -0.857 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.183989s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 457 feed throughs used by 359 nets
+PHY-1001 : End commit to database; 2.219159s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1155, peak = 1147.
+PHY-1001 : End phase 3; 9.783533s wall, 10.859375s user + 0.031250s system = 10.890625s CPU (111.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.857ns STNS -0.857ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.134245s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.8%)
+
+PHY-1022 : len = 2.28557e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.368122s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.857ns, -0.857ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16907(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.857 | -0.857 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.166824s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 457 feed throughs used by 359 nets
+PHY-1001 : End commit to database; 2.287930s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1164, peak = 1156.
+PHY-1001 : End phase 4; 5.847964s wall, 5.859375s user + 0.000000s system = 5.859375s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.28557e+06
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1166, peak = 1158.
+PHY-1001 : End export database. 0.058909s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.1%)
+
+PHY-1001 : End detail routing; 50.683888s wall, 82.828125s user + 0.375000s system = 83.203125s CPU (164.2%)
+
+RUN-1003 : finish command "route" in 56.521955s wall, 89.484375s user + 0.421875s system = 89.906250s CPU (159.1%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1090 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10237 out of 19600 52.23%
+#reg 9564 out of 19600 48.80%
+#le 12308
+ #lut only 2744 out of 12308 22.29%
+ #reg only 2071 out of 12308 16.83%
+ #lut® 7493 out of 12308 60.88%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1770
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1428
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1314
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 974
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 134
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/reg19_syn_82.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg45_syn_215.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P147 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P110 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P106 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P146 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P82 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P143 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P107 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12308 |9210 |1027 |9598 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |534 |438 |23 |434 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |82 |4 |88 |4 |0 |
+| U_crc16_24b |crc16_24b |37 |37 |0 |21 |0 |0 |
+| U_ecc_gen |ecc_gen |6 |6 |0 |5 |0 |0 |
+| exdev_ctl_a |exdev_ctl |758 |351 |96 |578 |0 |0 |
+| u_ADconfig |AD_config |190 |115 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |255 |150 |71 |121 |0 |0 |
+| exdev_ctl_b |exdev_ctl |725 |364 |96 |550 |0 |0 |
+| u_ADconfig |AD_config |167 |106 |25 |125 |0 |0 |
+| u_gen_sp |gen_sp |249 |166 |71 |116 |0 |0 |
+| sampling_fe_a |sampling_fe |2923 |2349 |306 |2103 |25 |0 |
+| u0_soft_n |cdc_sync |7 |4 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |188 |116 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_sort |sort |2698 |2214 |289 |1908 |25 |0 |
+| rddpram_ctl |rddpram_ctl |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |1 |0 |7 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2244 |1868 |253 |1546 |22 |0 |
+| channelPart |channel_part_8478 |147 |142 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1744 |1444 |197 |1145 |0 |0 |
+| adc_addr_gen |adc_addr_gen |214 |187 |27 |126 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |12 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |17 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |948 |676 |170 |656 |0 |0 |
+| ram_switch_state |ram_switch_state |582 |581 |0 |363 |0 |0 |
+| read_ram_i |read_ram |260 |207 |44 |187 |0 |0 |
+| read_ram_addr |read_ram_addr |211 |171 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |45 |32 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |344 |253 |36 |281 |3 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3154 |2473 |349 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |192 |117 |17 |162 |0 |0 |
+| u0_soft_n |cdc_sync |7 |5 |0 |7 |0 |0 |
+| u_sort |sort_rev |2928 |2342 |332 |1893 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2506 |2011 |290 |1546 |22 |1 |
+| channelPart |channel_part_8478 |153 |142 |3 |144 |0 |0 |
+| fifo_adc |fifo_adc |56 |47 |9 |41 |0 |1 |
+| ram_switch |ram_switch |1924 |1549 |197 |1134 |0 |0 |
+| adc_addr_gen |adc_addr_gen |201 |174 |27 |100 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |15 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |16 |13 |3 |6 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| insert |insert |978 |630 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |745 |745 |0 |355 |0 |0 |
+| read_ram_i |read_ram_rev |346 |249 |81 |200 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |289 |207 |73 |158 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |42 |8 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10014
+ #2 2 4303
+ #3 3 1657
+ #4 4 512
+ #5 5-10 826
+ #6 11-50 566
+ #7 51-100 11
+ #8 >500 1
+ Average 2.74
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.033772s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (172.9%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1091 MB, peak memory is 1158 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72430, tnet num: 17807, tinst num: 6777, tnode num: 95060, tedge num: 120465.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.585240s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.6%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1094 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17807 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.416238s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (99.3%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1096 MB, peak memory is 1158 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6777
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17985, pip num: 169722
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 457
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 472601 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.079872s wall, 69.453125s user + 0.187500s system = 69.640625s CPU (690.9%)
+
+RUN-1004 : used memory is 1249 MB, reserved memory is 1252 MB, peak memory is 1364 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_172934.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_183206.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_183206.log
new file mode 100644
index 0000000..4ab97a5
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_183206.log
@@ -0,0 +1,2119 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 18:32:06 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(886)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(895)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(919)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(921)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(927)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(930)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1101)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1190)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1491)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1502)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1520)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2098)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.176659s wall, 2.062500s user + 0.125000s system = 2.187500s CPU (100.5%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2227 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2067 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18020 instances
+RUN-0007 : 7669 luts, 9128 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20604 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13114 nets have 2 pins
+RUN-1001 : 6454 nets have [3 - 5] pins
+RUN-1001 : 615 nets have [6 - 10] pins
+RUN-1001 : 182 nets have [11 - 20] pins
+RUN-1001 : 169 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2027
+RUN-1001 : No | Yes | No | 3495
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18018 instances, 7669 luts, 9128 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 5981 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84154, tnet num: 20426, tinst num: 18018, tnode num: 114511, tedge num: 134206.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.148711s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.3%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.948836s wall, 1.890625s user + 0.046875s system = 1.937500s CPU (99.4%)
+
+PHY-3001 : Found 1251 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.02561e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18018.
+PHY-3001 : Level 1 #clusters 2040.
+PHY-3001 : End clustering; 0.127706s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.34064e+06, overlap = 450.281
+PHY-3002 : Step(2): len = 1.24055e+06, overlap = 475.781
+PHY-3002 : Step(3): len = 856612, overlap = 602.781
+PHY-3002 : Step(4): len = 792916, overlap = 648.312
+PHY-3002 : Step(5): len = 614315, overlap = 791.75
+PHY-3002 : Step(6): len = 551917, overlap = 845.719
+PHY-3002 : Step(7): len = 457366, overlap = 928.406
+PHY-3002 : Step(8): len = 427620, overlap = 934.219
+PHY-3002 : Step(9): len = 378620, overlap = 982.969
+PHY-3002 : Step(10): len = 361954, overlap = 1024.75
+PHY-3002 : Step(11): len = 325719, overlap = 1065.53
+PHY-3002 : Step(12): len = 304578, overlap = 1111.59
+PHY-3002 : Step(13): len = 276162, overlap = 1175.94
+PHY-3002 : Step(14): len = 265362, overlap = 1246.59
+PHY-3002 : Step(15): len = 234742, overlap = 1315.38
+PHY-3002 : Step(16): len = 230551, overlap = 1356.25
+PHY-3002 : Step(17): len = 193401, overlap = 1385.75
+PHY-3002 : Step(18): len = 186472, overlap = 1406.5
+PHY-3002 : Step(19): len = 165345, overlap = 1449.06
+PHY-3002 : Step(20): len = 159652, overlap = 1472.25
+PHY-3002 : Step(21): len = 147677, overlap = 1480.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.07341e-06
+PHY-3002 : Step(22): len = 147672, overlap = 1451.81
+PHY-3002 : Step(23): len = 177306, overlap = 1357.94
+PHY-3002 : Step(24): len = 186896, overlap = 1254.66
+PHY-3002 : Step(25): len = 197096, overlap = 1196.34
+PHY-3002 : Step(26): len = 195787, overlap = 1176
+PHY-3002 : Step(27): len = 194762, overlap = 1165.78
+PHY-3002 : Step(28): len = 191674, overlap = 1116.75
+PHY-3002 : Step(29): len = 190361, overlap = 1102.69
+PHY-3002 : Step(30): len = 188648, overlap = 1098.22
+PHY-3002 : Step(31): len = 188187, overlap = 1091.19
+PHY-3002 : Step(32): len = 186086, overlap = 1108.5
+PHY-3002 : Step(33): len = 185250, overlap = 1095
+PHY-3002 : Step(34): len = 183249, overlap = 1098.19
+PHY-3002 : Step(35): len = 183076, overlap = 1116.09
+PHY-3002 : Step(36): len = 181635, overlap = 1115.5
+PHY-3002 : Step(37): len = 182061, overlap = 1108.34
+PHY-3002 : Step(38): len = 180310, overlap = 1103.78
+PHY-3002 : Step(39): len = 180220, overlap = 1102.88
+PHY-3002 : Step(40): len = 178684, overlap = 1097.16
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.14683e-06
+PHY-3002 : Step(41): len = 185043, overlap = 1098.88
+PHY-3002 : Step(42): len = 196857, overlap = 1049.38
+PHY-3002 : Step(43): len = 200062, overlap = 1004.75
+PHY-3002 : Step(44): len = 205069, overlap = 1000.22
+PHY-3002 : Step(45): len = 206067, overlap = 1006.16
+PHY-3002 : Step(46): len = 206892, overlap = 1005.59
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.29365e-06
+PHY-3002 : Step(47): len = 215424, overlap = 1003.88
+PHY-3002 : Step(48): len = 233867, overlap = 959.656
+PHY-3002 : Step(49): len = 242329, overlap = 884.312
+PHY-3002 : Step(50): len = 249502, overlap = 828.281
+PHY-3002 : Step(51): len = 251163, overlap = 781.125
+PHY-3002 : Step(52): len = 251978, overlap = 761.906
+PHY-3002 : Step(53): len = 252280, overlap = 738.719
+PHY-3002 : Step(54): len = 252288, overlap = 737.281
+PHY-3002 : Step(55): len = 251976, overlap = 727.781
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.5873e-06
+PHY-3002 : Step(56): len = 266908, overlap = 703.5
+PHY-3002 : Step(57): len = 286413, overlap = 618.219
+PHY-3002 : Step(58): len = 294296, overlap = 560.531
+PHY-3002 : Step(59): len = 298285, overlap = 538.156
+PHY-3002 : Step(60): len = 298560, overlap = 529.281
+PHY-3002 : Step(61): len = 299898, overlap = 519.375
+PHY-3002 : Step(62): len = 298587, overlap = 508.156
+PHY-3002 : Step(63): len = 299952, overlap = 502.875
+PHY-3002 : Step(64): len = 298878, overlap = 514
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.71746e-05
+PHY-3002 : Step(65): len = 315600, overlap = 468.844
+PHY-3002 : Step(66): len = 330604, overlap = 419.75
+PHY-3002 : Step(67): len = 335423, overlap = 382.156
+PHY-3002 : Step(68): len = 339579, overlap = 363.312
+PHY-3002 : Step(69): len = 337977, overlap = 362.812
+PHY-3002 : Step(70): len = 339006, overlap = 374.656
+PHY-3002 : Step(71): len = 336642, overlap = 359.094
+PHY-3002 : Step(72): len = 337070, overlap = 364.375
+PHY-3002 : Step(73): len = 336875, overlap = 360.906
+PHY-3002 : Step(74): len = 336641, overlap = 356.031
+PHY-3002 : Step(75): len = 336652, overlap = 365.812
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.43492e-05
+PHY-3002 : Step(76): len = 352187, overlap = 349.344
+PHY-3002 : Step(77): len = 363617, overlap = 346.938
+PHY-3002 : Step(78): len = 365755, overlap = 352.031
+PHY-3002 : Step(79): len = 368952, overlap = 368.844
+PHY-3002 : Step(80): len = 370071, overlap = 347.562
+PHY-3002 : Step(81): len = 373485, overlap = 318.969
+PHY-3002 : Step(82): len = 374551, overlap = 320.531
+PHY-3002 : Step(83): len = 376364, overlap = 311.969
+PHY-3002 : Step(84): len = 376017, overlap = 295.094
+PHY-3002 : Step(85): len = 376572, overlap = 286.562
+PHY-3002 : Step(86): len = 374859, overlap = 271.688
+PHY-3002 : Step(87): len = 376351, overlap = 280.875
+PHY-3002 : Step(88): len = 376925, overlap = 292.625
+PHY-3002 : Step(89): len = 376630, overlap = 288.031
+PHY-3002 : Step(90): len = 375112, overlap = 305.125
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.86984e-05
+PHY-3002 : Step(91): len = 391869, overlap = 286.875
+PHY-3002 : Step(92): len = 401508, overlap = 283.406
+PHY-3002 : Step(93): len = 401280, overlap = 274.375
+PHY-3002 : Step(94): len = 402522, overlap = 272.219
+PHY-3002 : Step(95): len = 406465, overlap = 257.188
+PHY-3002 : Step(96): len = 410871, overlap = 262.469
+PHY-3002 : Step(97): len = 408419, overlap = 246.062
+PHY-3002 : Step(98): len = 409617, overlap = 243.969
+PHY-3002 : Step(99): len = 414853, overlap = 232.344
+PHY-3002 : Step(100): len = 418482, overlap = 223.062
+PHY-3002 : Step(101): len = 413733, overlap = 224.188
+PHY-3002 : Step(102): len = 412991, overlap = 220.406
+PHY-3002 : Step(103): len = 414399, overlap = 230.188
+PHY-3002 : Step(104): len = 416182, overlap = 215
+PHY-3002 : Step(105): len = 412399, overlap = 222.844
+PHY-3002 : Step(106): len = 412204, overlap = 221.125
+PHY-3002 : Step(107): len = 413551, overlap = 224.344
+PHY-3002 : Step(108): len = 415707, overlap = 229.031
+PHY-3002 : Step(109): len = 413347, overlap = 224.344
+PHY-3002 : Step(110): len = 413207, overlap = 207.438
+PHY-3002 : Step(111): len = 414754, overlap = 223.75
+PHY-3002 : Step(112): len = 416184, overlap = 221.625
+PHY-3002 : Step(113): len = 413076, overlap = 217.125
+PHY-3002 : Step(114): len = 412639, overlap = 216.625
+PHY-3002 : Step(115): len = 413553, overlap = 208.75
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000137201
+PHY-3002 : Step(116): len = 427928, overlap = 218.438
+PHY-3002 : Step(117): len = 434979, overlap = 215.562
+PHY-3002 : Step(118): len = 433662, overlap = 214.562
+PHY-3002 : Step(119): len = 433902, overlap = 205.25
+PHY-3002 : Step(120): len = 436996, overlap = 195.781
+PHY-3002 : Step(121): len = 439446, overlap = 189.094
+PHY-3002 : Step(122): len = 438840, overlap = 187.906
+PHY-3002 : Step(123): len = 440842, overlap = 175.938
+PHY-3002 : Step(124): len = 443634, overlap = 182.844
+PHY-3002 : Step(125): len = 445866, overlap = 190.969
+PHY-3002 : Step(126): len = 444604, overlap = 185.375
+PHY-3002 : Step(127): len = 444749, overlap = 181.469
+PHY-3002 : Step(128): len = 444973, overlap = 185.25
+PHY-3002 : Step(129): len = 445538, overlap = 189.344
+PHY-3002 : Step(130): len = 444528, overlap = 194.156
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000256763
+PHY-3002 : Step(131): len = 453699, overlap = 182.125
+PHY-3002 : Step(132): len = 460070, overlap = 178.031
+PHY-3002 : Step(133): len = 459541, overlap = 178.5
+PHY-3002 : Step(134): len = 460439, overlap = 179.969
+PHY-3002 : Step(135): len = 464030, overlap = 180.781
+PHY-3002 : Step(136): len = 466712, overlap = 173.469
+PHY-3002 : Step(137): len = 466626, overlap = 168.594
+PHY-3002 : Step(138): len = 467280, overlap = 166.938
+PHY-3002 : Step(139): len = 469048, overlap = 161.156
+PHY-3002 : Step(140): len = 470279, overlap = 158.062
+PHY-3002 : Step(141): len = 469543, overlap = 153.344
+PHY-3002 : Step(142): len = 470414, overlap = 149.469
+PHY-3002 : Step(143): len = 471832, overlap = 151.781
+PHY-3002 : Step(144): len = 472445, overlap = 150.312
+PHY-3002 : Step(145): len = 472145, overlap = 141.656
+PHY-3002 : Step(146): len = 472986, overlap = 144.5
+PHY-3002 : Step(147): len = 473727, overlap = 146.031
+PHY-3002 : Step(148): len = 474116, overlap = 145.781
+PHY-3002 : Step(149): len = 473574, overlap = 142.156
+PHY-3002 : Step(150): len = 473719, overlap = 142.969
+PHY-3002 : Step(151): len = 474730, overlap = 142.031
+PHY-3002 : Step(152): len = 475075, overlap = 141.781
+PHY-3002 : Step(153): len = 474324, overlap = 141.938
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000446946
+PHY-3002 : Step(154): len = 480659, overlap = 140.906
+PHY-3002 : Step(155): len = 485277, overlap = 141.25
+PHY-3002 : Step(156): len = 485178, overlap = 137.312
+PHY-3002 : Step(157): len = 485795, overlap = 136.312
+PHY-3002 : Step(158): len = 489872, overlap = 135.531
+PHY-3002 : Step(159): len = 494444, overlap = 130.719
+PHY-3002 : Step(160): len = 493908, overlap = 125.906
+PHY-3002 : Step(161): len = 493922, overlap = 125.125
+PHY-3002 : Step(162): len = 495372, overlap = 124.375
+PHY-3002 : Step(163): len = 495835, overlap = 123.625
+PHY-3002 : Step(164): len = 494600, overlap = 127.562
+PHY-3002 : Step(165): len = 494245, overlap = 129.5
+PHY-3002 : Step(166): len = 494858, overlap = 125.75
+PHY-3002 : Step(167): len = 495516, overlap = 123.281
+PHY-3002 : Step(168): len = 494672, overlap = 124.156
+PHY-3002 : Step(169): len = 494447, overlap = 124.688
+PHY-3002 : Step(170): len = 495580, overlap = 123.969
+PHY-3002 : Step(171): len = 496509, overlap = 120.844
+PHY-3002 : Step(172): len = 495437, overlap = 124.094
+PHY-3002 : Step(173): len = 495203, overlap = 124.094
+PHY-3002 : Step(174): len = 495908, overlap = 125.844
+PHY-3002 : Step(175): len = 496676, overlap = 125.125
+PHY-3002 : Step(176): len = 495751, overlap = 121.375
+PHY-3002 : Step(177): len = 495490, overlap = 124.906
+PHY-3002 : Step(178): len = 496248, overlap = 123.062
+PHY-3002 : Step(179): len = 496629, overlap = 124.469
+PHY-3002 : Step(180): len = 496142, overlap = 126.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000783016
+PHY-3002 : Step(181): len = 500986, overlap = 116.969
+PHY-3002 : Step(182): len = 505659, overlap = 122.25
+PHY-3002 : Step(183): len = 505608, overlap = 119.531
+PHY-3002 : Step(184): len = 505774, overlap = 119.719
+PHY-3002 : Step(185): len = 507822, overlap = 115.906
+PHY-3002 : Step(186): len = 509553, overlap = 119.688
+PHY-3002 : Step(187): len = 509182, overlap = 115.75
+PHY-3002 : Step(188): len = 509361, overlap = 113.688
+PHY-3002 : Step(189): len = 511425, overlap = 112.781
+PHY-3002 : Step(190): len = 512632, overlap = 113.062
+PHY-3002 : Step(191): len = 511713, overlap = 114.438
+PHY-3002 : Step(192): len = 511349, overlap = 113.688
+PHY-3002 : Step(193): len = 512398, overlap = 119.031
+PHY-3002 : Step(194): len = 512712, overlap = 119.344
+PHY-3002 : Step(195): len = 511790, overlap = 118.625
+PHY-3002 : Step(196): len = 511655, overlap = 118.406
+PHY-3002 : Step(197): len = 512233, overlap = 119.844
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00144303
+PHY-3002 : Step(198): len = 516369, overlap = 109.062
+PHY-3002 : Step(199): len = 522846, overlap = 109.156
+PHY-3002 : Step(200): len = 526936, overlap = 107.031
+PHY-3002 : Step(201): len = 529327, overlap = 102.625
+PHY-3002 : Step(202): len = 530563, overlap = 113.562
+PHY-3002 : Step(203): len = 531215, overlap = 111.031
+PHY-3002 : Step(204): len = 530152, overlap = 110
+PHY-3002 : Step(205): len = 529704, overlap = 108.406
+PHY-3002 : Step(206): len = 530741, overlap = 111.375
+PHY-3002 : Step(207): len = 531987, overlap = 110.125
+PHY-3002 : Step(208): len = 532314, overlap = 109.312
+PHY-3002 : Step(209): len = 533239, overlap = 109
+PHY-3002 : Step(210): len = 534008, overlap = 110.25
+PHY-3002 : Step(211): len = 534593, overlap = 111.125
+PHY-3002 : Step(212): len = 534032, overlap = 121.156
+PHY-3002 : Step(213): len = 533729, overlap = 120.906
+PHY-3002 : Step(214): len = 533616, overlap = 116.938
+PHY-3002 : Step(215): len = 533550, overlap = 115.219
+PHY-3002 : Step(216): len = 533206, overlap = 111.938
+PHY-3002 : Step(217): len = 533178, overlap = 110.656
+PHY-3002 : Step(218): len = 533228, overlap = 114.375
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00260661
+PHY-3002 : Step(219): len = 535479, overlap = 115.219
+PHY-3002 : Step(220): len = 539193, overlap = 115.062
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012223s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724736, over cnt = 1541(4%), over = 7339, worst = 42
+PHY-1001 : End global iterations; 0.693619s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 80.91, top5 = 59.41, top10 = 51.45, top15 = 46.28.
+PHY-3001 : End congestion estimation; 0.918293s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (127.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.841075s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000151009
+PHY-3002 : Step(221): len = 654859, overlap = 55.4375
+PHY-3002 : Step(222): len = 652171, overlap = 57.375
+PHY-3002 : Step(223): len = 646800, overlap = 56.0312
+PHY-3002 : Step(224): len = 644600, overlap = 48.7812
+PHY-3002 : Step(225): len = 644581, overlap = 47.375
+PHY-3002 : Step(226): len = 642154, overlap = 47.6875
+PHY-3002 : Step(227): len = 639393, overlap = 46.5312
+PHY-3002 : Step(228): len = 638048, overlap = 42.625
+PHY-3002 : Step(229): len = 636190, overlap = 39.0625
+PHY-3002 : Step(230): len = 632608, overlap = 38.375
+PHY-3002 : Step(231): len = 629322, overlap = 38.4062
+PHY-3002 : Step(232): len = 627795, overlap = 42.0312
+PHY-3002 : Step(233): len = 625949, overlap = 39.3125
+PHY-3002 : Step(234): len = 624684, overlap = 29.1562
+PHY-3002 : Step(235): len = 624126, overlap = 27.8125
+PHY-3002 : Step(236): len = 623474, overlap = 24.9375
+PHY-3002 : Step(237): len = 621871, overlap = 24.25
+PHY-3002 : Step(238): len = 619538, overlap = 24.1562
+PHY-3002 : Step(239): len = 617979, overlap = 25.75
+PHY-3002 : Step(240): len = 618024, overlap = 28.1875
+PHY-3002 : Step(241): len = 617921, overlap = 31.0938
+PHY-3002 : Step(242): len = 615820, overlap = 33.8125
+PHY-3002 : Step(243): len = 614593, overlap = 37.3438
+PHY-3002 : Step(244): len = 612626, overlap = 39.7188
+PHY-3002 : Step(245): len = 611123, overlap = 43.5938
+PHY-3002 : Step(246): len = 609801, overlap = 45.2812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000302017
+PHY-3002 : Step(247): len = 612182, overlap = 42.0938
+PHY-3002 : Step(248): len = 614611, overlap = 41.3125
+PHY-3002 : Step(249): len = 619837, overlap = 39.1562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000604034
+PHY-3002 : Step(250): len = 626120, overlap = 36.7188
+PHY-3002 : Step(251): len = 637426, overlap = 31.0625
+PHY-3002 : Step(252): len = 647204, overlap = 31.5312
+PHY-3002 : Step(253): len = 649726, overlap = 31.6562
+PHY-3002 : Step(254): len = 650949, overlap = 29.9062
+PHY-3002 : Step(255): len = 652857, overlap = 33.875
+PHY-3002 : Step(256): len = 651503, overlap = 37.75
+PHY-3002 : Step(257): len = 651333, overlap = 40.3438
+PHY-3002 : Step(258): len = 650208, overlap = 38.2188
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00120807
+PHY-3002 : Step(259): len = 654696, overlap = 38.2188
+PHY-3002 : Step(260): len = 662906, overlap = 38.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 60/20604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 748400, over cnt = 2704(7%), over = 12816, worst = 56
+PHY-1001 : End global iterations; 1.648907s wall, 2.171875s user + 0.015625s system = 2.187500s CPU (132.7%)
+
+PHY-1001 : Congestion index: top1 = 87.07, top5 = 68.67, top10 = 59.68, top15 = 54.44.
+PHY-3001 : End congestion estimation; 1.921778s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (127.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.866618s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000113157
+PHY-3002 : Step(261): len = 653866, overlap = 226.438
+PHY-3002 : Step(262): len = 651400, overlap = 192.844
+PHY-3002 : Step(263): len = 638094, overlap = 176.312
+PHY-3002 : Step(264): len = 632651, overlap = 156.938
+PHY-3002 : Step(265): len = 625661, overlap = 145.688
+PHY-3002 : Step(266): len = 622297, overlap = 142.062
+PHY-3002 : Step(267): len = 618547, overlap = 130.938
+PHY-3002 : Step(268): len = 614993, overlap = 123.875
+PHY-3002 : Step(269): len = 613524, overlap = 117.719
+PHY-3002 : Step(270): len = 609070, overlap = 119.438
+PHY-3002 : Step(271): len = 607716, overlap = 114.562
+PHY-3002 : Step(272): len = 605326, overlap = 114.406
+PHY-3002 : Step(273): len = 601176, overlap = 120.188
+PHY-3002 : Step(274): len = 597807, overlap = 125.906
+PHY-3002 : Step(275): len = 594916, overlap = 122.938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000226313
+PHY-3002 : Step(276): len = 595053, overlap = 120.438
+PHY-3002 : Step(277): len = 597680, overlap = 118.906
+PHY-3002 : Step(278): len = 599634, overlap = 112.469
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000452627
+PHY-3002 : Step(279): len = 606394, overlap = 106.688
+PHY-3002 : Step(280): len = 612923, overlap = 101.344
+PHY-3002 : Step(281): len = 616945, overlap = 96.8438
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84154, tnet num: 20426, tinst num: 18018, tnode num: 114511, tedge num: 134206.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.426862s wall, 1.390625s user + 0.031250s system = 1.421875s CPU (99.7%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 563 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 436.91 peak overflow 4.34
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 647/20604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712720, over cnt = 2940(8%), over = 10993, worst = 25
+PHY-1001 : End global iterations; 1.210564s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (148.4%)
+
+PHY-1001 : Congestion index: top1 = 72.82, top5 = 58.35, top10 = 51.69, top15 = 47.78.
+PHY-1001 : End incremental global routing; 1.534724s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (137.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.982578s wall, 0.937500s user + 0.046875s system = 0.984375s CPU (100.2%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17887 has valid locations, 305 needs to be replaced
+PHY-3001 : design contains 18277 instances, 7764 luts, 9292 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6099 pins
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 639231
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16879/20863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725672, over cnt = 2961(8%), over = 11015, worst = 26
+PHY-1001 : End global iterations; 0.227553s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (130.5%)
+
+PHY-1001 : Congestion index: top1 = 72.59, top5 = 58.55, top10 = 51.91, top15 = 48.01.
+PHY-3001 : End congestion estimation; 0.467055s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (110.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85181, tnet num: 20685, tinst num: 18277, tnode num: 116047, tedge num: 135742.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.510683s wall, 1.453125s user + 0.062500s system = 1.515625s CPU (100.3%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 628 MB, peak memory is 711 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.442536s wall, 2.390625s user + 0.062500s system = 2.453125s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(282): len = 638271, overlap = 0.25
+PHY-3002 : Step(283): len = 637931, overlap = 0.25
+PHY-3002 : Step(284): len = 637671, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16972/20863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 723624, over cnt = 2963(8%), over = 11047, worst = 25
+PHY-1001 : End global iterations; 0.190401s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (114.9%)
+
+PHY-1001 : Congestion index: top1 = 73.21, top5 = 58.75, top10 = 52.01, top15 = 48.09.
+PHY-3001 : End congestion estimation; 0.438250s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (107.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.909478s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (101.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000420616
+PHY-3002 : Step(285): len = 637394, overlap = 98.75
+PHY-3002 : Step(286): len = 637398, overlap = 98.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000841233
+PHY-3002 : Step(287): len = 637774, overlap = 98.8125
+PHY-3002 : Step(288): len = 638187, overlap = 98.6562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00161314
+PHY-3002 : Step(289): len = 638343, overlap = 98.8125
+PHY-3002 : Step(290): len = 639014, overlap = 99.1875
+PHY-3001 : Final: Len = 639014, Over = 99.1875
+PHY-3001 : End incremental placement; 4.983306s wall, 5.250000s user + 0.328125s system = 5.578125s CPU (111.9%)
+
+OPT-1001 : Total overflow 442.34 peak overflow 4.34
+OPT-1001 : End high-fanout net optimization; 8.014748s wall, 8.906250s user + 0.390625s system = 9.296875s CPU (116.0%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 711, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16902/20863.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 727184, over cnt = 2919(8%), over = 10018, worst = 25
+PHY-1002 : len = 781136, over cnt = 1949(5%), over = 4897, worst = 21
+PHY-1002 : len = 824504, over cnt = 849(2%), over = 1888, worst = 19
+PHY-1002 : len = 848032, over cnt = 222(0%), over = 414, worst = 12
+PHY-1002 : len = 855272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.017645s wall, 2.625000s user + 0.062500s system = 2.687500s CPU (133.2%)
+
+PHY-1001 : Congestion index: top1 = 59.18, top5 = 51.37, top10 = 47.56, top15 = 45.15.
+OPT-1001 : End congestion update; 2.271327s wall, 2.875000s user + 0.062500s system = 2.937500s CPU (129.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20685 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.783068s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (99.8%)
+
+OPT-0007 : Start: WNS -94 TNS -94 NUM_FEPS 1
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 110 cells processed and 14700 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 44 cells processed and 5500 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 36 cells processed and 3650 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 5: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved
+OPT-1001 : End bottleneck based optimization; 3.554894s wall, 4.140625s user + 0.078125s system = 4.218750s CPU (118.7%)
+
+OPT-1001 : Current memory(MB): used = 691, reserve = 689, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16958/20868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855648, over cnt = 117(0%), over = 142, worst = 4
+PHY-1002 : len = 855168, over cnt = 68(0%), over = 73, worst = 2
+PHY-1002 : len = 855472, over cnt = 15(0%), over = 16, worst = 2
+PHY-1002 : len = 855680, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 855800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.705816s wall, 0.734375s user + 0.015625s system = 0.750000s CPU (106.3%)
+
+PHY-1001 : Congestion index: top1 = 59.31, top5 = 51.24, top10 = 47.40, top15 = 45.03.
+OPT-1001 : End congestion update; 0.969389s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (104.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779300s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.3%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 21 cells processed and 10300 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.864248s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (103.1%)
+
+OPT-1001 : Current memory(MB): used = 701, reserve = 696, peak = 733.
+OPT-1001 : End physical optimization; 15.156519s wall, 16.718750s user + 0.531250s system = 17.250000s CPU (113.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7764 LUT to BLE ...
+SYN-4008 : Packed 7764 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6150 remaining SEQ's ...
+SYN-4005 : Packed 3877 SEQ with LUT/SLICE
+SYN-4006 : 1038 single LUT's are left
+SYN-4006 : 2273 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10037/13892 primitive instances ...
+PHY-3001 : End packing; 1.636591s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6787 instances
+RUN-1001 : 3320 mslices, 3319 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17857 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10000 nets have 2 pins
+RUN-1001 : 6501 nets have [3 - 5] pins
+RUN-1001 : 733 nets have [6 - 10] pins
+RUN-1001 : 293 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6785 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3540 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 650264, Over = 256.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7759/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 804272, over cnt = 1987(5%), over = 3262, worst = 8
+PHY-1002 : len = 813976, over cnt = 1199(3%), over = 1637, worst = 6
+PHY-1002 : len = 824744, over cnt = 550(1%), over = 746, worst = 5
+PHY-1002 : len = 836776, over cnt = 65(0%), over = 97, worst = 5
+PHY-1002 : len = 838688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.734754s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (143.2%)
+
+PHY-1001 : Congestion index: top1 = 60.22, top5 = 51.59, top10 = 47.40, top15 = 44.67.
+PHY-3001 : End congestion estimation; 2.119185s wall, 2.859375s user + 0.015625s system = 2.875000s CPU (135.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71443, tnet num: 17679, tinst num: 6785, tnode num: 93820, tedge num: 118743.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.586601s wall, 1.546875s user + 0.031250s system = 1.578125s CPU (99.5%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 609 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.420183s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.93356e-05
+PHY-3002 : Step(291): len = 638586, overlap = 263.25
+PHY-3002 : Step(292): len = 632650, overlap = 259.5
+PHY-3002 : Step(293): len = 629136, overlap = 252.5
+PHY-3002 : Step(294): len = 626094, overlap = 262.75
+PHY-3002 : Step(295): len = 623649, overlap = 264.25
+PHY-3002 : Step(296): len = 621291, overlap = 264.5
+PHY-3002 : Step(297): len = 618829, overlap = 267
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.86712e-05
+PHY-3002 : Step(298): len = 622087, overlap = 261.75
+PHY-3002 : Step(299): len = 624107, overlap = 255.25
+PHY-3002 : Step(300): len = 624189, overlap = 255
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000192864
+PHY-3002 : Step(301): len = 631297, overlap = 241
+PHY-3002 : Step(302): len = 638797, overlap = 229.75
+PHY-3002 : Step(303): len = 637820, overlap = 233.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.349954s wall, 0.312500s user + 0.546875s system = 0.859375s CPU (245.6%)
+
+PHY-3001 : Trial Legalized: Len = 723506
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 974/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 834952, over cnt = 2689(7%), over = 4513, worst = 9
+PHY-1002 : len = 854224, over cnt = 1501(4%), over = 2118, worst = 6
+PHY-1002 : len = 868944, over cnt = 703(1%), over = 996, worst = 6
+PHY-1002 : len = 880040, over cnt = 202(0%), over = 312, worst = 5
+PHY-1002 : len = 884488, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.404819s wall, 3.421875s user + 0.015625s system = 3.437500s CPU (142.9%)
+
+PHY-1001 : Congestion index: top1 = 54.94, top5 = 49.80, top10 = 46.69, top15 = 44.68.
+PHY-3001 : End congestion estimation; 2.866835s wall, 3.890625s user + 0.015625s system = 3.906250s CPU (136.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.865593s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00015925
+PHY-3002 : Step(304): len = 695351, overlap = 42
+PHY-3002 : Step(305): len = 679777, overlap = 66.25
+PHY-3002 : Step(306): len = 665729, overlap = 96
+PHY-3002 : Step(307): len = 656990, overlap = 115.25
+PHY-3002 : Step(308): len = 652269, overlap = 130.25
+PHY-3002 : Step(309): len = 648836, overlap = 148.25
+PHY-3002 : Step(310): len = 647146, overlap = 168
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.0003185
+PHY-3002 : Step(311): len = 651349, overlap = 159
+PHY-3002 : Step(312): len = 655008, overlap = 155.75
+PHY-3002 : Step(313): len = 656012, overlap = 160
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000632768
+PHY-3002 : Step(314): len = 659230, overlap = 156.5
+PHY-3002 : Step(315): len = 666200, overlap = 147.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033251s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (94.0%)
+
+PHY-3001 : Legalized: Len = 695269, Over = 0
+PHY-3001 : Spreading special nets. 420 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.098827s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (94.9%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 233, deltaY = 344, maxDist = 2.
+PHY-3001 : Final: Len = 705583, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71443, tnet num: 17679, tinst num: 6788, tnode num: 93820, tedge num: 118743.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.810715s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.2%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 643 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3768/17857.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 828568, over cnt = 2494(7%), over = 4222, worst = 7
+PHY-1002 : len = 845264, over cnt = 1387(3%), over = 1980, worst = 6
+PHY-1002 : len = 863536, over cnt = 425(1%), over = 580, worst = 6
+PHY-1002 : len = 869744, over cnt = 135(0%), over = 180, worst = 5
+PHY-1002 : len = 872808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.024496s wall, 2.796875s user + 0.015625s system = 2.812500s CPU (138.9%)
+
+PHY-1001 : Congestion index: top1 = 54.18, top5 = 48.41, top10 = 45.44, top15 = 43.47.
+PHY-1001 : End incremental global routing; 2.401728s wall, 3.171875s user + 0.015625s system = 3.187500s CPU (132.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17679 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.834755s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.2%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6694 has valid locations, 29 needs to be replaced
+PHY-3001 : design contains 6811 instances, 6662 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 708933
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16217/17880.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876424, over cnt = 95(0%), over = 107, worst = 2
+PHY-1002 : len = 876616, over cnt = 36(0%), over = 37, worst = 2
+PHY-1002 : len = 876768, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 876976, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 877168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.783940s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (103.6%)
+
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.46, top10 = 45.51, top15 = 43.58.
+PHY-3001 : End congestion estimation; 1.090210s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (103.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71645, tnet num: 17702, tinst num: 6811, tnode num: 94088, tedge num: 119008.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.801644s wall, 1.765625s user + 0.031250s system = 1.796875s CPU (99.7%)
+
+RUN-1004 : used memory is 683 MB, reserved memory is 694 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17702 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.676808s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(316): len = 708363, overlap = 0
+PHY-3002 : Step(317): len = 708106, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16217/17880.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876344, over cnt = 40(0%), over = 60, worst = 5
+PHY-1002 : len = 876496, over cnt = 23(0%), over = 29, worst = 4
+PHY-1002 : len = 876688, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 876720, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 876824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.748664s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.2%)
+
+PHY-1001 : Congestion index: top1 = 54.18, top5 = 48.46, top10 = 45.52, top15 = 43.57.
+PHY-3001 : End congestion estimation; 1.051923s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (99.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17702 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.109067s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000487697
+PHY-3002 : Step(318): len = 707951, overlap = 2
+PHY-3002 : Step(319): len = 707816, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005630s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 707956, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056770s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.6%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 2, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 708102, Over = 0
+PHY-3001 : End incremental placement; 6.397169s wall, 6.468750s user + 0.093750s system = 6.562500s CPU (102.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.097723s wall, 11.046875s user + 0.125000s system = 11.171875s CPU (110.6%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16189/17880.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876536, over cnt = 75(0%), over = 97, worst = 4
+PHY-1002 : len = 876624, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 876920, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 876976, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 877056, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.789797s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (106.8%)
+
+PHY-1001 : Congestion index: top1 = 54.18, top5 = 48.41, top10 = 45.53, top15 = 43.56.
+OPT-1001 : End congestion update; 1.096786s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (105.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17702 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.698448s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.7%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6723 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6811 instances, 6662 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 716519, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058625s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.6%)
+
+PHY-3001 : 34 instances has been re-located, deltaX = 15, deltaY = 28, maxDist = 3.
+PHY-3001 : Final: Len = 717199, Over = 0
+PHY-3001 : End incremental legalization; 0.376038s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 54 cells processed and 20391 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6723 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6811 instances, 6662 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3616 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 717935, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060120s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.0%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 12, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 718441, Over = 0
+PHY-3001 : End incremental legalization; 0.372770s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.6%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 25 cells processed and 1958 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6729 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6817 instances, 6668 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3619 pins
+PHY-3001 : Found 482 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 718845, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.055399s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (84.6%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 3, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 718951, Over = 0
+PHY-3001 : End incremental legalization; 0.371065s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (117.9%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 6 cells processed and 866 slack improved
+OPT-1001 : End bottleneck based optimization; 3.378167s wall, 3.546875s user + 0.031250s system = 3.578125s CPU (105.9%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15766/17881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 887944, over cnt = 203(0%), over = 256, worst = 5
+PHY-1002 : len = 888224, over cnt = 107(0%), over = 113, worst = 3
+PHY-1002 : len = 889232, over cnt = 29(0%), over = 31, worst = 2
+PHY-1002 : len = 889472, over cnt = 18(0%), over = 20, worst = 2
+PHY-1002 : len = 889768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.825835s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (104.1%)
+
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.39, top10 = 45.55, top15 = 43.62.
+OPT-1001 : End congestion update; 1.132123s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (102.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.704754s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.8%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6729 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6817 instances, 6668 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3619 pins
+PHY-3001 : Found 482 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 719433, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.055734s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (112.1%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 3, deltaY = 4, maxDist = 1.
+PHY-3001 : Final: Len = 719367, Over = 0
+PHY-3001 : End incremental legalization; 0.366334s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.1%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 11 cells processed and 2300 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.329433s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (101.3%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.702570s wall, 0.687500s user + 0.015625s system = 0.703125s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16205/17881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 889968, over cnt = 29(0%), over = 32, worst = 3
+PHY-1002 : len = 889904, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 889936, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 890072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.625325s wall, 0.640625s user + 0.031250s system = 0.671875s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 53.99, top5 = 48.36, top10 = 45.53, top15 = 43.63.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.698866s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.620690
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6729 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6817 instances, 6668 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3619 pins
+PHY-3001 : Found 482 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 719367, Over = 0
+PHY-3001 : End spreading; 0.056837s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.0%)
+
+PHY-3001 : Final: Len = 719367, Over = 0
+PHY-3001 : End incremental legalization; 0.371660s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (96.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.693281s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.2%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16235/17881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 890072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.124333s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (100.5%)
+
+PHY-1001 : Congestion index: top1 = 53.99, top5 = 48.36, top10 = 45.53, top15 = 43.63.
+OPT-1001 : End congestion update; 0.429667s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.695683s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.1%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.137547s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (98.9%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16235/17881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 890072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126040s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.2%)
+
+PHY-1001 : Congestion index: top1 = 53.99, top5 = 48.36, top10 = 45.53, top15 = 43.63.
+OPT-1001 : End congestion update; 0.425716s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.696557s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.276268s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.4%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694101s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 737.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.696321s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.7%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16235/17881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 890072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.128613s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (109.3%)
+
+PHY-1001 : Congestion index: top1 = 53.99, top5 = 48.36, top10 = 45.53, top15 = 43.63.
+RUN-1001 : End congestion update; 0.433305s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.0%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.132772s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.7%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 732, peak = 737.
+OPT-1001 : End physical optimization; 25.650574s wall, 26.765625s user + 0.218750s system = 26.984375s CPU (105.2%)
+
+RUN-1003 : finish command "place" in 69.242432s wall, 100.328125s user + 6.250000s system = 106.578125s CPU (153.9%)
+
+RUN-1004 : used memory is 678 MB, reserved memory is 688 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.665263s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (174.5%)
+
+RUN-1004 : used memory is 678 MB, reserved memory is 689 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6819 instances
+RUN-1001 : 3342 mslices, 3326 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17881 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9993 nets have 2 pins
+RUN-1001 : 6502 nets have [3 - 5] pins
+RUN-1001 : 743 nets have [6 - 10] pins
+RUN-1001 : 304 nets have [11 - 20] pins
+RUN-1001 : 311 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71696, tnet num: 17703, tinst num: 6817, tnode num: 94160, tedge num: 119082.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.589916s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.3%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 658 MB, peak memory is 737 MB
+PHY-1001 : 3342 mslices, 3326 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 821280, over cnt = 2705(7%), over = 4632, worst = 8
+PHY-1002 : len = 844016, over cnt = 1473(4%), over = 2051, worst = 6
+PHY-1002 : len = 858440, over cnt = 720(2%), over = 1005, worst = 5
+PHY-1002 : len = 874352, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 874528, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.937819s wall, 3.937500s user + 0.000000s system = 3.937500s CPU (134.0%)
+
+PHY-1001 : Congestion index: top1 = 53.60, top5 = 47.90, top10 = 45.11, top15 = 43.23.
+PHY-1001 : End global routing; 3.257379s wall, 4.265625s user + 0.000000s system = 4.265625s CPU (131.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 711, reserve = 713, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 981, reserve = 984, peak = 981.
+PHY-1001 : End build detailed router design. 3.918985s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 265576, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.315166s wall, 5.312500s user + 0.000000s system = 5.312500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 265632, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.476891s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.6%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1022, peak = 1018.
+PHY-1001 : End phase 1; 5.803743s wall, 5.796875s user + 0.000000s system = 5.796875s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.25066e+06, over cnt = 1679(0%), over = 1689, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1032, peak = 1030.
+PHY-1001 : End initial routed; 24.455045s wall, 56.937500s user + 0.203125s system = 57.140625s CPU (233.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16804(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.210498s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1048, peak = 1045.
+PHY-1001 : End phase 2; 27.665616s wall, 60.156250s user + 0.203125s system = 60.359375s CPU (218.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.128895s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (109.1%)
+
+PHY-1022 : len = 2.25066e+06, over cnt = 1680(0%), over = 1690, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.384402s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2258e+06, over cnt = 564(0%), over = 564, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.040616s wall, 2.015625s user + 0.015625s system = 2.031250s CPU (195.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.22387e+06, over cnt = 139(0%), over = 139, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.549840s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (159.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.22474e+06, over cnt = 15(0%), over = 15, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.300277s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (135.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.22492e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.179109s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (113.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.22494e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.171003s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16804(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.233436s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 495 feed throughs used by 382 nets
+PHY-1001 : End commit to database; 2.225782s wall, 2.203125s user + 0.015625s system = 2.218750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1142, reserve = 1148, peak = 1142.
+PHY-1001 : End phase 3; 8.480448s wall, 9.875000s user + 0.046875s system = 9.921875s CPU (117.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.149972s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.8%)
+
+PHY-1022 : len = 2.22494e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.393094s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16804(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.317140s wall, 3.281250s user + 0.015625s system = 3.296875s CPU (99.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 495 feed throughs used by 382 nets
+PHY-1001 : End commit to database; 2.298522s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (100.6%)
+
+PHY-1001 : Current memory(MB): used = 1150, reserve = 1156, peak = 1150.
+PHY-1001 : End phase 4; 6.037019s wall, 6.015625s user + 0.015625s system = 6.031250s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.22494e+06
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1158, peak = 1152.
+PHY-1001 : End export database. 0.059784s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.5%)
+
+PHY-1001 : End detail routing; 52.356014s wall, 86.187500s user + 0.281250s system = 86.468750s CPU (165.2%)
+
+RUN-1003 : finish command "route" in 58.234591s wall, 93.015625s user + 0.312500s system = 93.328125s CPU (160.3%)
+
+RUN-1004 : used memory is 1079 MB, reserved memory is 1084 MB, peak memory is 1152 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10183 out of 19600 51.95%
+#reg 9446 out of 19600 48.19%
+#le 12418
+ #lut only 2972 out of 12418 23.93%
+ #reg only 2235 out of 12418 18.00%
+ #lut® 7211 out of 12418 58.07%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1789
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1408
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1294
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 963
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice u_bus_top/u_local_bus_slve_cis/sel23_syn_6948.q0 134
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/u_ADconfig/en_adc_cfg_all_d2_reg_syn_5.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg9_syn_158.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P172 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P112 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12418 |9156 |1027 |9480 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |541 |436 |23 |439 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |106 |90 |4 |89 |4 |0 |
+| U_ecc_gen |ecc_gen |16 |16 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |26 |26 |0 |15 |0 |0 |
+| exdev_ctl_a |exdev_ctl |764 |377 |96 |589 |0 |0 |
+| u_ADconfig |AD_config |185 |113 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |254 |137 |71 |121 |0 |0 |
+| exdev_ctl_b |exdev_ctl |730 |400 |96 |551 |0 |0 |
+| u_ADconfig |AD_config |170 |107 |25 |127 |0 |0 |
+| u_gen_sp |gen_sp |254 |166 |71 |118 |0 |0 |
+| sampling_fe_a |sampling_fe |3013 |2430 |306 |2079 |25 |0 |
+| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |175 |127 |17 |143 |0 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_sort |sort |2805 |2300 |289 |1903 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2381 |1961 |253 |1554 |22 |0 |
+| channelPart |channel_part_8478 |141 |136 |3 |128 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1888 |1538 |197 |1171 |0 |0 |
+| adc_addr_gen |adc_addr_gen |230 |201 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |9 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |25 |22 |3 |11 |0 |0 |
+| insert |insert |956 |636 |170 |667 |0 |0 |
+| ram_switch_state |ram_switch_state |702 |701 |0 |383 |0 |0 |
+| read_ram_i |read_ram |267 |214 |44 |187 |0 |0 |
+| read_ram_addr |read_ram_addr |219 |179 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |46 |33 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |321 |243 |36 |271 |3 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3228 |2493 |349 |2081 |25 |1 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |91 |17 |153 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |3013 |2389 |332 |1896 |25 |1 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2610 |2112 |290 |1553 |22 |1 |
+| channelPart |channel_part_8478 |132 |124 |3 |127 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |45 |0 |1 |
+| ram_switch |ram_switch |2024 |1658 |197 |1137 |0 |0 |
+| adc_addr_gen |adc_addr_gen |206 |179 |27 |102 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |21 |18 |3 |7 |0 |0 |
+| insert |insert |980 |641 |170 |688 |0 |0 |
+| ram_switch_state |ram_switch_state |838 |838 |0 |347 |0 |0 |
+| read_ram_i |read_ram_rev |367 |262 |81 |216 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |302 |217 |73 |169 |0 |0 |
+| read_ram_data |read_ram_data_rev |65 |45 |8 |47 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9931
+ #2 2 4260
+ #3 3 1680
+ #4 4 559
+ #5 5-10 786
+ #6 11-50 560
+ #7 51-100 9
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.098347s wall, 3.546875s user + 0.046875s system = 3.593750s CPU (171.3%)
+
+RUN-1004 : used memory is 1080 MB, reserved memory is 1085 MB, peak memory is 1152 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71696, tnet num: 17703, tinst num: 6817, tnode num: 94160, tedge num: 119082.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.675529s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (99.8%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1090 MB, peak memory is 1152 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.462348s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.4%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1094 MB, peak memory is 1152 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6817
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17881, pip num: 167402
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 495
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3234 valid insts, and 467476 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.521402s wall, 58.453125s user + 0.156250s system = 58.609375s CPU (615.6%)
+
+RUN-1004 : used memory is 1240 MB, reserved memory is 1243 MB, peak memory is 1356 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_183206.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_184041.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_184041.log
new file mode 100644
index 0000000..6592d11
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_184041.log
@@ -0,0 +1,3405 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 18:40:41 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(886)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(895)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(919)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(921)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(927)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(930)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1101)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1190)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1491)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1502)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1520)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2098)
+HDL-5007 WARNING: identifier 'a_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'b_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.231438s wall, 2.093750s user + 0.140625s system = 2.234375s CPU (100.1%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18079 instances
+RUN-0007 : 7697 luts, 9159 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20656 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13176 nets have 2 pins
+RUN-1001 : 6400 nets have [3 - 5] pins
+RUN-1001 : 658 nets have [6 - 10] pins
+RUN-1001 : 173 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1983
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18077 instances, 7697 luts, 9159 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6032 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84742, tnet num: 20478, tinst num: 18077, tnode num: 115273, tedge num: 135278.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.196582s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (99.2%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 517 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20478 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.990890s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (99.7%)
+
+PHY-3001 : Found 1243 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.17873e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18077.
+PHY-3001 : Level 1 #clusters 1969.
+PHY-3001 : End clustering; 0.139116s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (112.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28686e+06, overlap = 476.625
+PHY-3002 : Step(2): len = 1.20866e+06, overlap = 544.438
+PHY-3002 : Step(3): len = 834021, overlap = 629.812
+PHY-3002 : Step(4): len = 760711, overlap = 683.812
+PHY-3002 : Step(5): len = 586810, overlap = 824.531
+PHY-3002 : Step(6): len = 515943, overlap = 891.438
+PHY-3002 : Step(7): len = 436963, overlap = 979.656
+PHY-3002 : Step(8): len = 404544, overlap = 1041.06
+PHY-3002 : Step(9): len = 363420, overlap = 1121
+PHY-3002 : Step(10): len = 341608, overlap = 1145.59
+PHY-3002 : Step(11): len = 303189, overlap = 1193.47
+PHY-3002 : Step(12): len = 289278, overlap = 1212.78
+PHY-3002 : Step(13): len = 260556, overlap = 1268.28
+PHY-3002 : Step(14): len = 252445, overlap = 1294.84
+PHY-3002 : Step(15): len = 229752, overlap = 1325.84
+PHY-3002 : Step(16): len = 221252, overlap = 1344.62
+PHY-3002 : Step(17): len = 198378, overlap = 1368.5
+PHY-3002 : Step(18): len = 192859, overlap = 1388.06
+PHY-3002 : Step(19): len = 173298, overlap = 1414.81
+PHY-3002 : Step(20): len = 161836, overlap = 1419.09
+PHY-3002 : Step(21): len = 149581, overlap = 1427.38
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.64754e-07
+PHY-3002 : Step(22): len = 151338, overlap = 1428.12
+PHY-3002 : Step(23): len = 185071, overlap = 1326.25
+PHY-3002 : Step(24): len = 188173, overlap = 1241.19
+PHY-3002 : Step(25): len = 192815, overlap = 1192.69
+PHY-3002 : Step(26): len = 191110, overlap = 1170.84
+PHY-3002 : Step(27): len = 189644, overlap = 1129.91
+PHY-3002 : Step(28): len = 187719, overlap = 1106.38
+PHY-3002 : Step(29): len = 186314, overlap = 1105.72
+PHY-3002 : Step(30): len = 185207, overlap = 1107.25
+PHY-3002 : Step(31): len = 182671, overlap = 1107.66
+PHY-3002 : Step(32): len = 179446, overlap = 1086.91
+PHY-3002 : Step(33): len = 177073, overlap = 1089.91
+PHY-3002 : Step(34): len = 175096, overlap = 1082.41
+PHY-3002 : Step(35): len = 173967, overlap = 1088.78
+PHY-3002 : Step(36): len = 172056, overlap = 1084.75
+PHY-3002 : Step(37): len = 170822, overlap = 1081.25
+PHY-3002 : Step(38): len = 167904, overlap = 1090.53
+PHY-3002 : Step(39): len = 166883, overlap = 1097.44
+PHY-3002 : Step(40): len = 166121, overlap = 1099.28
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.92951e-06
+PHY-3002 : Step(41): len = 168834, overlap = 1089.06
+PHY-3002 : Step(42): len = 181233, overlap = 1030.44
+PHY-3002 : Step(43): len = 185770, overlap = 992.906
+PHY-3002 : Step(44): len = 189746, overlap = 954.969
+PHY-3002 : Step(45): len = 192064, overlap = 954.875
+PHY-3002 : Step(46): len = 193115, overlap = 955.125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.85902e-06
+PHY-3002 : Step(47): len = 200699, overlap = 932.969
+PHY-3002 : Step(48): len = 217973, overlap = 903.906
+PHY-3002 : Step(49): len = 225369, overlap = 877.156
+PHY-3002 : Step(50): len = 232164, overlap = 826.094
+PHY-3002 : Step(51): len = 234907, overlap = 816.875
+PHY-3002 : Step(52): len = 236743, overlap = 809.062
+PHY-3002 : Step(53): len = 236692, overlap = 805.75
+PHY-3002 : Step(54): len = 236515, overlap = 795.219
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.71803e-06
+PHY-3002 : Step(55): len = 248688, overlap = 731.438
+PHY-3002 : Step(56): len = 269495, overlap = 644.75
+PHY-3002 : Step(57): len = 279354, overlap = 614.156
+PHY-3002 : Step(58): len = 289703, overlap = 586.531
+PHY-3002 : Step(59): len = 292225, overlap = 557.531
+PHY-3002 : Step(60): len = 291308, overlap = 554.562
+PHY-3002 : Step(61): len = 288096, overlap = 544.406
+PHY-3002 : Step(62): len = 286112, overlap = 545.25
+PHY-3002 : Step(63): len = 284972, overlap = 532.75
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.54361e-05
+PHY-3002 : Step(64): len = 302299, overlap = 496.438
+PHY-3002 : Step(65): len = 317802, overlap = 443.344
+PHY-3002 : Step(66): len = 323528, overlap = 421.125
+PHY-3002 : Step(67): len = 326523, overlap = 401.062
+PHY-3002 : Step(68): len = 326538, overlap = 410.375
+PHY-3002 : Step(69): len = 327072, overlap = 397.875
+PHY-3002 : Step(70): len = 324654, overlap = 396.469
+PHY-3002 : Step(71): len = 325983, overlap = 386.625
+PHY-3002 : Step(72): len = 327280, overlap = 366.125
+PHY-3002 : Step(73): len = 327942, overlap = 361.594
+PHY-3002 : Step(74): len = 326215, overlap = 358.875
+PHY-3002 : Step(75): len = 327503, overlap = 341.625
+PHY-3002 : Step(76): len = 327574, overlap = 347.219
+PHY-3002 : Step(77): len = 328755, overlap = 349.531
+PHY-3002 : Step(78): len = 325703, overlap = 335.375
+PHY-3002 : Step(79): len = 325401, overlap = 332.188
+PHY-3002 : Step(80): len = 327480, overlap = 342.219
+PHY-3002 : Step(81): len = 329230, overlap = 343.312
+PHY-3002 : Step(82): len = 326006, overlap = 354.688
+PHY-3002 : Step(83): len = 325399, overlap = 346.625
+PHY-3002 : Step(84): len = 325012, overlap = 345.656
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.08721e-05
+PHY-3002 : Step(85): len = 339628, overlap = 340.875
+PHY-3002 : Step(86): len = 351254, overlap = 323.469
+PHY-3002 : Step(87): len = 354586, overlap = 322.75
+PHY-3002 : Step(88): len = 356567, overlap = 317.438
+PHY-3002 : Step(89): len = 356448, overlap = 308.938
+PHY-3002 : Step(90): len = 359245, overlap = 286.594
+PHY-3002 : Step(91): len = 358001, overlap = 307.688
+PHY-3002 : Step(92): len = 358354, overlap = 319.156
+PHY-3002 : Step(93): len = 358493, overlap = 307.938
+PHY-3002 : Step(94): len = 358428, overlap = 310.344
+PHY-3002 : Step(95): len = 357788, overlap = 304.406
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.10577e-05
+PHY-3002 : Step(96): len = 374315, overlap = 284.719
+PHY-3002 : Step(97): len = 387182, overlap = 276.531
+PHY-3002 : Step(98): len = 387207, overlap = 274.188
+PHY-3002 : Step(99): len = 392042, overlap = 253.719
+PHY-3002 : Step(100): len = 397293, overlap = 250.281
+PHY-3002 : Step(101): len = 399808, overlap = 243.844
+PHY-3002 : Step(102): len = 393592, overlap = 235.344
+PHY-3002 : Step(103): len = 392762, overlap = 225.031
+PHY-3002 : Step(104): len = 394712, overlap = 241.969
+PHY-3002 : Step(105): len = 397254, overlap = 235.281
+PHY-3002 : Step(106): len = 393243, overlap = 243.062
+PHY-3002 : Step(107): len = 393680, overlap = 241.344
+PHY-3002 : Step(108): len = 395334, overlap = 246.062
+PHY-3002 : Step(109): len = 396424, overlap = 241.188
+PHY-3002 : Step(110): len = 394264, overlap = 238.406
+PHY-3002 : Step(111): len = 394360, overlap = 241.5
+PHY-3002 : Step(112): len = 395229, overlap = 232.531
+PHY-3002 : Step(113): len = 397218, overlap = 233.531
+PHY-3002 : Step(114): len = 395544, overlap = 239.25
+PHY-3002 : Step(115): len = 395978, overlap = 239
+PHY-3002 : Step(116): len = 397482, overlap = 238.375
+PHY-3002 : Step(117): len = 399327, overlap = 246.719
+PHY-3002 : Step(118): len = 396650, overlap = 244.344
+PHY-3002 : Step(119): len = 396238, overlap = 242
+PHY-3002 : Step(120): len = 397166, overlap = 235.781
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000122115
+PHY-3002 : Step(121): len = 411578, overlap = 227.688
+PHY-3002 : Step(122): len = 420865, overlap = 211
+PHY-3002 : Step(123): len = 420399, overlap = 211.625
+PHY-3002 : Step(124): len = 424547, overlap = 209.781
+PHY-3002 : Step(125): len = 430534, overlap = 209.438
+PHY-3002 : Step(126): len = 435154, overlap = 211.156
+PHY-3002 : Step(127): len = 433520, overlap = 210.094
+PHY-3002 : Step(128): len = 433773, overlap = 224.875
+PHY-3002 : Step(129): len = 435171, overlap = 220.781
+PHY-3002 : Step(130): len = 436759, overlap = 210.25
+PHY-3002 : Step(131): len = 434542, overlap = 202.781
+PHY-3002 : Step(132): len = 435196, overlap = 203.281
+PHY-3002 : Step(133): len = 435748, overlap = 202.406
+PHY-3002 : Step(134): len = 435636, overlap = 193.438
+PHY-3002 : Step(135): len = 434199, overlap = 196.406
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00023232
+PHY-3002 : Step(136): len = 442724, overlap = 190.625
+PHY-3002 : Step(137): len = 449166, overlap = 188.25
+PHY-3002 : Step(138): len = 449569, overlap = 183.688
+PHY-3002 : Step(139): len = 450830, overlap = 176.594
+PHY-3002 : Step(140): len = 453926, overlap = 169.344
+PHY-3002 : Step(141): len = 456340, overlap = 172.375
+PHY-3002 : Step(142): len = 455532, overlap = 171.906
+PHY-3002 : Step(143): len = 456211, overlap = 167.219
+PHY-3002 : Step(144): len = 458043, overlap = 161.219
+PHY-3002 : Step(145): len = 459207, overlap = 162.188
+PHY-3002 : Step(146): len = 458052, overlap = 173.375
+PHY-3002 : Step(147): len = 458434, overlap = 178.469
+PHY-3002 : Step(148): len = 460057, overlap = 164.469
+PHY-3002 : Step(149): len = 460997, overlap = 162.094
+PHY-3002 : Step(150): len = 460059, overlap = 170.719
+PHY-3002 : Step(151): len = 459939, overlap = 171.906
+PHY-3002 : Step(152): len = 461008, overlap = 168.438
+PHY-3002 : Step(153): len = 461418, overlap = 168.688
+PHY-3002 : Step(154): len = 460467, overlap = 172.469
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000431881
+PHY-3002 : Step(155): len = 467751, overlap = 165.625
+PHY-3002 : Step(156): len = 476387, overlap = 167.312
+PHY-3002 : Step(157): len = 478471, overlap = 161.281
+PHY-3002 : Step(158): len = 479975, overlap = 161.188
+PHY-3002 : Step(159): len = 482312, overlap = 158.156
+PHY-3002 : Step(160): len = 482946, overlap = 151.969
+PHY-3002 : Step(161): len = 481144, overlap = 154.969
+PHY-3002 : Step(162): len = 481043, overlap = 154.031
+PHY-3002 : Step(163): len = 483710, overlap = 157.406
+PHY-3002 : Step(164): len = 486126, overlap = 153.219
+PHY-3002 : Step(165): len = 485609, overlap = 160.344
+PHY-3002 : Step(166): len = 485884, overlap = 162.75
+PHY-3002 : Step(167): len = 486981, overlap = 158.719
+PHY-3002 : Step(168): len = 487362, overlap = 159.969
+PHY-3002 : Step(169): len = 486242, overlap = 166.719
+PHY-3002 : Step(170): len = 485996, overlap = 169.719
+PHY-3002 : Step(171): len = 486556, overlap = 164.875
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000863763
+PHY-3002 : Step(172): len = 493242, overlap = 156.906
+PHY-3002 : Step(173): len = 501828, overlap = 145.219
+PHY-3002 : Step(174): len = 504604, overlap = 141.969
+PHY-3002 : Step(175): len = 507258, overlap = 150.125
+PHY-3002 : Step(176): len = 510037, overlap = 143
+PHY-3002 : Step(177): len = 511304, overlap = 143.062
+PHY-3002 : Step(178): len = 510059, overlap = 137.188
+PHY-3002 : Step(179): len = 509700, overlap = 140.062
+PHY-3002 : Step(180): len = 511122, overlap = 142.844
+PHY-3002 : Step(181): len = 511843, overlap = 146.906
+PHY-3002 : Step(182): len = 510874, overlap = 147.688
+PHY-3002 : Step(183): len = 510598, overlap = 151.156
+PHY-3002 : Step(184): len = 511215, overlap = 150.938
+PHY-3002 : Step(185): len = 511334, overlap = 148.844
+PHY-3002 : Step(186): len = 510973, overlap = 151.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012259s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (127.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20656.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 716648, over cnt = 1652(4%), over = 7055, worst = 28
+PHY-1001 : End global iterations; 0.697989s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (127.6%)
+
+PHY-1001 : Congestion index: top1 = 75.50, top5 = 60.34, top10 = 52.08, top15 = 46.80.
+PHY-3001 : End congestion estimation; 0.943033s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (119.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20478 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.920773s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00016429
+PHY-3002 : Step(187): len = 651447, overlap = 86.0938
+PHY-3002 : Step(188): len = 656585, overlap = 80.6875
+PHY-3002 : Step(189): len = 655217, overlap = 75.2812
+PHY-3002 : Step(190): len = 655370, overlap = 66.2188
+PHY-3002 : Step(191): len = 654035, overlap = 66.5312
+PHY-3002 : Step(192): len = 651402, overlap = 61.4062
+PHY-3002 : Step(193): len = 648788, overlap = 54.9062
+PHY-3002 : Step(194): len = 646455, overlap = 49.7812
+PHY-3002 : Step(195): len = 644579, overlap = 47.9062
+PHY-3002 : Step(196): len = 643931, overlap = 45.0625
+PHY-3002 : Step(197): len = 642460, overlap = 41.1562
+PHY-3002 : Step(198): len = 642860, overlap = 40.6562
+PHY-3002 : Step(199): len = 639589, overlap = 41.1562
+PHY-3002 : Step(200): len = 639001, overlap = 39.875
+PHY-3002 : Step(201): len = 637141, overlap = 35.7812
+PHY-3002 : Step(202): len = 634990, overlap = 33.375
+PHY-3002 : Step(203): len = 635163, overlap = 32.125
+PHY-3002 : Step(204): len = 634152, overlap = 30.25
+PHY-3002 : Step(205): len = 634578, overlap = 29.375
+PHY-3002 : Step(206): len = 631942, overlap = 28.0938
+PHY-3002 : Step(207): len = 630970, overlap = 26.2188
+PHY-3002 : Step(208): len = 630416, overlap = 24.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00032858
+PHY-3002 : Step(209): len = 633178, overlap = 23.1875
+PHY-3002 : Step(210): len = 634923, overlap = 22.75
+PHY-3002 : Step(211): len = 639628, overlap = 21.8125
+PHY-3002 : Step(212): len = 646019, overlap = 19.625
+PHY-3002 : Step(213): len = 659151, overlap = 21.25
+PHY-3002 : Step(214): len = 656537, overlap = 20.2812
+PHY-3002 : Step(215): len = 655499, overlap = 21.875
+PHY-3002 : Step(216): len = 651022, overlap = 18.1562
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00065716
+PHY-3002 : Step(217): len = 659214, overlap = 21.8438
+PHY-3002 : Step(218): len = 667108, overlap = 20.8125
+PHY-3002 : Step(219): len = 679138, overlap = 21.5312
+PHY-3002 : Step(220): len = 691596, overlap = 22.7812
+PHY-3002 : Step(221): len = 691625, overlap = 22.7188
+PHY-3002 : Step(222): len = 690084, overlap = 20.9062
+PHY-3002 : Step(223): len = 689023, overlap = 21.2812
+PHY-3002 : Step(224): len = 688153, overlap = 20.5938
+PHY-3002 : Step(225): len = 688071, overlap = 20.3125
+PHY-3002 : Step(226): len = 688281, overlap = 21.2812
+PHY-3002 : Step(227): len = 689618, overlap = 23.4062
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00131432
+PHY-3002 : Step(228): len = 690593, overlap = 21.1562
+PHY-3002 : Step(229): len = 696555, overlap = 21.0938
+PHY-3002 : Step(230): len = 703832, overlap = 22.4375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00228519
+PHY-3002 : Step(231): len = 708148, overlap = 22.6562
+PHY-3002 : Step(232): len = 718482, overlap = 21.9062
+PHY-3002 : Step(233): len = 732368, overlap = 26.9062
+PHY-3002 : Step(234): len = 735217, overlap = 28.4375
+PHY-3002 : Step(235): len = 735323, overlap = 24.875
+PHY-3002 : Step(236): len = 734845, overlap = 24.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 38/20656.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 830760, over cnt = 2921(8%), over = 12896, worst = 35
+PHY-1001 : End global iterations; 1.812325s wall, 2.468750s user + 0.078125s system = 2.546875s CPU (140.5%)
+
+PHY-1001 : Congestion index: top1 = 84.05, top5 = 69.09, top10 = 60.50, top15 = 55.57.
+PHY-3001 : End congestion estimation; 2.116331s wall, 2.781250s user + 0.078125s system = 2.859375s CPU (135.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20478 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.914234s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000157441
+PHY-3002 : Step(237): len = 718830, overlap = 193.156
+PHY-3002 : Step(238): len = 706721, overlap = 157.906
+PHY-3002 : Step(239): len = 692166, overlap = 142.812
+PHY-3002 : Step(240): len = 681091, overlap = 134.031
+PHY-3002 : Step(241): len = 671643, overlap = 114.281
+PHY-3002 : Step(242): len = 665083, overlap = 108.438
+PHY-3002 : Step(243): len = 658896, overlap = 103.688
+PHY-3002 : Step(244): len = 655330, overlap = 106.125
+PHY-3002 : Step(245): len = 651766, overlap = 104
+PHY-3002 : Step(246): len = 648510, overlap = 108.094
+PHY-3002 : Step(247): len = 643083, overlap = 105.438
+PHY-3002 : Step(248): len = 639848, overlap = 106.906
+PHY-3002 : Step(249): len = 635249, overlap = 106.875
+PHY-3002 : Step(250): len = 631785, overlap = 101
+PHY-3002 : Step(251): len = 630818, overlap = 102.781
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000314881
+PHY-3002 : Step(252): len = 633378, overlap = 95.5
+PHY-3002 : Step(253): len = 635560, overlap = 94.5
+PHY-3002 : Step(254): len = 636236, overlap = 94.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000629762
+PHY-3002 : Step(255): len = 642086, overlap = 89.875
+PHY-3002 : Step(256): len = 648378, overlap = 88.5938
+PHY-3002 : Step(257): len = 650354, overlap = 85.7812
+PHY-3002 : Step(258): len = 649995, overlap = 80.9062
+PHY-3002 : Step(259): len = 650628, overlap = 75.7812
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00105096
+PHY-3002 : Step(260): len = 652943, overlap = 75.0625
+PHY-3002 : Step(261): len = 656485, overlap = 71.5938
+PHY-3002 : Step(262): len = 658649, overlap = 71.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00177331
+PHY-3002 : Step(263): len = 658895, overlap = 72.4688
+PHY-3002 : Step(264): len = 662460, overlap = 69.2188
+PHY-3002 : Step(265): len = 674923, overlap = 62.9375
+PHY-3002 : Step(266): len = 679627, overlap = 63.9688
+PHY-3002 : Step(267): len = 680474, overlap = 61.4375
+PHY-3002 : Step(268): len = 681362, overlap = 61.9375
+PHY-3002 : Step(269): len = 681779, overlap = 66.5
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84742, tnet num: 20478, tinst num: 18077, tnode num: 115273, tedge num: 135278.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.453012s wall, 1.390625s user + 0.062500s system = 1.453125s CPU (100.0%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 566 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 380.66 peak overflow 4.25
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 683/20656.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 789376, over cnt = 3165(8%), over = 11223, worst = 23
+PHY-1001 : End global iterations; 1.332905s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (147.7%)
+
+PHY-1001 : Congestion index: top1 = 74.70, top5 = 60.65, top10 = 54.06, top15 = 49.78.
+PHY-1001 : End incremental global routing; 1.688454s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (137.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20478 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.936245s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.1%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17948 has valid locations, 318 needs to be replaced
+PHY-3001 : design contains 18351 instances, 7796 luts, 9334 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6149 pins
+PHY-3001 : Found 1251 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 705946
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17313/20930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 804296, over cnt = 3187(9%), over = 11299, worst = 22
+PHY-1001 : End global iterations; 0.256005s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (109.9%)
+
+PHY-1001 : Congestion index: top1 = 74.35, top5 = 60.46, top10 = 54.21, top15 = 49.99.
+PHY-3001 : End congestion estimation; 0.606048s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (105.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85840, tnet num: 20752, tinst num: 18351, tnode num: 116913, tedge num: 136926.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.494919s wall, 1.468750s user + 0.031250s system = 1.500000s CPU (100.3%)
+
+RUN-1004 : used memory is 635 MB, reserved memory is 640 MB, peak memory is 717 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.831189s wall, 2.796875s user + 0.031250s system = 2.828125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 704869, overlap = 0
+PHY-3002 : Step(271): len = 704482, overlap = 0
+PHY-3002 : Step(272): len = 704208, overlap = 0
+PHY-3002 : Step(273): len = 703901, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17388/20930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 800912, over cnt = 3181(9%), over = 11342, worst = 23
+PHY-1001 : End global iterations; 0.215391s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (130.6%)
+
+PHY-1001 : Congestion index: top1 = 74.63, top5 = 60.83, top10 = 54.51, top15 = 50.25.
+PHY-3001 : End congestion estimation; 0.482549s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (113.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.996321s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000357686
+PHY-3002 : Step(274): len = 703838, overlap = 68.625
+PHY-3002 : Step(275): len = 703917, overlap = 68.4688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000715373
+PHY-3002 : Step(276): len = 703854, overlap = 68.5625
+PHY-3002 : Step(277): len = 704280, overlap = 68.4062
+PHY-3001 : Final: Len = 704280, Over = 68.4062
+PHY-3001 : End incremental placement; 5.632970s wall, 5.796875s user + 0.187500s system = 5.984375s CPU (106.2%)
+
+OPT-1001 : Total overflow 386.47 peak overflow 4.25
+OPT-1001 : End high-fanout net optimization; 8.788166s wall, 9.687500s user + 0.218750s system = 9.906250s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 714, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17364/20930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 804392, over cnt = 3153(8%), over = 10267, worst = 23
+PHY-1002 : len = 860304, over cnt = 1976(5%), over = 4664, worst = 19
+PHY-1002 : len = 905440, over cnt = 625(1%), over = 1185, worst = 14
+PHY-1002 : len = 916680, over cnt = 211(0%), over = 415, worst = 14
+PHY-1002 : len = 924064, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.026125s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (140.4%)
+
+PHY-1001 : Congestion index: top1 = 62.91, top5 = 53.24, top10 = 48.85, top15 = 46.13.
+OPT-1001 : End congestion update; 2.294425s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (136.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.807566s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (98.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 110 cells processed and 13100 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 38 cells processed and 2900 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 25 cells processed and 2850 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 5: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 250 slack improved
+OPT-1001 : End bottleneck based optimization; 3.590969s wall, 4.406250s user + 0.015625s system = 4.421875s CPU (123.1%)
+
+OPT-1001 : Current memory(MB): used = 714, reserve = 709, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17410/20932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924168, over cnt = 77(0%), over = 107, worst = 4
+PHY-1002 : len = 924048, over cnt = 49(0%), over = 69, worst = 4
+PHY-1002 : len = 924416, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 924536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.535992s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (102.0%)
+
+PHY-1001 : Congestion index: top1 = 62.65, top5 = 52.95, top10 = 48.68, top15 = 46.04.
+OPT-1001 : End congestion update; 0.801328s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779597s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 20 cells processed and 3700 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.696945s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (99.4%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 708, peak = 738.
+OPT-1001 : End physical optimization; 15.825568s wall, 17.578125s user + 0.296875s system = 17.875000s CPU (113.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7796 LUT to BLE ...
+SYN-4008 : Packed 7796 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6189 remaining SEQ's ...
+SYN-4005 : Packed 4232 SEQ with LUT/SLICE
+SYN-4006 : 714 single LUT's are left
+SYN-4006 : 1957 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9753/13520 primitive instances ...
+PHY-3001 : End packing; 1.632557s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6703 instances
+RUN-1001 : 3277 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17924 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10019 nets have 2 pins
+RUN-1001 : 6492 nets have [3 - 5] pins
+RUN-1001 : 768 nets have [6 - 10] pins
+RUN-1001 : 316 nets have [11 - 20] pins
+RUN-1001 : 297 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6701 instances, 6555 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3569 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 711292, Over = 205
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7625/17924.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 868400, over cnt = 2126(6%), over = 3490, worst = 8
+PHY-1002 : len = 877080, over cnt = 1403(3%), over = 1999, worst = 8
+PHY-1002 : len = 892520, over cnt = 482(1%), over = 655, worst = 6
+PHY-1002 : len = 899784, over cnt = 132(0%), over = 174, worst = 5
+PHY-1002 : len = 903608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.701421s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (141.4%)
+
+PHY-1001 : Congestion index: top1 = 61.27, top5 = 52.57, top10 = 48.28, top15 = 45.56.
+PHY-3001 : End congestion estimation; 2.104875s wall, 2.765625s user + 0.031250s system = 2.796875s CPU (132.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72190, tnet num: 17746, tinst num: 6701, tnode num: 94734, tedge num: 120183.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.604354s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (100.3%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 622 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17746 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.475496s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.0092e-05
+PHY-3002 : Step(278): len = 695778, overlap = 207.25
+PHY-3002 : Step(279): len = 687617, overlap = 199.5
+PHY-3002 : Step(280): len = 682116, overlap = 201
+PHY-3002 : Step(281): len = 678240, overlap = 206.25
+PHY-3002 : Step(282): len = 674833, overlap = 207.75
+PHY-3002 : Step(283): len = 670980, overlap = 206.75
+PHY-3002 : Step(284): len = 667790, overlap = 205.5
+PHY-3002 : Step(285): len = 665316, overlap = 210.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000120184
+PHY-3002 : Step(286): len = 669598, overlap = 200.25
+PHY-3002 : Step(287): len = 673360, overlap = 193.5
+PHY-3002 : Step(288): len = 672643, overlap = 188.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000240368
+PHY-3002 : Step(289): len = 677907, overlap = 181.5
+PHY-3002 : Step(290): len = 685411, overlap = 169.25
+PHY-3002 : Step(291): len = 685582, overlap = 171.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.407658s wall, 0.390625s user + 0.765625s system = 1.156250s CPU (283.6%)
+
+PHY-3001 : Trial Legalized: Len = 760970
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 783/17924.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879080, over cnt = 2718(7%), over = 4551, worst = 7
+PHY-1002 : len = 898640, over cnt = 1461(4%), over = 2112, worst = 6
+PHY-1002 : len = 912664, over cnt = 703(1%), over = 1003, worst = 6
+PHY-1002 : len = 926728, over cnt = 128(0%), over = 163, worst = 6
+PHY-1002 : len = 929608, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.614539s wall, 3.656250s user + 0.015625s system = 3.671875s CPU (140.4%)
+
+PHY-1001 : Congestion index: top1 = 57.54, top5 = 51.16, top10 = 47.96, top15 = 45.83.
+PHY-3001 : End congestion estimation; 3.079324s wall, 4.125000s user + 0.015625s system = 4.140625s CPU (134.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17746 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.830006s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000163208
+PHY-3002 : Step(292): len = 733801, overlap = 38.75
+PHY-3002 : Step(293): len = 719002, overlap = 61
+PHY-3002 : Step(294): len = 707459, overlap = 81.25
+PHY-3002 : Step(295): len = 699984, overlap = 93.75
+PHY-3002 : Step(296): len = 694765, overlap = 112
+PHY-3002 : Step(297): len = 693031, overlap = 117
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000326417
+PHY-3002 : Step(298): len = 697794, overlap = 111.5
+PHY-3002 : Step(299): len = 701577, overlap = 108.75
+PHY-3002 : Step(300): len = 701287, overlap = 111.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000652834
+PHY-3002 : Step(301): len = 704516, overlap = 111
+PHY-3002 : Step(302): len = 711293, overlap = 109.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.030312s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (103.1%)
+
+PHY-3001 : Legalized: Len = 737191, Over = 0
+PHY-3001 : Spreading special nets. 494 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.099762s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (109.6%)
+
+PHY-3001 : 718 instances has been re-located, deltaX = 210, deltaY = 426, maxDist = 3.
+PHY-3001 : Final: Len = 750201, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72190, tnet num: 17746, tinst num: 6704, tnode num: 94734, tedge num: 120183.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.861977s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.9%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 656 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4553/17924.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 884328, over cnt = 2503(7%), over = 4008, worst = 8
+PHY-1002 : len = 897760, over cnt = 1490(4%), over = 2103, worst = 6
+PHY-1002 : len = 911848, over cnt = 686(1%), over = 976, worst = 5
+PHY-1002 : len = 918360, over cnt = 401(1%), over = 581, worst = 5
+PHY-1002 : len = 928400, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.046457s wall, 2.953125s user + 0.031250s system = 2.984375s CPU (145.8%)
+
+PHY-1001 : Congestion index: top1 = 57.46, top5 = 50.78, top10 = 47.33, top15 = 45.13.
+PHY-1001 : End incremental global routing; 2.431882s wall, 3.343750s user + 0.031250s system = 3.375000s CPU (138.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17746 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.860743s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6612 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6721 instances, 6572 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3642 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 753309
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16334/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 931752, over cnt = 80(0%), over = 88, worst = 3
+PHY-1002 : len = 931832, over cnt = 29(0%), over = 29, worst = 1
+PHY-1002 : len = 932056, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 932216, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 932232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.802950s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (109.0%)
+
+PHY-1001 : Congestion index: top1 = 57.41, top5 = 50.80, top10 = 47.42, top15 = 45.23.
+PHY-3001 : End congestion estimation; 1.112171s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (105.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72342, tnet num: 17770, tinst num: 6721, tnode num: 94920, tedge num: 120391.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.811123s wall, 1.781250s user + 0.031250s system = 1.812500s CPU (100.1%)
+
+RUN-1004 : used memory is 650 MB, reserved memory is 646 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.704002s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(303): len = 752726, overlap = 0
+PHY-3002 : Step(304): len = 752146, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16323/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930568, over cnt = 60(0%), over = 71, worst = 4
+PHY-1002 : len = 930752, over cnt = 29(0%), over = 32, worst = 2
+PHY-1002 : len = 931024, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 931080, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 931136, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.761325s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 50.72, top10 = 47.31, top15 = 45.15.
+PHY-3001 : End congestion estimation; 1.074906s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (98.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.881374s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000323202
+PHY-3002 : Step(305): len = 752155, overlap = 1.5
+PHY-3002 : Step(306): len = 752171, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006086s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 752146, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058800s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.3%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 2, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 752292, Over = 0
+PHY-3001 : End incremental placement; 6.247432s wall, 6.234375s user + 0.156250s system = 6.390625s CPU (102.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.024183s wall, 11.031250s user + 0.187500s system = 11.218750s CPU (111.9%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16292/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930952, over cnt = 73(0%), over = 83, worst = 2
+PHY-1002 : len = 931168, over cnt = 28(0%), over = 30, worst = 2
+PHY-1002 : len = 931416, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 931488, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.630420s wall, 0.656250s user + 0.015625s system = 0.671875s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 57.18, top5 = 50.69, top10 = 47.28, top15 = 45.12.
+OPT-1001 : End congestion update; 0.943555s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (104.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.864429s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.4%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6633 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6721 instances, 6572 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3642 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 759532, Over = 0
+PHY-3001 : Spreading special nets. 32 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062408s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-3001 : 44 instances has been re-located, deltaX = 22, deltaY = 33, maxDist = 2.
+PHY-3001 : Final: Len = 760452, Over = 0
+PHY-3001 : End incremental legalization; 0.376084s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 56 cells processed and 20924 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6633 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6721 instances, 6572 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3642 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 760516, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058981s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.0%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 5, deltaY = 16, maxDist = 2.
+PHY-3001 : Final: Len = 760758, Over = 0
+PHY-3001 : End incremental legalization; 0.381394s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.4%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 1032 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3644 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 762122, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059224s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.5%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 9, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 762360, Over = 0
+PHY-3001 : End incremental legalization; 0.374348s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (108.5%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 1100 slack improved
+OPT-1001 : End bottleneck based optimization; 3.383415s wall, 3.640625s user + 0.031250s system = 3.671875s CPU (108.5%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15908/17953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 941960, over cnt = 189(0%), over = 232, worst = 6
+PHY-1002 : len = 942304, over cnt = 102(0%), over = 107, worst = 2
+PHY-1002 : len = 942872, over cnt = 51(0%), over = 54, worst = 2
+PHY-1002 : len = 943328, over cnt = 19(0%), over = 21, worst = 2
+PHY-1002 : len = 943760, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.856630s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (104.0%)
+
+PHY-1001 : Congestion index: top1 = 56.77, top5 = 50.58, top10 = 47.26, top15 = 45.15.
+OPT-1001 : End congestion update; 1.176279s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.715259s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.3%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3644 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 762962, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059093s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.8%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 1.
+PHY-3001 : Final: Len = 763300, Over = 0
+PHY-3001 : End incremental legalization; 0.380397s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (123.2%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 1600 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.401830s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (104.7%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 738.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.715807s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16258/17953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944136, over cnt = 77(0%), over = 86, worst = 3
+PHY-1002 : len = 944120, over cnt = 44(0%), over = 47, worst = 3
+PHY-1002 : len = 944504, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 944568, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 944808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.806377s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (104.6%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 50.63, top10 = 47.38, top15 = 45.23.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.715046s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.620690
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3644 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 763300, Over = 0
+PHY-3001 : End spreading; 0.058080s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.6%)
+
+PHY-3001 : Final: Len = 763300, Over = 0
+PHY-3001 : End incremental legalization; 0.377373s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.730318s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.4%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16345/17953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136790s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.4%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 50.63, top10 = 47.38, top15 = 45.23.
+OPT-1001 : End congestion update; 0.462611s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.705578s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3644 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 763266, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057994s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.8%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 763284, Over = 0
+PHY-3001 : End incremental legalization; 0.403069s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.677789s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.6%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 729, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16339/17953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944760, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 944792, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 944800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.414257s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.1%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 50.63, top10 = 47.38, top15 = 45.23.
+OPT-1001 : End congestion update; 0.722846s wall, 0.703125s user + 0.015625s system = 0.718750s CPU (99.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.704442s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.8%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3644 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 763242, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057262s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.9%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 763284, Over = 0
+PHY-3001 : End incremental legalization; 0.365316s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3644 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 763242, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057035s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 763284, Over = 0
+PHY-3001 : End incremental legalization; 0.366941s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (102.2%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.434384s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (99.5%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 738.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701960s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 738.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.705074s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.9%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16345/17953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 944800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.129267s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.7%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 50.63, top10 = 47.38, top15 = 45.23.
+RUN-1001 : End congestion update; 0.437204s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.145420s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.9%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 729, peak = 738.
+OPT-1001 : End physical optimization; 27.667521s wall, 29.140625s user + 0.250000s system = 29.390625s CPU (106.2%)
+
+RUN-1003 : finish command "place" in 74.262609s wall, 108.171875s user + 6.515625s system = 114.687500s CPU (154.4%)
+
+RUN-1004 : used memory is 678 MB, reserved memory is 690 MB, peak memory is 738 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.665932s wall, 2.859375s user + 0.031250s system = 2.890625s CPU (173.5%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 691 MB, peak memory is 738 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6735 instances
+RUN-1001 : 3289 mslices, 3295 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17953 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10007 nets have 2 pins
+RUN-1001 : 6503 nets have [3 - 5] pins
+RUN-1001 : 789 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 309 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72450, tnet num: 17775, tinst num: 6733, tnode num: 95066, tedge num: 120545.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.575459s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.2%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 660 MB, peak memory is 738 MB
+PHY-1001 : 3289 mslices, 3295 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 873016, over cnt = 2753(7%), over = 4476, worst = 9
+PHY-1002 : len = 889488, over cnt = 1684(4%), over = 2459, worst = 7
+PHY-1002 : len = 910280, over cnt = 622(1%), over = 859, worst = 5
+PHY-1002 : len = 924336, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 924456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.151170s wall, 4.203125s user + 0.031250s system = 4.234375s CPU (134.4%)
+
+PHY-1001 : Congestion index: top1 = 56.38, top5 = 50.40, top10 = 47.08, top15 = 44.86.
+PHY-1001 : End global routing; 3.474205s wall, 4.515625s user + 0.031250s system = 4.546875s CPU (130.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 712, reserve = 714, peak = 738.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 985, reserve = 988, peak = 985.
+PHY-1001 : End build detailed router design. 3.963612s wall, 3.875000s user + 0.062500s system = 3.937500s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 278456, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.908810s wall, 4.906250s user + 0.000000s system = 4.906250s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 278512, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.418490s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.1%)
+
+PHY-1001 : Current memory(MB): used = 1020, reserve = 1024, peak = 1020.
+PHY-1001 : End phase 1; 5.339223s wall, 5.328125s user + 0.000000s system = 5.328125s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.36425e+06, over cnt = 1592(0%), over = 1600, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1039, peak = 1036.
+PHY-1001 : End initial routed; 34.581009s wall, 67.984375s user + 0.218750s system = 68.203125s CPU (197.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 3/16876(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.811 | -0.839 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.307606s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1051, peak = 1047.
+PHY-1001 : End phase 2; 37.888683s wall, 71.265625s user + 0.218750s system = 71.484375s CPU (188.7%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.141738s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.2%)
+
+PHY-1022 : len = 2.36428e+06, over cnt = 1596(0%), over = 1604, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.402552s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33822e+06, over cnt = 648(0%), over = 648, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.445359s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (163.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33589e+06, over cnt = 110(0%), over = 110, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.727175s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (159.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33604e+06, over cnt = 14(0%), over = 14, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.496855s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (113.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33611e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.287219s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (103.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.200728s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.243097s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.351085s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.174578s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.179391s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.204765s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (91.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.230529s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.333763s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (98.3%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.175434s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.176205s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (133.0%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.198818s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.3%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.226719s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (124.1%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.313289s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.365385s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.4%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.175437s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (124.7%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.181775s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.1%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.203448s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.237913s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.310508s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.387425s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.201991s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.169361s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.169392s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.2%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.196665s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (119.2%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.224446s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.303505s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.338819s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.057704s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.146252s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.169100s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.4%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.171162s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.199247s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (109.8%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.224671s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.305662s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.339419s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.059337s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.067939s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.067981s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.171091s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.172947s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.219047s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.254097s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.363260s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.346197s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.086182s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.075187s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.104883s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.201589s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.173514s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.174609s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.202606s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.234771s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.355836s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.352053s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.147396s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.094995s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.336879s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.153635s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.059751s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.167674s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.169617s wall, 0.187500s user + 0.031250s system = 0.218750s CPU (129.0%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.197510s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.224143s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.302627s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.342871s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.066626s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.176707s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.184672s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.087464s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.161556s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.354732s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (100.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16876(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.230144s wall, 3.203125s user + 0.015625s system = 3.218750s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1057, reserve = 1060, peak = 1057.
+PHY-1001 : End phase 3; 43.044101s wall, 44.500000s user + 0.109375s system = 44.609375s CPU (103.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135866s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.5%)
+
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.375930s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.805ns, -0.805ns, 1}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.181517s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.191201s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.236285s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.170792s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 5 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.172961s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.204366s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.245552s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.315735s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 9 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.177024s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (105.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.181039s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.194824s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.227915s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.300027s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.350458s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (98.1%)
+
+PHY-1001 : ===== DR Iter 15 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.175317s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.9%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.177145s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.202299s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.642613s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.749930s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.865446s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 1.096501s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 22 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.165820s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.183999s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.203192s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.223967s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.303869s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.343706s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 1.140696s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 1.300158s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 30 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.167619s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.2%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.177416s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (88.1%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.211303s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.247425s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.327688s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.347497s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (103.4%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 1.196323s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 1.176604s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.339153s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 39 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.174357s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.5%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.180573s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.2%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.219205s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.246928s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.311763s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.342557s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 1.113878s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.133363s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.069829s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.060098s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 49 =====
+PHY-1022 : len = 2.33622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.178085s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.177137s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.199276s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.228940s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.311997s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.356744s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 1.078194s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 1.256909s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.133731s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.115771s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.124461s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 60 =====
+PHY-1022 : len = 2.33618e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.168624s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.169929s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (128.7%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.197593s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.223196s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (112.0%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.298582s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.341955s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 1.121060s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 1.110563s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.129240s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.181337s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.297783s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.103890s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16876(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.281100s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1059, reserve = 1062, peak = 1059.
+PHY-1001 : End phase 4; 41.229411s wall, 41.234375s user + 0.046875s system = 41.281250s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.33617e+06
+PHY-1001 : 508 feed throughs used by 390 nets
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1160, peak = 1154.
+PHY-1001 : End export database. 2.340501s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (100.1%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6735 instances
+RUN-1001 : 3289 mslices, 3295 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17953 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10007 nets have 2 pins
+RUN-1001 : 6503 nets have [3 - 5] pins
+RUN-1001 : 789 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 309 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 4 1) is for feedthrough
+PHY-3001 : eco cells: (1 53 3) is for feedthrough
+PHY-3001 : eco cells: (1 54 3) is for feedthrough
+PHY-3001 : eco cells: (2 8 0) is for feedthrough
+PHY-3001 : eco cells: (2 8 2) is for feedthrough
+PHY-3001 : eco cells: (2 12 2) is for feedthrough
+PHY-3001 : eco cells: (2 21 0) is for feedthrough
+PHY-3001 : eco cells: (2 44 0) is for feedthrough
+PHY-3001 : eco cells: (2 54 3) is for feedthrough
+PHY-3001 : eco cells: (3 8 0) is for feedthrough
+PHY-3001 : eco cells: (3 9 3) is for feedthrough
+PHY-3001 : eco cells: (3 12 3) is for feedthrough
+PHY-3001 : eco cells: (3 13 1) is for feedthrough
+PHY-3001 : eco cells: (3 14 3) is for feedthrough
+PHY-3001 : eco cells: (3 19 1) is for feedthrough
+PHY-3001 : eco cells: (3 21 1) is for feedthrough
+PHY-3001 : eco cells: (3 30 0) is for feedthrough
+PHY-3001 : eco cells: (3 37 0) is for feedthrough
+PHY-3001 : eco cells: (3 42 3) is for feedthrough
+PHY-3001 : eco cells: (3 46 3) is for feedthrough
+PHY-3001 : eco cells: (3 47 1) is for feedthrough
+PHY-3001 : eco cells: (3 49 0) is for feedthrough
+PHY-3001 : eco cells: (3 51 3) is for feedthrough
+PHY-3001 : eco cells: (4 2 2) is for feedthrough
+PHY-3001 : eco cells: (4 4 2) is for feedthrough
+PHY-3001 : eco cells: (4 8 3) is for feedthrough
+PHY-3001 : eco cells: (4 12 2) is for feedthrough
+PHY-3001 : eco cells: (4 19 1) is for feedthrough
+PHY-3001 : eco cells: (4 25 3) is for feedthrough
+PHY-3001 : eco cells: (4 29 2) is for feedthrough
+PHY-3001 : eco cells: (4 33 0) is for feedthrough
+PHY-3001 : eco cells: (4 33 2) is for feedthrough
+PHY-3001 : eco cells: (4 34 1) is for feedthrough
+PHY-3001 : eco cells: (4 35 2) is for feedthrough
+PHY-3001 : eco cells: (4 37 3) is for feedthrough
+PHY-3001 : eco cells: (4 43 2) is for feedthrough
+PHY-3001 : eco cells: (4 44 3) is for feedthrough
+PHY-3001 : eco cells: (4 45 2) is for feedthrough
+PHY-3001 : eco cells: (4 46 3) is for feedthrough
+PHY-3001 : eco cells: (4 47 0) is for feedthrough
+PHY-3001 : eco cells: (4 49 3) is for feedthrough
+PHY-3001 : eco cells: (4 51 3) is for feedthrough
+PHY-3001 : eco cells: (4 53 1) is for feedthrough
+PHY-3001 : eco cells: (4 53 2) is for feedthrough
+PHY-3001 : eco cells: (4 56 0) is for feedthrough
+PHY-3001 : eco cells: (4 59 1) is for feedthrough
+PHY-3001 : eco cells: (4 62 3) is for feedthrough
+PHY-3001 : eco cells: (5 3 3) is for feedthrough
+PHY-3001 : eco cells: (5 5 0) is for feedthrough
+PHY-3001 : eco cells: (5 6 1) is for feedthrough
+PHY-3001 : eco cells: (5 8 0) is for feedthrough
+PHY-3001 : eco cells: (5 9 3) is for feedthrough
+PHY-3001 : eco cells: (5 11 3) is for feedthrough
+PHY-3001 : eco cells: (5 13 2) is for feedthrough
+PHY-3001 : eco cells: (5 18 0) is for feedthrough
+PHY-3001 : eco cells: (5 21 2) is for feedthrough
+PHY-3001 : eco cells: (5 22 2) is for feedthrough
+PHY-3001 : eco cells: (5 33 1) is for feedthrough
+PHY-3001 : eco cells: (5 34 3) is for feedthrough
+PHY-3001 : eco cells: (5 35 0) is for feedthrough
+PHY-3001 : eco cells: (5 35 2) is for feedthrough
+PHY-3001 : eco cells: (5 46 0) is for feedthrough
+PHY-3001 : eco cells: (5 51 1) is for feedthrough
+PHY-3001 : eco cells: (5 51 2) is for feedthrough
+PHY-3001 : eco cells: (5 52 0) is for feedthrough
+PHY-3001 : eco cells: (5 53 3) is for feedthrough
+PHY-3001 : eco cells: (5 54 0) is for feedthrough
+PHY-3001 : eco cells: (5 57 3) is for feedthrough
+PHY-3001 : eco cells: (5 62 1) is for feedthrough
+PHY-3001 : eco cells: (5 63 3) is for feedthrough
+PHY-3001 : eco cells: (5 65 3) is for feedthrough
+PHY-3001 : eco cells: (5 67 2) is for feedthrough
+PHY-3001 : eco cells: (5 68 2) is for feedthrough
+PHY-3001 : eco cells: (5 68 3) is for feedthrough
+PHY-3001 : eco cells: (5 70 0) is for feedthrough
+PHY-3001 : eco cells: (6 5 0) is for feedthrough
+PHY-3001 : eco cells: (6 9 3) is for feedthrough
+PHY-3001 : eco cells: (6 18 1) is for feedthrough
+PHY-3001 : eco cells: (6 24 0) is for feedthrough
+PHY-3001 : eco cells: (6 36 2) is for feedthrough
+PHY-3001 : eco cells: (6 52 0) is for feedthrough
+PHY-3001 : eco cells: (6 65 0) is for feedthrough
+PHY-3001 : eco cells: (6 65 2) is for feedthrough
+PHY-3001 : eco cells: (6 70 3) is for feedthrough
+PHY-3001 : eco cells: (7 7 2) is for feedthrough
+PHY-3001 : eco cells: (7 10 1) is for feedthrough
+PHY-3001 : eco cells: (7 17 2) is for feedthrough
+PHY-3001 : eco cells: (7 54 3) is for feedthrough
+PHY-3001 : eco cells: (7 56 1) is for feedthrough
+PHY-3001 : eco cells: (7 56 3) is for feedthrough
+PHY-3001 : eco cells: (9 8 0) is for feedthrough
+PHY-3001 : eco cells: (9 8 1) is for feedthrough
+PHY-3001 : eco cells: (9 9 1) is for feedthrough
+PHY-3001 : eco cells: (9 9 3) is for feedthrough
+PHY-3001 : eco cells: (9 10 0) is for feedthrough
+PHY-3001 : eco cells: (9 19 2) is for feedthrough
+PHY-3001 : eco cells: (9 30 1) is for feedthrough
+PHY-3001 : eco cells: (9 33 2) is for feedthrough
+PHY-3001 : eco cells: (9 34 1) is for feedthrough
+PHY-3001 : eco cells: (9 39 1) is for feedthrough
+PHY-3001 : eco cells: (9 53 1) is for feedthrough
+PHY-3001 : eco cells: (9 53 3) is for feedthrough
+PHY-3001 : eco cells: (10 2 0) is for feedthrough
+PHY-3001 : eco cells: (10 5 0) is for feedthrough
+PHY-3001 : eco cells: (10 7 1) is for feedthrough
+PHY-3001 : eco cells: (10 7 2) is for feedthrough
+PHY-3001 : eco cells: (10 15 3) is for feedthrough
+PHY-3001 : eco cells: (10 16 1) is for feedthrough
+PHY-3001 : eco cells: (10 16 2) is for feedthrough
+PHY-3001 : eco cells: (10 16 3) is for feedthrough
+PHY-3001 : eco cells: (10 18 0) is for feedthrough
+PHY-3001 : eco cells: (10 18 3) is for feedthrough
+PHY-3001 : eco cells: (10 19 0) is for feedthrough
+PHY-3001 : eco cells: (10 19 2) is for feedthrough
+PHY-3001 : eco cells: (10 22 3) is for feedthrough
+PHY-3001 : eco cells: (10 26 2) is for feedthrough
+PHY-3001 : eco cells: (10 27 2) is for feedthrough
+PHY-3001 : eco cells: (10 30 1) is for feedthrough
+PHY-3001 : eco cells: (10 34 1) is for feedthrough
+PHY-3001 : eco cells: (10 41 2) is for feedthrough
+PHY-3001 : eco cells: (10 45 2) is for feedthrough
+PHY-3001 : eco cells: (10 50 0) is for feedthrough
+PHY-3001 : eco cells: (10 63 1) is for feedthrough
+PHY-3001 : eco cells: (11 8 3) is for feedthrough
+PHY-3001 : eco cells: (11 9 3) is for feedthrough
+PHY-3001 : eco cells: (11 11 2) is for feedthrough
+PHY-3001 : eco cells: (11 13 1) is for feedthrough
+PHY-3001 : eco cells: (11 14 0) is for feedthrough
+PHY-3001 : eco cells: (11 16 1) is for feedthrough
+PHY-3001 : eco cells: (11 17 3) is for feedthrough
+PHY-3001 : eco cells: (11 18 3) is for feedthrough
+PHY-3001 : eco cells: (11 20 0) is for feedthrough
+PHY-3001 : eco cells: (11 24 3) is for feedthrough
+PHY-3001 : eco cells: (11 25 3) is for feedthrough
+PHY-3001 : eco cells: (11 30 0) is for feedthrough
+PHY-3001 : eco cells: (11 30 1) is for feedthrough
+PHY-3001 : eco cells: (11 38 0) is for feedthrough
+PHY-3001 : eco cells: (11 39 0) is for feedthrough
+PHY-3001 : eco cells: (11 54 2) is for feedthrough
+PHY-3001 : eco cells: (12 2 2) is for feedthrough
+PHY-3001 : eco cells: (12 4 3) is for feedthrough
+PHY-3001 : eco cells: (12 6 1) is for feedthrough
+PHY-3001 : eco cells: (12 6 3) is for feedthrough
+PHY-3001 : eco cells: (12 8 2) is for feedthrough
+PHY-3001 : eco cells: (12 8 3) is for feedthrough
+PHY-3001 : eco cells: (12 10 1) is for feedthrough
+PHY-3001 : eco cells: (12 10 2) is for feedthrough
+PHY-3001 : eco cells: (12 15 3) is for feedthrough
+PHY-3001 : eco cells: (12 17 2) is for feedthrough
+PHY-3001 : eco cells: (12 25 2) is for feedthrough
+PHY-3001 : eco cells: (12 26 3) is for feedthrough
+PHY-3001 : eco cells: (12 27 3) is for feedthrough
+PHY-3001 : eco cells: (12 31 1) is for feedthrough
+PHY-3001 : eco cells: (12 37 0) is for feedthrough
+PHY-3001 : eco cells: (12 39 2) is for feedthrough
+PHY-3001 : eco cells: (12 42 1) is for feedthrough
+PHY-3001 : eco cells: (12 43 2) is for feedthrough
+PHY-3001 : eco cells: (12 44 1) is for feedthrough
+PHY-3001 : eco cells: (12 55 0) is for feedthrough
+PHY-3001 : eco cells: (12 66 2) is for feedthrough
+PHY-3001 : eco cells: (13 10 1) is for feedthrough
+PHY-3001 : eco cells: (13 12 1) is for feedthrough
+PHY-3001 : eco cells: (13 24 1) is for feedthrough
+PHY-3001 : eco cells: (13 25 2) is for feedthrough
+PHY-3001 : eco cells: (13 35 2) is for feedthrough
+PHY-3001 : eco cells: (13 36 1) is for feedthrough
+PHY-3001 : eco cells: (13 58 3) is for feedthrough
+PHY-3001 : eco cells: (13 60 0) is for feedthrough
+PHY-3001 : eco cells: (13 68 1) is for feedthrough
+PHY-3001 : eco cells: (14 1 0) is for feedthrough
+PHY-3001 : eco cells: (14 9 2) is for feedthrough
+PHY-3001 : eco cells: (14 11 2) is for feedthrough
+PHY-3001 : eco cells: (14 20 1) is for feedthrough
+PHY-3001 : eco cells: (14 24 0) is for feedthrough
+PHY-3001 : eco cells: (14 24 1) is for feedthrough
+PHY-3001 : eco cells: (14 28 3) is for feedthrough
+PHY-3001 : eco cells: (14 31 1) is for feedthrough
+PHY-3001 : eco cells: (14 42 0) is for feedthrough
+PHY-3001 : eco cells: (14 42 2) is for feedthrough
+PHY-3001 : eco cells: (14 43 2) is for feedthrough
+PHY-3001 : eco cells: (14 52 1) is for feedthrough
+PHY-3001 : eco cells: (14 55 2) is for feedthrough
+PHY-3001 : eco cells: (14 57 2) is for feedthrough
+PHY-3001 : eco cells: (14 62 0) is for feedthrough
+PHY-3001 : eco cells: (15 3 1) is for feedthrough
+PHY-3001 : eco cells: (15 10 2) is for feedthrough
+PHY-3001 : eco cells: (15 10 3) is for feedthrough
+PHY-3001 : eco cells: (15 12 0) is for feedthrough
+PHY-3001 : eco cells: (15 28 3) is for feedthrough
+PHY-3001 : eco cells: (15 31 2) is for feedthrough
+PHY-3001 : eco cells: (15 35 3) is for feedthrough
+PHY-3001 : eco cells: (15 53 2) is for feedthrough
+PHY-3001 : eco cells: (17 6 0) is for feedthrough
+PHY-3001 : eco cells: (17 9 0) is for feedthrough
+PHY-3001 : eco cells: (17 18 1) is for feedthrough
+PHY-3001 : eco cells: (17 21 3) is for feedthrough
+PHY-3001 : eco cells: (17 25 0) is for feedthrough
+PHY-3001 : eco cells: (17 27 2) is for feedthrough
+PHY-3001 : eco cells: (17 40 3) is for feedthrough
+PHY-3001 : eco cells: (17 42 3) is for feedthrough
+PHY-3001 : eco cells: (17 52 2) is for feedthrough
+PHY-3001 : eco cells: (17 59 3) is for feedthrough
+PHY-3001 : eco cells: (18 1 0) is for feedthrough
+PHY-3001 : eco cells: (18 2 0) is for feedthrough
+PHY-3001 : eco cells: (18 3 3) is for feedthrough
+PHY-3001 : eco cells: (18 4 1) is for feedthrough
+PHY-3001 : eco cells: (18 9 0) is for feedthrough
+PHY-3001 : eco cells: (18 11 0) is for feedthrough
+PHY-3001 : eco cells: (18 14 3) is for feedthrough
+PHY-3001 : eco cells: (18 17 2) is for feedthrough
+PHY-3001 : eco cells: (18 18 3) is for feedthrough
+PHY-3001 : eco cells: (18 25 0) is for feedthrough
+PHY-3001 : eco cells: (18 25 2) is for feedthrough
+PHY-3001 : eco cells: (18 27 0) is for feedthrough
+PHY-3001 : eco cells: (18 29 3) is for feedthrough
+PHY-3001 : eco cells: (18 31 3) is for feedthrough
+PHY-3001 : eco cells: (18 34 1) is for feedthrough
+PHY-3001 : eco cells: (18 36 1) is for feedthrough
+PHY-3001 : eco cells: (18 57 2) is for feedthrough
+PHY-3001 : eco cells: (18 58 0) is for feedthrough
+PHY-3001 : eco cells: (19 7 0) is for feedthrough
+PHY-3001 : eco cells: (19 10 2) is for feedthrough
+PHY-3001 : eco cells: (19 16 2) is for feedthrough
+PHY-3001 : eco cells: (19 17 1) is for feedthrough
+PHY-3001 : eco cells: (19 18 2) is for feedthrough
+PHY-3001 : eco cells: (19 26 0) is for feedthrough
+PHY-3001 : eco cells: (19 27 0) is for feedthrough
+PHY-3001 : eco cells: (19 28 1) is for feedthrough
+PHY-3001 : eco cells: (19 42 0) is for feedthrough
+PHY-3001 : eco cells: (19 53 2) is for feedthrough
+PHY-3001 : eco cells: (19 59 2) is for feedthrough
+PHY-3001 : eco cells: (20 3 0) is for feedthrough
+PHY-3001 : eco cells: (20 10 1) is for feedthrough
+PHY-3001 : eco cells: (20 10 2) is for feedthrough
+PHY-3001 : eco cells: (20 10 3) is for feedthrough
+PHY-3001 : eco cells: (20 13 0) is for feedthrough
+PHY-3001 : eco cells: (20 13 1) is for feedthrough
+PHY-3001 : eco cells: (20 19 1) is for feedthrough
+PHY-3001 : eco cells: (20 28 0) is for feedthrough
+PHY-3001 : eco cells: (20 28 1) is for feedthrough
+PHY-3001 : eco cells: (20 38 2) is for feedthrough
+PHY-3001 : eco cells: (20 43 0) is for feedthrough
+PHY-3001 : eco cells: (20 51 1) is for feedthrough
+PHY-3001 : eco cells: (21 2 0) is for feedthrough
+PHY-3001 : eco cells: (21 7 3) is for feedthrough
+PHY-3001 : eco cells: (21 24 1) is for feedthrough
+PHY-3001 : eco cells: (21 29 0) is for feedthrough
+PHY-3001 : eco cells: (21 30 1) is for feedthrough
+PHY-3001 : eco cells: (21 31 2) is for feedthrough
+PHY-3001 : eco cells: (21 32 2) is for feedthrough
+PHY-3001 : eco cells: (21 41 1) is for feedthrough
+PHY-3001 : eco cells: (21 43 0) is for feedthrough
+PHY-3001 : eco cells: (21 43 2) is for feedthrough
+PHY-3001 : eco cells: (21 53 1) is for feedthrough
+PHY-3001 : eco cells: (21 54 0) is for feedthrough
+PHY-3001 : eco cells: (21 54 2) is for feedthrough
+PHY-3001 : eco cells: (22 3 0) is for feedthrough
+PHY-3001 : eco cells: (22 26 1) is for feedthrough
+PHY-3001 : eco cells: (22 30 1) is for feedthrough
+PHY-3001 : eco cells: (22 34 0) is for feedthrough
+PHY-3001 : eco cells: (22 35 0) is for feedthrough
+PHY-3001 : eco cells: (22 37 2) is for feedthrough
+PHY-3001 : eco cells: (22 44 2) is for feedthrough
+PHY-3001 : eco cells: (22 44 3) is for feedthrough
+PHY-3001 : eco cells: (22 57 2) is for feedthrough
+PHY-3001 : eco cells: (23 7 2) is for feedthrough
+PHY-3001 : eco cells: (23 10 0) is for feedthrough
+PHY-3001 : eco cells: (23 28 0) is for feedthrough
+PHY-3001 : eco cells: (23 31 3) is for feedthrough
+PHY-3001 : eco cells: (23 36 1) is for feedthrough
+PHY-3001 : eco cells: (23 54 1) is for feedthrough
+PHY-3001 : eco cells: (23 55 1) is for feedthrough
+PHY-3001 : eco cells: (23 55 3) is for feedthrough
+PHY-3001 : eco cells: (23 60 1) is for feedthrough
+PHY-3001 : eco cells: (25 7 1) is for feedthrough
+PHY-3001 : eco cells: (25 8 0) is for feedthrough
+PHY-3001 : eco cells: (25 11 2) is for feedthrough
+PHY-3001 : eco cells: (25 29 0) is for feedthrough
+PHY-3001 : eco cells: (25 32 0) is for feedthrough
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+PHY-3001 : eco cells: (25 57 0) is for feedthrough
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+PHY-3001 : eco cells: (26 20 3) is for feedthrough
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+PHY-3001 : eco cells: (26 36 3) is for feedthrough
+PHY-3001 : eco cells: (26 52 1) is for feedthrough
+PHY-3001 : eco cells: (26 53 3) is for feedthrough
+PHY-3001 : eco cells: (26 60 0) is for feedthrough
+PHY-3001 : eco cells: (26 60 1) is for feedthrough
+PHY-3001 : eco cells: (27 25 0) is for feedthrough
+PHY-3001 : eco cells: (27 32 0) is for feedthrough
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+PHY-3001 : eco cells: (27 56 1) is for feedthrough
+PHY-3001 : eco cells: (27 59 2) is for feedthrough
+PHY-3001 : eco cells: (27 64 3) is for feedthrough
+PHY-3001 : eco cells: (27 69 0) is for feedthrough
+PHY-3001 : eco cells: (28 8 1) is for feedthrough
+PHY-3001 : eco cells: (28 15 2) is for feedthrough
+PHY-3001 : eco cells: (28 24 0) is for feedthrough
+PHY-3001 : eco cells: (28 28 3) is for feedthrough
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+PHY-3001 : eco cells: (28 38 1) is for feedthrough
+PHY-3001 : eco cells: (28 39 2) is for feedthrough
+PHY-3001 : eco cells: (28 41 2) is for feedthrough
+PHY-3001 : eco cells: (28 42 3) is for feedthrough
+PHY-3001 : eco cells: (28 43 2) is for feedthrough
+PHY-3001 : eco cells: (29 28 2) is for feedthrough
+PHY-3001 : eco cells: (29 31 3) is for feedthrough
+PHY-3001 : eco cells: (29 32 1) is for feedthrough
+PHY-3001 : eco cells: (29 33 0) is for feedthrough
+PHY-3001 : eco cells: (29 47 2) is for feedthrough
+PHY-3001 : eco cells: (29 50 0) is for feedthrough
+PHY-3001 : eco cells: (29 55 0) is for feedthrough
+PHY-3001 : eco cells: (29 55 3) is for feedthrough
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+PHY-3001 : eco cells: (31 25 2) is for feedthrough
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+PHY-3001 : eco cells: (31 37 2) is for feedthrough
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+PHY-3001 : eco cells: (33 37 0) is for feedthrough
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+PHY-3001 : eco cells: (33 58 3) is for feedthrough
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+PHY-3001 : eco cells: (34 10 2) is for feedthrough
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+PHY-3001 : eco cells: (34 39 3) is for feedthrough
+PHY-3001 : eco cells: (34 40 3) is for feedthrough
+PHY-3001 : eco cells: (34 41 3) is for feedthrough
+PHY-3001 : eco cells: (34 44 1) is for feedthrough
+PHY-3001 : eco cells: (34 55 0) is for feedthrough
+PHY-3001 : eco cells: (34 56 0) is for feedthrough
+PHY-3001 : eco cells: (34 58 3) is for feedthrough
+PHY-3001 : eco cells: (35 7 2) is for feedthrough
+PHY-3001 : eco cells: (35 9 2) is for feedthrough
+PHY-3001 : eco cells: (35 12 0) is for feedthrough
+PHY-3001 : eco cells: (35 15 1) is for feedthrough
+PHY-3001 : eco cells: (35 17 1) is for feedthrough
+PHY-3001 : eco cells: (35 24 3) is for feedthrough
+PHY-3001 : eco cells: (35 25 0) is for feedthrough
+PHY-3001 : eco cells: (35 25 2) is for feedthrough
+PHY-3001 : eco cells: (35 27 2) is for feedthrough
+PHY-3001 : eco cells: (35 28 0) is for feedthrough
+PHY-3001 : eco cells: (35 29 3) is for feedthrough
+PHY-3001 : eco cells: (35 31 0) is for feedthrough
+PHY-3001 : eco cells: (35 32 3) is for feedthrough
+PHY-3001 : eco cells: (35 33 2) is for feedthrough
+PHY-3001 : eco cells: (35 35 3) is for feedthrough
+PHY-3001 : eco cells: (35 36 0) is for feedthrough
+PHY-3001 : eco cells: (35 36 2) is for feedthrough
+PHY-3001 : eco cells: (35 36 3) is for feedthrough
+PHY-3001 : eco cells: (35 39 1) is for feedthrough
+PHY-3001 : eco cells: (35 39 3) is for feedthrough
+PHY-3001 : eco cells: (35 44 2) is for feedthrough
+PHY-3001 : eco cells: (35 54 2) is for feedthrough
+PHY-3001 : eco cells: (35 56 0) is for feedthrough
+PHY-3001 : eco cells: (35 57 2) is for feedthrough
+PHY-3001 : eco cells: (35 59 1) is for feedthrough
+PHY-3001 : eco cells: (36 13 1) is for feedthrough
+PHY-3001 : eco cells: (36 13 3) is for feedthrough
+PHY-3001 : eco cells: (36 18 0) is for feedthrough
+PHY-3001 : eco cells: (36 19 2) is for feedthrough
+PHY-3001 : eco cells: (36 28 2) is for feedthrough
+PHY-3001 : eco cells: (36 30 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 2) is for feedthrough
+PHY-3001 : eco cells: (36 31 3) is for feedthrough
+PHY-3001 : eco cells: (36 32 1) is for feedthrough
+PHY-3001 : eco cells: (36 33 0) is for feedthrough
+PHY-3001 : eco cells: (36 34 0) is for feedthrough
+PHY-3001 : eco cells: (36 34 2) is for feedthrough
+PHY-3001 : eco cells: (36 35 0) is for feedthrough
+PHY-3001 : eco cells: (36 37 1) is for feedthrough
+PHY-3001 : eco cells: (36 39 1) is for feedthrough
+PHY-3001 : eco cells: (36 46 1) is for feedthrough
+PHY-3001 : eco cells: (36 58 2) is for feedthrough
+PHY-3001 : eco cells: (36 58 3) is for feedthrough
+PHY-3001 : eco cells: (37 1 0) is for feedthrough
+PHY-3001 : eco cells: (37 11 2) is for feedthrough
+PHY-3001 : eco cells: (37 12 2) is for feedthrough
+PHY-3001 : eco cells: (37 18 0) is for feedthrough
+PHY-3001 : eco cells: (37 22 1) is for feedthrough
+PHY-3001 : eco cells: (37 24 0) is for feedthrough
+PHY-3001 : eco cells: (37 26 1) is for feedthrough
+PHY-3001 : eco cells: (37 34 3) is for feedthrough
+PHY-3001 : eco cells: (37 36 3) is for feedthrough
+PHY-3001 : eco cells: (37 37 2) is for feedthrough
+PHY-3001 : eco cells: (37 38 0) is for feedthrough
+PHY-3001 : eco cells: (37 38 1) is for feedthrough
+PHY-3001 : eco cells: (37 39 0) is for feedthrough
+PHY-3001 : eco cells: (37 39 3) is for feedthrough
+PHY-3001 : eco cells: (37 40 0) is for feedthrough
+PHY-3001 : eco cells: (37 43 3) is for feedthrough
+PHY-3001 : eco cells: (38 18 0) is for feedthrough
+PHY-3001 : eco cells: (38 18 1) is for feedthrough
+PHY-3001 : eco cells: (38 18 3) is for feedthrough
+PHY-3001 : eco cells: (38 35 3) is for feedthrough
+PHY-3001 : eco cells: (38 36 0) is for feedthrough
+PHY-3001 : eco cells: (38 37 1) is for feedthrough
+PHY-3001 : eco cells: (38 37 2) is for feedthrough
+PHY-3001 : eco cells: (38 40 2) is for feedthrough
+PHY-3001 : eco cells: (38 41 0) is for feedthrough
+PHY-3001 : eco cells: (38 66 1) is for feedthrough
+PHY-3001 : eco cells: (38 67 1) is for feedthrough
+PHY-3001 : eco cells: (39 8 0) is for feedthrough
+PHY-3001 : eco cells: (39 42 2) is for feedthrough
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3644 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.784576s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.6%)
+
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.231296s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.3%)
+
+RUN-1004 : used memory is 1150 MB, reserved memory is 1156 MB, peak memory is 1154 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6735 instances
+RUN-1001 : 3289 mslices, 3295 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17953 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10007 nets have 2 pins
+RUN-1001 : 6503 nets have [3 - 5] pins
+RUN-1001 : 789 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 309 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3289 mslices, 3295 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1161, peak = 1156.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1173, reserve = 1178, peak = 1173.
+PHY-1001 : End build detailed router design. 1.823672s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.021543s wall, 0.000000s user + 0.015625s system = 0.015625s CPU (72.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.029221s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (106.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.032090s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.4%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.029494s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (106.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.028917s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (108.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.028718s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (54.4%)
+
+PHY-1001 : Current memory(MB): used = 1173, reserve = 1178, peak = 1173.
+PHY-1001 : End phase 1; 0.204657s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (99.3%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1173, reserve = 1178, peak = 1173.
+PHY-1001 : End initial routed; 0.165591s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16876(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.180563s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1174, reserve = 1180, peak = 1174.
+PHY-1001 : End phase 2; 3.346210s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.122630s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.9%)
+
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.349192s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (98.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.131956s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.132643s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.131800s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.211806s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.136018s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.9%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.142263s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.138957s wall, 0.156250s user + 0.046875s system = 0.203125s CPU (146.2%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.137111s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (114.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.137447s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.131775s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.133470s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.4%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.141438s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.134759s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.130290s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.132060s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.5%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.139842s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.139070s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.140637s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.212969s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.4%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.140043s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.215747s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (130.4%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.136612s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.130219s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.130250s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.0%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.134211s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.1%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.135938s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.0%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.134322s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (116.3%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.136634s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.136953s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.3%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.136485s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (114.5%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.134333s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.130086s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.1%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.134050s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.129645s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.130009s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (108.2%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.130155s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.130223s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.131118s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.3%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.133130s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.9%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.129911s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.2%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.130359s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.9%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.132975s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.0%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.131546s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.0%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.129557s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.129054s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (121.1%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.131296s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.2%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.129551s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.129372s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.7%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.131153s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.129630s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.130902s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.4%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.134057s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.2%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.130507s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.130796s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.6%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.129866s wall, 0.171875s user + 0.031250s system = 0.203125s CPU (156.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.132593s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.3%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.131178s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.2%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.129673s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.131215s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.129968s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.2%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.129566s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.129897s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.2%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.134289s wall, 0.125000s user + 0.031250s system = 0.156250s CPU (116.4%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.130059s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.129720s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.129389s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.130754s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.5%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.131137s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.130029s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.129906s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.3%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.131355s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.2%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.131162s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.129526s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.6%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.33617e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.130360s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16876(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.156626s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1174, reserve = 1180, peak = 1174.
+PHY-1001 : End phase 3; 13.670326s wall, 13.750000s user + 0.171875s system = 13.921875s CPU (101.8%)
+
+PHY-1001 : 508 feed throughs used by 390 nets
+PHY-1001 : Current memory(MB): used = 1174, reserve = 1180, peak = 1174.
+PHY-1001 : End export database. 2.356928s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (100.1%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x13y26_w2beg4), nets: sys_initial_done_dup_1175 sampling_fe_a/u_sort/u_transfer_300_to_200/data_tmp_b2_n
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 22.555008s wall, 22.593750s user + 0.187500s system = 22.781250s CPU (101.0%)
+
+RUN-1004 : used memory is 1160 MB, reserved memory is 1165 MB, peak memory is 1174 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x13y26_w2beg4), nets: sys_initial_done_dup_1175 sampling_fe_a/u_sort/u_transfer_300_to_200/data_tmp_b2_n
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 163.871490s wall, 199.734375s user + 0.656250s system = 200.390625s CPU (122.3%)
+
+RUN-1004 : used memory is 1160 MB, reserved memory is 1165 MB, peak memory is 1174 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_184041.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_184627.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_184627.log
new file mode 100644
index 0000000..b24eacd
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_184627.log
@@ -0,0 +1,1989 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 18:46:27 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(886)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(895)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(919)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(921)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(927)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(930)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1101)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1190)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1491)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1502)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1520)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2098)
+HDL-5007 WARNING: identifier 'a_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'a_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(172)
+HDL-5007 WARNING: identifier 'b_vs_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl1_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_cl0_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_en_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-5007 WARNING: identifier 'b_ch_sync_d2' is used before its declaration in ../../../../hg_mp/drx_top/huagao_mipi_top.v(277)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.197203s wall, 2.109375s user + 0.062500s system = 2.171875s CPU (98.8%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 317 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18083 instances
+RUN-0007 : 7697 luts, 9163 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20660 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13180 nets have 2 pins
+RUN-1001 : 6400 nets have [3 - 5] pins
+RUN-1001 : 658 nets have [6 - 10] pins
+RUN-1001 : 173 nets have [11 - 20] pins
+RUN-1001 : 175 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1987
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18081 instances, 7697 luts, 9163 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6036 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84758, tnet num: 20482, tinst num: 18081, tnode num: 115301, tedge num: 135302.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.209459s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.5%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 518 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20482 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.019520s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (99.8%)
+
+PHY-3001 : Found 1243 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.1993e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18081.
+PHY-3001 : Level 1 #clusters 1968.
+PHY-3001 : End clustering; 0.134072s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29072e+06, overlap = 467.594
+PHY-3002 : Step(2): len = 1.20499e+06, overlap = 542.312
+PHY-3002 : Step(3): len = 827154, overlap = 651.5
+PHY-3002 : Step(4): len = 753383, overlap = 677.188
+PHY-3002 : Step(5): len = 588854, overlap = 802.25
+PHY-3002 : Step(6): len = 509847, overlap = 886.656
+PHY-3002 : Step(7): len = 441492, overlap = 988.375
+PHY-3002 : Step(8): len = 397756, overlap = 1056.34
+PHY-3002 : Step(9): len = 368895, overlap = 1123.84
+PHY-3002 : Step(10): len = 335877, overlap = 1159.78
+PHY-3002 : Step(11): len = 305040, overlap = 1189.69
+PHY-3002 : Step(12): len = 279352, overlap = 1219.25
+PHY-3002 : Step(13): len = 258672, overlap = 1282.09
+PHY-3002 : Step(14): len = 239859, overlap = 1293.78
+PHY-3002 : Step(15): len = 227245, overlap = 1351.38
+PHY-3002 : Step(16): len = 210485, overlap = 1382.41
+PHY-3002 : Step(17): len = 197707, overlap = 1398.38
+PHY-3002 : Step(18): len = 178513, overlap = 1408.44
+PHY-3002 : Step(19): len = 169602, overlap = 1415.38
+PHY-3002 : Step(20): len = 160494, overlap = 1454.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.11862e-06
+PHY-3002 : Step(21): len = 164541, overlap = 1411
+PHY-3002 : Step(22): len = 201609, overlap = 1274.38
+PHY-3002 : Step(23): len = 206243, overlap = 1192.56
+PHY-3002 : Step(24): len = 207268, overlap = 1163.56
+PHY-3002 : Step(25): len = 203089, overlap = 1143.22
+PHY-3002 : Step(26): len = 202066, overlap = 1134.62
+PHY-3002 : Step(27): len = 197847, overlap = 1125.59
+PHY-3002 : Step(28): len = 194457, overlap = 1132.44
+PHY-3002 : Step(29): len = 191810, overlap = 1133.59
+PHY-3002 : Step(30): len = 188980, overlap = 1125.53
+PHY-3002 : Step(31): len = 185823, overlap = 1114.09
+PHY-3002 : Step(32): len = 183141, overlap = 1098.31
+PHY-3002 : Step(33): len = 180280, overlap = 1099.38
+PHY-3002 : Step(34): len = 179443, overlap = 1105.88
+PHY-3002 : Step(35): len = 177518, overlap = 1106.75
+PHY-3002 : Step(36): len = 175654, overlap = 1115.22
+PHY-3002 : Step(37): len = 173913, overlap = 1117.22
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.23724e-06
+PHY-3002 : Step(38): len = 177392, overlap = 1101.5
+PHY-3002 : Step(39): len = 189762, overlap = 1055.72
+PHY-3002 : Step(40): len = 194923, overlap = 1032.56
+PHY-3002 : Step(41): len = 200477, overlap = 1008.31
+PHY-3002 : Step(42): len = 203391, overlap = 983.906
+PHY-3002 : Step(43): len = 205749, overlap = 965.281
+PHY-3002 : Step(44): len = 203730, overlap = 967.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.47448e-06
+PHY-3002 : Step(45): len = 211554, overlap = 942.062
+PHY-3002 : Step(46): len = 231238, overlap = 832.031
+PHY-3002 : Step(47): len = 242703, overlap = 766.188
+PHY-3002 : Step(48): len = 250265, overlap = 746.062
+PHY-3002 : Step(49): len = 252288, overlap = 739.25
+PHY-3002 : Step(50): len = 251678, overlap = 734.844
+PHY-3002 : Step(51): len = 250504, overlap = 702.719
+PHY-3002 : Step(52): len = 249441, overlap = 699.688
+PHY-3002 : Step(53): len = 247762, overlap = 694.688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.94896e-06
+PHY-3002 : Step(54): len = 259591, overlap = 674.938
+PHY-3002 : Step(55): len = 279783, overlap = 634.812
+PHY-3002 : Step(56): len = 289572, overlap = 582.5
+PHY-3002 : Step(57): len = 295113, overlap = 572.562
+PHY-3002 : Step(58): len = 296661, overlap = 562.75
+PHY-3002 : Step(59): len = 294946, overlap = 538.469
+PHY-3002 : Step(60): len = 292241, overlap = 531.375
+PHY-3002 : Step(61): len = 291332, overlap = 521.75
+PHY-3002 : Step(62): len = 292418, overlap = 507.281
+PHY-3002 : Step(63): len = 293209, overlap = 503.719
+PHY-3002 : Step(64): len = 292287, overlap = 486.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.78979e-05
+PHY-3002 : Step(65): len = 306331, overlap = 449.781
+PHY-3002 : Step(66): len = 321595, overlap = 420.875
+PHY-3002 : Step(67): len = 326090, overlap = 391.281
+PHY-3002 : Step(68): len = 329248, overlap = 365.094
+PHY-3002 : Step(69): len = 329035, overlap = 361.438
+PHY-3002 : Step(70): len = 331055, overlap = 349.406
+PHY-3002 : Step(71): len = 328636, overlap = 343.406
+PHY-3002 : Step(72): len = 331110, overlap = 335
+PHY-3002 : Step(73): len = 331064, overlap = 346.969
+PHY-3002 : Step(74): len = 331354, overlap = 348.781
+PHY-3002 : Step(75): len = 328244, overlap = 318.469
+PHY-3002 : Step(76): len = 328279, overlap = 322.781
+PHY-3002 : Step(77): len = 328396, overlap = 318.531
+PHY-3002 : Step(78): len = 329784, overlap = 331.031
+PHY-3002 : Step(79): len = 328117, overlap = 337.281
+PHY-3002 : Step(80): len = 328297, overlap = 330.688
+PHY-3002 : Step(81): len = 326561, overlap = 327.188
+PHY-3002 : Step(82): len = 326490, overlap = 334.969
+PHY-3002 : Step(83): len = 325294, overlap = 343.406
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.57958e-05
+PHY-3002 : Step(84): len = 338256, overlap = 325
+PHY-3002 : Step(85): len = 349830, overlap = 308.125
+PHY-3002 : Step(86): len = 354906, overlap = 293.625
+PHY-3002 : Step(87): len = 356267, overlap = 283.906
+PHY-3002 : Step(88): len = 356031, overlap = 282.031
+PHY-3002 : Step(89): len = 358728, overlap = 266.812
+PHY-3002 : Step(90): len = 359572, overlap = 255.719
+PHY-3002 : Step(91): len = 361512, overlap = 245.812
+PHY-3002 : Step(92): len = 363277, overlap = 250.688
+PHY-3002 : Step(93): len = 363837, overlap = 239.219
+PHY-3002 : Step(94): len = 362787, overlap = 236.219
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.15916e-05
+PHY-3002 : Step(95): len = 375279, overlap = 234.156
+PHY-3002 : Step(96): len = 385267, overlap = 230.344
+PHY-3002 : Step(97): len = 385653, overlap = 223.969
+PHY-3002 : Step(98): len = 388228, overlap = 227.312
+PHY-3002 : Step(99): len = 392382, overlap = 221.906
+PHY-3002 : Step(100): len = 395634, overlap = 223.219
+PHY-3002 : Step(101): len = 392074, overlap = 222.812
+PHY-3002 : Step(102): len = 392110, overlap = 227.344
+PHY-3002 : Step(103): len = 394892, overlap = 231.312
+PHY-3002 : Step(104): len = 398341, overlap = 225.75
+PHY-3002 : Step(105): len = 396032, overlap = 213.156
+PHY-3002 : Step(106): len = 396901, overlap = 209.969
+PHY-3002 : Step(107): len = 398215, overlap = 214.188
+PHY-3002 : Step(108): len = 399414, overlap = 212.656
+PHY-3002 : Step(109): len = 398754, overlap = 208.281
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000141311
+PHY-3002 : Step(110): len = 411007, overlap = 207.594
+PHY-3002 : Step(111): len = 420525, overlap = 203.938
+PHY-3002 : Step(112): len = 419805, overlap = 190.281
+PHY-3002 : Step(113): len = 420746, overlap = 190.344
+PHY-3002 : Step(114): len = 425147, overlap = 190.094
+PHY-3002 : Step(115): len = 429306, overlap = 201.812
+PHY-3002 : Step(116): len = 427190, overlap = 196.938
+PHY-3002 : Step(117): len = 427931, overlap = 198.531
+PHY-3002 : Step(118): len = 430025, overlap = 194.688
+PHY-3002 : Step(119): len = 431860, overlap = 193.469
+PHY-3002 : Step(120): len = 430104, overlap = 199.969
+PHY-3002 : Step(121): len = 430580, overlap = 200.094
+PHY-3002 : Step(122): len = 432566, overlap = 196.031
+PHY-3002 : Step(123): len = 433738, overlap = 190.25
+PHY-3002 : Step(124): len = 431686, overlap = 196.219
+PHY-3002 : Step(125): len = 431482, overlap = 198.25
+PHY-3002 : Step(126): len = 433134, overlap = 186.375
+PHY-3002 : Step(127): len = 434474, overlap = 185.312
+PHY-3002 : Step(128): len = 432888, overlap = 188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000265539
+PHY-3002 : Step(129): len = 440451, overlap = 186.719
+PHY-3002 : Step(130): len = 448049, overlap = 178.5
+PHY-3002 : Step(131): len = 449471, overlap = 186.844
+PHY-3002 : Step(132): len = 451340, overlap = 180.5
+PHY-3002 : Step(133): len = 454649, overlap = 176.281
+PHY-3002 : Step(134): len = 456776, overlap = 173.625
+PHY-3002 : Step(135): len = 455657, overlap = 167.625
+PHY-3002 : Step(136): len = 456197, overlap = 162.656
+PHY-3002 : Step(137): len = 458444, overlap = 163.875
+PHY-3002 : Step(138): len = 460158, overlap = 160.031
+PHY-3002 : Step(139): len = 459053, overlap = 158.375
+PHY-3002 : Step(140): len = 459557, overlap = 153.375
+PHY-3002 : Step(141): len = 461815, overlap = 160
+PHY-3002 : Step(142): len = 463389, overlap = 165.406
+PHY-3002 : Step(143): len = 462030, overlap = 160.406
+PHY-3002 : Step(144): len = 462122, overlap = 162.375
+PHY-3002 : Step(145): len = 463150, overlap = 164.5
+PHY-3002 : Step(146): len = 463756, overlap = 161.156
+PHY-3002 : Step(147): len = 463421, overlap = 160.156
+PHY-3002 : Step(148): len = 464490, overlap = 168.156
+PHY-3002 : Step(149): len = 465605, overlap = 175.656
+PHY-3002 : Step(150): len = 465844, overlap = 173.875
+PHY-3002 : Step(151): len = 464529, overlap = 173.938
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000486789
+PHY-3002 : Step(152): len = 471567, overlap = 174
+PHY-3002 : Step(153): len = 478250, overlap = 172.656
+PHY-3002 : Step(154): len = 479504, overlap = 174.094
+PHY-3002 : Step(155): len = 480845, overlap = 168.906
+PHY-3002 : Step(156): len = 483811, overlap = 163.562
+PHY-3002 : Step(157): len = 486142, overlap = 166.031
+PHY-3002 : Step(158): len = 485453, overlap = 168.156
+PHY-3002 : Step(159): len = 485583, overlap = 164
+PHY-3002 : Step(160): len = 486915, overlap = 158.906
+PHY-3002 : Step(161): len = 487536, overlap = 154.969
+PHY-3002 : Step(162): len = 486288, overlap = 155.281
+PHY-3002 : Step(163): len = 486209, overlap = 157.438
+PHY-3002 : Step(164): len = 487246, overlap = 148.25
+PHY-3002 : Step(165): len = 487817, overlap = 146.375
+PHY-3002 : Step(166): len = 487032, overlap = 149.312
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000884614
+PHY-3002 : Step(167): len = 492080, overlap = 147.812
+PHY-3002 : Step(168): len = 496822, overlap = 145.125
+PHY-3002 : Step(169): len = 497455, overlap = 144.219
+PHY-3002 : Step(170): len = 498141, overlap = 142.031
+PHY-3002 : Step(171): len = 501398, overlap = 137.938
+PHY-3002 : Step(172): len = 504567, overlap = 140.375
+PHY-3002 : Step(173): len = 504441, overlap = 137.656
+PHY-3002 : Step(174): len = 504593, overlap = 135.375
+PHY-3002 : Step(175): len = 506335, overlap = 137.219
+PHY-3002 : Step(176): len = 507948, overlap = 130.469
+PHY-3002 : Step(177): len = 506988, overlap = 127.938
+PHY-3002 : Step(178): len = 506831, overlap = 128.25
+PHY-3002 : Step(179): len = 507882, overlap = 133.219
+PHY-3002 : Step(180): len = 508447, overlap = 132.656
+PHY-3002 : Step(181): len = 507917, overlap = 133.75
+PHY-3002 : Step(182): len = 507902, overlap = 133
+PHY-3002 : Step(183): len = 508557, overlap = 132.656
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00154577
+PHY-3002 : Step(184): len = 511215, overlap = 132.625
+PHY-3002 : Step(185): len = 515915, overlap = 127.25
+PHY-3002 : Step(186): len = 517798, overlap = 129.094
+PHY-3002 : Step(187): len = 518592, overlap = 125.969
+PHY-3002 : Step(188): len = 519411, overlap = 126.125
+PHY-3002 : Step(189): len = 520175, overlap = 126.219
+PHY-3002 : Step(190): len = 521141, overlap = 115.875
+PHY-3002 : Step(191): len = 521393, overlap = 114.188
+PHY-3002 : Step(192): len = 521262, overlap = 114.125
+PHY-3002 : Step(193): len = 521385, overlap = 115.281
+PHY-3002 : Step(194): len = 522016, overlap = 119.125
+PHY-3002 : Step(195): len = 522788, overlap = 120.062
+PHY-3002 : Step(196): len = 523398, overlap = 116.438
+PHY-3002 : Step(197): len = 524210, overlap = 113.562
+PHY-3002 : Step(198): len = 524915, overlap = 112.75
+PHY-3002 : Step(199): len = 525133, overlap = 112.531
+PHY-3002 : Step(200): len = 525229, overlap = 112.812
+PHY-3002 : Step(201): len = 526757, overlap = 110.062
+PHY-3002 : Step(202): len = 529555, overlap = 107.344
+PHY-3002 : Step(203): len = 531783, overlap = 106.969
+PHY-3002 : Step(204): len = 531831, overlap = 108.688
+PHY-3002 : Step(205): len = 531900, overlap = 105.156
+PHY-3002 : Step(206): len = 532283, overlap = 107.094
+PHY-3002 : Step(207): len = 532455, overlap = 107.875
+PHY-3002 : Step(208): len = 531851, overlap = 108.531
+PHY-3002 : Step(209): len = 531732, overlap = 108.531
+PHY-3002 : Step(210): len = 532047, overlap = 109.594
+PHY-3002 : Step(211): len = 532087, overlap = 111.812
+PHY-3002 : Step(212): len = 531760, overlap = 108.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.017718s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (176.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20660.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 716272, over cnt = 1691(4%), over = 7336, worst = 57
+PHY-1001 : End global iterations; 0.754770s wall, 0.937500s user + 0.046875s system = 0.984375s CPU (130.4%)
+
+PHY-1001 : Congestion index: top1 = 82.67, top5 = 63.52, top10 = 54.15, top15 = 48.00.
+PHY-3001 : End congestion estimation; 0.973939s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (121.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20482 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.843718s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160564
+PHY-3002 : Step(213): len = 647265, overlap = 70.1875
+PHY-3002 : Step(214): len = 647487, overlap = 66.7188
+PHY-3002 : Step(215): len = 647836, overlap = 66.9062
+PHY-3002 : Step(216): len = 646593, overlap = 51.8438
+PHY-3002 : Step(217): len = 644011, overlap = 47.4688
+PHY-3002 : Step(218): len = 640585, overlap = 47.3438
+PHY-3002 : Step(219): len = 637009, overlap = 48.1875
+PHY-3002 : Step(220): len = 634736, overlap = 46.9688
+PHY-3002 : Step(221): len = 632511, overlap = 35.875
+PHY-3002 : Step(222): len = 631703, overlap = 31.625
+PHY-3002 : Step(223): len = 629402, overlap = 31
+PHY-3002 : Step(224): len = 629109, overlap = 29.1562
+PHY-3002 : Step(225): len = 626622, overlap = 30.0938
+PHY-3002 : Step(226): len = 626474, overlap = 28.6875
+PHY-3002 : Step(227): len = 625045, overlap = 29.1562
+PHY-3002 : Step(228): len = 624351, overlap = 29.125
+PHY-3002 : Step(229): len = 623127, overlap = 29.0312
+PHY-3002 : Step(230): len = 622968, overlap = 29.6875
+PHY-3002 : Step(231): len = 621511, overlap = 29.2812
+PHY-3002 : Step(232): len = 621448, overlap = 28.2188
+PHY-3002 : Step(233): len = 621025, overlap = 28.3438
+PHY-3002 : Step(234): len = 621188, overlap = 26.6562
+PHY-3002 : Step(235): len = 621094, overlap = 30.8438
+PHY-3002 : Step(236): len = 621539, overlap = 35.9375
+PHY-3002 : Step(237): len = 621457, overlap = 38.75
+PHY-3002 : Step(238): len = 622156, overlap = 38.4375
+PHY-3002 : Step(239): len = 622422, overlap = 41.6562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000321127
+PHY-3002 : Step(240): len = 625043, overlap = 43.0938
+PHY-3002 : Step(241): len = 626356, overlap = 43.125
+PHY-3002 : Step(242): len = 628819, overlap = 43.0625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000532704
+PHY-3002 : Step(243): len = 634926, overlap = 44.4062
+PHY-3002 : Step(244): len = 643696, overlap = 42.375
+PHY-3002 : Step(245): len = 654024, overlap = 42.2188
+PHY-3002 : Step(246): len = 660010, overlap = 43.1875
+PHY-3002 : Step(247): len = 663203, overlap = 43.875
+PHY-3002 : Step(248): len = 662520, overlap = 43.8438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 78/20660.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 748992, over cnt = 2723(7%), over = 12417, worst = 38
+PHY-1001 : End global iterations; 1.686375s wall, 2.156250s user + 0.031250s system = 2.187500s CPU (129.7%)
+
+PHY-1001 : Congestion index: top1 = 85.52, top5 = 67.49, top10 = 59.10, top15 = 53.75.
+PHY-3001 : End congestion estimation; 1.999337s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (125.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20482 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.346439s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000112673
+PHY-3002 : Step(249): len = 654775, overlap = 245.281
+PHY-3002 : Step(250): len = 656652, overlap = 191.906
+PHY-3002 : Step(251): len = 646142, overlap = 182.594
+PHY-3002 : Step(252): len = 639662, overlap = 172.188
+PHY-3002 : Step(253): len = 635363, overlap = 166.625
+PHY-3002 : Step(254): len = 633511, overlap = 147.5
+PHY-3002 : Step(255): len = 629147, overlap = 132.594
+PHY-3002 : Step(256): len = 626295, overlap = 120.531
+PHY-3002 : Step(257): len = 623983, overlap = 115.188
+PHY-3002 : Step(258): len = 620720, overlap = 111
+PHY-3002 : Step(259): len = 617848, overlap = 107.781
+PHY-3002 : Step(260): len = 615105, overlap = 107.594
+PHY-3002 : Step(261): len = 613066, overlap = 102.469
+PHY-3002 : Step(262): len = 611021, overlap = 105.688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000225346
+PHY-3002 : Step(263): len = 611566, overlap = 103.031
+PHY-3002 : Step(264): len = 614105, overlap = 99.3125
+PHY-3002 : Step(265): len = 618646, overlap = 97.5938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000450693
+PHY-3002 : Step(266): len = 622113, overlap = 89.5
+PHY-3002 : Step(267): len = 625425, overlap = 86.4062
+PHY-3002 : Step(268): len = 630637, overlap = 84.7812
+PHY-3002 : Step(269): len = 634893, overlap = 86.7812
+PHY-3002 : Step(270): len = 638480, overlap = 82.5625
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84758, tnet num: 20482, tinst num: 18081, tnode num: 115301, tedge num: 135302.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.436236s wall, 1.390625s user + 0.046875s system = 1.437500s CPU (100.1%)
+
+RUN-1004 : used memory is 577 MB, reserved memory is 567 MB, peak memory is 712 MB
+OPT-1001 : Total overflow 409.12 peak overflow 5.44
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 740/20660.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738376, over cnt = 3052(8%), over = 10934, worst = 32
+PHY-1001 : End global iterations; 1.249632s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (145.0%)
+
+PHY-1001 : Congestion index: top1 = 72.50, top5 = 58.86, top10 = 52.38, top15 = 48.42.
+PHY-1001 : End incremental global routing; 1.588580s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (135.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20482 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.921039s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.1%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17952 has valid locations, 292 needs to be replaced
+PHY-3001 : design contains 18329 instances, 7784 luts, 9324 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6137 pins
+PHY-3001 : Found 1252 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 660699
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16950/20908.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753496, over cnt = 3082(8%), over = 10995, worst = 32
+PHY-1001 : End global iterations; 0.247650s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (138.8%)
+
+PHY-1001 : Congestion index: top1 = 72.44, top5 = 58.84, top10 = 52.53, top15 = 48.70.
+PHY-3001 : End congestion estimation; 0.521264s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (116.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85756, tnet num: 20730, tinst num: 18329, tnode num: 116799, tedge num: 136802.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.483063s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (100.1%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 624 MB, peak memory is 717 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20730 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.539088s wall, 2.484375s user + 0.062500s system = 2.546875s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(271): len = 659604, overlap = 0.125
+PHY-3002 : Step(272): len = 659112, overlap = 0.1875
+PHY-3002 : Step(273): len = 658684, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17012/20908.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 750600, over cnt = 3107(8%), over = 11064, worst = 32
+PHY-1001 : End global iterations; 0.198080s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (157.8%)
+
+PHY-1001 : Congestion index: top1 = 73.19, top5 = 59.52, top10 = 53.01, top15 = 49.11.
+PHY-3001 : End congestion estimation; 0.448882s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (125.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20730 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.944957s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000439245
+PHY-3002 : Step(274): len = 658420, overlap = 84.5312
+PHY-3002 : Step(275): len = 658563, overlap = 84.7812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000878489
+PHY-3002 : Step(276): len = 658915, overlap = 84.125
+PHY-3002 : Step(277): len = 659497, overlap = 84.7188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00175698
+PHY-3002 : Step(278): len = 659750, overlap = 84.3125
+PHY-3002 : Step(279): len = 660056, overlap = 84.0312
+PHY-3001 : Final: Len = 660056, Over = 84.0312
+PHY-3001 : End incremental placement; 5.178611s wall, 5.656250s user + 0.312500s system = 5.968750s CPU (115.3%)
+
+OPT-1001 : Total overflow 414.28 peak overflow 5.44
+OPT-1001 : End high-fanout net optimization; 8.251913s wall, 9.250000s user + 0.343750s system = 9.593750s CPU (116.3%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 713, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16966/20908.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753200, over cnt = 3014(8%), over = 10026, worst = 32
+PHY-1002 : len = 809096, over cnt = 1969(5%), over = 4504, worst = 16
+PHY-1002 : len = 836480, over cnt = 1187(3%), over = 2418, worst = 16
+PHY-1002 : len = 854560, over cnt = 704(2%), over = 1331, worst = 16
+PHY-1002 : len = 879320, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.753861s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (139.0%)
+
+PHY-1001 : Congestion index: top1 = 58.86, top5 = 51.85, top10 = 48.08, top15 = 45.60.
+OPT-1001 : End congestion update; 2.013081s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (133.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20730 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.789422s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 129 cells processed and 19750 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 62 cells processed and 5750 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 10 cells processed and 900 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.211914s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (121.1%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 692, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16948/20910.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 878776, over cnt = 112(0%), over = 166, worst = 7
+PHY-1002 : len = 878344, over cnt = 59(0%), over = 73, worst = 2
+PHY-1002 : len = 878744, over cnt = 30(0%), over = 36, worst = 2
+PHY-1002 : len = 879432, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 879568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.727942s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (109.5%)
+
+PHY-1001 : Congestion index: top1 = 58.88, top5 = 51.68, top10 = 47.96, top15 = 45.50.
+OPT-1001 : End congestion update; 0.994993s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (105.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20732 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.783561s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (97.7%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 24 cells processed and 4250 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.902326s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (101.8%)
+
+OPT-1001 : Current memory(MB): used = 708, reserve = 704, peak = 735.
+OPT-1001 : End physical optimization; 15.109999s wall, 16.890625s user + 0.390625s system = 17.281250s CPU (114.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7784 LUT to BLE ...
+SYN-4008 : Packed 7784 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6179 remaining SEQ's ...
+SYN-4005 : Packed 3999 SEQ with LUT/SLICE
+SYN-4006 : 935 single LUT's are left
+SYN-4006 : 2180 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9964/13739 primitive instances ...
+PHY-3001 : End packing; 1.693809s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6744 instances
+RUN-1001 : 3298 mslices, 3298 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17902 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10023 nets have 2 pins
+RUN-1001 : 6484 nets have [3 - 5] pins
+RUN-1001 : 764 nets have [6 - 10] pins
+RUN-1001 : 288 nets have [11 - 20] pins
+RUN-1001 : 311 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6742 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3557 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 670753, Over = 219.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7629/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825496, over cnt = 2067(5%), over = 3325, worst = 8
+PHY-1002 : len = 834248, over cnt = 1293(3%), over = 1741, worst = 8
+PHY-1002 : len = 846048, over cnt = 544(1%), over = 693, worst = 6
+PHY-1002 : len = 855232, over cnt = 104(0%), over = 140, worst = 5
+PHY-1002 : len = 857712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.873837s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (134.2%)
+
+PHY-1001 : Congestion index: top1 = 59.25, top5 = 51.85, top10 = 47.91, top15 = 45.28.
+PHY-3001 : End congestion estimation; 2.288986s wall, 2.921875s user + 0.015625s system = 2.937500s CPU (128.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72089, tnet num: 17724, tinst num: 6742, tnode num: 94574, tedge num: 120039.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.596098s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (99.9%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 628 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.439992s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.37681e-05
+PHY-3002 : Step(280): len = 658866, overlap = 224.5
+PHY-3002 : Step(281): len = 653248, overlap = 231.75
+PHY-3002 : Step(282): len = 649194, overlap = 239.75
+PHY-3002 : Step(283): len = 645785, overlap = 234.25
+PHY-3002 : Step(284): len = 642855, overlap = 228
+PHY-3002 : Step(285): len = 640656, overlap = 234.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000107536
+PHY-3002 : Step(286): len = 643317, overlap = 225.75
+PHY-3002 : Step(287): len = 647141, overlap = 219
+PHY-3002 : Step(288): len = 647861, overlap = 219.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000215073
+PHY-3002 : Step(289): len = 656192, overlap = 203.75
+PHY-3002 : Step(290): len = 662951, overlap = 197.25
+PHY-3002 : Step(291): len = 661814, overlap = 198
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.383147s wall, 0.328125s user + 0.562500s system = 0.890625s CPU (232.4%)
+
+PHY-3001 : Trial Legalized: Len = 749098
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1011/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865048, over cnt = 2653(7%), over = 4400, worst = 7
+PHY-1002 : len = 879816, over cnt = 1694(4%), over = 2500, worst = 7
+PHY-1002 : len = 897400, over cnt = 742(2%), over = 1097, worst = 6
+PHY-1002 : len = 909744, over cnt = 371(1%), over = 533, worst = 5
+PHY-1002 : len = 915152, over cnt = 152(0%), over = 231, worst = 5
+PHY-1001 : End global iterations; 2.359320s wall, 3.296875s user + 0.015625s system = 3.312500s CPU (140.4%)
+
+PHY-1001 : Congestion index: top1 = 56.55, top5 = 50.84, top10 = 47.64, top15 = 45.63.
+PHY-3001 : End congestion estimation; 2.821950s wall, 3.734375s user + 0.031250s system = 3.765625s CPU (133.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.855997s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000166098
+PHY-3002 : Step(292): len = 719876, overlap = 37.75
+PHY-3002 : Step(293): len = 703515, overlap = 60
+PHY-3002 : Step(294): len = 688616, overlap = 89.25
+PHY-3002 : Step(295): len = 681313, overlap = 101.25
+PHY-3002 : Step(296): len = 676360, overlap = 117.75
+PHY-3002 : Step(297): len = 673678, overlap = 125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000332196
+PHY-3002 : Step(298): len = 678703, overlap = 122
+PHY-3002 : Step(299): len = 682862, overlap = 126.5
+PHY-3002 : Step(300): len = 682538, overlap = 126.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000664392
+PHY-3002 : Step(301): len = 686212, overlap = 126.25
+PHY-3002 : Step(302): len = 693154, overlap = 131.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033606s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (93.0%)
+
+PHY-3001 : Legalized: Len = 721009, Over = 0
+PHY-3001 : Spreading special nets. 463 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.098841s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (94.8%)
+
+PHY-3001 : 671 instances has been re-located, deltaX = 181, deltaY = 405, maxDist = 3.
+PHY-3001 : Final: Len = 732345, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72089, tnet num: 17724, tinst num: 6745, tnode num: 94574, tedge num: 120039.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.830497s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (99.0%)
+
+RUN-1004 : used memory is 634 MB, reserved memory is 653 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4490/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861016, over cnt = 2429(6%), over = 3874, worst = 7
+PHY-1002 : len = 874600, over cnt = 1390(3%), over = 1967, worst = 6
+PHY-1002 : len = 892952, over cnt = 374(1%), over = 509, worst = 5
+PHY-1002 : len = 898872, over cnt = 73(0%), over = 86, worst = 3
+PHY-1002 : len = 900592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.919298s wall, 2.734375s user + 0.046875s system = 2.781250s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 54.61, top5 = 48.62, top10 = 45.72, top15 = 43.81.
+PHY-1001 : End incremental global routing; 2.291126s wall, 3.109375s user + 0.046875s system = 3.156250s CPU (137.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.843544s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.0%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 20 needs to be replaced
+PHY-3001 : design contains 6761 instances, 6612 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3628 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 736014
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16356/17927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905024, over cnt = 70(0%), over = 84, worst = 5
+PHY-1002 : len = 904952, over cnt = 52(0%), over = 57, worst = 3
+PHY-1002 : len = 905408, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 905504, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.578555s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (105.3%)
+
+PHY-1001 : Congestion index: top1 = 54.74, top5 = 48.70, top10 = 45.82, top15 = 43.91.
+PHY-3001 : End congestion estimation; 0.886707s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (104.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72246, tnet num: 17749, tinst num: 6761, tnode num: 94771, tedge num: 120245.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.873125s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.1%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 667 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.739839s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(303): len = 734522, overlap = 0.25
+PHY-3002 : Step(304): len = 734039, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16339/17927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902320, over cnt = 55(0%), over = 62, worst = 3
+PHY-1002 : len = 902360, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 902456, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 902624, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.584166s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 54.70, top5 = 48.65, top10 = 45.74, top15 = 43.88.
+PHY-3001 : End congestion estimation; 0.887279s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (103.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.860656s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000209964
+PHY-3002 : Step(305): len = 734126, overlap = 2
+PHY-3002 : Step(306): len = 734224, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005621s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 734516, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059744s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 734666, Over = 0
+PHY-3001 : End incremental placement; 5.831396s wall, 5.953125s user + 0.093750s system = 6.046875s CPU (103.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.478840s wall, 10.421875s user + 0.140625s system = 10.562500s CPU (111.4%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 723, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16326/17927.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903592, over cnt = 38(0%), over = 43, worst = 4
+PHY-1002 : len = 903664, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 903696, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 903728, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.609182s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 54.63, top5 = 48.60, top10 = 45.69, top15 = 43.82.
+OPT-1001 : End congestion update; 0.914370s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (105.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17749 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.724588s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.2%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6673 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6761 instances, 6612 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3628 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 741078, Over = 0
+PHY-3001 : Spreading special nets. 27 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063481s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.5%)
+
+PHY-3001 : 41 instances has been re-located, deltaX = 33, deltaY = 33, maxDist = 3.
+PHY-3001 : Final: Len = 742200, Over = 0
+PHY-3001 : End incremental legalization; 0.404644s wall, 0.421875s user + 0.046875s system = 0.468750s CPU (115.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 55 cells processed and 20644 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6673 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6761 instances, 6612 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3628 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 741814, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064293s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 14, deltaY = 16, maxDist = 2.
+PHY-3001 : Final: Len = 742390, Over = 0
+PHY-3001 : End incremental legalization; 0.420776s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.3%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 37 cells processed and 3467 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6684 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6772 instances, 6623 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 506 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744255, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059770s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 7, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 744559, Over = 0
+PHY-3001 : End incremental legalization; 0.382306s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.2%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 9 cells processed and 1550 slack improved
+OPT-1001 : End bottleneck based optimization; 3.421649s wall, 3.562500s user + 0.046875s system = 3.609375s CPU (105.5%)
+
+OPT-1001 : Current memory(MB): used = 727, reserve = 725, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15871/17934.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912768, over cnt = 225(0%), over = 296, worst = 5
+PHY-1002 : len = 913248, over cnt = 120(0%), over = 138, worst = 3
+PHY-1002 : len = 914096, over cnt = 44(0%), over = 49, worst = 3
+PHY-1002 : len = 915016, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 915048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.844201s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (112.9%)
+
+PHY-1001 : Congestion index: top1 = 54.31, top5 = 48.81, top10 = 45.89, top15 = 43.95.
+OPT-1001 : End congestion update; 1.165464s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (109.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.750193s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6684 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6772 instances, 6623 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 506 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744347, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059171s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.6%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 3.
+PHY-3001 : Final: Len = 744585, Over = 0
+PHY-3001 : End incremental legalization; 0.405665s wall, 0.406250s user + 0.046875s system = 0.453125s CPU (111.7%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 1350 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.451882s wall, 2.562500s user + 0.046875s system = 2.609375s CPU (106.4%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 730, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.744000s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16321/17934.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914672, over cnt = 43(0%), over = 55, worst = 4
+PHY-1002 : len = 914696, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 914832, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 914856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.622858s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (102.9%)
+
+PHY-1001 : Congestion index: top1 = 54.46, top5 = 48.87, top10 = 45.94, top15 = 43.99.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.705676s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.034483
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 221ps with logic level 1
+OPT-1001 : End physical optimization; 19.853782s wall, 21.015625s user + 0.265625s system = 21.281250s CPU (107.2%)
+
+RUN-1003 : finish command "place" in 64.210125s wall, 93.031250s user + 6.109375s system = 99.140625s CPU (154.4%)
+
+RUN-1004 : used memory is 597 MB, reserved memory is 601 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.687448s wall, 2.890625s user + 0.046875s system = 2.937500s CPU (174.1%)
+
+RUN-1004 : used memory is 598 MB, reserved memory is 601 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6774 instances
+RUN-1001 : 3315 mslices, 3308 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17934 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10010 nets have 2 pins
+RUN-1001 : 6501 nets have [3 - 5] pins
+RUN-1001 : 782 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 323 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72349, tnet num: 17756, tinst num: 6772, tnode num: 94905, tedge num: 120392.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.573169s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.3%)
+
+RUN-1004 : used memory is 597 MB, reserved memory is 595 MB, peak memory is 740 MB
+PHY-1001 : 3315 mslices, 3308 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17756 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847984, over cnt = 2706(7%), over = 4355, worst = 8
+PHY-1002 : len = 863472, over cnt = 1649(4%), over = 2373, worst = 7
+PHY-1002 : len = 888296, over cnt = 378(1%), over = 496, worst = 5
+PHY-1002 : len = 896248, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 896576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.105238s wall, 4.062500s user + 0.031250s system = 4.093750s CPU (131.8%)
+
+PHY-1001 : Congestion index: top1 = 53.75, top5 = 48.41, top10 = 45.36, top15 = 43.44.
+PHY-1001 : End global routing; 3.435801s wall, 4.406250s user + 0.031250s system = 4.437500s CPU (129.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 707, reserve = 718, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 989, peak = 982.
+PHY-1001 : End build detailed router design. 4.065703s wall, 4.015625s user + 0.046875s system = 4.062500s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 274192, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.195665s wall, 5.187500s user + 0.000000s system = 5.187500s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 274248, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.423614s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1025, peak = 1017.
+PHY-1001 : End phase 1; 5.631216s wall, 5.625000s user + 0.000000s system = 5.625000s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.32604e+06, over cnt = 1515(0%), over = 1519, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1040, peak = 1033.
+PHY-1001 : End initial routed; 27.295521s wall, 56.359375s user + 0.218750s system = 56.578125s CPU (207.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16857(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.238380s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1060, peak = 1053.
+PHY-1001 : End phase 2; 30.533964s wall, 59.578125s user + 0.234375s system = 59.812500s CPU (195.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.139114s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.1%)
+
+PHY-1022 : len = 2.32604e+06, over cnt = 1515(0%), over = 1519, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.433772s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.30113e+06, over cnt = 551(0%), over = 551, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.119495s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (182.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.30126e+06, over cnt = 95(0%), over = 95, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.546938s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (142.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.30217e+06, over cnt = 15(0%), over = 15, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.293260s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (117.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.30235e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 4; 0.236443s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16857(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.180020s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 465 feed throughs used by 365 nets
+PHY-1001 : End commit to database; 2.208598s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1155, reserve = 1165, peak = 1155.
+PHY-1001 : End phase 3; 8.408467s wall, 9.562500s user + 0.015625s system = 9.578125s CPU (113.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.131061s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.3%)
+
+PHY-1022 : len = 2.30235e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.364776s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16857(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.224870s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (99.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 465 feed throughs used by 365 nets
+PHY-1001 : End commit to database; 2.303497s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1173, peak = 1162.
+PHY-1001 : End phase 4; 5.917667s wall, 5.890625s user + 0.015625s system = 5.906250s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.30235e+06
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1178, peak = 1167.
+PHY-1001 : End export database. 0.060036s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.1%)
+
+PHY-1001 : End detail routing; 55.009537s wall, 85.109375s user + 0.328125s system = 85.437500s CPU (155.3%)
+
+RUN-1003 : finish command "route" in 61.089176s wall, 92.093750s user + 0.421875s system = 92.515625s CPU (151.4%)
+
+RUN-1004 : used memory is 1027 MB, reserved memory is 1032 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10242 out of 19600 52.26%
+#reg 9520 out of 19600 48.57%
+#le 12386
+ #lut only 2866 out of 12386 23.14%
+ #reg only 2144 out of 12386 17.31%
+ #lut® 7376 out of 12386 59.55%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1782
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1443
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1326
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 920
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 134
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_sot_min/reg1_syn_316.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg1_syn_182.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P147 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P110 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P106 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P146 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P82 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P143 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P107 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12386 |9215 |1027 |9554 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |569 |462 |23 |461 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |107 |92 |4 |95 |4 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| U_crc16_24b |crc16_24b |39 |39 |0 |22 |0 |0 |
+| exdev_ctl_a |exdev_ctl |767 |403 |96 |591 |0 |0 |
+| u_ADconfig |AD_config |186 |120 |25 |141 |0 |0 |
+| u_gen_sp |gen_sp |256 |146 |71 |125 |0 |0 |
+| exdev_ctl_b |exdev_ctl |736 |322 |96 |558 |0 |0 |
+| u_ADconfig |AD_config |177 |114 |25 |132 |0 |0 |
+| u_gen_sp |gen_sp |251 |149 |71 |118 |0 |0 |
+| sampling_fe_a |sampling_fe |2874 |2323 |306 |2064 |25 |0 |
+| u0_soft_n |cdc_sync |7 |1 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |123 |17 |154 |0 |0 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_sort |sort |2656 |2187 |289 |1876 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2223 |1839 |253 |1518 |22 |0 |
+| channelPart |channel_part_8478 |133 |126 |3 |124 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |47 |0 |0 |
+| ram_switch |ram_switch |1739 |1439 |197 |1131 |0 |0 |
+| adc_addr_gen |adc_addr_gen |224 |195 |27 |127 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |11 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |23 |20 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |918 |647 |170 |628 |0 |0 |
+| ram_switch_state |ram_switch_state |597 |597 |0 |376 |0 |0 |
+| read_ram_i |read_ram |262 |203 |44 |188 |0 |0 |
+| read_ram_addr |read_ram_addr |213 |173 |40 |150 |0 |0 |
+| read_ram_data |read_ram_data |46 |28 |4 |35 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |315 |247 |36 |268 |3 |0 |
+| u0_soft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3269 |2603 |349 |2075 |25 |1 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |196 |120 |17 |165 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort_rev |3038 |2477 |332 |1875 |25 |1 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2616 |2161 |290 |1533 |22 |1 |
+| channelPart |channel_part_8478 |141 |131 |3 |130 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |41 |0 |1 |
+| ram_switch |ram_switch |2031 |1717 |197 |1124 |0 |0 |
+| adc_addr_gen |adc_addr_gen |207 |180 |27 |101 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |14 |11 |3 |6 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |18 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |6 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 |
+| insert |insert |984 |697 |170 |677 |0 |0 |
+| ram_switch_state |ram_switch_state |840 |840 |0 |346 |0 |0 |
+| read_ram_i |read_ram_rev |352 |237 |81 |204 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |292 |207 |73 |160 |0 |0 |
+| read_ram_data |read_ram_data_rev |60 |30 |8 |44 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9948
+ #2 2 4303
+ #3 3 1672
+ #4 4 523
+ #5 5-10 815
+ #6 11-50 562
+ #7 51-100 15
+ #8 >500 1
+ Average 2.75
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.025952s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (172.8%)
+
+RUN-1004 : used memory is 1028 MB, reserved memory is 1033 MB, peak memory is 1167 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72349, tnet num: 17756, tinst num: 6772, tnode num: 94905, tedge num: 120392.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.570558s wall, 1.546875s user + 0.015625s system = 1.562500s CPU (99.5%)
+
+RUN-1004 : used memory is 1032 MB, reserved memory is 1037 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17756 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.457841s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.7%)
+
+RUN-1004 : used memory is 1071 MB, reserved memory is 1076 MB, peak memory is 1167 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6772
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17934, pip num: 169848
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 465
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3244 valid insts, and 472951 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.605028s wall, 63.640625s user + 0.140625s system = 63.781250s CPU (664.0%)
+
+RUN-1004 : used memory is 1254 MB, reserved memory is 1257 MB, peak memory is 1369 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_184627.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_190601.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_190601.log
new file mode 100644
index 0000000..ca7360d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_190601.log
@@ -0,0 +1,2019 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 19:06:01 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(886)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(895)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(919)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(921)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(927)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(930)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1101)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1190)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1491)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1502)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1520)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1702)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2098)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.226470s wall, 2.078125s user + 0.140625s system = 2.218750s CPU (99.7%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 315 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2227 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2067 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17980 instances
+RUN-0007 : 7669 luts, 9088 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20564 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13074 nets have 2 pins
+RUN-1001 : 6454 nets have [3 - 5] pins
+RUN-1001 : 615 nets have [6 - 10] pins
+RUN-1001 : 182 nets have [11 - 20] pins
+RUN-1001 : 169 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1987
+RUN-1001 : No | Yes | No | 3495
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17978 instances, 7669 luts, 9088 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 5941 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83994, tnet num: 20386, tinst num: 17978, tnode num: 114231, tedge num: 133966.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.169266s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (100.2%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 514 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.963365s wall, 1.906250s user + 0.046875s system = 1.953125s CPU (99.5%)
+
+PHY-3001 : Found 1251 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.04908e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17978.
+PHY-3001 : Level 1 #clusters 2037.
+PHY-3001 : End clustering; 0.124928s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (100.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35679e+06, overlap = 455.75
+PHY-3002 : Step(2): len = 1.2376e+06, overlap = 484.312
+PHY-3002 : Step(3): len = 861926, overlap = 618.406
+PHY-3002 : Step(4): len = 797981, overlap = 638.938
+PHY-3002 : Step(5): len = 624359, overlap = 797.781
+PHY-3002 : Step(6): len = 556541, overlap = 830.438
+PHY-3002 : Step(7): len = 468491, overlap = 903.531
+PHY-3002 : Step(8): len = 430067, overlap = 937.531
+PHY-3002 : Step(9): len = 381727, overlap = 987.438
+PHY-3002 : Step(10): len = 366088, overlap = 1008.5
+PHY-3002 : Step(11): len = 325707, overlap = 1093.19
+PHY-3002 : Step(12): len = 303227, overlap = 1106.53
+PHY-3002 : Step(13): len = 268494, overlap = 1171.72
+PHY-3002 : Step(14): len = 254630, overlap = 1235.91
+PHY-3002 : Step(15): len = 229072, overlap = 1285.28
+PHY-3002 : Step(16): len = 216769, overlap = 1348.34
+PHY-3002 : Step(17): len = 192324, overlap = 1359.75
+PHY-3002 : Step(18): len = 175850, overlap = 1403.22
+PHY-3002 : Step(19): len = 157862, overlap = 1409.28
+PHY-3002 : Step(20): len = 146980, overlap = 1436.84
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.15911e-06
+PHY-3002 : Step(21): len = 150282, overlap = 1406.28
+PHY-3002 : Step(22): len = 184820, overlap = 1283.34
+PHY-3002 : Step(23): len = 192659, overlap = 1197.72
+PHY-3002 : Step(24): len = 201756, overlap = 1151.06
+PHY-3002 : Step(25): len = 199614, overlap = 1095.56
+PHY-3002 : Step(26): len = 198843, overlap = 1075.75
+PHY-3002 : Step(27): len = 195449, overlap = 1057.94
+PHY-3002 : Step(28): len = 194225, overlap = 1038.84
+PHY-3002 : Step(29): len = 191448, overlap = 1028.72
+PHY-3002 : Step(30): len = 188957, overlap = 1014.09
+PHY-3002 : Step(31): len = 186378, overlap = 1006.09
+PHY-3002 : Step(32): len = 184035, overlap = 1022.66
+PHY-3002 : Step(33): len = 182444, overlap = 1017.97
+PHY-3002 : Step(34): len = 180505, overlap = 1010.72
+PHY-3002 : Step(35): len = 180281, overlap = 1025.38
+PHY-3002 : Step(36): len = 179980, overlap = 1021.97
+PHY-3002 : Step(37): len = 179199, overlap = 1023.12
+PHY-3002 : Step(38): len = 178845, overlap = 1027.75
+PHY-3002 : Step(39): len = 178080, overlap = 1032.16
+PHY-3002 : Step(40): len = 176762, overlap = 1052.84
+PHY-3002 : Step(41): len = 175728, overlap = 1072.97
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.31822e-06
+PHY-3002 : Step(42): len = 178978, overlap = 1048.16
+PHY-3002 : Step(43): len = 189004, overlap = 1022.53
+PHY-3002 : Step(44): len = 194136, overlap = 1013.72
+PHY-3002 : Step(45): len = 199127, overlap = 1037.47
+PHY-3002 : Step(46): len = 200211, overlap = 1030.03
+PHY-3002 : Step(47): len = 200103, overlap = 1022.59
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.63645e-06
+PHY-3002 : Step(48): len = 207933, overlap = 1001.72
+PHY-3002 : Step(49): len = 222733, overlap = 940.781
+PHY-3002 : Step(50): len = 233389, overlap = 864.656
+PHY-3002 : Step(51): len = 243972, overlap = 796.094
+PHY-3002 : Step(52): len = 249315, overlap = 739.281
+PHY-3002 : Step(53): len = 252700, overlap = 688.531
+PHY-3002 : Step(54): len = 253065, overlap = 664.406
+PHY-3002 : Step(55): len = 253564, overlap = 661.125
+PHY-3002 : Step(56): len = 254064, overlap = 654.25
+PHY-3002 : Step(57): len = 253829, overlap = 667
+PHY-3002 : Step(58): len = 252573, overlap = 659.719
+PHY-3002 : Step(59): len = 251775, overlap = 672
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.27289e-06
+PHY-3002 : Step(60): len = 266144, overlap = 619.688
+PHY-3002 : Step(61): len = 283522, overlap = 545.156
+PHY-3002 : Step(62): len = 292302, overlap = 530.031
+PHY-3002 : Step(63): len = 296880, overlap = 514.719
+PHY-3002 : Step(64): len = 295320, overlap = 507.25
+PHY-3002 : Step(65): len = 295024, overlap = 516.562
+PHY-3002 : Step(66): len = 293175, overlap = 501.156
+PHY-3002 : Step(67): len = 293610, overlap = 499.281
+PHY-3002 : Step(68): len = 293326, overlap = 506.344
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.85458e-05
+PHY-3002 : Step(69): len = 313496, overlap = 478.281
+PHY-3002 : Step(70): len = 329584, overlap = 451.719
+PHY-3002 : Step(71): len = 333249, overlap = 428.656
+PHY-3002 : Step(72): len = 334702, overlap = 414.844
+PHY-3002 : Step(73): len = 333092, overlap = 406.469
+PHY-3002 : Step(74): len = 334234, overlap = 399
+PHY-3002 : Step(75): len = 332373, overlap = 389.906
+PHY-3002 : Step(76): len = 333378, overlap = 373.594
+PHY-3002 : Step(77): len = 333444, overlap = 359.25
+PHY-3002 : Step(78): len = 334886, overlap = 366.281
+PHY-3002 : Step(79): len = 334718, overlap = 361.281
+PHY-3002 : Step(80): len = 334478, overlap = 363.875
+PHY-3002 : Step(81): len = 333965, overlap = 372.125
+PHY-3002 : Step(82): len = 334061, overlap = 380.938
+PHY-3002 : Step(83): len = 333540, overlap = 387.25
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.70916e-05
+PHY-3002 : Step(84): len = 352508, overlap = 370.188
+PHY-3002 : Step(85): len = 366396, overlap = 358.938
+PHY-3002 : Step(86): len = 366897, overlap = 345.406
+PHY-3002 : Step(87): len = 368412, overlap = 340.688
+PHY-3002 : Step(88): len = 368024, overlap = 330.594
+PHY-3002 : Step(89): len = 370906, overlap = 336.406
+PHY-3002 : Step(90): len = 370313, overlap = 318.938
+PHY-3002 : Step(91): len = 373073, overlap = 304.906
+PHY-3002 : Step(92): len = 375357, overlap = 305.75
+PHY-3002 : Step(93): len = 378295, overlap = 311.031
+PHY-3002 : Step(94): len = 376693, overlap = 296.594
+PHY-3002 : Step(95): len = 377691, overlap = 299
+PHY-3002 : Step(96): len = 378040, overlap = 296.438
+PHY-3002 : Step(97): len = 378676, overlap = 286.594
+PHY-3002 : Step(98): len = 376079, overlap = 289.938
+PHY-3002 : Step(99): len = 375459, overlap = 290.469
+PHY-3002 : Step(100): len = 375300, overlap = 295.531
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.41831e-05
+PHY-3002 : Step(101): len = 391806, overlap = 267.75
+PHY-3002 : Step(102): len = 403165, overlap = 245.469
+PHY-3002 : Step(103): len = 400594, overlap = 257.438
+PHY-3002 : Step(104): len = 401421, overlap = 245.844
+PHY-3002 : Step(105): len = 405577, overlap = 236.219
+PHY-3002 : Step(106): len = 409142, overlap = 227.031
+PHY-3002 : Step(107): len = 407208, overlap = 229.969
+PHY-3002 : Step(108): len = 408778, overlap = 231.531
+PHY-3002 : Step(109): len = 410864, overlap = 216.688
+PHY-3002 : Step(110): len = 413058, overlap = 212.969
+PHY-3002 : Step(111): len = 410569, overlap = 207.562
+PHY-3002 : Step(112): len = 410275, overlap = 212.312
+PHY-3002 : Step(113): len = 411882, overlap = 204.625
+PHY-3002 : Step(114): len = 414009, overlap = 196.812
+PHY-3002 : Step(115): len = 410671, overlap = 195.219
+PHY-3002 : Step(116): len = 410619, overlap = 204.75
+PHY-3002 : Step(117): len = 411779, overlap = 205.906
+PHY-3002 : Step(118): len = 412750, overlap = 218.688
+PHY-3002 : Step(119): len = 409750, overlap = 219.344
+PHY-3002 : Step(120): len = 409267, overlap = 211.5
+PHY-3002 : Step(121): len = 410153, overlap = 223.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000148366
+PHY-3002 : Step(122): len = 423691, overlap = 202.5
+PHY-3002 : Step(123): len = 431488, overlap = 194.281
+PHY-3002 : Step(124): len = 430523, overlap = 199.25
+PHY-3002 : Step(125): len = 430851, overlap = 194.5
+PHY-3002 : Step(126): len = 433461, overlap = 184.625
+PHY-3002 : Step(127): len = 436999, overlap = 178.719
+PHY-3002 : Step(128): len = 436443, overlap = 183.188
+PHY-3002 : Step(129): len = 437196, overlap = 183.188
+PHY-3002 : Step(130): len = 438624, overlap = 175.594
+PHY-3002 : Step(131): len = 439856, overlap = 173.344
+PHY-3002 : Step(132): len = 438105, overlap = 182.188
+PHY-3002 : Step(133): len = 438298, overlap = 188.531
+PHY-3002 : Step(134): len = 439598, overlap = 179
+PHY-3002 : Step(135): len = 440537, overlap = 180.219
+PHY-3002 : Step(136): len = 439911, overlap = 182.531
+PHY-3002 : Step(137): len = 440751, overlap = 187
+PHY-3002 : Step(138): len = 442159, overlap = 177.969
+PHY-3002 : Step(139): len = 443447, overlap = 176.344
+PHY-3002 : Step(140): len = 442027, overlap = 181.969
+PHY-3002 : Step(141): len = 442290, overlap = 181.406
+PHY-3002 : Step(142): len = 443135, overlap = 165.844
+PHY-3002 : Step(143): len = 444329, overlap = 168.344
+PHY-3002 : Step(144): len = 443615, overlap = 173.188
+PHY-3002 : Step(145): len = 443773, overlap = 176
+PHY-3002 : Step(146): len = 443894, overlap = 178.219
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000289571
+PHY-3002 : Step(147): len = 456636, overlap = 167.781
+PHY-3002 : Step(148): len = 465781, overlap = 163.062
+PHY-3002 : Step(149): len = 464954, overlap = 169.281
+PHY-3002 : Step(150): len = 465345, overlap = 170.094
+PHY-3002 : Step(151): len = 469359, overlap = 165.969
+PHY-3002 : Step(152): len = 473104, overlap = 164.812
+PHY-3002 : Step(153): len = 472630, overlap = 162.5
+PHY-3002 : Step(154): len = 474079, overlap = 168.219
+PHY-3002 : Step(155): len = 476483, overlap = 164.438
+PHY-3002 : Step(156): len = 477723, overlap = 167.781
+PHY-3002 : Step(157): len = 475157, overlap = 172.844
+PHY-3002 : Step(158): len = 474557, overlap = 174.062
+PHY-3002 : Step(159): len = 475996, overlap = 169.75
+PHY-3002 : Step(160): len = 476996, overlap = 171.344
+PHY-3002 : Step(161): len = 475429, overlap = 169.281
+PHY-3002 : Step(162): len = 475186, overlap = 166.906
+PHY-3002 : Step(163): len = 476522, overlap = 174.25
+PHY-3002 : Step(164): len = 477535, overlap = 171.438
+PHY-3002 : Step(165): len = 476163, overlap = 167.875
+PHY-3002 : Step(166): len = 475986, overlap = 170.875
+PHY-3002 : Step(167): len = 476431, overlap = 169.031
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000565758
+PHY-3002 : Step(168): len = 485193, overlap = 172
+PHY-3002 : Step(169): len = 493982, overlap = 165.062
+PHY-3002 : Step(170): len = 494659, overlap = 150.969
+PHY-3002 : Step(171): len = 494961, overlap = 141.906
+PHY-3002 : Step(172): len = 497624, overlap = 147.25
+PHY-3002 : Step(173): len = 500094, overlap = 145
+PHY-3002 : Step(174): len = 499338, overlap = 141.469
+PHY-3002 : Step(175): len = 499410, overlap = 146.219
+PHY-3002 : Step(176): len = 500547, overlap = 142.531
+PHY-3002 : Step(177): len = 502205, overlap = 137.344
+PHY-3002 : Step(178): len = 501136, overlap = 137.656
+PHY-3002 : Step(179): len = 500653, overlap = 132.969
+PHY-3002 : Step(180): len = 501881, overlap = 131.312
+PHY-3002 : Step(181): len = 502858, overlap = 126.688
+PHY-3002 : Step(182): len = 501834, overlap = 124.688
+PHY-3002 : Step(183): len = 501780, overlap = 125.906
+PHY-3002 : Step(184): len = 503141, overlap = 130
+PHY-3002 : Step(185): len = 503631, overlap = 127.031
+PHY-3002 : Step(186): len = 502723, overlap = 123.438
+PHY-3002 : Step(187): len = 502404, overlap = 123.875
+PHY-3002 : Step(188): len = 503031, overlap = 122.656
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00108622
+PHY-3002 : Step(189): len = 507853, overlap = 119.062
+PHY-3002 : Step(190): len = 512818, overlap = 117.438
+PHY-3002 : Step(191): len = 514217, overlap = 109.844
+PHY-3002 : Step(192): len = 515220, overlap = 106.906
+PHY-3002 : Step(193): len = 516616, overlap = 106
+PHY-3002 : Step(194): len = 517688, overlap = 106.562
+PHY-3002 : Step(195): len = 517420, overlap = 113.625
+PHY-3002 : Step(196): len = 517731, overlap = 113.469
+PHY-3002 : Step(197): len = 519147, overlap = 114.938
+PHY-3002 : Step(198): len = 520060, overlap = 113.531
+PHY-3002 : Step(199): len = 519990, overlap = 109.656
+PHY-3002 : Step(200): len = 519985, overlap = 111.781
+PHY-3002 : Step(201): len = 520303, overlap = 110.344
+PHY-3002 : Step(202): len = 520470, overlap = 110.219
+PHY-3002 : Step(203): len = 520364, overlap = 111.375
+PHY-3002 : Step(204): len = 520460, overlap = 111.125
+PHY-3002 : Step(205): len = 520769, overlap = 111.688
+PHY-3002 : Step(206): len = 520769, overlap = 111.688
+PHY-3002 : Step(207): len = 520782, overlap = 111.125
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00183365
+PHY-3002 : Step(208): len = 523433, overlap = 113.344
+PHY-3002 : Step(209): len = 527780, overlap = 113.531
+PHY-3002 : Step(210): len = 528455, overlap = 112.031
+PHY-3002 : Step(211): len = 528832, overlap = 111.844
+PHY-3002 : Step(212): len = 530146, overlap = 110.906
+PHY-3002 : Step(213): len = 531092, overlap = 113.719
+PHY-3002 : Step(214): len = 531118, overlap = 114.031
+PHY-3002 : Step(215): len = 531288, overlap = 111.781
+PHY-3002 : Step(216): len = 532306, overlap = 111.781
+PHY-3002 : Step(217): len = 532901, overlap = 112.094
+PHY-3002 : Step(218): len = 532472, overlap = 107.969
+PHY-3002 : Step(219): len = 532387, overlap = 106.625
+PHY-3002 : Step(220): len = 533306, overlap = 103.875
+PHY-3002 : Step(221): len = 533886, overlap = 107.5
+PHY-3002 : Step(222): len = 533444, overlap = 102.312
+PHY-3002 : Step(223): len = 533444, overlap = 102.312
+PHY-3002 : Step(224): len = 533998, overlap = 102.688
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00296684
+PHY-3002 : Step(225): len = 535165, overlap = 101.094
+PHY-3002 : Step(226): len = 539668, overlap = 103.469
+PHY-3002 : Step(227): len = 542438, overlap = 98.25
+PHY-3002 : Step(228): len = 544185, overlap = 96.4375
+PHY-3002 : Step(229): len = 544332, overlap = 100.875
+PHY-3002 : Step(230): len = 544386, overlap = 102.656
+PHY-3002 : Step(231): len = 544630, overlap = 99
+PHY-3002 : Step(232): len = 544796, overlap = 97.875
+PHY-3002 : Step(233): len = 544971, overlap = 100.438
+PHY-3002 : Step(234): len = 545340, overlap = 100.438
+PHY-3002 : Step(235): len = 545858, overlap = 99.3125
+PHY-3002 : Step(236): len = 546157, overlap = 101.188
+PHY-3002 : Step(237): len = 546590, overlap = 100.25
+PHY-3002 : Step(238): len = 546788, overlap = 101.75
+PHY-3002 : Step(239): len = 546993, overlap = 100.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014191s wall, 0.000000s user + 0.062500s system = 0.062500s CPU (440.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736288, over cnt = 1679(4%), over = 7383, worst = 46
+PHY-1001 : End global iterations; 0.688604s wall, 0.906250s user + 0.046875s system = 0.953125s CPU (138.4%)
+
+PHY-1001 : Congestion index: top1 = 81.79, top5 = 62.49, top10 = 53.15, top15 = 47.20.
+PHY-3001 : End congestion estimation; 0.904303s wall, 1.093750s user + 0.062500s system = 1.156250s CPU (127.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.142579s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000170438
+PHY-3002 : Step(240): len = 664002, overlap = 64.125
+PHY-3002 : Step(241): len = 661577, overlap = 53.2812
+PHY-3002 : Step(242): len = 654851, overlap = 51.9375
+PHY-3002 : Step(243): len = 654352, overlap = 53.1875
+PHY-3002 : Step(244): len = 654350, overlap = 49.1875
+PHY-3002 : Step(245): len = 653117, overlap = 50.25
+PHY-3002 : Step(246): len = 650613, overlap = 50.5625
+PHY-3002 : Step(247): len = 648153, overlap = 46.4062
+PHY-3002 : Step(248): len = 647795, overlap = 36.625
+PHY-3002 : Step(249): len = 646882, overlap = 35.4062
+PHY-3002 : Step(250): len = 646571, overlap = 36.3438
+PHY-3002 : Step(251): len = 647343, overlap = 37.0312
+PHY-3002 : Step(252): len = 649235, overlap = 34.375
+PHY-3002 : Step(253): len = 648558, overlap = 36.2812
+PHY-3002 : Step(254): len = 649358, overlap = 42.6875
+PHY-3002 : Step(255): len = 648153, overlap = 43.9688
+PHY-3002 : Step(256): len = 647576, overlap = 46.6875
+PHY-3002 : Step(257): len = 645466, overlap = 44.6562
+PHY-3002 : Step(258): len = 644359, overlap = 45.0938
+PHY-3002 : Step(259): len = 642611, overlap = 46.4062
+PHY-3002 : Step(260): len = 641168, overlap = 45.9375
+PHY-3002 : Step(261): len = 639355, overlap = 46.9062
+PHY-3002 : Step(262): len = 637588, overlap = 44.875
+PHY-3002 : Step(263): len = 636183, overlap = 42.3438
+PHY-3002 : Step(264): len = 634830, overlap = 39.25
+PHY-3002 : Step(265): len = 633818, overlap = 38.8125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000340876
+PHY-3002 : Step(266): len = 636854, overlap = 38.625
+PHY-3002 : Step(267): len = 639779, overlap = 38.875
+PHY-3002 : Step(268): len = 647608, overlap = 37.3125
+PHY-3002 : Step(269): len = 652316, overlap = 37.9062
+PHY-3002 : Step(270): len = 654996, overlap = 36.9375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000681751
+PHY-3002 : Step(271): len = 657456, overlap = 36
+PHY-3002 : Step(272): len = 662393, overlap = 34.7812
+PHY-3002 : Step(273): len = 670475, overlap = 33.5312
+PHY-3002 : Step(274): len = 676341, overlap = 32.6875
+PHY-3002 : Step(275): len = 681293, overlap = 34.7812
+PHY-3002 : Step(276): len = 685567, overlap = 35.0312
+PHY-3002 : Step(277): len = 685418, overlap = 34.1562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 52/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 772424, over cnt = 2696(7%), over = 12465, worst = 74
+PHY-1001 : End global iterations; 1.587701s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (138.8%)
+
+PHY-1001 : Congestion index: top1 = 92.63, top5 = 71.06, top10 = 61.12, top15 = 55.27.
+PHY-3001 : End congestion estimation; 1.847103s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (132.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.914331s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000133693
+PHY-3002 : Step(278): len = 678336, overlap = 244.844
+PHY-3002 : Step(279): len = 677796, overlap = 193.812
+PHY-3002 : Step(280): len = 665861, overlap = 186.625
+PHY-3002 : Step(281): len = 660011, overlap = 175.312
+PHY-3002 : Step(282): len = 653751, overlap = 158.75
+PHY-3002 : Step(283): len = 649250, overlap = 138.719
+PHY-3002 : Step(284): len = 645498, overlap = 129.812
+PHY-3002 : Step(285): len = 643057, overlap = 119.688
+PHY-3002 : Step(286): len = 639320, overlap = 114.469
+PHY-3002 : Step(287): len = 635894, overlap = 111.969
+PHY-3002 : Step(288): len = 633524, overlap = 110.938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000267386
+PHY-3002 : Step(289): len = 634902, overlap = 107.344
+PHY-3002 : Step(290): len = 637497, overlap = 105.094
+PHY-3002 : Step(291): len = 641386, overlap = 98.9062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000534772
+PHY-3002 : Step(292): len = 645156, overlap = 93.625
+PHY-3002 : Step(293): len = 651534, overlap = 83.7812
+PHY-3002 : Step(294): len = 656188, overlap = 78.1875
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 83994, tnet num: 20386, tinst num: 17978, tnode num: 114231, tedge num: 133966.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.433939s wall, 1.437500s user + 0.000000s system = 1.437500s CPU (100.2%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 562 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 391.34 peak overflow 5.44
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 844/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 752640, over cnt = 3020(8%), over = 10565, worst = 22
+PHY-1001 : End global iterations; 1.223713s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (148.1%)
+
+PHY-1001 : Congestion index: top1 = 68.43, top5 = 56.59, top10 = 50.49, top15 = 46.86.
+PHY-1001 : End incremental global routing; 1.555022s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (136.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.890151s wall, 0.843750s user + 0.046875s system = 0.890625s CPU (100.1%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17846 has valid locations, 297 needs to be replaced
+PHY-3001 : design contains 18228 instances, 7764 luts, 9243 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6050 pins
+PHY-3001 : Found 1259 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 679338
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16866/20814.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 767016, over cnt = 3066(8%), over = 10621, worst = 22
+PHY-1001 : End global iterations; 0.235204s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (106.3%)
+
+PHY-1001 : Congestion index: top1 = 68.08, top5 = 56.54, top10 = 50.80, top15 = 47.23.
+PHY-3001 : End congestion estimation; 0.480471s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84989, tnet num: 20636, tinst num: 18228, tnode num: 115711, tedge num: 135456.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.447252s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.3%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 634 MB, peak memory is 711 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20636 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.410036s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(295): len = 678319, overlap = 0
+PHY-3002 : Step(296): len = 677782, overlap = 0
+PHY-3002 : Step(297): len = 677318, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16959/20814.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 764136, over cnt = 3064(8%), over = 10660, worst = 22
+PHY-1001 : End global iterations; 0.199646s wall, 0.234375s user + 0.109375s system = 0.343750s CPU (172.2%)
+
+PHY-1001 : Congestion index: top1 = 68.97, top5 = 56.98, top10 = 50.96, top15 = 47.34.
+PHY-3001 : End congestion estimation; 0.480303s wall, 0.484375s user + 0.125000s system = 0.609375s CPU (126.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20636 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.909335s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000384477
+PHY-3002 : Step(298): len = 677042, overlap = 79.5625
+PHY-3002 : Step(299): len = 677107, overlap = 79.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000768954
+PHY-3002 : Step(300): len = 677348, overlap = 79.4375
+PHY-3002 : Step(301): len = 677863, overlap = 79.2188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00150983
+PHY-3002 : Step(302): len = 678234, overlap = 79.3125
+PHY-3002 : Step(303): len = 679083, overlap = 79.4375
+PHY-3001 : Final: Len = 679083, Over = 79.4375
+PHY-3001 : End incremental placement; 4.995593s wall, 5.312500s user + 0.296875s system = 5.609375s CPU (112.3%)
+
+OPT-1001 : Total overflow 396.50 peak overflow 5.44
+OPT-1001 : End high-fanout net optimization; 7.948856s wall, 8.828125s user + 0.359375s system = 9.187500s CPU (115.6%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 708, peak = 730.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16882/20814.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 767952, over cnt = 2980(8%), over = 9667, worst = 20
+PHY-1002 : len = 814272, over cnt = 2076(5%), over = 5151, worst = 18
+PHY-1002 : len = 857720, over cnt = 737(2%), over = 1710, worst = 18
+PHY-1002 : len = 872688, over cnt = 330(0%), over = 652, worst = 11
+PHY-1002 : len = 881904, over cnt = 7(0%), over = 8, worst = 2
+PHY-1001 : End global iterations; 1.848596s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (129.3%)
+
+PHY-1001 : Congestion index: top1 = 57.65, top5 = 50.32, top10 = 46.39, top15 = 43.97.
+OPT-1001 : End congestion update; 2.100964s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (125.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20636 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.824355s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 112 cells processed and 19500 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 53 cells processed and 6250 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 100 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 646 slack improved
+OPT-1001 : End bottleneck based optimization; 3.328911s wall, 3.875000s user + 0.000000s system = 3.875000s CPU (116.4%)
+
+OPT-1001 : Current memory(MB): used = 691, reserve = 691, peak = 730.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16950/20819.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 882872, over cnt = 79(0%), over = 104, worst = 4
+PHY-1002 : len = 882656, over cnt = 50(0%), over = 58, worst = 2
+PHY-1002 : len = 882856, over cnt = 28(0%), over = 32, worst = 2
+PHY-1002 : len = 883336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.586282s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (101.3%)
+
+PHY-1001 : Congestion index: top1 = 57.91, top5 = 50.28, top10 = 46.34, top15 = 43.89.
+OPT-1001 : End congestion update; 0.862230s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.806973s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (98.7%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 3700 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.793019s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.2%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 700, peak = 730.
+OPT-1001 : End physical optimization; 14.808144s wall, 16.328125s user + 0.375000s system = 16.703125s CPU (112.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7764 LUT to BLE ...
+SYN-4008 : Packed 7764 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6101 remaining SEQ's ...
+SYN-4005 : Packed 3942 SEQ with LUT/SLICE
+SYN-4006 : 970 single LUT's are left
+SYN-4006 : 2159 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9923/13698 primitive instances ...
+PHY-3001 : End packing; 1.605766s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6685 instances
+RUN-1001 : 3269 mslices, 3268 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17807 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9957 nets have 2 pins
+RUN-1001 : 6498 nets have [3 - 5] pins
+RUN-1001 : 724 nets have [6 - 10] pins
+RUN-1001 : 293 nets have [11 - 20] pins
+RUN-1001 : 304 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6683 instances, 6537 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3523 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 688545, Over = 216.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7542/17807.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 832896, over cnt = 1965(5%), over = 3298, worst = 7
+PHY-1002 : len = 843464, over cnt = 1211(3%), over = 1703, worst = 7
+PHY-1002 : len = 857448, over cnt = 442(1%), over = 567, worst = 6
+PHY-1002 : len = 864560, over cnt = 171(0%), over = 206, worst = 3
+PHY-1002 : len = 867776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.714411s wall, 2.390625s user + 0.062500s system = 2.453125s CPU (143.1%)
+
+PHY-1001 : Congestion index: top1 = 57.11, top5 = 50.02, top10 = 46.31, top15 = 43.86.
+PHY-3001 : End congestion estimation; 2.109122s wall, 2.781250s user + 0.078125s system = 2.859375s CPU (135.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71227, tnet num: 17629, tinst num: 6683, tnode num: 93434, tedge num: 118440.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.574465s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.2%)
+
+RUN-1004 : used memory is 608 MB, reserved memory is 608 MB, peak memory is 730 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17629 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.453722s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.36849e-05
+PHY-3002 : Step(304): len = 675561, overlap = 226
+PHY-3002 : Step(305): len = 668460, overlap = 223.5
+PHY-3002 : Step(306): len = 663516, overlap = 222.75
+PHY-3002 : Step(307): len = 660299, overlap = 228
+PHY-3002 : Step(308): len = 657627, overlap = 235.5
+PHY-3002 : Step(309): len = 654509, overlap = 242.75
+PHY-3002 : Step(310): len = 650700, overlap = 244.5
+PHY-3002 : Step(311): len = 648686, overlap = 248.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00010737
+PHY-3002 : Step(312): len = 652075, overlap = 242.25
+PHY-3002 : Step(313): len = 657075, overlap = 236.5
+PHY-3002 : Step(314): len = 657684, overlap = 232.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000214739
+PHY-3002 : Step(315): len = 663661, overlap = 222.25
+PHY-3002 : Step(316): len = 671862, overlap = 212.5
+PHY-3002 : Step(317): len = 672595, overlap = 208
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.398457s wall, 0.281250s user + 0.609375s system = 0.890625s CPU (223.5%)
+
+PHY-3001 : Trial Legalized: Len = 757705
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 688/17807.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865168, over cnt = 2602(7%), over = 4380, worst = 9
+PHY-1002 : len = 883280, over cnt = 1458(4%), over = 2065, worst = 9
+PHY-1002 : len = 901720, over cnt = 496(1%), over = 669, worst = 5
+PHY-1002 : len = 909152, over cnt = 192(0%), over = 242, worst = 5
+PHY-1002 : len = 913688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.514321s wall, 3.609375s user + 0.093750s system = 3.703125s CPU (147.3%)
+
+PHY-1001 : Congestion index: top1 = 56.01, top5 = 49.77, top10 = 46.94, top15 = 44.99.
+PHY-3001 : End congestion estimation; 2.994797s wall, 4.093750s user + 0.093750s system = 4.187500s CPU (139.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17629 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.829867s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00017312
+PHY-3002 : Step(318): len = 730826, overlap = 36.5
+PHY-3002 : Step(319): len = 715312, overlap = 61.5
+PHY-3002 : Step(320): len = 701676, overlap = 91.25
+PHY-3002 : Step(321): len = 692491, overlap = 112
+PHY-3002 : Step(322): len = 687621, overlap = 127.5
+PHY-3002 : Step(323): len = 684040, overlap = 142.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00034624
+PHY-3002 : Step(324): len = 688454, overlap = 138.25
+PHY-3002 : Step(325): len = 693281, overlap = 138.5
+PHY-3002 : Step(326): len = 695687, overlap = 141
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000692481
+PHY-3002 : Step(327): len = 698138, overlap = 140.75
+PHY-3002 : Step(328): len = 704637, overlap = 135.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.031781s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (98.3%)
+
+PHY-3001 : Legalized: Len = 733206, Over = 0
+PHY-3001 : Spreading special nets. 425 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.093431s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (100.3%)
+
+PHY-3001 : 600 instances has been re-located, deltaX = 172, deltaY = 358, maxDist = 3.
+PHY-3001 : Final: Len = 743012, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71227, tnet num: 17629, tinst num: 6686, tnode num: 93434, tedge num: 118440.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.789135s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.4%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 640 MB, peak memory is 730 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4062/17807.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862776, over cnt = 2369(6%), over = 3887, worst = 8
+PHY-1002 : len = 875360, over cnt = 1475(4%), over = 2134, worst = 6
+PHY-1002 : len = 892200, over cnt = 567(1%), over = 787, worst = 6
+PHY-1002 : len = 902544, over cnt = 141(0%), over = 173, worst = 4
+PHY-1002 : len = 905352, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.922458s wall, 2.859375s user + 0.078125s system = 2.937500s CPU (152.8%)
+
+PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.42, top10 = 45.86, top15 = 44.02.
+PHY-1001 : End incremental global routing; 2.292044s wall, 3.234375s user + 0.078125s system = 3.312500s CPU (144.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17629 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.840954s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.3%)
+
+OPT-1001 : 3 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6595 has valid locations, 20 needs to be replaced
+PHY-3001 : design contains 6703 instances, 6554 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3600 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 745875
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16224/17821.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908680, over cnt = 54(0%), over = 64, worst = 4
+PHY-1002 : len = 908792, over cnt = 19(0%), over = 22, worst = 2
+PHY-1002 : len = 908832, over cnt = 12(0%), over = 14, worst = 2
+PHY-1002 : len = 909024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.580252s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.46, top10 = 45.94, top15 = 44.12.
+PHY-3001 : End congestion estimation; 0.886058s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (107.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71359, tnet num: 17643, tinst num: 6703, tnode num: 93600, tedge num: 118603.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.782612s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (99.9%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 642 MB, peak memory is 730 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17643 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.628627s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(329): len = 745345, overlap = 0
+PHY-3002 : Step(330): len = 745109, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16216/17821.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 907776, over cnt = 49(0%), over = 58, worst = 4
+PHY-1002 : len = 908000, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 908072, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 908232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.586617s wall, 0.640625s user + 0.015625s system = 0.656250s CPU (111.9%)
+
+PHY-1001 : Congestion index: top1 = 53.17, top5 = 48.46, top10 = 45.89, top15 = 44.06.
+PHY-3001 : End congestion estimation; 0.894974s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (106.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17643 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.850037s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000257651
+PHY-3002 : Step(331): len = 745031, overlap = 0.5
+PHY-3002 : Step(332): len = 745029, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005567s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 745143, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057943s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.9%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 745135, Over = 0
+PHY-3001 : End incremental placement; 5.739535s wall, 5.812500s user + 0.062500s system = 5.875000s CPU (102.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.384235s wall, 10.484375s user + 0.140625s system = 10.625000s CPU (113.2%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 732, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16197/17821.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 907872, over cnt = 35(0%), over = 46, worst = 4
+PHY-1002 : len = 908088, over cnt = 12(0%), over = 13, worst = 2
+PHY-1002 : len = 908224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.440863s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (106.3%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.39, top10 = 45.87, top15 = 44.02.
+OPT-1001 : End congestion update; 0.739353s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17643 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.691876s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.4%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6615 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6703 instances, 6554 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3600 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 751159, Over = 0
+PHY-3001 : Spreading special nets. 24 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060046s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.1%)
+
+PHY-3001 : 32 instances has been re-located, deltaX = 15, deltaY = 21, maxDist = 4.
+PHY-3001 : Final: Len = 751765, Over = 0
+PHY-3001 : End incremental legalization; 0.365392s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.6%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 57 cells processed and 18602 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6615 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6703 instances, 6554 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3600 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 751791, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056718s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.6%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 11, deltaY = 16, maxDist = 3.
+PHY-3001 : Final: Len = 752339, Over = 0
+PHY-3001 : End incremental legalization; 0.358748s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.2%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 24 cells processed and 1858 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6618 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6706 instances, 6557 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3601 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 752451, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.055188s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (84.9%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 752471, Over = 0
+PHY-3001 : End incremental legalization; 0.358307s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (135.2%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 3 cells processed and 579 slack improved
+OPT-1001 : End bottleneck based optimization; 2.933248s wall, 3.093750s user + 0.000000s system = 3.093750s CPU (105.5%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 732, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15855/17823.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915008, over cnt = 170(0%), over = 220, worst = 5
+PHY-1002 : len = 915240, over cnt = 90(0%), over = 106, worst = 3
+PHY-1002 : len = 915896, over cnt = 41(0%), over = 47, worst = 3
+PHY-1002 : len = 916328, over cnt = 13(0%), over = 14, worst = 2
+PHY-1002 : len = 916440, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.851961s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 53.45, top5 = 48.40, top10 = 45.84, top15 = 44.04.
+OPT-1001 : End congestion update; 1.164223s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (104.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17645 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.707701s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.4%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6618 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6706 instances, 6557 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3601 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 752633, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057626s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.5%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 6, maxDist = 1.
+PHY-3001 : Final: Len = 752775, Over = 0
+PHY-3001 : End incremental legalization; 0.400713s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.4%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 10 cells processed and 900 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.394003s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (102.5%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 732, peak = 733.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17645 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694605s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16204/17823.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 916704, over cnt = 30(0%), over = 37, worst = 3
+PHY-1002 : len = 916776, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 916808, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 916872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.565152s wall, 0.578125s user + 0.015625s system = 0.593750s CPU (105.1%)
+
+PHY-1001 : Congestion index: top1 = 53.47, top5 = 48.44, top10 = 45.89, top15 = 44.07.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17645 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.689921s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.965517
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 18.988393s wall, 20.328125s user + 0.156250s system = 20.484375s CPU (107.9%)
+
+RUN-1003 : finish command "place" in 62.436603s wall, 90.265625s user + 7.015625s system = 97.281250s CPU (155.8%)
+
+RUN-1004 : used memory is 673 MB, reserved memory is 684 MB, peak memory is 733 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.641918s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (174.1%)
+
+RUN-1004 : used memory is 673 MB, reserved memory is 684 MB, peak memory is 733 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6708 instances
+RUN-1001 : 3282 mslices, 3275 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17823 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9954 nets have 2 pins
+RUN-1001 : 6500 nets have [3 - 5] pins
+RUN-1001 : 732 nets have [6 - 10] pins
+RUN-1001 : 294 nets have [11 - 20] pins
+RUN-1001 : 315 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71380, tnet num: 17645, tinst num: 6706, tnode num: 93630, tedge num: 118632.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.538713s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (100.5%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 654 MB, peak memory is 733 MB
+PHY-1001 : 3282 mslices, 3275 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17645 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 850816, over cnt = 2631(7%), over = 4339, worst = 7
+PHY-1002 : len = 868608, over cnt = 1656(4%), over = 2320, worst = 6
+PHY-1002 : len = 892152, over cnt = 430(1%), over = 546, worst = 4
+PHY-1002 : len = 899584, over cnt = 34(0%), over = 34, worst = 1
+PHY-1002 : len = 900456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.924943s wall, 3.984375s user + 0.000000s system = 3.984375s CPU (136.2%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.40, top10 = 45.57, top15 = 43.69.
+PHY-1001 : End global routing; 3.239656s wall, 4.296875s user + 0.015625s system = 4.312500s CPU (133.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 705, reserve = 709, peak = 733.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 976, reserve = 979, peak = 976.
+PHY-1001 : End build detailed router design. 3.922597s wall, 3.890625s user + 0.031250s system = 3.921875s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273632, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.261917s wall, 5.265625s user + 0.000000s system = 5.265625s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273688, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.439014s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1013, reserve = 1017, peak = 1013.
+PHY-1001 : End phase 1; 5.714539s wall, 5.718750s user + 0.000000s system = 5.718750s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28053e+06, over cnt = 1468(0%), over = 1474, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1026, reserve = 1027, peak = 1026.
+PHY-1001 : End initial routed; 28.556554s wall, 56.718750s user + 0.359375s system = 57.078125s CPU (199.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16745(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.132056s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1041, peak = 1038.
+PHY-1001 : End phase 2; 31.688671s wall, 59.859375s user + 0.359375s system = 60.218750s CPU (190.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.126491s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.8%)
+
+PHY-1022 : len = 2.28053e+06, over cnt = 1468(0%), over = 1474, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.376849s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.25965e+06, over cnt = 652(0%), over = 653, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 0.836840s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (192.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25165e+06, over cnt = 116(0%), over = 116, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.941988s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (126.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25245e+06, over cnt = 28(0%), over = 28, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.303421s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (133.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25282e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.293572s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (95.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2528e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.209122s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16745(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.214360s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 442 feed throughs used by 334 nets
+PHY-1001 : End commit to database; 2.587046s wall, 2.578125s user + 0.015625s system = 2.593750s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1137, reserve = 1143, peak = 1137.
+PHY-1001 : End phase 3; 9.154227s wall, 10.265625s user + 0.015625s system = 10.281250s CPU (112.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135481s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.8%)
+
+PHY-1022 : len = 2.2528e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.389956s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16745(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.182422s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 442 feed throughs used by 334 nets
+PHY-1001 : End commit to database; 2.271374s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1152, peak = 1146.
+PHY-1001 : End phase 4; 5.871766s wall, 5.875000s user + 0.000000s system = 5.875000s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.2528e+06
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1154, peak = 1147.
+PHY-1001 : End export database. 0.058152s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.5%)
+
+PHY-1001 : End detail routing; 56.791097s wall, 86.031250s user + 0.406250s system = 86.437500s CPU (152.2%)
+
+RUN-1003 : finish command "route" in 62.583529s wall, 92.828125s user + 0.484375s system = 93.312500s CPU (149.1%)
+
+RUN-1004 : used memory is 1075 MB, reserved memory is 1079 MB, peak memory is 1148 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10172 out of 19600 51.90%
+#reg 9384 out of 19600 47.88%
+#le 12298
+ #lut only 2914 out of 12298 23.69%
+ #reg only 2126 out of 12298 17.29%
+ #lut® 7258 out of 12298 59.02%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1779
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1370
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1287
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 945
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 137
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg0_syn_155.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_295.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P104 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P16 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE OREG
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P35 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P110 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P172 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P112 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12298 |9145 |1027 |9418 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |547 |461 |23 |443 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |107 |99 |4 |97 |4 |0 |
+| U_crc16_24b |crc16_24b |49 |49 |0 |25 |0 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |744 |422 |96 |570 |0 |0 |
+| u_ADconfig |AD_config |182 |136 |25 |138 |0 |0 |
+| u_gen_sp |gen_sp |252 |150 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |740 |382 |96 |564 |0 |0 |
+| u_ADconfig |AD_config |170 |110 |25 |128 |0 |0 |
+| u_gen_sp |gen_sp |253 |158 |71 |119 |0 |0 |
+| sampling_fe_a |sampling_fe |2980 |2390 |306 |2105 |25 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |182 |88 |17 |152 |0 |0 |
+| u0_soft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_sort |sort |2766 |2289 |289 |1921 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2305 |1945 |253 |1547 |22 |0 |
+| channelPart |channel_part_8478 |139 |135 |3 |134 |0 |0 |
+| fifo_adc |fifo_adc |63 |54 |9 |49 |0 |0 |
+| ram_switch |ram_switch |1812 |1523 |197 |1152 |0 |0 |
+| adc_addr_gen |adc_addr_gen |209 |182 |27 |121 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |12 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |15 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| insert |insert |948 |687 |170 |654 |0 |0 |
+| ram_switch_state |ram_switch_state |655 |654 |0 |377 |0 |0 |
+| read_ram_i |read_ram |269 |211 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |222 |182 |40 |155 |0 |0 |
+| read_ram_data |read_ram_data |44 |28 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |325 |239 |36 |277 |3 |0 |
+| u0_soft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3230 |2560 |349 |2080 |25 |1 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |121 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_sort |sort_rev |3009 |2423 |332 |1890 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |6 |6 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2576 |2120 |290 |1532 |22 |1 |
+| channelPart |channel_part_8478 |141 |138 |3 |131 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1993 |1660 |197 |1126 |0 |0 |
+| adc_addr_gen |adc_addr_gen |202 |175 |27 |103 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |5 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| insert |insert |948 |642 |170 |651 |0 |0 |
+| ram_switch_state |ram_switch_state |843 |843 |0 |372 |0 |0 |
+| read_ram_i |read_ram_rev |359 |251 |81 |210 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |296 |211 |73 |163 |0 |0 |
+| read_ram_data |read_ram_data_rev |63 |40 |8 |47 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9892
+ #2 2 4247
+ #3 3 1693
+ #4 4 557
+ #5 5-10 767
+ #6 11-50 561
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.054385s wall, 3.468750s user + 0.015625s system = 3.484375s CPU (169.6%)
+
+RUN-1004 : used memory is 1076 MB, reserved memory is 1081 MB, peak memory is 1148 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71380, tnet num: 17645, tinst num: 6706, tnode num: 93630, tedge num: 118632.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.532927s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (99.9%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1086 MB, peak memory is 1148 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17645 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.402724s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (100.3%)
+
+RUN-1004 : used memory is 1083 MB, reserved memory is 1088 MB, peak memory is 1148 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6706
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17823, pip num: 167193
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 442
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 466284 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.655557s wall, 68.046875s user + 0.281250s system = 68.328125s CPU (641.2%)
+
+RUN-1004 : used memory is 1238 MB, reserved memory is 1242 MB, peak memory is 1353 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_190601.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_191907.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_191907.log
new file mode 100644
index 0000000..7e6e8a3
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_191907.log
@@ -0,0 +1,2145 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 19:19:07 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(887)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(896)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(920)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(922)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(928)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(931)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1102)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1191)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1492)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1503)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1521)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2099)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.206294s wall, 2.078125s user + 0.125000s system = 2.203125s CPU (99.9%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18047 instances
+RUN-0007 : 7655 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20624 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13126 nets have 2 pins
+RUN-1001 : 6467 nets have [3 - 5] pins
+RUN-1001 : 615 nets have [6 - 10] pins
+RUN-1001 : 177 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18045 instances, 7655 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6041 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84311, tnet num: 20446, tinst num: 18045, tnode num: 114866, tedge num: 134480.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.181473s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (97.9%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 516 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.121632s wall, 2.031250s user + 0.062500s system = 2.093750s CPU (98.7%)
+
+PHY-3001 : Found 1246 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.16397e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18045.
+PHY-3001 : Level 1 #clusters 2079.
+PHY-3001 : End clustering; 0.142315s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (131.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.37824e+06, overlap = 452.844
+PHY-3002 : Step(2): len = 1.26186e+06, overlap = 490.594
+PHY-3002 : Step(3): len = 852553, overlap = 609.344
+PHY-3002 : Step(4): len = 790501, overlap = 629.469
+PHY-3002 : Step(5): len = 633379, overlap = 761.625
+PHY-3002 : Step(6): len = 544208, overlap = 826.344
+PHY-3002 : Step(7): len = 476055, overlap = 893.188
+PHY-3002 : Step(8): len = 424608, overlap = 956.562
+PHY-3002 : Step(9): len = 393368, overlap = 1011.91
+PHY-3002 : Step(10): len = 354033, overlap = 1063.66
+PHY-3002 : Step(11): len = 329025, overlap = 1119.47
+PHY-3002 : Step(12): len = 299221, overlap = 1157.59
+PHY-3002 : Step(13): len = 276869, overlap = 1188.44
+PHY-3002 : Step(14): len = 250681, overlap = 1263.41
+PHY-3002 : Step(15): len = 235861, overlap = 1275.47
+PHY-3002 : Step(16): len = 218479, overlap = 1358.41
+PHY-3002 : Step(17): len = 197856, overlap = 1395.16
+PHY-3002 : Step(18): len = 183778, overlap = 1420.81
+PHY-3002 : Step(19): len = 167411, overlap = 1463.12
+PHY-3002 : Step(20): len = 157139, overlap = 1469.09
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.22614e-06
+PHY-3002 : Step(21): len = 157391, overlap = 1437.59
+PHY-3002 : Step(22): len = 196222, overlap = 1251.34
+PHY-3002 : Step(23): len = 202297, overlap = 1198.94
+PHY-3002 : Step(24): len = 204865, overlap = 1137.28
+PHY-3002 : Step(25): len = 203845, overlap = 1097.69
+PHY-3002 : Step(26): len = 201577, overlap = 1090.03
+PHY-3002 : Step(27): len = 197189, overlap = 1090.25
+PHY-3002 : Step(28): len = 193920, overlap = 1075.09
+PHY-3002 : Step(29): len = 188345, overlap = 1055.97
+PHY-3002 : Step(30): len = 185486, overlap = 1050.88
+PHY-3002 : Step(31): len = 182394, overlap = 1055.56
+PHY-3002 : Step(32): len = 181564, overlap = 1035.97
+PHY-3002 : Step(33): len = 178835, overlap = 1025.69
+PHY-3002 : Step(34): len = 176841, overlap = 1023.94
+PHY-3002 : Step(35): len = 174879, overlap = 1015.91
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.45228e-06
+PHY-3002 : Step(36): len = 180168, overlap = 993
+PHY-3002 : Step(37): len = 194875, overlap = 952.062
+PHY-3002 : Step(38): len = 201343, overlap = 970.656
+PHY-3002 : Step(39): len = 207014, overlap = 960.906
+PHY-3002 : Step(40): len = 207925, overlap = 981.344
+PHY-3002 : Step(41): len = 209094, overlap = 997.406
+PHY-3002 : Step(42): len = 206598, overlap = 997.688
+PHY-3002 : Step(43): len = 205669, overlap = 983.188
+PHY-3002 : Step(44): len = 203103, overlap = 978.219
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.90456e-06
+PHY-3002 : Step(45): len = 211701, overlap = 952.875
+PHY-3002 : Step(46): len = 230644, overlap = 892.781
+PHY-3002 : Step(47): len = 241323, overlap = 764.344
+PHY-3002 : Step(48): len = 249368, overlap = 745.844
+PHY-3002 : Step(49): len = 253777, overlap = 737.219
+PHY-3002 : Step(50): len = 255150, overlap = 740.312
+PHY-3002 : Step(51): len = 254024, overlap = 730.531
+PHY-3002 : Step(52): len = 253673, overlap = 723.219
+PHY-3002 : Step(53): len = 253381, overlap = 730.938
+PHY-3002 : Step(54): len = 252496, overlap = 718.406
+PHY-3002 : Step(55): len = 250524, overlap = 721.406
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.80912e-06
+PHY-3002 : Step(56): len = 265416, overlap = 687.812
+PHY-3002 : Step(57): len = 281260, overlap = 605.344
+PHY-3002 : Step(58): len = 291304, overlap = 564.219
+PHY-3002 : Step(59): len = 296307, overlap = 555.375
+PHY-3002 : Step(60): len = 295352, overlap = 539.938
+PHY-3002 : Step(61): len = 297274, overlap = 513.906
+PHY-3002 : Step(62): len = 295935, overlap = 521.906
+PHY-3002 : Step(63): len = 295312, overlap = 522.219
+PHY-3002 : Step(64): len = 295017, overlap = 534.281
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.96182e-05
+PHY-3002 : Step(65): len = 311172, overlap = 532.219
+PHY-3002 : Step(66): len = 326027, overlap = 498
+PHY-3002 : Step(67): len = 332851, overlap = 438.656
+PHY-3002 : Step(68): len = 336520, overlap = 423.812
+PHY-3002 : Step(69): len = 337838, overlap = 399.781
+PHY-3002 : Step(70): len = 338999, overlap = 403.188
+PHY-3002 : Step(71): len = 338910, overlap = 384.938
+PHY-3002 : Step(72): len = 340250, overlap = 371.688
+PHY-3002 : Step(73): len = 339701, overlap = 353.562
+PHY-3002 : Step(74): len = 340402, overlap = 351.281
+PHY-3002 : Step(75): len = 341365, overlap = 336.656
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.92365e-05
+PHY-3002 : Step(76): len = 360185, overlap = 332.031
+PHY-3002 : Step(77): len = 373117, overlap = 329.969
+PHY-3002 : Step(78): len = 373886, overlap = 306.625
+PHY-3002 : Step(79): len = 376891, overlap = 302.594
+PHY-3002 : Step(80): len = 378416, overlap = 302.406
+PHY-3002 : Step(81): len = 382893, overlap = 293.375
+PHY-3002 : Step(82): len = 379744, overlap = 271.094
+PHY-3002 : Step(83): len = 382300, overlap = 264.312
+PHY-3002 : Step(84): len = 383559, overlap = 263.562
+PHY-3002 : Step(85): len = 385004, overlap = 265.312
+PHY-3002 : Step(86): len = 381215, overlap = 264.031
+PHY-3002 : Step(87): len = 381757, overlap = 254.406
+PHY-3002 : Step(88): len = 383142, overlap = 255.25
+PHY-3002 : Step(89): len = 384847, overlap = 262.812
+PHY-3002 : Step(90): len = 383610, overlap = 264.969
+PHY-3002 : Step(91): len = 383815, overlap = 276.438
+PHY-3002 : Step(92): len = 384125, overlap = 277
+PHY-3002 : Step(93): len = 384343, overlap = 272.688
+PHY-3002 : Step(94): len = 381836, overlap = 263.938
+PHY-3002 : Step(95): len = 381720, overlap = 259.656
+PHY-3002 : Step(96): len = 381692, overlap = 264.094
+PHY-3002 : Step(97): len = 382394, overlap = 257.469
+PHY-3002 : Step(98): len = 380899, overlap = 258.594
+PHY-3002 : Step(99): len = 380760, overlap = 252.562
+PHY-3002 : Step(100): len = 380594, overlap = 250.656
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.84729e-05
+PHY-3002 : Step(101): len = 397722, overlap = 253
+PHY-3002 : Step(102): len = 407464, overlap = 237.375
+PHY-3002 : Step(103): len = 407228, overlap = 231.781
+PHY-3002 : Step(104): len = 407548, overlap = 222.719
+PHY-3002 : Step(105): len = 409899, overlap = 222.188
+PHY-3002 : Step(106): len = 412812, overlap = 222.812
+PHY-3002 : Step(107): len = 412280, overlap = 220.938
+PHY-3002 : Step(108): len = 412299, overlap = 233
+PHY-3002 : Step(109): len = 413424, overlap = 242.469
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000156946
+PHY-3002 : Step(110): len = 426480, overlap = 241.094
+PHY-3002 : Step(111): len = 435835, overlap = 219.406
+PHY-3002 : Step(112): len = 436496, overlap = 218.25
+PHY-3002 : Step(113): len = 438613, overlap = 213.188
+PHY-3002 : Step(114): len = 443211, overlap = 206.469
+PHY-3002 : Step(115): len = 446865, overlap = 197.75
+PHY-3002 : Step(116): len = 444338, overlap = 191.188
+PHY-3002 : Step(117): len = 443849, overlap = 180.625
+PHY-3002 : Step(118): len = 445267, overlap = 183.969
+PHY-3002 : Step(119): len = 446007, overlap = 187.219
+PHY-3002 : Step(120): len = 443700, overlap = 183.062
+PHY-3002 : Step(121): len = 443225, overlap = 190.094
+PHY-3002 : Step(122): len = 444869, overlap = 194.344
+PHY-3002 : Step(123): len = 446307, overlap = 188.812
+PHY-3002 : Step(124): len = 444168, overlap = 183.156
+PHY-3002 : Step(125): len = 443804, overlap = 180.062
+PHY-3002 : Step(126): len = 445367, overlap = 179.312
+PHY-3002 : Step(127): len = 446749, overlap = 175.5
+PHY-3002 : Step(128): len = 445802, overlap = 175.656
+PHY-3002 : Step(129): len = 446071, overlap = 170.906
+PHY-3002 : Step(130): len = 448441, overlap = 174.562
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000313892
+PHY-3002 : Step(131): len = 455941, overlap = 170.062
+PHY-3002 : Step(132): len = 464644, overlap = 160.469
+PHY-3002 : Step(133): len = 466812, overlap = 161.125
+PHY-3002 : Step(134): len = 467754, overlap = 160.812
+PHY-3002 : Step(135): len = 467990, overlap = 160.031
+PHY-3002 : Step(136): len = 468672, overlap = 159.594
+PHY-3002 : Step(137): len = 469104, overlap = 156.062
+PHY-3002 : Step(138): len = 469975, overlap = 159.281
+PHY-3002 : Step(139): len = 471080, overlap = 161.594
+PHY-3002 : Step(140): len = 471773, overlap = 160.625
+PHY-3002 : Step(141): len = 471393, overlap = 167.062
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000567297
+PHY-3002 : Step(142): len = 477871, overlap = 157.188
+PHY-3002 : Step(143): len = 483546, overlap = 157.469
+PHY-3002 : Step(144): len = 484664, overlap = 162.719
+PHY-3002 : Step(145): len = 485424, overlap = 168.25
+PHY-3002 : Step(146): len = 487814, overlap = 167.25
+PHY-3002 : Step(147): len = 491064, overlap = 153.656
+PHY-3002 : Step(148): len = 491916, overlap = 150.125
+PHY-3002 : Step(149): len = 492816, overlap = 149.438
+PHY-3002 : Step(150): len = 494155, overlap = 143.844
+PHY-3002 : Step(151): len = 494697, overlap = 140.219
+PHY-3002 : Step(152): len = 494043, overlap = 142.625
+PHY-3002 : Step(153): len = 493819, overlap = 145.312
+PHY-3002 : Step(154): len = 494017, overlap = 143.562
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00104208
+PHY-3002 : Step(155): len = 497762, overlap = 141.812
+PHY-3002 : Step(156): len = 505095, overlap = 144.875
+PHY-3002 : Step(157): len = 506716, overlap = 144.375
+PHY-3002 : Step(158): len = 508193, overlap = 145.5
+PHY-3002 : Step(159): len = 510464, overlap = 141.219
+PHY-3002 : Step(160): len = 512088, overlap = 134.906
+PHY-3002 : Step(161): len = 511727, overlap = 142.938
+PHY-3002 : Step(162): len = 511830, overlap = 138.938
+PHY-3002 : Step(163): len = 513338, overlap = 131.25
+PHY-3002 : Step(164): len = 514039, overlap = 131.188
+PHY-3002 : Step(165): len = 513665, overlap = 139.438
+PHY-3002 : Step(166): len = 513656, overlap = 140.344
+PHY-3002 : Step(167): len = 514634, overlap = 140.344
+PHY-3002 : Step(168): len = 514817, overlap = 140.656
+PHY-3002 : Step(169): len = 514378, overlap = 141.031
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00168608
+PHY-3002 : Step(170): len = 516522, overlap = 141.906
+PHY-3002 : Step(171): len = 520910, overlap = 145.812
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.011495s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (135.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20624.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712088, over cnt = 1598(4%), over = 7445, worst = 36
+PHY-1001 : End global iterations; 0.648640s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (154.2%)
+
+PHY-1001 : Congestion index: top1 = 85.02, top5 = 63.08, top10 = 53.83, top15 = 48.05.
+PHY-3001 : End congestion estimation; 0.862630s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (141.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.834474s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155357
+PHY-3002 : Step(172): len = 647287, overlap = 78.7812
+PHY-3002 : Step(173): len = 647601, overlap = 80.7188
+PHY-3002 : Step(174): len = 640678, overlap = 80.2188
+PHY-3002 : Step(175): len = 637473, overlap = 83.5625
+PHY-3002 : Step(176): len = 635603, overlap = 76.375
+PHY-3002 : Step(177): len = 633053, overlap = 71.25
+PHY-3002 : Step(178): len = 631948, overlap = 57.9375
+PHY-3002 : Step(179): len = 630831, overlap = 55.5312
+PHY-3002 : Step(180): len = 629447, overlap = 43.25
+PHY-3002 : Step(181): len = 627174, overlap = 38.9062
+PHY-3002 : Step(182): len = 626206, overlap = 36.1562
+PHY-3002 : Step(183): len = 624986, overlap = 35.3125
+PHY-3002 : Step(184): len = 625365, overlap = 34.25
+PHY-3002 : Step(185): len = 624177, overlap = 34.25
+PHY-3002 : Step(186): len = 624329, overlap = 35.8125
+PHY-3002 : Step(187): len = 622211, overlap = 35.8125
+PHY-3002 : Step(188): len = 621353, overlap = 35.5
+PHY-3002 : Step(189): len = 618756, overlap = 36.6562
+PHY-3002 : Step(190): len = 617011, overlap = 35.875
+PHY-3002 : Step(191): len = 616208, overlap = 36.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000310713
+PHY-3002 : Step(192): len = 617427, overlap = 36.3125
+PHY-3002 : Step(193): len = 621001, overlap = 35.6562
+PHY-3002 : Step(194): len = 626782, overlap = 35.4688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000605889
+PHY-3002 : Step(195): len = 636524, overlap = 34.4062
+PHY-3002 : Step(196): len = 655930, overlap = 30.8438
+PHY-3002 : Step(197): len = 673142, overlap = 28.5312
+PHY-3002 : Step(198): len = 674702, overlap = 25.4688
+PHY-3002 : Step(199): len = 675798, overlap = 22.0312
+PHY-3002 : Step(200): len = 674088, overlap = 20.2188
+PHY-3002 : Step(201): len = 672758, overlap = 20.0625
+PHY-3002 : Step(202): len = 672625, overlap = 19.9688
+PHY-3002 : Step(203): len = 670105, overlap = 17.9375
+PHY-3002 : Step(204): len = 668005, overlap = 17.4688
+PHY-3002 : Step(205): len = 665778, overlap = 18.9688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00117027
+PHY-3002 : Step(206): len = 672688, overlap = 16.5938
+PHY-3002 : Step(207): len = 682048, overlap = 17.8125
+PHY-3002 : Step(208): len = 687433, overlap = 17.8438
+PHY-3002 : Step(209): len = 692923, overlap = 21.4688
+PHY-3002 : Step(210): len = 699396, overlap = 22.3125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00195545
+PHY-3002 : Step(211): len = 702763, overlap = 21.3125
+PHY-3002 : Step(212): len = 707365, overlap = 21.5312
+PHY-3002 : Step(213): len = 713324, overlap = 21.5625
+PHY-3002 : Step(214): len = 718992, overlap = 20.8438
+PHY-3002 : Step(215): len = 722282, overlap = 21.7188
+PHY-3002 : Step(216): len = 723559, overlap = 22.9375
+PHY-3002 : Step(217): len = 723023, overlap = 23.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 33/20624.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812232, over cnt = 2927(8%), over = 13631, worst = 47
+PHY-1001 : End global iterations; 1.592898s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 91.94, top5 = 72.28, top10 = 63.44, top15 = 57.98.
+PHY-3001 : End congestion estimation; 1.867481s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (133.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.908100s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000136521
+PHY-3002 : Step(218): len = 706562, overlap = 217.812
+PHY-3002 : Step(219): len = 695766, overlap = 175.312
+PHY-3002 : Step(220): len = 679560, overlap = 154.188
+PHY-3002 : Step(221): len = 666304, overlap = 133.875
+PHY-3002 : Step(222): len = 657689, overlap = 123.594
+PHY-3002 : Step(223): len = 649506, overlap = 118.719
+PHY-3002 : Step(224): len = 642927, overlap = 119.312
+PHY-3002 : Step(225): len = 638593, overlap = 112.219
+PHY-3002 : Step(226): len = 634344, overlap = 109.5
+PHY-3002 : Step(227): len = 629374, overlap = 106.75
+PHY-3002 : Step(228): len = 625581, overlap = 105.906
+PHY-3002 : Step(229): len = 621095, overlap = 108.969
+PHY-3002 : Step(230): len = 617852, overlap = 113.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000273042
+PHY-3002 : Step(231): len = 617742, overlap = 106.344
+PHY-3002 : Step(232): len = 620772, overlap = 101.406
+PHY-3002 : Step(233): len = 624500, overlap = 97.4375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000546084
+PHY-3002 : Step(234): len = 627651, overlap = 97.5938
+PHY-3002 : Step(235): len = 633605, overlap = 92.0625
+PHY-3002 : Step(236): len = 640439, overlap = 85.0625
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84311, tnet num: 20446, tinst num: 18045, tnode num: 114866, tedge num: 134480.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.434975s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.2%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 566 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 398.72 peak overflow 3.25
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 670/20624.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735696, over cnt = 3091(8%), over = 10909, worst = 30
+PHY-1001 : End global iterations; 1.318313s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (135.1%)
+
+PHY-1001 : Congestion index: top1 = 70.11, top5 = 58.29, top10 = 52.09, top15 = 48.23.
+PHY-1001 : End incremental global routing; 1.649601s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (128.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.898412s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.1%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17914 has valid locations, 303 needs to be replaced
+PHY-3001 : design contains 18302 instances, 7744 luts, 9337 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6162 pins
+PHY-3001 : Found 1256 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 663552
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16930/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751632, over cnt = 3093(8%), over = 10962, worst = 30
+PHY-1001 : End global iterations; 0.220607s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 69.61, top5 = 58.17, top10 = 52.15, top15 = 48.49.
+PHY-3001 : End congestion estimation; 0.481798s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (116.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85345, tnet num: 20703, tinst num: 18302, tnode num: 116431, tedge num: 136034.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.470987s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (99.8%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 632 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.427707s wall, 2.375000s user + 0.046875s system = 2.421875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(237): len = 662748, overlap = 0.25
+PHY-3002 : Step(238): len = 662186, overlap = 0.25
+PHY-3002 : Step(239): len = 661813, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17044/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749368, over cnt = 3094(8%), over = 10999, worst = 30
+PHY-1001 : End global iterations; 0.175981s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (133.2%)
+
+PHY-1001 : Congestion index: top1 = 70.41, top5 = 58.64, top10 = 52.52, top15 = 48.77.
+PHY-3001 : End congestion estimation; 0.439124s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (113.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.963002s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000338828
+PHY-3002 : Step(240): len = 661424, overlap = 86.875
+PHY-3002 : Step(241): len = 661465, overlap = 87.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000677657
+PHY-3002 : Step(242): len = 661773, overlap = 87.2812
+PHY-3002 : Step(243): len = 662289, overlap = 87.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00130041
+PHY-3002 : Step(244): len = 662600, overlap = 86.75
+PHY-3002 : Step(245): len = 663104, overlap = 86.5625
+PHY-3001 : Final: Len = 663104, Over = 86.5625
+PHY-3001 : End incremental placement; 5.047652s wall, 5.312500s user + 0.218750s system = 5.531250s CPU (109.6%)
+
+OPT-1001 : Total overflow 404.84 peak overflow 3.25
+OPT-1001 : End high-fanout net optimization; 8.136281s wall, 8.968750s user + 0.234375s system = 9.203125s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 712, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16959/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 752928, over cnt = 3027(8%), over = 9911, worst = 30
+PHY-1002 : len = 805584, over cnt = 2031(5%), over = 4912, worst = 20
+PHY-1002 : len = 848240, over cnt = 822(2%), over = 1664, worst = 16
+PHY-1002 : len = 860704, over cnt = 456(1%), over = 921, worst = 11
+PHY-1002 : len = 879816, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.825426s wall, 2.609375s user + 0.031250s system = 2.640625s CPU (144.7%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.80, top10 = 47.95, top15 = 45.46.
+OPT-1001 : End congestion update; 2.082226s wall, 2.859375s user + 0.031250s system = 2.890625s CPU (138.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.789463s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (100.9%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 125 cells processed and 17400 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 29 cells processed and 2550 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 1250 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.272775s wall, 4.031250s user + 0.046875s system = 4.078125s CPU (124.6%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 694, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16983/20883.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879600, over cnt = 79(0%), over = 109, worst = 4
+PHY-1002 : len = 879576, over cnt = 36(0%), over = 39, worst = 2
+PHY-1002 : len = 879824, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 879904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 879968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.681284s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (107.8%)
+
+PHY-1001 : Congestion index: top1 = 58.32, top5 = 51.53, top10 = 47.76, top15 = 45.32.
+OPT-1001 : End congestion update; 0.939139s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (106.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20705 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.775207s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.8%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 41 cells processed and 7000 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 5 cells processed and 500 slack improved
+OPT-1001 : End path based optimization; 1.924402s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (103.9%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 699, peak = 734.
+OPT-1001 : End physical optimization; 15.069251s wall, 16.828125s user + 0.296875s system = 17.125000s CPU (113.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7744 LUT to BLE ...
+SYN-4008 : Packed 7744 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6192 remaining SEQ's ...
+SYN-4005 : Packed 4011 SEQ with LUT/SLICE
+SYN-4006 : 888 single LUT's are left
+SYN-4006 : 2181 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9925/13712 primitive instances ...
+PHY-3001 : End packing; 1.732242s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6704 instances
+RUN-1001 : 3278 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17870 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 6541 nets have [3 - 5] pins
+RUN-1001 : 725 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 304 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6702 instances, 6556 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3572 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 673801, Over = 221.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7610/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 830704, over cnt = 1985(5%), over = 3157, worst = 9
+PHY-1002 : len = 837376, over cnt = 1297(3%), over = 1828, worst = 8
+PHY-1002 : len = 850104, over cnt = 520(1%), over = 690, worst = 7
+PHY-1002 : len = 857912, over cnt = 165(0%), over = 215, worst = 5
+PHY-1002 : len = 861904, over cnt = 4(0%), over = 5, worst = 2
+PHY-1001 : End global iterations; 1.770840s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (135.0%)
+
+PHY-1001 : Congestion index: top1 = 57.87, top5 = 51.67, top10 = 47.87, top15 = 45.22.
+PHY-3001 : End congestion estimation; 2.200935s wall, 2.812500s user + 0.015625s system = 2.828125s CPU (128.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71589, tnet num: 17692, tinst num: 6702, tnode num: 94109, tedge num: 119050.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.612394s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (99.8%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 617 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.459097s wall, 2.390625s user + 0.062500s system = 2.453125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.71995e-05
+PHY-3002 : Step(246): len = 662174, overlap = 220
+PHY-3002 : Step(247): len = 655931, overlap = 221.5
+PHY-3002 : Step(248): len = 652095, overlap = 222.5
+PHY-3002 : Step(249): len = 648922, overlap = 219.25
+PHY-3002 : Step(250): len = 645743, overlap = 228
+PHY-3002 : Step(251): len = 643720, overlap = 227
+PHY-3002 : Step(252): len = 641908, overlap = 233
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000114399
+PHY-3002 : Step(253): len = 644550, overlap = 223.75
+PHY-3002 : Step(254): len = 650049, overlap = 208.5
+PHY-3002 : Step(255): len = 651181, overlap = 210.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000228798
+PHY-3002 : Step(256): len = 656507, overlap = 200.75
+PHY-3002 : Step(257): len = 664876, overlap = 195.5
+PHY-3002 : Step(258): len = 665271, overlap = 194
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.383131s wall, 0.359375s user + 0.593750s system = 0.953125s CPU (248.8%)
+
+PHY-3001 : Trial Legalized: Len = 744817
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 899/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856040, over cnt = 2628(7%), over = 4411, worst = 7
+PHY-1002 : len = 873360, over cnt = 1570(4%), over = 2287, worst = 6
+PHY-1002 : len = 896192, over cnt = 452(1%), over = 591, worst = 5
+PHY-1002 : len = 903808, over cnt = 122(0%), over = 152, worst = 3
+PHY-1002 : len = 906784, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.365432s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (144.0%)
+
+PHY-1001 : Congestion index: top1 = 56.47, top5 = 50.97, top10 = 47.55, top15 = 45.30.
+PHY-3001 : End congestion estimation; 2.832302s wall, 3.875000s user + 0.000000s system = 3.875000s CPU (136.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.829728s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000172415
+PHY-3002 : Step(259): len = 717221, overlap = 39
+PHY-3002 : Step(260): len = 701250, overlap = 64.75
+PHY-3002 : Step(261): len = 688225, overlap = 83.25
+PHY-3002 : Step(262): len = 680736, overlap = 98.75
+PHY-3002 : Step(263): len = 675754, overlap = 116
+PHY-3002 : Step(264): len = 673165, overlap = 129.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000344829
+PHY-3002 : Step(265): len = 677434, overlap = 128.5
+PHY-3002 : Step(266): len = 682067, overlap = 127.75
+PHY-3002 : Step(267): len = 684644, overlap = 128.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000689658
+PHY-3002 : Step(268): len = 687220, overlap = 128.5
+PHY-3002 : Step(269): len = 692573, overlap = 126
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033240s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (94.0%)
+
+PHY-3001 : Legalized: Len = 719837, Over = 0
+PHY-3001 : Spreading special nets. 403 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.104807s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (104.4%)
+
+PHY-3001 : 592 instances has been re-located, deltaX = 168, deltaY = 350, maxDist = 2.
+PHY-3001 : Final: Len = 727997, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71589, tnet num: 17692, tinst num: 6705, tnode num: 94109, tedge num: 119050.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.862848s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (99.8%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 641 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4494/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858528, over cnt = 2450(6%), over = 3884, worst = 7
+PHY-1002 : len = 872208, over cnt = 1426(4%), over = 1956, worst = 5
+PHY-1002 : len = 889928, over cnt = 398(1%), over = 504, worst = 5
+PHY-1002 : len = 896168, over cnt = 68(0%), over = 93, worst = 5
+PHY-1002 : len = 897968, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 1.913064s wall, 2.812500s user + 0.046875s system = 2.859375s CPU (149.5%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.37, top10 = 46.31, top15 = 44.39.
+PHY-1001 : End incremental global routing; 2.288451s wall, 3.203125s user + 0.046875s system = 3.250000s CPU (142.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.834479s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (99.2%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6613 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 733234
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16308/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904088, over cnt = 81(0%), over = 95, worst = 4
+PHY-1002 : len = 904256, over cnt = 37(0%), over = 42, worst = 3
+PHY-1002 : len = 904672, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 904800, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 904904, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.757457s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.1%)
+
+PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.46, top10 = 46.42, top15 = 44.50.
+PHY-3001 : End congestion estimation; 1.066817s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (101.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71807, tnet num: 17722, tinst num: 6727, tnode num: 94377, tedge num: 119359.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.819248s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (99.6%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 655 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.705965s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 731421, overlap = 0.5
+PHY-3002 : Step(271): len = 730760, overlap = 1
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16293/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901040, over cnt = 74(0%), over = 93, worst = 3
+PHY-1002 : len = 901408, over cnt = 27(0%), over = 27, worst = 1
+PHY-1002 : len = 901552, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 901856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.621250s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 55.41, top5 = 49.43, top10 = 46.39, top15 = 44.46.
+PHY-3001 : End congestion estimation; 0.937927s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (103.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.859932s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.25652e-05
+PHY-3002 : Step(272): len = 730790, overlap = 3.75
+PHY-3002 : Step(273): len = 730711, overlap = 2.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005639s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (277.1%)
+
+PHY-3001 : Legalized: Len = 730837, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057741s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.2%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 0, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 730969, Over = 0
+PHY-3001 : End incremental placement; 6.033660s wall, 6.046875s user + 0.078125s system = 6.125000s CPU (101.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.623960s wall, 10.515625s user + 0.156250s system = 10.671875s CPU (110.9%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 735, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16282/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902168, over cnt = 57(0%), over = 67, worst = 4
+PHY-1002 : len = 902176, over cnt = 34(0%), over = 35, worst = 2
+PHY-1002 : len = 902496, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 902664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.578071s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (108.1%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.40, top10 = 46.32, top15 = 44.39.
+OPT-1001 : End congestion update; 0.877742s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (105.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.001652s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (101.4%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738754, Over = 0
+PHY-3001 : Spreading special nets. 23 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059202s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.6%)
+
+PHY-3001 : 36 instances has been re-located, deltaX = 18, deltaY = 26, maxDist = 4.
+PHY-3001 : Final: Len = 740022, Over = 0
+PHY-3001 : End incremental legalization; 0.374053s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (125.3%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 57 cells processed and 19167 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 739720, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060294s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.7%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 0, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 740248, Over = 0
+PHY-3001 : End incremental legalization; 0.415072s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (105.4%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 21 cells processed and 2391 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 739796, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058208s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.5%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 8, deltaY = 12, maxDist = 4.
+PHY-3001 : Final: Len = 740332, Over = 0
+PHY-3001 : End incremental legalization; 0.467959s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.2%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 1807 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740374, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060653s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.0%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740506, Over = 0
+PHY-3001 : End incremental legalization; 0.369578s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.5%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 3 cells processed and 950 slack improved
+OPT-1001 : End bottleneck based optimization; 4.107231s wall, 4.328125s user + 0.015625s system = 4.343750s CPU (105.8%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 736, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15889/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911864, over cnt = 172(0%), over = 223, worst = 6
+PHY-1002 : len = 912536, over cnt = 75(0%), over = 78, worst = 2
+PHY-1002 : len = 912920, over cnt = 44(0%), over = 46, worst = 2
+PHY-1002 : len = 913592, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 913672, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.836142s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (104.6%)
+
+PHY-1001 : Congestion index: top1 = 55.02, top5 = 49.29, top10 = 46.30, top15 = 44.38.
+OPT-1001 : End congestion update; 1.139076s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (102.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701833s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740908, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056681s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 2, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.366514s wall, 0.343750s user + 0.031250s system = 0.375000s CPU (102.3%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 11 cells processed and 1400 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.358010s wall, 2.468750s user + 0.046875s system = 2.515625s CPU (106.7%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 736, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701384s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16294/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913968, over cnt = 46(0%), over = 57, worst = 4
+PHY-1002 : len = 914024, over cnt = 21(0%), over = 22, worst = 2
+PHY-1002 : len = 914256, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.620224s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (98.3%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.736347s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 21 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.655172
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 21ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740944, Over = 0
+PHY-3001 : End spreading; 0.057738s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.2%)
+
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.404192s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (112.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.723905s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.4%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16328/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126392s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.9%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+OPT-1001 : End congestion update; 0.436064s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (96.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701628s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740960, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056801s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.365434s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.3%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.608452s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.1%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 736, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16328/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.124329s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (100.5%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+OPT-1001 : End congestion update; 0.425348s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.993898s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.0%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740960, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061944s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.9%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.403401s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (143.3%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740960, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059194s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.417707s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.3%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.578033s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (106.1%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 736, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.718228s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 733, reserve = 736, peak = 737.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.723135s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.4%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16328/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126459s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.8%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+RUN-1001 : End congestion update; 0.435507s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.5%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.161789s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.5%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 736, peak = 737.
+OPT-1001 : End physical optimization; 27.927738s wall, 29.296875s user + 0.250000s system = 29.546875s CPU (105.8%)
+
+RUN-1003 : finish command "place" in 71.993578s wall, 101.406250s user + 6.046875s system = 107.453125s CPU (149.3%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 651 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.676751s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (173.3%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 652 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6732 instances
+RUN-1001 : 3292 mslices, 3289 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17900 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9980 nets have 2 pins
+RUN-1001 : 6546 nets have [3 - 5] pins
+RUN-1001 : 730 nets have [6 - 10] pins
+RUN-1001 : 302 nets have [11 - 20] pins
+RUN-1001 : 314 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71834, tnet num: 17722, tinst num: 6730, tnode num: 94415, tedge num: 119394.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.590821s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.2%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 617 MB, peak memory is 737 MB
+PHY-1001 : 3292 mslices, 3289 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 845368, over cnt = 2704(7%), over = 4369, worst = 7
+PHY-1002 : len = 862784, over cnt = 1666(4%), over = 2380, worst = 7
+PHY-1002 : len = 884176, over cnt = 537(1%), over = 769, worst = 5
+PHY-1002 : len = 896248, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 896472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.927777s wall, 3.921875s user + 0.015625s system = 3.937500s CPU (134.5%)
+
+PHY-1001 : Congestion index: top1 = 54.76, top5 = 49.22, top10 = 46.21, top15 = 44.14.
+PHY-1001 : End global routing; 3.242987s wall, 4.234375s user + 0.015625s system = 4.250000s CPU (131.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 702, reserve = 705, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 977, reserve = 981, peak = 977.
+PHY-1001 : End build detailed router design. 3.970132s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (99.6%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271464, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.019410s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271520, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.435784s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1012, reserve = 1016, peak = 1012.
+PHY-1001 : End phase 1; 5.467179s wall, 5.453125s user + 0.000000s system = 5.453125s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28506e+06, over cnt = 1600(0%), over = 1610, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1028, reserve = 1031, peak = 1028.
+PHY-1001 : End initial routed; 25.999823s wall, 60.421875s user + 0.203125s system = 60.625000s CPU (233.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16823(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.811 | -0.811 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.216742s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1042, peak = 1038.
+PHY-1001 : End phase 2; 29.216630s wall, 63.640625s user + 0.203125s system = 63.843750s CPU (218.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.807ns STNS -0.807ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.142300s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.8%)
+
+PHY-1022 : len = 2.28506e+06, over cnt = 1604(0%), over = 1614, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.395864s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.25794e+06, over cnt = 627(0%), over = 628, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.272903s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (179.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25642e+06, over cnt = 141(0%), over = 141, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.611484s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (166.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25698e+06, over cnt = 29(0%), over = 29, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.288748s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (124.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25733e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.190908s wall, 0.187500s user + 0.031250s system = 0.218750s CPU (114.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25737e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.196500s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (95.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16823(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.807 | -0.807 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.273229s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 364 nets
+PHY-1001 : End commit to database; 2.241782s wall, 2.218750s user + 0.031250s system = 2.250000s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1142, reserve = 1149, peak = 1142.
+PHY-1001 : End phase 3; 8.868904s wall, 10.312500s user + 0.078125s system = 10.390625s CPU (117.2%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.807ns STNS -0.807ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.133600s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.3%)
+
+PHY-1022 : len = 2.25737e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.367774s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.807ns, -0.807ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16823(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.807 | -0.807 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.155182s wall, 3.156250s user + 0.000000s system = 3.156250s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 364 nets
+PHY-1001 : End commit to database; 2.315115s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1150, reserve = 1157, peak = 1150.
+PHY-1001 : End phase 4; 5.863981s wall, 5.859375s user + 0.000000s system = 5.859375s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.25737e+06
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1159, peak = 1152.
+PHY-1001 : End export database. 0.059402s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.9%)
+
+PHY-1001 : End detail routing; 53.837216s wall, 89.640625s user + 0.312500s system = 89.953125s CPU (167.1%)
+
+RUN-1003 : finish command "route" in 59.755109s wall, 96.531250s user + 0.343750s system = 96.875000s CPU (162.1%)
+
+RUN-1004 : used memory is 1078 MB, reserved memory is 1083 MB, peak memory is 1152 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10185 out of 19600 51.96%
+#reg 9527 out of 19600 48.61%
+#le 12324
+ #lut only 2797 out of 12324 22.70%
+ #reg only 2139 out of 12324 17.36%
+ #lut® 7388 out of 12324 59.95%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1753
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1425
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1327
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 962
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 133
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/u_ADconfig/reg2_syn_84.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg32_syn_204.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P39 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P163 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P16 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P147 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P133 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P172 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P148 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12324 |9158 |1027 |9559 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |531 |458 |23 |446 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |81 |4 |88 |4 |0 |
+| U_crc16_24b |crc16_24b |38 |38 |0 |21 |0 |0 |
+| U_ecc_gen |ecc_gen |11 |11 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |750 |373 |96 |572 |0 |0 |
+| u_ADconfig |AD_config |186 |122 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |251 |159 |71 |117 |0 |0 |
+| exdev_ctl_b |exdev_ctl |732 |410 |96 |554 |0 |0 |
+| u_ADconfig |AD_config |165 |117 |25 |122 |0 |0 |
+| u_gen_sp |gen_sp |252 |159 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |2949 |2400 |306 |2094 |25 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |191 |136 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort |2726 |2245 |289 |1903 |25 |0 |
+| rddpram_ctl |rddpram_ctl |7 |3 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |3 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2281 |1899 |253 |1537 |22 |0 |
+| channelPart |channel_part_8478 |130 |123 |3 |125 |0 |0 |
+| fifo_adc |fifo_adc |57 |48 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1795 |1490 |197 |1153 |0 |0 |
+| adc_addr_gen |adc_addr_gen |223 |196 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |16 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| insert |insert |967 |689 |170 |663 |0 |0 |
+| ram_switch_state |ram_switch_state |605 |605 |0 |367 |0 |0 |
+| read_ram_i |read_ram |266 |217 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |219 |179 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |43 |34 |4 |31 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |318 |232 |36 |270 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3168 |2463 |349 |2092 |25 |1 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |114 |17 |157 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |2945 |2344 |332 |1902 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2515 |2013 |290 |1557 |22 |1 |
+| channelPart |channel_part_8478 |143 |135 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1931 |1557 |197 |1143 |0 |0 |
+| adc_addr_gen |adc_addr_gen |199 |172 |27 |103 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |14 |11 |3 |6 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| insert |insert |947 |606 |170 |659 |0 |0 |
+| ram_switch_state |ram_switch_state |785 |779 |0 |381 |0 |0 |
+| read_ram_i |read_ram_rev |352 |247 |81 |209 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |166 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |37 |8 |43 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9918
+ #2 2 4275
+ #3 3 1701
+ #4 4 567
+ #5 5-10 765
+ #6 11-50 565
+ #7 51-100 13
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.031784s wall, 3.453125s user + 0.046875s system = 3.500000s CPU (172.3%)
+
+RUN-1004 : used memory is 1079 MB, reserved memory is 1084 MB, peak memory is 1152 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71834, tnet num: 17722, tinst num: 6730, tnode num: 94415, tedge num: 119394.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.553400s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.6%)
+
+RUN-1004 : used memory is 1083 MB, reserved memory is 1088 MB, peak memory is 1152 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.393625s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (100.9%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1090 MB, peak memory is 1152 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6730
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17900, pip num: 168360
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 496
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3251 valid insts, and 469670 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.994543s wall, 67.625000s user + 0.171875s system = 67.796875s CPU (678.3%)
+
+RUN-1004 : used memory is 1245 MB, reserved memory is 1248 MB, peak memory is 1361 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_191907.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_193153.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_193153.log
new file mode 100644
index 0000000..5b7f029
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_193153.log
@@ -0,0 +1,2025 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 19:31:53 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(911)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(920)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(944)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(952)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(955)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1126)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1215)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1527)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1545)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1727)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.225713s wall, 2.171875s user + 0.062500s system = 2.234375s CPU (100.4%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 316 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18043 instances
+RUN-0007 : 7651 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20620 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13128 nets have 2 pins
+RUN-1001 : 6458 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 177 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18041 instances, 7651 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6041 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84277, tnet num: 20442, tinst num: 18041, tnode num: 114832, tedge num: 134420.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.172331s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (100.0%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 516 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20442 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.945295s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (99.6%)
+
+PHY-3001 : Found 1252 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.13245e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18041.
+PHY-3001 : Level 1 #clusters 1993.
+PHY-3001 : End clustering; 0.123708s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.34197e+06, overlap = 466.938
+PHY-3002 : Step(2): len = 1.24427e+06, overlap = 513.062
+PHY-3002 : Step(3): len = 852201, overlap = 605
+PHY-3002 : Step(4): len = 785348, overlap = 640.438
+PHY-3002 : Step(5): len = 609157, overlap = 753.219
+PHY-3002 : Step(6): len = 540844, overlap = 831.938
+PHY-3002 : Step(7): len = 453456, overlap = 949.906
+PHY-3002 : Step(8): len = 414967, overlap = 981.438
+PHY-3002 : Step(9): len = 380016, overlap = 1035.16
+PHY-3002 : Step(10): len = 358898, overlap = 1051.38
+PHY-3002 : Step(11): len = 317478, overlap = 1131.19
+PHY-3002 : Step(12): len = 297738, overlap = 1165.22
+PHY-3002 : Step(13): len = 264372, overlap = 1211.97
+PHY-3002 : Step(14): len = 250662, overlap = 1279.16
+PHY-3002 : Step(15): len = 228888, overlap = 1353.59
+PHY-3002 : Step(16): len = 216467, overlap = 1362.94
+PHY-3002 : Step(17): len = 190813, overlap = 1384.22
+PHY-3002 : Step(18): len = 179489, overlap = 1389.75
+PHY-3002 : Step(19): len = 160429, overlap = 1412.28
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.15648e-06
+PHY-3002 : Step(20): len = 163972, overlap = 1354.12
+PHY-3002 : Step(21): len = 201281, overlap = 1252.66
+PHY-3002 : Step(22): len = 206721, overlap = 1156.44
+PHY-3002 : Step(23): len = 208610, overlap = 1096.31
+PHY-3002 : Step(24): len = 204925, overlap = 1068.09
+PHY-3002 : Step(25): len = 204113, overlap = 1063.53
+PHY-3002 : Step(26): len = 199189, overlap = 1069.16
+PHY-3002 : Step(27): len = 195373, overlap = 1031.41
+PHY-3002 : Step(28): len = 191117, overlap = 1026.25
+PHY-3002 : Step(29): len = 189460, overlap = 1046.06
+PHY-3002 : Step(30): len = 183657, overlap = 1071.22
+PHY-3002 : Step(31): len = 182341, overlap = 1076.5
+PHY-3002 : Step(32): len = 179551, overlap = 1068.31
+PHY-3002 : Step(33): len = 177911, overlap = 1061.53
+PHY-3002 : Step(34): len = 175711, overlap = 1052.69
+PHY-3002 : Step(35): len = 174310, overlap = 1061.78
+PHY-3002 : Step(36): len = 173599, overlap = 1073.59
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.31297e-06
+PHY-3002 : Step(37): len = 178620, overlap = 1034.09
+PHY-3002 : Step(38): len = 191435, overlap = 986.625
+PHY-3002 : Step(39): len = 195811, overlap = 959.188
+PHY-3002 : Step(40): len = 200342, overlap = 958
+PHY-3002 : Step(41): len = 201322, overlap = 948.719
+PHY-3002 : Step(42): len = 202487, overlap = 939.562
+PHY-3002 : Step(43): len = 200994, overlap = 937.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.62593e-06
+PHY-3002 : Step(44): len = 209064, overlap = 921.406
+PHY-3002 : Step(45): len = 227413, overlap = 840.906
+PHY-3002 : Step(46): len = 237771, overlap = 800.062
+PHY-3002 : Step(47): len = 247731, overlap = 784.531
+PHY-3002 : Step(48): len = 248772, overlap = 737.688
+PHY-3002 : Step(49): len = 249695, overlap = 704.094
+PHY-3002 : Step(50): len = 247011, overlap = 702.875
+PHY-3002 : Step(51): len = 246000, overlap = 694.594
+PHY-3002 : Step(52): len = 244238, overlap = 696.344
+PHY-3002 : Step(53): len = 244102, overlap = 682.75
+PHY-3002 : Step(54): len = 242183, overlap = 692.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.25186e-06
+PHY-3002 : Step(55): len = 258698, overlap = 657.781
+PHY-3002 : Step(56): len = 280221, overlap = 625.906
+PHY-3002 : Step(57): len = 292855, overlap = 553.156
+PHY-3002 : Step(58): len = 299685, overlap = 534.281
+PHY-3002 : Step(59): len = 299290, overlap = 521.531
+PHY-3002 : Step(60): len = 298426, overlap = 522.938
+PHY-3002 : Step(61): len = 294494, overlap = 511.094
+PHY-3002 : Step(62): len = 294480, overlap = 510.438
+PHY-3002 : Step(63): len = 294785, overlap = 518.75
+PHY-3002 : Step(64): len = 294441, overlap = 517.156
+PHY-3002 : Step(65): len = 292685, overlap = 507.281
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.85037e-05
+PHY-3002 : Step(66): len = 309552, overlap = 473.906
+PHY-3002 : Step(67): len = 322213, overlap = 449.625
+PHY-3002 : Step(68): len = 328638, overlap = 421.812
+PHY-3002 : Step(69): len = 334979, overlap = 384.969
+PHY-3002 : Step(70): len = 333742, overlap = 366.125
+PHY-3002 : Step(71): len = 334969, overlap = 380.969
+PHY-3002 : Step(72): len = 333734, overlap = 367.219
+PHY-3002 : Step(73): len = 333599, overlap = 368.281
+PHY-3002 : Step(74): len = 332967, overlap = 356.188
+PHY-3002 : Step(75): len = 332548, overlap = 362.812
+PHY-3002 : Step(76): len = 331582, overlap = 368.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.70075e-05
+PHY-3002 : Step(77): len = 346935, overlap = 355.531
+PHY-3002 : Step(78): len = 360541, overlap = 340.5
+PHY-3002 : Step(79): len = 365585, overlap = 345.438
+PHY-3002 : Step(80): len = 368061, overlap = 326.375
+PHY-3002 : Step(81): len = 368156, overlap = 327.969
+PHY-3002 : Step(82): len = 371772, overlap = 315.406
+PHY-3002 : Step(83): len = 371705, overlap = 316.25
+PHY-3002 : Step(84): len = 374787, overlap = 299.25
+PHY-3002 : Step(85): len = 375389, overlap = 305.531
+PHY-3002 : Step(86): len = 378571, overlap = 319.906
+PHY-3002 : Step(87): len = 376491, overlap = 324.344
+PHY-3002 : Step(88): len = 375943, overlap = 318.906
+PHY-3002 : Step(89): len = 374849, overlap = 312.812
+PHY-3002 : Step(90): len = 376186, overlap = 304.312
+PHY-3002 : Step(91): len = 374732, overlap = 307.25
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.40149e-05
+PHY-3002 : Step(92): len = 392549, overlap = 314.656
+PHY-3002 : Step(93): len = 402031, overlap = 306
+PHY-3002 : Step(94): len = 400355, overlap = 304.125
+PHY-3002 : Step(95): len = 400584, overlap = 291.406
+PHY-3002 : Step(96): len = 402880, overlap = 289.594
+PHY-3002 : Step(97): len = 405851, overlap = 290.594
+PHY-3002 : Step(98): len = 405212, overlap = 285.656
+PHY-3002 : Step(99): len = 406774, overlap = 272.25
+PHY-3002 : Step(100): len = 409007, overlap = 274.812
+PHY-3002 : Step(101): len = 410856, overlap = 253.562
+PHY-3002 : Step(102): len = 408887, overlap = 245.688
+PHY-3002 : Step(103): len = 409536, overlap = 238.562
+PHY-3002 : Step(104): len = 410454, overlap = 239.688
+PHY-3002 : Step(105): len = 411529, overlap = 233.156
+PHY-3002 : Step(106): len = 410189, overlap = 232.75
+PHY-3002 : Step(107): len = 411151, overlap = 227.844
+PHY-3002 : Step(108): len = 412120, overlap = 223.594
+PHY-3002 : Step(109): len = 413857, overlap = 225.156
+PHY-3002 : Step(110): len = 411994, overlap = 213.531
+PHY-3002 : Step(111): len = 412726, overlap = 205.969
+PHY-3002 : Step(112): len = 413694, overlap = 205.531
+PHY-3002 : Step(113): len = 415201, overlap = 201.938
+PHY-3002 : Step(114): len = 413284, overlap = 212.312
+PHY-3002 : Step(115): len = 413577, overlap = 223
+PHY-3002 : Step(116): len = 413948, overlap = 220.125
+PHY-3002 : Step(117): len = 414703, overlap = 210.625
+PHY-3002 : Step(118): len = 412425, overlap = 225.875
+PHY-3002 : Step(119): len = 412305, overlap = 223.594
+PHY-3002 : Step(120): len = 412370, overlap = 220.281
+PHY-3002 : Step(121): len = 412966, overlap = 214.375
+PHY-3002 : Step(122): len = 411157, overlap = 218.938
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00014803
+PHY-3002 : Step(123): len = 423906, overlap = 216.688
+PHY-3002 : Step(124): len = 430715, overlap = 208.375
+PHY-3002 : Step(125): len = 430889, overlap = 209.219
+PHY-3002 : Step(126): len = 432021, overlap = 202.688
+PHY-3002 : Step(127): len = 435312, overlap = 198.219
+PHY-3002 : Step(128): len = 438295, overlap = 196.969
+PHY-3002 : Step(129): len = 437427, overlap = 192.844
+PHY-3002 : Step(130): len = 437998, overlap = 206.969
+PHY-3002 : Step(131): len = 440582, overlap = 195.844
+PHY-3002 : Step(132): len = 442391, overlap = 194.156
+PHY-3002 : Step(133): len = 440198, overlap = 194.188
+PHY-3002 : Step(134): len = 439515, overlap = 192.562
+PHY-3002 : Step(135): len = 440457, overlap = 185.969
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00029606
+PHY-3002 : Step(136): len = 450143, overlap = 184.375
+PHY-3002 : Step(137): len = 457161, overlap = 187.125
+PHY-3002 : Step(138): len = 457846, overlap = 188.656
+PHY-3002 : Step(139): len = 459051, overlap = 188.312
+PHY-3002 : Step(140): len = 461731, overlap = 181.844
+PHY-3002 : Step(141): len = 464778, overlap = 175.188
+PHY-3002 : Step(142): len = 465194, overlap = 169.812
+PHY-3002 : Step(143): len = 467850, overlap = 169.625
+PHY-3002 : Step(144): len = 471018, overlap = 171.156
+PHY-3002 : Step(145): len = 473746, overlap = 169.312
+PHY-3002 : Step(146): len = 473908, overlap = 160.906
+PHY-3002 : Step(147): len = 474662, overlap = 155.875
+PHY-3002 : Step(148): len = 475942, overlap = 159.969
+PHY-3002 : Step(149): len = 476507, overlap = 159.75
+PHY-3002 : Step(150): len = 475070, overlap = 168.219
+PHY-3002 : Step(151): len = 474936, overlap = 167
+PHY-3002 : Step(152): len = 475680, overlap = 162.875
+PHY-3002 : Step(153): len = 475979, overlap = 161.906
+PHY-3002 : Step(154): len = 475139, overlap = 156.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00053253
+PHY-3002 : Step(155): len = 480495, overlap = 151.688
+PHY-3002 : Step(156): len = 486210, overlap = 135.875
+PHY-3002 : Step(157): len = 487783, overlap = 139.875
+PHY-3002 : Step(158): len = 488914, overlap = 141.438
+PHY-3002 : Step(159): len = 491409, overlap = 139.969
+PHY-3002 : Step(160): len = 493061, overlap = 135.75
+PHY-3002 : Step(161): len = 492488, overlap = 134.781
+PHY-3002 : Step(162): len = 492508, overlap = 135.594
+PHY-3002 : Step(163): len = 493588, overlap = 133
+PHY-3002 : Step(164): len = 494730, overlap = 135.375
+PHY-3002 : Step(165): len = 493713, overlap = 133.969
+PHY-3002 : Step(166): len = 493539, overlap = 131.125
+PHY-3002 : Step(167): len = 494667, overlap = 127.312
+PHY-3002 : Step(168): len = 495482, overlap = 128.812
+PHY-3002 : Step(169): len = 494704, overlap = 129.875
+PHY-3002 : Step(170): len = 494608, overlap = 129.125
+PHY-3002 : Step(171): len = 495540, overlap = 133.594
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00102595
+PHY-3002 : Step(172): len = 500446, overlap = 133.219
+PHY-3002 : Step(173): len = 509392, overlap = 136.375
+PHY-3002 : Step(174): len = 514927, overlap = 135.062
+PHY-3002 : Step(175): len = 518967, overlap = 132.812
+PHY-3002 : Step(176): len = 519623, overlap = 127.188
+PHY-3002 : Step(177): len = 519706, overlap = 129.5
+PHY-3002 : Step(178): len = 519023, overlap = 130.594
+PHY-3002 : Step(179): len = 518873, overlap = 139.469
+PHY-3002 : Step(180): len = 519508, overlap = 138.938
+PHY-3002 : Step(181): len = 519954, overlap = 135.938
+PHY-3002 : Step(182): len = 519697, overlap = 132.312
+PHY-3002 : Step(183): len = 520145, overlap = 131
+PHY-3002 : Step(184): len = 520965, overlap = 132.688
+PHY-3002 : Step(185): len = 521357, overlap = 133.75
+PHY-3002 : Step(186): len = 521059, overlap = 133.875
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00178127
+PHY-3002 : Step(187): len = 523218, overlap = 136.375
+PHY-3002 : Step(188): len = 525924, overlap = 136
+PHY-3002 : Step(189): len = 526937, overlap = 136.656
+PHY-3002 : Step(190): len = 527885, overlap = 137.656
+PHY-3002 : Step(191): len = 529186, overlap = 137.281
+PHY-3002 : Step(192): len = 530153, overlap = 140.688
+PHY-3002 : Step(193): len = 530395, overlap = 140.938
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.036662s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (127.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20620.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724952, over cnt = 1645(4%), over = 7927, worst = 37
+PHY-1001 : End global iterations; 0.742895s wall, 1.078125s user + 0.046875s system = 1.125000s CPU (151.4%)
+
+PHY-1001 : Congestion index: top1 = 88.53, top5 = 65.86, top10 = 55.65, top15 = 49.14.
+PHY-3001 : End congestion estimation; 1.015742s wall, 1.343750s user + 0.046875s system = 1.390625s CPU (136.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20442 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.921204s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000141256
+PHY-3002 : Step(194): len = 655790, overlap = 89.8438
+PHY-3002 : Step(195): len = 658562, overlap = 82.8125
+PHY-3002 : Step(196): len = 652387, overlap = 75.7812
+PHY-3002 : Step(197): len = 648349, overlap = 72.4688
+PHY-3002 : Step(198): len = 646784, overlap = 68.375
+PHY-3002 : Step(199): len = 646855, overlap = 73.1562
+PHY-3002 : Step(200): len = 645075, overlap = 73.4062
+PHY-3002 : Step(201): len = 643128, overlap = 71.0312
+PHY-3002 : Step(202): len = 640669, overlap = 64.7188
+PHY-3002 : Step(203): len = 637655, overlap = 61.2812
+PHY-3002 : Step(204): len = 634283, overlap = 58.9062
+PHY-3002 : Step(205): len = 632408, overlap = 55.1875
+PHY-3002 : Step(206): len = 631735, overlap = 47.8125
+PHY-3002 : Step(207): len = 631547, overlap = 43.4688
+PHY-3002 : Step(208): len = 632161, overlap = 38.5625
+PHY-3002 : Step(209): len = 631801, overlap = 35.9062
+PHY-3002 : Step(210): len = 631371, overlap = 36.6875
+PHY-3002 : Step(211): len = 632196, overlap = 37.0625
+PHY-3002 : Step(212): len = 631715, overlap = 33.3125
+PHY-3002 : Step(213): len = 630556, overlap = 33.0625
+PHY-3002 : Step(214): len = 630519, overlap = 33.8438
+PHY-3002 : Step(215): len = 630027, overlap = 31.9688
+PHY-3002 : Step(216): len = 629238, overlap = 31.3125
+PHY-3002 : Step(217): len = 627936, overlap = 29.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000282512
+PHY-3002 : Step(218): len = 630696, overlap = 28.5938
+PHY-3002 : Step(219): len = 633404, overlap = 27.9688
+PHY-3002 : Step(220): len = 635531, overlap = 28.2812
+PHY-3002 : Step(221): len = 638426, overlap = 27.9375
+PHY-3002 : Step(222): len = 641664, overlap = 27.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000557925
+PHY-3002 : Step(223): len = 644649, overlap = 28.4062
+PHY-3002 : Step(224): len = 659811, overlap = 25.8438
+PHY-3002 : Step(225): len = 685281, overlap = 33.4688
+PHY-3002 : Step(226): len = 683960, overlap = 30.25
+PHY-3002 : Step(227): len = 680144, overlap = 29.1875
+PHY-3002 : Step(228): len = 677151, overlap = 31.3125
+PHY-3002 : Step(229): len = 675999, overlap = 32.875
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000933545
+PHY-3002 : Step(230): len = 682493, overlap = 35.5625
+PHY-3002 : Step(231): len = 690714, overlap = 37.375
+PHY-3002 : Step(232): len = 693518, overlap = 37.1875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00152519
+PHY-3002 : Step(233): len = 697394, overlap = 36.8438
+PHY-3002 : Step(234): len = 722445, overlap = 39.0938
+PHY-3002 : Step(235): len = 741280, overlap = 43.75
+PHY-3002 : Step(236): len = 738693, overlap = 44.8438
+PHY-3002 : Step(237): len = 732230, overlap = 47.125
+PHY-3002 : Step(238): len = 725958, overlap = 46
+PHY-3002 : Step(239): len = 724675, overlap = 45.875
+PHY-3002 : Step(240): len = 725183, overlap = 44.4062
+PHY-3002 : Step(241): len = 728298, overlap = 44.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 61/20620.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 810000, over cnt = 2790(7%), over = 13848, worst = 54
+PHY-1001 : End global iterations; 1.617003s wall, 2.140625s user + 0.000000s system = 2.140625s CPU (132.4%)
+
+PHY-1001 : Congestion index: top1 = 96.25, top5 = 75.14, top10 = 65.63, top15 = 59.65.
+PHY-3001 : End congestion estimation; 1.926563s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (126.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20442 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.107483s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000122139
+PHY-3002 : Step(242): len = 714798, overlap = 271.594
+PHY-3002 : Step(243): len = 705130, overlap = 231.781
+PHY-3002 : Step(244): len = 692348, overlap = 209.75
+PHY-3002 : Step(245): len = 680300, overlap = 192.031
+PHY-3002 : Step(246): len = 669717, overlap = 164.188
+PHY-3002 : Step(247): len = 662612, overlap = 155.094
+PHY-3002 : Step(248): len = 656297, overlap = 153
+PHY-3002 : Step(249): len = 650296, overlap = 147.188
+PHY-3002 : Step(250): len = 647302, overlap = 137.344
+PHY-3002 : Step(251): len = 642350, overlap = 129.531
+PHY-3002 : Step(252): len = 637744, overlap = 134.281
+PHY-3002 : Step(253): len = 633423, overlap = 142
+PHY-3002 : Step(254): len = 630984, overlap = 142.188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000244277
+PHY-3002 : Step(255): len = 630798, overlap = 135.688
+PHY-3002 : Step(256): len = 632684, overlap = 133.062
+PHY-3002 : Step(257): len = 636403, overlap = 124.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000488555
+PHY-3002 : Step(258): len = 639868, overlap = 113.312
+PHY-3002 : Step(259): len = 646150, overlap = 99.0312
+PHY-3002 : Step(260): len = 651786, overlap = 91.5625
+PHY-3002 : Step(261): len = 653653, overlap = 86.9375
+PHY-3002 : Step(262): len = 653845, overlap = 82.9688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00097711
+PHY-3002 : Step(263): len = 656347, overlap = 77.2812
+PHY-3002 : Step(264): len = 660237, overlap = 75.8438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.0016972
+PHY-3002 : Step(265): len = 662531, overlap = 70.0312
+PHY-3002 : Step(266): len = 673095, overlap = 60.4688
+PHY-3002 : Step(267): len = 681282, overlap = 59.3125
+PHY-3002 : Step(268): len = 680752, overlap = 58.4375
+PHY-3002 : Step(269): len = 679618, overlap = 58.0625
+PHY-3002 : Step(270): len = 679533, overlap = 57.5
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84277, tnet num: 20442, tinst num: 18041, tnode num: 114832, tedge num: 134420.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.490052s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (99.6%)
+
+RUN-1004 : used memory is 580 MB, reserved memory is 565 MB, peak memory is 716 MB
+OPT-1001 : Total overflow 374.28 peak overflow 3.69
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 641/20620.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 776760, over cnt = 3171(9%), over = 11211, worst = 26
+PHY-1001 : End global iterations; 1.381248s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 71.77, top5 = 59.12, top10 = 53.02, top15 = 49.14.
+PHY-1001 : End incremental global routing; 1.729300s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (131.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20442 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.912465s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (101.0%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17909 has valid locations, 297 needs to be replaced
+PHY-3001 : design contains 18291 instances, 7739 luts, 9331 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6156 pins
+PHY-3001 : Found 1261 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 703467
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17263/20870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 792168, over cnt = 3180(9%), over = 11273, worst = 26
+PHY-1001 : End global iterations; 0.228349s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 71.29, top5 = 59.30, top10 = 53.19, top15 = 49.33.
+PHY-3001 : End congestion estimation; 0.478009s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (120.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85274, tnet num: 20692, tinst num: 18291, tnode num: 116331, tedge num: 135914.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.452012s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (100.1%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 615 MB, peak memory is 719 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.393649s wall, 2.312500s user + 0.078125s system = 2.390625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(271): len = 702266, overlap = 0
+PHY-3002 : Step(272): len = 701767, overlap = 0
+PHY-3002 : Step(273): len = 701456, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17368/20870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 790584, over cnt = 3191(9%), over = 11343, worst = 26
+PHY-1001 : End global iterations; 0.187311s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (125.1%)
+
+PHY-1001 : Congestion index: top1 = 71.47, top5 = 59.89, top10 = 53.62, top15 = 49.62.
+PHY-3001 : End congestion estimation; 0.451221s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (110.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.338079s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000476517
+PHY-3002 : Step(274): len = 701327, overlap = 59.625
+PHY-3002 : Step(275): len = 701676, overlap = 59.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000953034
+PHY-3002 : Step(276): len = 701687, overlap = 58.9062
+PHY-3002 : Step(277): len = 702116, overlap = 58.6875
+PHY-3001 : Final: Len = 702116, Over = 58.6875
+PHY-3001 : End incremental placement; 5.306610s wall, 5.453125s user + 0.296875s system = 5.750000s CPU (108.4%)
+
+OPT-1001 : Total overflow 380.41 peak overflow 3.69
+OPT-1001 : End high-fanout net optimization; 8.637123s wall, 9.375000s user + 0.343750s system = 9.718750s CPU (112.5%)
+
+OPT-1001 : Current memory(MB): used = 724, reserve = 714, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17286/20870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 794440, over cnt = 3127(8%), over = 10244, worst = 26
+PHY-1002 : len = 843104, over cnt = 2135(6%), over = 5358, worst = 20
+PHY-1002 : len = 885064, over cnt = 793(2%), over = 1976, worst = 16
+PHY-1002 : len = 902992, over cnt = 321(0%), over = 717, worst = 13
+PHY-1002 : len = 915040, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.003366s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (137.3%)
+
+PHY-1001 : Congestion index: top1 = 58.49, top5 = 51.64, top10 = 47.98, top15 = 45.57.
+OPT-1001 : End congestion update; 2.271545s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (132.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.780388s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.1%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 132 cells processed and 22900 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 11 cells processed and 1800 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 4 cells processed and 1100 slack improved
+OPT-1001 : End bottleneck based optimization; 3.374098s wall, 4.109375s user + 0.000000s system = 4.109375s CPU (121.8%)
+
+OPT-1001 : Current memory(MB): used = 700, reserve = 693, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17337/20878.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 916096, over cnt = 84(0%), over = 111, worst = 4
+PHY-1002 : len = 915824, over cnt = 43(0%), over = 46, worst = 2
+PHY-1002 : len = 916120, over cnt = 18(0%), over = 19, worst = 2
+PHY-1002 : len = 916312, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 916408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.747740s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.3%)
+
+PHY-1001 : Congestion index: top1 = 58.32, top5 = 51.62, top10 = 47.91, top15 = 45.53.
+OPT-1001 : End congestion update; 1.012323s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20700 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804911s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (100.9%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 18 cells processed and 3700 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.944010s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 702, peak = 740.
+OPT-1001 : End physical optimization; 15.743451s wall, 17.171875s user + 0.390625s system = 17.562500s CPU (111.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7739 LUT to BLE ...
+SYN-4008 : Packed 7739 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6192 remaining SEQ's ...
+SYN-4005 : Packed 4165 SEQ with LUT/SLICE
+SYN-4006 : 726 single LUT's are left
+SYN-4006 : 2027 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9766/13553 primitive instances ...
+PHY-3001 : End packing; 1.633511s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6628 instances
+RUN-1001 : 3240 mslices, 3240 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17868 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10007 nets have 2 pins
+RUN-1001 : 6516 nets have [3 - 5] pins
+RUN-1001 : 723 nets have [6 - 10] pins
+RUN-1001 : 291 nets have [11 - 20] pins
+RUN-1001 : 299 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6626 instances, 6480 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3546 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 708210, Over = 191.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7608/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858808, over cnt = 1941(5%), over = 3178, worst = 9
+PHY-1002 : len = 866408, over cnt = 1325(3%), over = 1935, worst = 9
+PHY-1002 : len = 883768, over cnt = 331(0%), over = 445, worst = 5
+PHY-1002 : len = 889096, over cnt = 53(0%), over = 62, worst = 4
+PHY-1002 : len = 890896, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.751268s wall, 2.234375s user + 0.031250s system = 2.265625s CPU (129.4%)
+
+PHY-1001 : Congestion index: top1 = 57.46, top5 = 50.66, top10 = 47.02, top15 = 44.59.
+PHY-3001 : End congestion estimation; 2.166834s wall, 2.656250s user + 0.031250s system = 2.687500s CPU (124.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71368, tnet num: 17690, tinst num: 6626, tnode num: 93752, tedge num: 118683.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.576321s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.1%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 616 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.411844s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.07457e-05
+PHY-3002 : Step(278): len = 695277, overlap = 194.75
+PHY-3002 : Step(279): len = 687561, overlap = 202
+PHY-3002 : Step(280): len = 681989, overlap = 204.5
+PHY-3002 : Step(281): len = 677959, overlap = 215
+PHY-3002 : Step(282): len = 674713, overlap = 223.25
+PHY-3002 : Step(283): len = 671683, overlap = 225
+PHY-3002 : Step(284): len = 668798, overlap = 229.5
+PHY-3002 : Step(285): len = 665610, overlap = 234.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000121491
+PHY-3002 : Step(286): len = 669025, overlap = 230.25
+PHY-3002 : Step(287): len = 673020, overlap = 225.25
+PHY-3002 : Step(288): len = 672942, overlap = 227
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000242983
+PHY-3002 : Step(289): len = 681700, overlap = 201
+PHY-3002 : Step(290): len = 689059, overlap = 190.75
+PHY-3002 : Step(291): len = 687686, overlap = 193.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.386931s wall, 0.375000s user + 0.609375s system = 0.984375s CPU (254.4%)
+
+PHY-3001 : Trial Legalized: Len = 763721
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 748/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876200, over cnt = 2707(7%), over = 4621, worst = 11
+PHY-1002 : len = 892488, over cnt = 1774(5%), over = 2662, worst = 7
+PHY-1002 : len = 913936, over cnt = 646(1%), over = 964, worst = 6
+PHY-1002 : len = 926104, over cnt = 185(0%), over = 283, worst = 6
+PHY-1002 : len = 931144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.357989s wall, 3.343750s user + 0.015625s system = 3.359375s CPU (142.5%)
+
+PHY-1001 : Congestion index: top1 = 57.89, top5 = 50.36, top10 = 47.21, top15 = 45.14.
+PHY-3001 : End congestion estimation; 2.829417s wall, 3.796875s user + 0.031250s system = 3.828125s CPU (135.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.878007s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000174701
+PHY-3002 : Step(292): len = 737938, overlap = 41.75
+PHY-3002 : Step(293): len = 722232, overlap = 65
+PHY-3002 : Step(294): len = 708693, overlap = 92
+PHY-3002 : Step(295): len = 701401, overlap = 110.5
+PHY-3002 : Step(296): len = 696519, overlap = 125.25
+PHY-3002 : Step(297): len = 694466, overlap = 134.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000349402
+PHY-3002 : Step(298): len = 698764, overlap = 129.5
+PHY-3002 : Step(299): len = 703075, overlap = 125.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000698804
+PHY-3002 : Step(300): len = 709503, overlap = 121.5
+PHY-3002 : Step(301): len = 716505, overlap = 120
+PHY-3002 : Step(302): len = 716226, overlap = 121.5
+PHY-3002 : Step(303): len = 715766, overlap = 120.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032550s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (96.0%)
+
+PHY-3001 : Legalized: Len = 742148, Over = 0
+PHY-3001 : Spreading special nets. 462 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.102872s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (106.3%)
+
+PHY-3001 : 667 instances has been re-located, deltaX = 179, deltaY = 416, maxDist = 3.
+PHY-3001 : Final: Len = 753944, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71368, tnet num: 17690, tinst num: 6629, tnode num: 93752, tedge num: 118683.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.923309s wall, 1.843750s user + 0.062500s system = 1.906250s CPU (99.1%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 645 MB, peak memory is 740 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4253/17868.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 882064, over cnt = 2461(6%), over = 3983, worst = 9
+PHY-1002 : len = 893120, over cnt = 1530(4%), over = 2289, worst = 7
+PHY-1002 : len = 910928, over cnt = 633(1%), over = 941, worst = 7
+PHY-1002 : len = 923856, over cnt = 71(0%), over = 93, worst = 3
+PHY-1002 : len = 925200, over cnt = 5(0%), over = 5, worst = 1
+PHY-1001 : End global iterations; 2.177622s wall, 3.109375s user + 0.000000s system = 3.109375s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 56.77, top5 = 49.94, top10 = 46.47, top15 = 44.30.
+PHY-1001 : End incremental global routing; 2.585520s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (136.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.889862s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.1%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6536 has valid locations, 29 needs to be replaced
+PHY-3001 : design contains 6653 instances, 6504 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3610 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 758797
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16232/17891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 931368, over cnt = 111(0%), over = 137, worst = 7
+PHY-1002 : len = 931640, over cnt = 61(0%), over = 67, worst = 4
+PHY-1002 : len = 931984, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 932248, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 932568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.797796s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 56.77, top5 = 50.11, top10 = 46.74, top15 = 44.60.
+PHY-3001 : End congestion estimation; 1.107746s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (104.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71573, tnet num: 17713, tinst num: 6653, tnode num: 94012, tedge num: 118947.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.991453s wall, 1.890625s user + 0.031250s system = 1.921875s CPU (96.5%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 655 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.954712s wall, 2.828125s user + 0.046875s system = 2.875000s CPU (97.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(304): len = 757369, overlap = 0.25
+PHY-3002 : Step(305): len = 756888, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16218/17891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929168, over cnt = 93(0%), over = 120, worst = 7
+PHY-1002 : len = 929512, over cnt = 40(0%), over = 40, worst = 1
+PHY-1002 : len = 929824, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 929960, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 930032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.855916s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (105.9%)
+
+PHY-1001 : Congestion index: top1 = 56.77, top5 = 49.97, top10 = 46.56, top15 = 44.44.
+PHY-3001 : End congestion estimation; 1.189709s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (105.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.936560s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (98.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000173116
+PHY-3002 : Step(306): len = 756680, overlap = 2.5
+PHY-3002 : Step(307): len = 756685, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006362s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 756828, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065964s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.7%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 756828, Over = 0
+PHY-3001 : End incremental placement; 6.701622s wall, 6.875000s user + 0.140625s system = 7.015625s CPU (104.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.673674s wall, 11.781250s user + 0.140625s system = 11.921875s CPU (111.7%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 729, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16214/17891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929808, over cnt = 52(0%), over = 70, worst = 5
+PHY-1002 : len = 930016, over cnt = 26(0%), over = 32, worst = 4
+PHY-1002 : len = 930216, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 930264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.669795s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (109.6%)
+
+PHY-1001 : Congestion index: top1 = 56.77, top5 = 49.95, top10 = 46.56, top15 = 44.41.
+OPT-1001 : End congestion update; 1.010657s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (105.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717813s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.1%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6565 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6653 instances, 6504 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3610 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 764167, Over = 0
+PHY-3001 : Spreading special nets. 39 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065162s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.9%)
+
+PHY-3001 : 63 instances has been re-located, deltaX = 35, deltaY = 47, maxDist = 4.
+PHY-3001 : Final: Len = 765609, Over = 0
+PHY-3001 : End incremental legalization; 0.393063s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 65 cells processed and 20372 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6565 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6653 instances, 6504 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3610 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 765451, Over = 0
+PHY-3001 : Spreading special nets. 23 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062168s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 33 instances has been re-located, deltaX = 22, deltaY = 22, maxDist = 3.
+PHY-3001 : Final: Len = 766263, Over = 0
+PHY-3001 : End incremental legalization; 0.382275s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.2%)
+
+OPT-0007 : Iter 2: improved WNS 21 TNS 0 NUM_FEPS 0 with 33 cells processed and 3463 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6575 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6663 instances, 6514 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3613 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 767061, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059125s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.7%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 8, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 767259, Over = 0
+PHY-3001 : End incremental legalization; 0.385082s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.4%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 10 cells processed and 1846 slack improved
+OPT-1001 : End bottleneck based optimization; 3.388883s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (103.7%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 729, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15709/17893.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 939784, over cnt = 228(0%), over = 298, worst = 8
+PHY-1002 : len = 939792, over cnt = 144(0%), over = 170, worst = 6
+PHY-1002 : len = 941096, over cnt = 53(0%), over = 55, worst = 2
+PHY-1002 : len = 942072, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 942200, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.892102s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (106.8%)
+
+PHY-1001 : Congestion index: top1 = 56.44, top5 = 49.88, top10 = 46.46, top15 = 44.39.
+OPT-1001 : End congestion update; 1.215733s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (105.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.729387s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.7%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6575 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6663 instances, 6514 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3613 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 767087, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060783s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.8%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 767391, Over = 0
+PHY-3001 : End incremental legalization; 0.385315s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.3%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 13 cells processed and 1150 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.458858s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (106.1%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 729, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.737445s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16218/17893.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942056, over cnt = 28(0%), over = 36, worst = 3
+PHY-1002 : len = 942080, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 942096, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 942224, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 942368, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.803966s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (104.9%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 49.85, top10 = 46.42, top15 = 44.40.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.896714s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (101.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.862069
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 221ps with logic level 1
+OPT-1001 : End physical optimization; 21.480413s wall, 22.781250s user + 0.218750s system = 23.000000s CPU (107.1%)
+
+RUN-1003 : finish command "place" in 67.904823s wall, 102.484375s user + 6.062500s system = 108.546875s CPU (159.9%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 599 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.708059s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (172.0%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 600 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6665 instances
+RUN-1001 : 3270 mslices, 3244 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17893 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9993 nets have 2 pins
+RUN-1001 : 6529 nets have [3 - 5] pins
+RUN-1001 : 732 nets have [6 - 10] pins
+RUN-1001 : 295 nets have [11 - 20] pins
+RUN-1001 : 316 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71654, tnet num: 17715, tinst num: 6663, tnode num: 94125, tedge num: 119060.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.601894s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (100.5%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 630 MB, peak memory is 740 MB
+PHY-1001 : 3270 mslices, 3244 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 871264, over cnt = 2721(7%), over = 4436, worst = 9
+PHY-1002 : len = 888168, over cnt = 1678(4%), over = 2442, worst = 7
+PHY-1002 : len = 909656, over cnt = 588(1%), over = 851, worst = 7
+PHY-1002 : len = 922152, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 922312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.223464s wall, 4.218750s user + 0.015625s system = 4.234375s CPU (131.4%)
+
+PHY-1001 : Congestion index: top1 = 56.51, top5 = 49.50, top10 = 46.04, top15 = 43.87.
+PHY-1001 : End global routing; 3.561120s wall, 4.531250s user + 0.031250s system = 4.562500s CPU (128.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 715, reserve = 711, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 984, reserve = 980, peak = 984.
+PHY-1001 : End build detailed router design. 4.153662s wall, 4.078125s user + 0.062500s system = 4.140625s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 274640, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.385643s wall, 5.390625s user + 0.000000s system = 5.390625s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 274696, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.441022s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1020, reserve = 1018, peak = 1020.
+PHY-1001 : End phase 1; 5.838434s wall, 5.843750s user + 0.000000s system = 5.843750s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.31157e+06, over cnt = 1574(0%), over = 1577, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1032, peak = 1035.
+PHY-1001 : End initial routed; 35.613225s wall, 69.140625s user + 0.375000s system = 69.515625s CPU (195.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16816(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.243813s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1040, peak = 1038.
+PHY-1001 : End phase 2; 38.857101s wall, 72.375000s user + 0.375000s system = 72.750000s CPU (187.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.130605s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.7%)
+
+PHY-1022 : len = 2.31157e+06, over cnt = 1574(0%), over = 1577, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.386933s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.28514e+06, over cnt = 616(0%), over = 617, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.345685s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (173.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.28305e+06, over cnt = 69(0%), over = 69, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.717537s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (148.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28354e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.279649s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (122.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28355e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.218647s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28355e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.205585s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.28355e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.335542s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (102.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.28355e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.448359s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.28357e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.173530s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.28355e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.161435s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.28355e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.191593s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.28355e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.247741s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (107.2%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.28354e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.428593s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.28356e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.166689s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.7%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.28356e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.159378s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16816(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.270525s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 443 feed throughs used by 339 nets
+PHY-1001 : End commit to database; 2.232539s wall, 2.203125s user + 0.015625s system = 2.218750s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1142, reserve = 1148, peak = 1142.
+PHY-1001 : End phase 3; 11.393847s wall, 12.750000s user + 0.046875s system = 12.796875s CPU (112.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.149825s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.9%)
+
+PHY-1022 : len = 2.28356e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.422036s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16816(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.292075s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 443 feed throughs used by 339 nets
+PHY-1001 : End commit to database; 2.285286s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1150, reserve = 1157, peak = 1150.
+PHY-1001 : End phase 4; 6.025398s wall, 6.031250s user + 0.000000s system = 6.031250s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.28356e+06
+PHY-1001 : Current memory(MB): used = 1155, reserve = 1162, peak = 1155.
+PHY-1001 : End export database. 0.060776s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.8%)
+
+PHY-1001 : End detail routing; 66.728796s wall, 101.546875s user + 0.484375s system = 102.031250s CPU (152.9%)
+
+RUN-1003 : finish command "route" in 72.966118s wall, 108.718750s user + 0.531250s system = 109.250000s CPU (149.7%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1106 MB, peak memory is 1155 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10174 out of 19600 51.91%
+#reg 9525 out of 19600 48.60%
+#le 12162
+ #lut only 2637 out of 12162 21.68%
+ #reg only 1988 out of 12162 16.35%
+ #lut® 7537 out of 12162 61.97%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1773
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1421
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1307
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 930
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 134
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg0_syn_162.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg2_syn_189.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P19 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P148 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P16 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P147 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P140 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P106 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P115 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P172 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12162 |9147 |1027 |9557 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |536 |450 |23 |437 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |84 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |48 |48 |0 |23 |0 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |757 |433 |96 |578 |0 |0 |
+| u_ADconfig |AD_config |190 |136 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |250 |146 |71 |117 |0 |0 |
+| exdev_ctl_b |exdev_ctl |731 |377 |96 |554 |0 |0 |
+| u_ADconfig |AD_config |164 |121 |25 |121 |0 |0 |
+| u_gen_sp |gen_sp |255 |137 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2879 |2311 |306 |2070 |25 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |122 |17 |161 |0 |0 |
+| u0_soft_n |cdc_sync |7 |6 |0 |7 |0 |0 |
+| u_sort |sort |2659 |2173 |289 |1878 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2253 |1841 |253 |1530 |22 |0 |
+| channelPart |channel_part_8478 |140 |126 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |47 |0 |0 |
+| ram_switch |ram_switch |1747 |1417 |197 |1130 |0 |0 |
+| adc_addr_gen |adc_addr_gen |225 |198 |27 |117 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |17 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 |
+| insert |insert |969 |669 |170 |667 |0 |0 |
+| ram_switch_state |ram_switch_state |553 |550 |0 |346 |0 |0 |
+| read_ram_i |read_ram |274 |217 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |155 |0 |0 |
+| read_ram_data |read_ram_data |43 |27 |4 |33 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |313 |253 |36 |274 |3 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3106 |2455 |349 |2112 |25 |1 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |105 |17 |160 |0 |0 |
+| u0_soft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u_sort |sort_rev |2883 |2322 |332 |1918 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |3 |3 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2443 |1983 |290 |1566 |22 |1 |
+| channelPart |channel_part_8478 |139 |136 |3 |131 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |40 |0 |1 |
+| ram_switch |ram_switch |1852 |1507 |197 |1150 |0 |0 |
+| adc_addr_gen |adc_addr_gen |220 |193 |27 |116 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |18 |15 |3 |13 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |16 |13 |3 |6 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |19 |16 |3 |7 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |963 |645 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |669 |669 |0 |355 |0 |0 |
+| read_ram_i |read_ram_rev |360 |262 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |296 |211 |73 |163 |0 |0 |
+| read_ram_data |read_ram_data_rev |64 |51 |8 |49 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9931
+ #2 2 4245
+ #3 3 1718
+ #4 4 563
+ #5 5-10 764
+ #6 11-50 567
+ #7 51-100 9
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.021744s wall, 3.453125s user + 0.015625s system = 3.468750s CPU (171.6%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1107 MB, peak memory is 1155 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71654, tnet num: 17715, tinst num: 6663, tnode num: 94125, tedge num: 119060.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.533350s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (99.9%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1110 MB, peak memory is 1155 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.406391s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (100.0%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1125 MB, peak memory is 1155 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6663
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17893, pip num: 168817
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 443
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 469787 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.327922s wall, 61.562500s user + 0.171875s system = 61.734375s CPU (661.8%)
+
+RUN-1004 : used memory is 1250 MB, reserved memory is 1248 MB, peak memory is 1365 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_193153.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_205341.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_205341.log
new file mode 100644
index 0000000..3c58561
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240316_205341.log
@@ -0,0 +1,2148 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Sat Mar 16 20:53:41 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(887)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(896)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(920)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(922)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(928)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(931)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1102)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1191)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1492)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1503)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1521)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1703)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2099)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1003 : finish command "open_project hg_anlogic.prj" in 1.048381s wall, 0.265625s user + 0.093750s system = 0.359375s CPU (34.3%)
+
+RUN-1004 : used memory is 57 MB, reserved memory is 26 MB, peak memory is 57 MB
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.201926s wall, 2.031250s user + 0.140625s system = 2.171875s CPU (98.6%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18047 instances
+RUN-0007 : 7655 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20624 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13126 nets have 2 pins
+RUN-1001 : 6467 nets have [3 - 5] pins
+RUN-1001 : 615 nets have [6 - 10] pins
+RUN-1001 : 177 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18045 instances, 7655 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6041 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84311, tnet num: 20446, tinst num: 18045, tnode num: 114866, tedge num: 134480.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.158120s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.8%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 515 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.926105s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (99.8%)
+
+PHY-3001 : Found 1246 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.16397e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18045.
+PHY-3001 : Level 1 #clusters 2079.
+PHY-3001 : End clustering; 0.125474s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (112.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.37824e+06, overlap = 452.844
+PHY-3002 : Step(2): len = 1.26186e+06, overlap = 490.594
+PHY-3002 : Step(3): len = 852553, overlap = 609.344
+PHY-3002 : Step(4): len = 790501, overlap = 629.469
+PHY-3002 : Step(5): len = 633379, overlap = 761.625
+PHY-3002 : Step(6): len = 544208, overlap = 826.344
+PHY-3002 : Step(7): len = 476055, overlap = 893.188
+PHY-3002 : Step(8): len = 424608, overlap = 956.562
+PHY-3002 : Step(9): len = 393368, overlap = 1011.91
+PHY-3002 : Step(10): len = 354033, overlap = 1063.66
+PHY-3002 : Step(11): len = 329025, overlap = 1119.47
+PHY-3002 : Step(12): len = 299221, overlap = 1157.59
+PHY-3002 : Step(13): len = 276869, overlap = 1188.44
+PHY-3002 : Step(14): len = 250681, overlap = 1263.41
+PHY-3002 : Step(15): len = 235861, overlap = 1275.47
+PHY-3002 : Step(16): len = 218479, overlap = 1358.41
+PHY-3002 : Step(17): len = 197856, overlap = 1395.16
+PHY-3002 : Step(18): len = 183778, overlap = 1420.81
+PHY-3002 : Step(19): len = 167411, overlap = 1463.12
+PHY-3002 : Step(20): len = 157139, overlap = 1469.09
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.22614e-06
+PHY-3002 : Step(21): len = 157391, overlap = 1437.59
+PHY-3002 : Step(22): len = 196222, overlap = 1251.34
+PHY-3002 : Step(23): len = 202297, overlap = 1198.94
+PHY-3002 : Step(24): len = 204865, overlap = 1137.28
+PHY-3002 : Step(25): len = 203845, overlap = 1097.69
+PHY-3002 : Step(26): len = 201577, overlap = 1090.03
+PHY-3002 : Step(27): len = 197189, overlap = 1090.25
+PHY-3002 : Step(28): len = 193920, overlap = 1075.09
+PHY-3002 : Step(29): len = 188345, overlap = 1055.97
+PHY-3002 : Step(30): len = 185486, overlap = 1050.88
+PHY-3002 : Step(31): len = 182394, overlap = 1055.56
+PHY-3002 : Step(32): len = 181564, overlap = 1035.97
+PHY-3002 : Step(33): len = 178835, overlap = 1025.69
+PHY-3002 : Step(34): len = 176841, overlap = 1023.94
+PHY-3002 : Step(35): len = 174879, overlap = 1015.91
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.45228e-06
+PHY-3002 : Step(36): len = 180168, overlap = 993
+PHY-3002 : Step(37): len = 194875, overlap = 952.062
+PHY-3002 : Step(38): len = 201343, overlap = 970.656
+PHY-3002 : Step(39): len = 207014, overlap = 960.906
+PHY-3002 : Step(40): len = 207925, overlap = 981.344
+PHY-3002 : Step(41): len = 209094, overlap = 997.406
+PHY-3002 : Step(42): len = 206598, overlap = 997.688
+PHY-3002 : Step(43): len = 205669, overlap = 983.188
+PHY-3002 : Step(44): len = 203103, overlap = 978.219
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.90456e-06
+PHY-3002 : Step(45): len = 211701, overlap = 952.875
+PHY-3002 : Step(46): len = 230644, overlap = 892.781
+PHY-3002 : Step(47): len = 241323, overlap = 764.344
+PHY-3002 : Step(48): len = 249368, overlap = 745.844
+PHY-3002 : Step(49): len = 253777, overlap = 737.219
+PHY-3002 : Step(50): len = 255150, overlap = 740.312
+PHY-3002 : Step(51): len = 254024, overlap = 730.531
+PHY-3002 : Step(52): len = 253673, overlap = 723.219
+PHY-3002 : Step(53): len = 253381, overlap = 730.938
+PHY-3002 : Step(54): len = 252496, overlap = 718.406
+PHY-3002 : Step(55): len = 250524, overlap = 721.406
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.80912e-06
+PHY-3002 : Step(56): len = 265416, overlap = 687.812
+PHY-3002 : Step(57): len = 281260, overlap = 605.344
+PHY-3002 : Step(58): len = 291304, overlap = 564.219
+PHY-3002 : Step(59): len = 296307, overlap = 555.375
+PHY-3002 : Step(60): len = 295352, overlap = 539.938
+PHY-3002 : Step(61): len = 297274, overlap = 513.906
+PHY-3002 : Step(62): len = 295935, overlap = 521.906
+PHY-3002 : Step(63): len = 295312, overlap = 522.219
+PHY-3002 : Step(64): len = 295017, overlap = 534.281
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.96182e-05
+PHY-3002 : Step(65): len = 311172, overlap = 532.219
+PHY-3002 : Step(66): len = 326027, overlap = 498
+PHY-3002 : Step(67): len = 332851, overlap = 438.656
+PHY-3002 : Step(68): len = 336520, overlap = 423.812
+PHY-3002 : Step(69): len = 337838, overlap = 399.781
+PHY-3002 : Step(70): len = 338999, overlap = 403.188
+PHY-3002 : Step(71): len = 338910, overlap = 384.938
+PHY-3002 : Step(72): len = 340250, overlap = 371.688
+PHY-3002 : Step(73): len = 339701, overlap = 353.562
+PHY-3002 : Step(74): len = 340402, overlap = 351.281
+PHY-3002 : Step(75): len = 341365, overlap = 336.656
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.92365e-05
+PHY-3002 : Step(76): len = 360185, overlap = 332.031
+PHY-3002 : Step(77): len = 373117, overlap = 329.969
+PHY-3002 : Step(78): len = 373886, overlap = 306.625
+PHY-3002 : Step(79): len = 376891, overlap = 302.594
+PHY-3002 : Step(80): len = 378416, overlap = 302.406
+PHY-3002 : Step(81): len = 382893, overlap = 293.375
+PHY-3002 : Step(82): len = 379744, overlap = 271.094
+PHY-3002 : Step(83): len = 382300, overlap = 264.312
+PHY-3002 : Step(84): len = 383559, overlap = 263.562
+PHY-3002 : Step(85): len = 385004, overlap = 265.312
+PHY-3002 : Step(86): len = 381215, overlap = 264.031
+PHY-3002 : Step(87): len = 381757, overlap = 254.406
+PHY-3002 : Step(88): len = 383142, overlap = 255.25
+PHY-3002 : Step(89): len = 384847, overlap = 262.812
+PHY-3002 : Step(90): len = 383610, overlap = 264.969
+PHY-3002 : Step(91): len = 383815, overlap = 276.438
+PHY-3002 : Step(92): len = 384125, overlap = 277
+PHY-3002 : Step(93): len = 384343, overlap = 272.688
+PHY-3002 : Step(94): len = 381836, overlap = 263.938
+PHY-3002 : Step(95): len = 381720, overlap = 259.656
+PHY-3002 : Step(96): len = 381692, overlap = 264.094
+PHY-3002 : Step(97): len = 382394, overlap = 257.469
+PHY-3002 : Step(98): len = 380899, overlap = 258.594
+PHY-3002 : Step(99): len = 380760, overlap = 252.562
+PHY-3002 : Step(100): len = 380594, overlap = 250.656
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.84729e-05
+PHY-3002 : Step(101): len = 397722, overlap = 253
+PHY-3002 : Step(102): len = 407464, overlap = 237.375
+PHY-3002 : Step(103): len = 407228, overlap = 231.781
+PHY-3002 : Step(104): len = 407548, overlap = 222.719
+PHY-3002 : Step(105): len = 409899, overlap = 222.188
+PHY-3002 : Step(106): len = 412812, overlap = 222.812
+PHY-3002 : Step(107): len = 412280, overlap = 220.938
+PHY-3002 : Step(108): len = 412299, overlap = 233
+PHY-3002 : Step(109): len = 413424, overlap = 242.469
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000156946
+PHY-3002 : Step(110): len = 426480, overlap = 241.094
+PHY-3002 : Step(111): len = 435835, overlap = 219.406
+PHY-3002 : Step(112): len = 436496, overlap = 218.25
+PHY-3002 : Step(113): len = 438613, overlap = 213.188
+PHY-3002 : Step(114): len = 443211, overlap = 206.469
+PHY-3002 : Step(115): len = 446865, overlap = 197.75
+PHY-3002 : Step(116): len = 444338, overlap = 191.188
+PHY-3002 : Step(117): len = 443849, overlap = 180.625
+PHY-3002 : Step(118): len = 445267, overlap = 183.969
+PHY-3002 : Step(119): len = 446007, overlap = 187.219
+PHY-3002 : Step(120): len = 443700, overlap = 183.062
+PHY-3002 : Step(121): len = 443225, overlap = 190.094
+PHY-3002 : Step(122): len = 444869, overlap = 194.344
+PHY-3002 : Step(123): len = 446307, overlap = 188.812
+PHY-3002 : Step(124): len = 444168, overlap = 183.156
+PHY-3002 : Step(125): len = 443804, overlap = 180.062
+PHY-3002 : Step(126): len = 445367, overlap = 179.312
+PHY-3002 : Step(127): len = 446749, overlap = 175.5
+PHY-3002 : Step(128): len = 445802, overlap = 175.656
+PHY-3002 : Step(129): len = 446071, overlap = 170.906
+PHY-3002 : Step(130): len = 448441, overlap = 174.562
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000313892
+PHY-3002 : Step(131): len = 455941, overlap = 170.062
+PHY-3002 : Step(132): len = 464644, overlap = 160.469
+PHY-3002 : Step(133): len = 466812, overlap = 161.125
+PHY-3002 : Step(134): len = 467754, overlap = 160.812
+PHY-3002 : Step(135): len = 467990, overlap = 160.031
+PHY-3002 : Step(136): len = 468672, overlap = 159.594
+PHY-3002 : Step(137): len = 469104, overlap = 156.062
+PHY-3002 : Step(138): len = 469975, overlap = 159.281
+PHY-3002 : Step(139): len = 471080, overlap = 161.594
+PHY-3002 : Step(140): len = 471773, overlap = 160.625
+PHY-3002 : Step(141): len = 471393, overlap = 167.062
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000567297
+PHY-3002 : Step(142): len = 477871, overlap = 157.188
+PHY-3002 : Step(143): len = 483546, overlap = 157.469
+PHY-3002 : Step(144): len = 484664, overlap = 162.719
+PHY-3002 : Step(145): len = 485424, overlap = 168.25
+PHY-3002 : Step(146): len = 487814, overlap = 167.25
+PHY-3002 : Step(147): len = 491064, overlap = 153.656
+PHY-3002 : Step(148): len = 491916, overlap = 150.125
+PHY-3002 : Step(149): len = 492816, overlap = 149.438
+PHY-3002 : Step(150): len = 494155, overlap = 143.844
+PHY-3002 : Step(151): len = 494697, overlap = 140.219
+PHY-3002 : Step(152): len = 494043, overlap = 142.625
+PHY-3002 : Step(153): len = 493819, overlap = 145.312
+PHY-3002 : Step(154): len = 494017, overlap = 143.562
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00104208
+PHY-3002 : Step(155): len = 497762, overlap = 141.812
+PHY-3002 : Step(156): len = 505095, overlap = 144.875
+PHY-3002 : Step(157): len = 506716, overlap = 144.375
+PHY-3002 : Step(158): len = 508193, overlap = 145.5
+PHY-3002 : Step(159): len = 510464, overlap = 141.219
+PHY-3002 : Step(160): len = 512088, overlap = 134.906
+PHY-3002 : Step(161): len = 511727, overlap = 142.938
+PHY-3002 : Step(162): len = 511830, overlap = 138.938
+PHY-3002 : Step(163): len = 513338, overlap = 131.25
+PHY-3002 : Step(164): len = 514039, overlap = 131.188
+PHY-3002 : Step(165): len = 513665, overlap = 139.438
+PHY-3002 : Step(166): len = 513656, overlap = 140.344
+PHY-3002 : Step(167): len = 514634, overlap = 140.344
+PHY-3002 : Step(168): len = 514817, overlap = 140.656
+PHY-3002 : Step(169): len = 514378, overlap = 141.031
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00168608
+PHY-3002 : Step(170): len = 516522, overlap = 141.906
+PHY-3002 : Step(171): len = 520910, overlap = 145.812
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.011088s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (422.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20624.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712088, over cnt = 1598(4%), over = 7445, worst = 36
+PHY-1001 : End global iterations; 0.648556s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (144.6%)
+
+PHY-1001 : Congestion index: top1 = 85.02, top5 = 63.08, top10 = 53.83, top15 = 48.05.
+PHY-3001 : End congestion estimation; 0.863583s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (133.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.832689s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (101.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155357
+PHY-3002 : Step(172): len = 647287, overlap = 78.7812
+PHY-3002 : Step(173): len = 647601, overlap = 80.7188
+PHY-3002 : Step(174): len = 640678, overlap = 80.2188
+PHY-3002 : Step(175): len = 637473, overlap = 83.5625
+PHY-3002 : Step(176): len = 635603, overlap = 76.375
+PHY-3002 : Step(177): len = 633053, overlap = 71.25
+PHY-3002 : Step(178): len = 631948, overlap = 57.9375
+PHY-3002 : Step(179): len = 630831, overlap = 55.5312
+PHY-3002 : Step(180): len = 629447, overlap = 43.25
+PHY-3002 : Step(181): len = 627174, overlap = 38.9062
+PHY-3002 : Step(182): len = 626206, overlap = 36.1562
+PHY-3002 : Step(183): len = 624986, overlap = 35.3125
+PHY-3002 : Step(184): len = 625365, overlap = 34.25
+PHY-3002 : Step(185): len = 624177, overlap = 34.25
+PHY-3002 : Step(186): len = 624329, overlap = 35.8125
+PHY-3002 : Step(187): len = 622211, overlap = 35.8125
+PHY-3002 : Step(188): len = 621353, overlap = 35.5
+PHY-3002 : Step(189): len = 618756, overlap = 36.6562
+PHY-3002 : Step(190): len = 617011, overlap = 35.875
+PHY-3002 : Step(191): len = 616208, overlap = 36.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000310713
+PHY-3002 : Step(192): len = 617427, overlap = 36.3125
+PHY-3002 : Step(193): len = 621001, overlap = 35.6562
+PHY-3002 : Step(194): len = 626782, overlap = 35.4688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000605889
+PHY-3002 : Step(195): len = 636524, overlap = 34.4062
+PHY-3002 : Step(196): len = 655930, overlap = 30.8438
+PHY-3002 : Step(197): len = 673142, overlap = 28.5312
+PHY-3002 : Step(198): len = 674702, overlap = 25.4688
+PHY-3002 : Step(199): len = 675798, overlap = 22.0312
+PHY-3002 : Step(200): len = 674088, overlap = 20.2188
+PHY-3002 : Step(201): len = 672758, overlap = 20.0625
+PHY-3002 : Step(202): len = 672625, overlap = 19.9688
+PHY-3002 : Step(203): len = 670105, overlap = 17.9375
+PHY-3002 : Step(204): len = 668005, overlap = 17.4688
+PHY-3002 : Step(205): len = 665778, overlap = 18.9688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00117027
+PHY-3002 : Step(206): len = 672688, overlap = 16.5938
+PHY-3002 : Step(207): len = 682048, overlap = 17.8125
+PHY-3002 : Step(208): len = 687433, overlap = 17.8438
+PHY-3002 : Step(209): len = 692923, overlap = 21.4688
+PHY-3002 : Step(210): len = 699396, overlap = 22.3125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00195545
+PHY-3002 : Step(211): len = 702763, overlap = 21.3125
+PHY-3002 : Step(212): len = 707365, overlap = 21.5312
+PHY-3002 : Step(213): len = 713324, overlap = 21.5625
+PHY-3002 : Step(214): len = 718992, overlap = 20.8438
+PHY-3002 : Step(215): len = 722282, overlap = 21.7188
+PHY-3002 : Step(216): len = 723559, overlap = 22.9375
+PHY-3002 : Step(217): len = 723023, overlap = 23.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 33/20624.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812232, over cnt = 2927(8%), over = 13631, worst = 47
+PHY-1001 : End global iterations; 1.562167s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (142.0%)
+
+PHY-1001 : Congestion index: top1 = 91.94, top5 = 72.28, top10 = 63.44, top15 = 57.98.
+PHY-3001 : End congestion estimation; 1.822917s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (136.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.216974s wall, 1.187500s user + 0.031250s system = 1.218750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000136521
+PHY-3002 : Step(218): len = 706562, overlap = 217.812
+PHY-3002 : Step(219): len = 695766, overlap = 175.312
+PHY-3002 : Step(220): len = 679560, overlap = 154.188
+PHY-3002 : Step(221): len = 666304, overlap = 133.875
+PHY-3002 : Step(222): len = 657689, overlap = 123.594
+PHY-3002 : Step(223): len = 649506, overlap = 118.719
+PHY-3002 : Step(224): len = 642927, overlap = 119.312
+PHY-3002 : Step(225): len = 638593, overlap = 112.219
+PHY-3002 : Step(226): len = 634344, overlap = 109.5
+PHY-3002 : Step(227): len = 629374, overlap = 106.75
+PHY-3002 : Step(228): len = 625581, overlap = 105.906
+PHY-3002 : Step(229): len = 621095, overlap = 108.969
+PHY-3002 : Step(230): len = 617852, overlap = 113.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000273042
+PHY-3002 : Step(231): len = 617742, overlap = 106.344
+PHY-3002 : Step(232): len = 620772, overlap = 101.406
+PHY-3002 : Step(233): len = 624500, overlap = 97.4375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000546084
+PHY-3002 : Step(234): len = 627651, overlap = 97.5938
+PHY-3002 : Step(235): len = 633605, overlap = 92.0625
+PHY-3002 : Step(236): len = 640439, overlap = 85.0625
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84311, tnet num: 20446, tinst num: 18045, tnode num: 114866, tedge num: 134480.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.399965s wall, 1.375000s user + 0.031250s system = 1.406250s CPU (100.4%)
+
+RUN-1004 : used memory is 577 MB, reserved memory is 566 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 398.72 peak overflow 3.25
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 670/20624.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735696, over cnt = 3091(8%), over = 10909, worst = 30
+PHY-1001 : End global iterations; 1.340611s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 70.11, top5 = 58.29, top10 = 52.09, top15 = 48.23.
+PHY-1001 : End incremental global routing; 1.682601s wall, 2.250000s user + 0.031250s system = 2.281250s CPU (135.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20446 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.901143s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.6%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17914 has valid locations, 303 needs to be replaced
+PHY-3001 : design contains 18302 instances, 7744 luts, 9337 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6162 pins
+PHY-3001 : Found 1256 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 663552
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16930/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751632, over cnt = 3093(8%), over = 10962, worst = 30
+PHY-1001 : End global iterations; 0.218158s wall, 0.296875s user + 0.046875s system = 0.343750s CPU (157.6%)
+
+PHY-1001 : Congestion index: top1 = 69.61, top5 = 58.17, top10 = 52.15, top15 = 48.49.
+PHY-3001 : End congestion estimation; 0.468364s wall, 0.546875s user + 0.046875s system = 0.593750s CPU (126.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85345, tnet num: 20703, tinst num: 18302, tnode num: 116431, tedge num: 136034.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.426689s wall, 1.375000s user + 0.046875s system = 1.421875s CPU (99.7%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 612 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.355107s wall, 2.312500s user + 0.046875s system = 2.359375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(237): len = 662748, overlap = 0.25
+PHY-3002 : Step(238): len = 662186, overlap = 0.25
+PHY-3002 : Step(239): len = 661813, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17044/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749368, over cnt = 3094(8%), over = 10999, worst = 30
+PHY-1001 : End global iterations; 0.174353s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (134.4%)
+
+PHY-1001 : Congestion index: top1 = 70.41, top5 = 58.64, top10 = 52.52, top15 = 48.77.
+PHY-3001 : End congestion estimation; 0.422900s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (114.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.917954s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000338828
+PHY-3002 : Step(240): len = 661424, overlap = 86.875
+PHY-3002 : Step(241): len = 661465, overlap = 87.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000677657
+PHY-3002 : Step(242): len = 661773, overlap = 87.2812
+PHY-3002 : Step(243): len = 662289, overlap = 87.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00130041
+PHY-3002 : Step(244): len = 662600, overlap = 86.75
+PHY-3002 : Step(245): len = 663104, overlap = 86.5625
+PHY-3001 : Final: Len = 663104, Over = 86.5625
+PHY-3001 : End incremental placement; 4.842589s wall, 5.156250s user + 0.218750s system = 5.375000s CPU (111.0%)
+
+OPT-1001 : Total overflow 404.84 peak overflow 3.25
+OPT-1001 : End high-fanout net optimization; 7.934815s wall, 8.812500s user + 0.281250s system = 9.093750s CPU (114.6%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 712, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16959/20881.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 752928, over cnt = 3027(8%), over = 9911, worst = 30
+PHY-1002 : len = 805584, over cnt = 2031(5%), over = 4912, worst = 20
+PHY-1002 : len = 848240, over cnt = 822(2%), over = 1664, worst = 16
+PHY-1002 : len = 860704, over cnt = 456(1%), over = 921, worst = 11
+PHY-1002 : len = 879816, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.834480s wall, 2.656250s user + 0.031250s system = 2.687500s CPU (146.5%)
+
+PHY-1001 : Congestion index: top1 = 58.69, top5 = 51.80, top10 = 47.95, top15 = 45.46.
+OPT-1001 : End congestion update; 2.084982s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (140.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20703 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.780400s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.1%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 125 cells processed and 17400 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 29 cells processed and 2550 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 1250 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.271955s wall, 4.093750s user + 0.031250s system = 4.125000s CPU (126.1%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 696, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16983/20883.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879600, over cnt = 79(0%), over = 109, worst = 4
+PHY-1002 : len = 879576, over cnt = 36(0%), over = 39, worst = 2
+PHY-1002 : len = 879824, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 879904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 879968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.711828s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (111.9%)
+
+PHY-1001 : Congestion index: top1 = 58.32, top5 = 51.53, top10 = 47.76, top15 = 45.32.
+OPT-1001 : End congestion update; 0.981112s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (108.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20705 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779050s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.3%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 41 cells processed and 7000 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 5 cells processed and 500 slack improved
+OPT-1001 : End path based optimization; 1.969696s wall, 2.031250s user + 0.015625s system = 2.046875s CPU (103.9%)
+
+OPT-1001 : Current memory(MB): used = 706, reserve = 702, peak = 733.
+OPT-1001 : End physical optimization; 14.875652s wall, 16.703125s user + 0.375000s system = 17.078125s CPU (114.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7744 LUT to BLE ...
+SYN-4008 : Packed 7744 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6192 remaining SEQ's ...
+SYN-4005 : Packed 4011 SEQ with LUT/SLICE
+SYN-4006 : 888 single LUT's are left
+SYN-4006 : 2181 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9925/13712 primitive instances ...
+PHY-3001 : End packing; 1.611736s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6704 instances
+RUN-1001 : 3278 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17870 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 6541 nets have [3 - 5] pins
+RUN-1001 : 725 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 304 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6702 instances, 6556 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3572 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 673801, Over = 221.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7610/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 830704, over cnt = 1985(5%), over = 3157, worst = 9
+PHY-1002 : len = 837376, over cnt = 1297(3%), over = 1828, worst = 8
+PHY-1002 : len = 850104, over cnt = 520(1%), over = 690, worst = 7
+PHY-1002 : len = 857912, over cnt = 165(0%), over = 215, worst = 5
+PHY-1002 : len = 861904, over cnt = 4(0%), over = 5, worst = 2
+PHY-1001 : End global iterations; 1.737410s wall, 2.390625s user + 0.140625s system = 2.531250s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 57.87, top5 = 51.67, top10 = 47.87, top15 = 45.22.
+PHY-3001 : End congestion estimation; 2.126118s wall, 2.781250s user + 0.140625s system = 2.921875s CPU (137.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71589, tnet num: 17692, tinst num: 6702, tnode num: 94109, tedge num: 119050.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.564161s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.9%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 609 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.393709s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.71995e-05
+PHY-3002 : Step(246): len = 662174, overlap = 220
+PHY-3002 : Step(247): len = 655931, overlap = 221.5
+PHY-3002 : Step(248): len = 652095, overlap = 222.5
+PHY-3002 : Step(249): len = 648922, overlap = 219.25
+PHY-3002 : Step(250): len = 645743, overlap = 228
+PHY-3002 : Step(251): len = 643720, overlap = 227
+PHY-3002 : Step(252): len = 641908, overlap = 233
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000114399
+PHY-3002 : Step(253): len = 644550, overlap = 223.75
+PHY-3002 : Step(254): len = 650049, overlap = 208.5
+PHY-3002 : Step(255): len = 651181, overlap = 210.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000228798
+PHY-3002 : Step(256): len = 656507, overlap = 200.75
+PHY-3002 : Step(257): len = 664876, overlap = 195.5
+PHY-3002 : Step(258): len = 665271, overlap = 194
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.397574s wall, 0.296875s user + 0.687500s system = 0.984375s CPU (247.6%)
+
+PHY-3001 : Trial Legalized: Len = 744817
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 899/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856040, over cnt = 2628(7%), over = 4411, worst = 7
+PHY-1002 : len = 873360, over cnt = 1570(4%), over = 2287, worst = 6
+PHY-1002 : len = 896192, over cnt = 452(1%), over = 591, worst = 5
+PHY-1002 : len = 903808, over cnt = 122(0%), over = 152, worst = 3
+PHY-1002 : len = 906784, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.284422s wall, 3.328125s user + 0.015625s system = 3.343750s CPU (146.4%)
+
+PHY-1001 : Congestion index: top1 = 56.47, top5 = 50.97, top10 = 47.55, top15 = 45.30.
+PHY-3001 : End congestion estimation; 2.744112s wall, 3.781250s user + 0.015625s system = 3.796875s CPU (138.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.829846s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000172415
+PHY-3002 : Step(259): len = 717221, overlap = 39
+PHY-3002 : Step(260): len = 701250, overlap = 64.75
+PHY-3002 : Step(261): len = 688225, overlap = 83.25
+PHY-3002 : Step(262): len = 680736, overlap = 98.75
+PHY-3002 : Step(263): len = 675754, overlap = 116
+PHY-3002 : Step(264): len = 673165, overlap = 129.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000344829
+PHY-3002 : Step(265): len = 677434, overlap = 128.5
+PHY-3002 : Step(266): len = 682067, overlap = 127.75
+PHY-3002 : Step(267): len = 684644, overlap = 128.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000689658
+PHY-3002 : Step(268): len = 687220, overlap = 128.5
+PHY-3002 : Step(269): len = 692573, overlap = 126
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.029849s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (104.7%)
+
+PHY-3001 : Legalized: Len = 719837, Over = 0
+PHY-3001 : Spreading special nets. 403 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.093182s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (100.6%)
+
+PHY-3001 : 592 instances has been re-located, deltaX = 168, deltaY = 350, maxDist = 2.
+PHY-3001 : Final: Len = 727997, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71589, tnet num: 17692, tinst num: 6705, tnode num: 94109, tedge num: 119050.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.780439s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (100.0%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 625 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4494/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858528, over cnt = 2450(6%), over = 3884, worst = 7
+PHY-1002 : len = 872208, over cnt = 1426(4%), over = 1956, worst = 5
+PHY-1002 : len = 889928, over cnt = 398(1%), over = 504, worst = 5
+PHY-1002 : len = 896168, over cnt = 68(0%), over = 93, worst = 5
+PHY-1002 : len = 897968, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 1.939067s wall, 2.750000s user + 0.015625s system = 2.765625s CPU (142.6%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.37, top10 = 46.31, top15 = 44.39.
+PHY-1001 : End incremental global routing; 2.312248s wall, 3.125000s user + 0.015625s system = 3.140625s CPU (135.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.831202s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.6%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6613 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 733234
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16308/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904088, over cnt = 81(0%), over = 95, worst = 4
+PHY-1002 : len = 904256, over cnt = 37(0%), over = 42, worst = 3
+PHY-1002 : len = 904672, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 904800, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 904904, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.785801s wall, 0.828125s user + 0.031250s system = 0.859375s CPU (109.4%)
+
+PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.46, top10 = 46.42, top15 = 44.50.
+PHY-3001 : End congestion estimation; 1.100215s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (106.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71807, tnet num: 17722, tinst num: 6727, tnode num: 94377, tedge num: 119359.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.777205s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (100.2%)
+
+RUN-1004 : used memory is 651 MB, reserved memory is 656 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.631672s wall, 2.609375s user + 0.031250s system = 2.640625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 731421, overlap = 0.5
+PHY-3002 : Step(271): len = 730760, overlap = 1
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16293/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901040, over cnt = 74(0%), over = 93, worst = 3
+PHY-1002 : len = 901408, over cnt = 27(0%), over = 27, worst = 1
+PHY-1002 : len = 901552, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 901856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.589371s wall, 0.640625s user + 0.015625s system = 0.656250s CPU (111.3%)
+
+PHY-1001 : Congestion index: top1 = 55.41, top5 = 49.43, top10 = 46.39, top15 = 44.46.
+PHY-3001 : End congestion estimation; 0.895086s wall, 0.937500s user + 0.031250s system = 0.968750s CPU (108.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.825153s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.25652e-05
+PHY-3002 : Step(272): len = 730790, overlap = 3.75
+PHY-3002 : Step(273): len = 730711, overlap = 2.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005516s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 730837, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056416s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.8%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 0, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 730969, Over = 0
+PHY-3001 : End incremental placement; 5.899923s wall, 5.968750s user + 0.140625s system = 6.109375s CPU (103.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.506263s wall, 10.359375s user + 0.171875s system = 10.531250s CPU (110.8%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 736, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16282/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902168, over cnt = 57(0%), over = 67, worst = 4
+PHY-1002 : len = 902176, over cnt = 34(0%), over = 35, worst = 2
+PHY-1002 : len = 902496, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 902664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.586858s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (111.8%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 49.40, top10 = 46.32, top15 = 44.39.
+OPT-1001 : End congestion update; 0.892146s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (106.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.689369s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.7%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738754, Over = 0
+PHY-3001 : Spreading special nets. 23 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059692s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%)
+
+PHY-3001 : 36 instances has been re-located, deltaX = 18, deltaY = 26, maxDist = 4.
+PHY-3001 : Final: Len = 740022, Over = 0
+PHY-3001 : End incremental legalization; 0.366115s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 57 cells processed and 19167 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 739720, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056674s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.3%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 0, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 740248, Over = 0
+PHY-3001 : End incremental legalization; 0.361146s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.5%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 21 cells processed and 2391 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6727 instances, 6578 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 479 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 739796, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058123s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.5%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 8, deltaY = 12, maxDist = 4.
+PHY-3001 : Final: Len = 740332, Over = 0
+PHY-3001 : End incremental legalization; 0.364567s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.6%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 1807 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740374, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057410s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.7%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740506, Over = 0
+PHY-3001 : End incremental legalization; 0.361694s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (138.2%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 3 cells processed and 950 slack improved
+OPT-1001 : End bottleneck based optimization; 3.553694s wall, 3.859375s user + 0.046875s system = 3.906250s CPU (109.9%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15889/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911864, over cnt = 172(0%), over = 223, worst = 6
+PHY-1002 : len = 912536, over cnt = 75(0%), over = 78, worst = 2
+PHY-1002 : len = 912920, over cnt = 44(0%), over = 46, worst = 2
+PHY-1002 : len = 913592, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 913672, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.847576s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 55.02, top5 = 49.29, top10 = 46.30, top15 = 44.38.
+OPT-1001 : End congestion update; 1.161598s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (102.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.728000s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.9%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740908, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056318s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (83.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 2, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.366242s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.1%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 11 cells processed and 1400 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.385145s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (100.9%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 738.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.713605s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16294/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913968, over cnt = 46(0%), over = 57, worst = 4
+PHY-1002 : len = 914024, over cnt = 21(0%), over = 22, worst = 2
+PHY-1002 : len = 914256, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.596857s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (107.3%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694461s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (96.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 21 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.655172
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 21ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740944, Over = 0
+PHY-3001 : End spreading; 0.056694s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.2%)
+
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.360713s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.693220s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (99.2%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16328/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.128493s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.3%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+OPT-1001 : End congestion update; 0.434192s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.690681s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.8%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740960, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057323s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.364038s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.0%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.594378s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16328/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.128826s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.0%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+OPT-1001 : End congestion update; 0.430559s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694160s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.3%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740960, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.055718s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (112.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.363757s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.1%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6730 instances, 6581 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3637 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740960, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.055663s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (112.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740944, Over = 0
+PHY-3001 : End incremental legalization; 0.364255s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.7%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.127315s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (101.4%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 738.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.695601s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 738.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694262s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.3%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16328/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.135578s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.2%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.27, top10 = 46.30, top15 = 44.41.
+RUN-1001 : End congestion update; 0.461835s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.1%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.159218s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.7%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 737, peak = 738.
+OPT-1001 : End physical optimization; 26.577819s wall, 27.796875s user + 0.250000s system = 28.046875s CPU (105.5%)
+
+RUN-1003 : finish command "place" in 69.185161s wall, 97.562500s user + 6.000000s system = 103.562500s CPU (149.7%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 639 MB, peak memory is 738 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.648710s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (174.4%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 639 MB, peak memory is 738 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6732 instances
+RUN-1001 : 3292 mslices, 3289 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17900 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9980 nets have 2 pins
+RUN-1001 : 6546 nets have [3 - 5] pins
+RUN-1001 : 730 nets have [6 - 10] pins
+RUN-1001 : 302 nets have [11 - 20] pins
+RUN-1001 : 314 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71834, tnet num: 17722, tinst num: 6730, tnode num: 94415, tedge num: 119394.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.546894s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.0%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 615 MB, peak memory is 738 MB
+PHY-1001 : 3292 mslices, 3289 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 845368, over cnt = 2704(7%), over = 4369, worst = 7
+PHY-1002 : len = 862784, over cnt = 1666(4%), over = 2380, worst = 7
+PHY-1002 : len = 884176, over cnt = 537(1%), over = 769, worst = 5
+PHY-1002 : len = 896248, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 896472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.946832s wall, 3.921875s user + 0.046875s system = 3.968750s CPU (134.7%)
+
+PHY-1001 : Congestion index: top1 = 54.76, top5 = 49.22, top10 = 46.21, top15 = 44.14.
+PHY-1001 : End global routing; 3.266225s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (131.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 701, reserve = 707, peak = 738.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 978, reserve = 984, peak = 978.
+PHY-1001 : End build detailed router design. 4.002805s wall, 3.984375s user + 0.015625s system = 4.000000s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271464, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.793953s wall, 4.796875s user + 0.000000s system = 4.796875s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271520, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.402583s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.9%)
+
+PHY-1001 : Current memory(MB): used = 1013, reserve = 1020, peak = 1013.
+PHY-1001 : End phase 1; 5.208191s wall, 5.218750s user + 0.000000s system = 5.218750s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28506e+06, over cnt = 1600(0%), over = 1610, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1033, peak = 1030.
+PHY-1001 : End initial routed; 24.382561s wall, 56.921875s user + 0.312500s system = 57.234375s CPU (234.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16823(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.811 | -0.811 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.139891s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1043, reserve = 1048, peak = 1043.
+PHY-1001 : End phase 2; 27.522523s wall, 60.062500s user + 0.312500s system = 60.375000s CPU (219.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.807ns STNS -0.807ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.138530s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.5%)
+
+PHY-1022 : len = 2.28506e+06, over cnt = 1604(0%), over = 1614, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.396835s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.25794e+06, over cnt = 627(0%), over = 628, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.219339s wall, 2.140625s user + 0.000000s system = 2.140625s CPU (175.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.25642e+06, over cnt = 141(0%), over = 141, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.597499s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (164.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.25698e+06, over cnt = 29(0%), over = 29, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.278290s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (117.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.25733e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.198896s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.25737e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.193883s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16823(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.807 | -0.807 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.177827s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 364 nets
+PHY-1001 : End commit to database; 2.218481s wall, 2.203125s user + 0.015625s system = 2.218750s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1143, reserve = 1150, peak = 1143.
+PHY-1001 : End phase 3; 8.672307s wall, 10.015625s user + 0.015625s system = 10.031250s CPU (115.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.807ns STNS -0.807ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.137396s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.3%)
+
+PHY-1022 : len = 2.25737e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.368584s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.807ns, -0.807ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16823(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.807 | -0.807 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.131042s wall, 3.125000s user + 0.000000s system = 3.125000s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 364 nets
+PHY-1001 : End commit to database; 2.315959s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1160, peak = 1152.
+PHY-1001 : End phase 4; 5.843371s wall, 5.843750s user + 0.000000s system = 5.843750s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.25737e+06
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1162, peak = 1154.
+PHY-1001 : End export database. 0.058900s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.1%)
+
+PHY-1001 : End detail routing; 51.697616s wall, 85.562500s user + 0.343750s system = 85.906250s CPU (166.2%)
+
+RUN-1003 : finish command "route" in 57.531580s wall, 92.359375s user + 0.421875s system = 92.781250s CPU (161.3%)
+
+RUN-1004 : used memory is 1082 MB, reserved memory is 1085 MB, peak memory is 1154 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10185 out of 19600 51.96%
+#reg 9527 out of 19600 48.61%
+#le 12324
+ #lut only 2797 out of 12324 22.70%
+ #reg only 2139 out of 12324 17.36%
+ #lut® 7388 out of 12324 59.95%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1753
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1425
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1327
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 962
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 133
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_b/u_ADconfig/reg2_syn_84.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg32_syn_204.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P39 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P163 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P16 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P147 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P133 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P172 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P148 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12324 |9158 |1027 |9559 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |531 |458 |23 |446 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |98 |81 |4 |88 |4 |0 |
+| U_crc16_24b |crc16_24b |38 |38 |0 |21 |0 |0 |
+| U_ecc_gen |ecc_gen |11 |11 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |750 |373 |96 |572 |0 |0 |
+| u_ADconfig |AD_config |186 |122 |25 |142 |0 |0 |
+| u_gen_sp |gen_sp |251 |159 |71 |117 |0 |0 |
+| exdev_ctl_b |exdev_ctl |732 |410 |96 |554 |0 |0 |
+| u_ADconfig |AD_config |165 |117 |25 |122 |0 |0 |
+| u_gen_sp |gen_sp |252 |159 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |2949 |2400 |306 |2094 |25 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |191 |136 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort |2726 |2245 |289 |1903 |25 |0 |
+| rddpram_ctl |rddpram_ctl |7 |3 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |3 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2281 |1899 |253 |1537 |22 |0 |
+| channelPart |channel_part_8478 |130 |123 |3 |125 |0 |0 |
+| fifo_adc |fifo_adc |57 |48 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1795 |1490 |197 |1153 |0 |0 |
+| adc_addr_gen |adc_addr_gen |223 |196 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |16 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| insert |insert |967 |689 |170 |663 |0 |0 |
+| ram_switch_state |ram_switch_state |605 |605 |0 |367 |0 |0 |
+| read_ram_i |read_ram |266 |217 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |219 |179 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |43 |34 |4 |31 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |318 |232 |36 |270 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3168 |2463 |349 |2092 |25 |1 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |114 |17 |157 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |2945 |2344 |332 |1902 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2515 |2013 |290 |1557 |22 |1 |
+| channelPart |channel_part_8478 |143 |135 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1931 |1557 |197 |1143 |0 |0 |
+| adc_addr_gen |adc_addr_gen |199 |172 |27 |103 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |16 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |14 |11 |3 |6 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| insert |insert |947 |606 |170 |659 |0 |0 |
+| ram_switch_state |ram_switch_state |785 |779 |0 |381 |0 |0 |
+| read_ram_i |read_ram_rev |352 |247 |81 |209 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |295 |210 |73 |166 |0 |0 |
+| read_ram_data |read_ram_data_rev |57 |37 |8 |43 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9918
+ #2 2 4275
+ #3 3 1701
+ #4 4 567
+ #5 5-10 765
+ #6 11-50 565
+ #7 51-100 13
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.050525s wall, 3.484375s user + 0.046875s system = 3.531250s CPU (172.2%)
+
+RUN-1004 : used memory is 1083 MB, reserved memory is 1087 MB, peak memory is 1154 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71834, tnet num: 17722, tinst num: 6730, tnode num: 94415, tedge num: 119394.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.569236s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.6%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1091 MB, peak memory is 1154 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.716957s wall, 1.671875s user + 0.031250s system = 1.703125s CPU (99.2%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1095 MB, peak memory is 1154 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6730
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17900, pip num: 168360
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 496
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3251 valid insts, and 469670 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.056630s wall, 61.437500s user + 0.187500s system = 61.625000s CPU (680.4%)
+
+RUN-1004 : used memory is 1247 MB, reserved memory is 1250 MB, peak memory is 1362 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240316_205341.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_093416.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_093416.log
new file mode 100644
index 0000000..8a10286
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_093416.log
@@ -0,0 +1,2005 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 09:34:16 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.205961s wall, 2.078125s user + 0.125000s system = 2.203125s CPU (99.9%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2279 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2120 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18061 instances
+RUN-0007 : 7659 luts, 9179 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20638 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13126 nets have 2 pins
+RUN-1001 : 6478 nets have [3 - 5] pins
+RUN-1001 : 616 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 169 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 798
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3579
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18059 instances, 7659 luts, 9179 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6051 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84374, tnet num: 20460, tinst num: 18059, tnode num: 114958, tedge num: 134578.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.143539s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (101.1%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 516 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20460 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.912074s wall, 1.875000s user + 0.046875s system = 1.921875s CPU (100.5%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.17322e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18059.
+PHY-3001 : Level 1 #clusters 2035.
+PHY-3001 : End clustering; 0.125629s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (111.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.33576e+06, overlap = 469.281
+PHY-3002 : Step(2): len = 1.23486e+06, overlap = 535
+PHY-3002 : Step(3): len = 871791, overlap = 619.156
+PHY-3002 : Step(4): len = 791612, overlap = 660.406
+PHY-3002 : Step(5): len = 622996, overlap = 810.5
+PHY-3002 : Step(6): len = 552830, overlap = 856.469
+PHY-3002 : Step(7): len = 452970, overlap = 957.938
+PHY-3002 : Step(8): len = 414807, overlap = 1006.78
+PHY-3002 : Step(9): len = 365653, overlap = 1076.91
+PHY-3002 : Step(10): len = 342226, overlap = 1104.81
+PHY-3002 : Step(11): len = 300498, overlap = 1157.69
+PHY-3002 : Step(12): len = 282990, overlap = 1199.31
+PHY-3002 : Step(13): len = 255019, overlap = 1250.56
+PHY-3002 : Step(14): len = 232496, overlap = 1298.34
+PHY-3002 : Step(15): len = 214836, overlap = 1328.06
+PHY-3002 : Step(16): len = 198516, overlap = 1364.34
+PHY-3002 : Step(17): len = 183782, overlap = 1396.34
+PHY-3002 : Step(18): len = 168976, overlap = 1420.06
+PHY-3002 : Step(19): len = 155959, overlap = 1434.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.22196e-06
+PHY-3002 : Step(20): len = 156943, overlap = 1410.72
+PHY-3002 : Step(21): len = 192398, overlap = 1285.28
+PHY-3002 : Step(22): len = 202119, overlap = 1204.59
+PHY-3002 : Step(23): len = 208573, overlap = 1122.25
+PHY-3002 : Step(24): len = 208405, overlap = 1096.94
+PHY-3002 : Step(25): len = 206704, overlap = 1080.94
+PHY-3002 : Step(26): len = 203151, overlap = 1076.38
+PHY-3002 : Step(27): len = 199877, overlap = 1036.19
+PHY-3002 : Step(28): len = 196118, overlap = 1025.97
+PHY-3002 : Step(29): len = 193526, overlap = 1041.94
+PHY-3002 : Step(30): len = 189940, overlap = 1015.72
+PHY-3002 : Step(31): len = 186152, overlap = 1015.72
+PHY-3002 : Step(32): len = 183767, overlap = 1022.31
+PHY-3002 : Step(33): len = 181445, overlap = 1017.34
+PHY-3002 : Step(34): len = 180465, overlap = 1022.78
+PHY-3002 : Step(35): len = 179289, overlap = 1029.31
+PHY-3002 : Step(36): len = 178757, overlap = 1030.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.44391e-06
+PHY-3002 : Step(37): len = 183489, overlap = 988.562
+PHY-3002 : Step(38): len = 194656, overlap = 975.688
+PHY-3002 : Step(39): len = 199564, overlap = 955.875
+PHY-3002 : Step(40): len = 205319, overlap = 939.094
+PHY-3002 : Step(41): len = 206686, overlap = 939.875
+PHY-3002 : Step(42): len = 207974, overlap = 939.531
+PHY-3002 : Step(43): len = 205493, overlap = 936.562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.88783e-06
+PHY-3002 : Step(44): len = 212758, overlap = 915.25
+PHY-3002 : Step(45): len = 233632, overlap = 866.156
+PHY-3002 : Step(46): len = 245778, overlap = 798.25
+PHY-3002 : Step(47): len = 253554, overlap = 766.75
+PHY-3002 : Step(48): len = 254351, overlap = 735.906
+PHY-3002 : Step(49): len = 254281, overlap = 718.438
+PHY-3002 : Step(50): len = 254395, overlap = 714.469
+PHY-3002 : Step(51): len = 253505, overlap = 713.812
+PHY-3002 : Step(52): len = 252570, overlap = 712.719
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.77566e-06
+PHY-3002 : Step(53): len = 266264, overlap = 657.562
+PHY-3002 : Step(54): len = 281768, overlap = 608.875
+PHY-3002 : Step(55): len = 289231, overlap = 552.969
+PHY-3002 : Step(56): len = 295140, overlap = 521.062
+PHY-3002 : Step(57): len = 296844, overlap = 511.969
+PHY-3002 : Step(58): len = 297816, overlap = 514.562
+PHY-3002 : Step(59): len = 296557, overlap = 498.469
+PHY-3002 : Step(60): len = 297425, overlap = 497.25
+PHY-3002 : Step(61): len = 295580, overlap = 491.25
+PHY-3002 : Step(62): len = 296143, overlap = 468.656
+PHY-3002 : Step(63): len = 294887, overlap = 479.844
+PHY-3002 : Step(64): len = 294799, overlap = 488.125
+PHY-3002 : Step(65): len = 294706, overlap = 494.406
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.95513e-05
+PHY-3002 : Step(66): len = 310833, overlap = 445.562
+PHY-3002 : Step(67): len = 324567, overlap = 419.719
+PHY-3002 : Step(68): len = 331135, overlap = 399.719
+PHY-3002 : Step(69): len = 335903, overlap = 398.125
+PHY-3002 : Step(70): len = 334937, overlap = 403.906
+PHY-3002 : Step(71): len = 336616, overlap = 395.969
+PHY-3002 : Step(72): len = 335930, overlap = 389
+PHY-3002 : Step(73): len = 337096, overlap = 380
+PHY-3002 : Step(74): len = 335569, overlap = 378.25
+PHY-3002 : Step(75): len = 335317, overlap = 384.844
+PHY-3002 : Step(76): len = 333566, overlap = 376.812
+PHY-3002 : Step(77): len = 334193, overlap = 378.125
+PHY-3002 : Step(78): len = 333115, overlap = 387.219
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.91026e-05
+PHY-3002 : Step(79): len = 350304, overlap = 374.312
+PHY-3002 : Step(80): len = 365520, overlap = 365.562
+PHY-3002 : Step(81): len = 370358, overlap = 326.188
+PHY-3002 : Step(82): len = 372150, overlap = 314.75
+PHY-3002 : Step(83): len = 371578, overlap = 306.719
+PHY-3002 : Step(84): len = 373174, overlap = 306.969
+PHY-3002 : Step(85): len = 373044, overlap = 305.531
+PHY-3002 : Step(86): len = 375074, overlap = 306.812
+PHY-3002 : Step(87): len = 376830, overlap = 313.625
+PHY-3002 : Step(88): len = 377179, overlap = 317.156
+PHY-3002 : Step(89): len = 376809, overlap = 317.719
+PHY-3002 : Step(90): len = 377879, overlap = 304.156
+PHY-3002 : Step(91): len = 377664, overlap = 310.062
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.82053e-05
+PHY-3002 : Step(92): len = 392552, overlap = 292.219
+PHY-3002 : Step(93): len = 402347, overlap = 288.5
+PHY-3002 : Step(94): len = 402854, overlap = 267.656
+PHY-3002 : Step(95): len = 405968, overlap = 254.906
+PHY-3002 : Step(96): len = 408736, overlap = 247.312
+PHY-3002 : Step(97): len = 410875, overlap = 255.344
+PHY-3002 : Step(98): len = 408202, overlap = 248.656
+PHY-3002 : Step(99): len = 407661, overlap = 252.219
+PHY-3002 : Step(100): len = 408663, overlap = 251.062
+PHY-3002 : Step(101): len = 410309, overlap = 259.281
+PHY-3002 : Step(102): len = 407931, overlap = 253.438
+PHY-3002 : Step(103): len = 408068, overlap = 257.375
+PHY-3002 : Step(104): len = 408918, overlap = 253.156
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000156411
+PHY-3002 : Step(105): len = 422274, overlap = 251.938
+PHY-3002 : Step(106): len = 431661, overlap = 240.344
+PHY-3002 : Step(107): len = 431676, overlap = 222.531
+PHY-3002 : Step(108): len = 434313, overlap = 215.219
+PHY-3002 : Step(109): len = 439009, overlap = 210.375
+PHY-3002 : Step(110): len = 441577, overlap = 204.469
+PHY-3002 : Step(111): len = 439432, overlap = 204
+PHY-3002 : Step(112): len = 440692, overlap = 190.844
+PHY-3002 : Step(113): len = 443381, overlap = 189.25
+PHY-3002 : Step(114): len = 445155, overlap = 185.969
+PHY-3002 : Step(115): len = 442654, overlap = 185.562
+PHY-3002 : Step(116): len = 442534, overlap = 188.188
+PHY-3002 : Step(117): len = 443868, overlap = 174.688
+PHY-3002 : Step(118): len = 445363, overlap = 171.344
+PHY-3002 : Step(119): len = 443351, overlap = 181.562
+PHY-3002 : Step(120): len = 443311, overlap = 184.312
+PHY-3002 : Step(121): len = 445191, overlap = 177.156
+PHY-3002 : Step(122): len = 446914, overlap = 180.812
+PHY-3002 : Step(123): len = 444416, overlap = 183.156
+PHY-3002 : Step(124): len = 444210, overlap = 185.281
+PHY-3002 : Step(125): len = 445641, overlap = 183.656
+PHY-3002 : Step(126): len = 446772, overlap = 185.781
+PHY-3002 : Step(127): len = 445002, overlap = 190.344
+PHY-3002 : Step(128): len = 445265, overlap = 190.938
+PHY-3002 : Step(129): len = 446540, overlap = 190.125
+PHY-3002 : Step(130): len = 447265, overlap = 188.688
+PHY-3002 : Step(131): len = 445256, overlap = 186.438
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000299854
+PHY-3002 : Step(132): len = 454047, overlap = 195.469
+PHY-3002 : Step(133): len = 460327, overlap = 189.125
+PHY-3002 : Step(134): len = 459569, overlap = 184.531
+PHY-3002 : Step(135): len = 460395, overlap = 178.062
+PHY-3002 : Step(136): len = 463819, overlap = 180.781
+PHY-3002 : Step(137): len = 466679, overlap = 181.594
+PHY-3002 : Step(138): len = 465941, overlap = 176.062
+PHY-3002 : Step(139): len = 466515, overlap = 173.844
+PHY-3002 : Step(140): len = 469688, overlap = 177.062
+PHY-3002 : Step(141): len = 471435, overlap = 183.688
+PHY-3002 : Step(142): len = 469633, overlap = 176.281
+PHY-3002 : Step(143): len = 469165, overlap = 172.156
+PHY-3002 : Step(144): len = 471460, overlap = 171.156
+PHY-3002 : Step(145): len = 474232, overlap = 170.156
+PHY-3002 : Step(146): len = 474066, overlap = 169.625
+PHY-3002 : Step(147): len = 474930, overlap = 159.75
+PHY-3002 : Step(148): len = 476269, overlap = 154.125
+PHY-3002 : Step(149): len = 477065, overlap = 153.969
+PHY-3002 : Step(150): len = 475189, overlap = 161.344
+PHY-3002 : Step(151): len = 474818, overlap = 163.281
+PHY-3002 : Step(152): len = 475646, overlap = 159.438
+PHY-3002 : Step(153): len = 475907, overlap = 158.531
+PHY-3002 : Step(154): len = 474675, overlap = 161.5
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000541068
+PHY-3002 : Step(155): len = 479796, overlap = 153.188
+PHY-3002 : Step(156): len = 485510, overlap = 159.594
+PHY-3002 : Step(157): len = 486261, overlap = 155.562
+PHY-3002 : Step(158): len = 486932, overlap = 160.812
+PHY-3002 : Step(159): len = 489046, overlap = 157.781
+PHY-3002 : Step(160): len = 490417, overlap = 153.875
+PHY-3002 : Step(161): len = 489250, overlap = 153.156
+PHY-3002 : Step(162): len = 489138, overlap = 154.562
+PHY-3002 : Step(163): len = 490535, overlap = 150.5
+PHY-3002 : Step(164): len = 491131, overlap = 153.094
+PHY-3002 : Step(165): len = 490243, overlap = 150.156
+PHY-3002 : Step(166): len = 489951, overlap = 145.656
+PHY-3002 : Step(167): len = 491099, overlap = 142.062
+PHY-3002 : Step(168): len = 491598, overlap = 142.219
+PHY-3002 : Step(169): len = 490752, overlap = 141.906
+PHY-3002 : Step(170): len = 490688, overlap = 147.094
+PHY-3002 : Step(171): len = 491494, overlap = 140.094
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00100032
+PHY-3002 : Step(172): len = 496732, overlap = 141.906
+PHY-3002 : Step(173): len = 504407, overlap = 136.344
+PHY-3002 : Step(174): len = 508971, overlap = 133.406
+PHY-3002 : Step(175): len = 512086, overlap = 128.75
+PHY-3002 : Step(176): len = 513163, overlap = 125.656
+PHY-3002 : Step(177): len = 513707, overlap = 128.938
+PHY-3002 : Step(178): len = 512770, overlap = 120.781
+PHY-3002 : Step(179): len = 512394, overlap = 122.062
+PHY-3002 : Step(180): len = 512887, overlap = 118.156
+PHY-3002 : Step(181): len = 512865, overlap = 125.375
+PHY-3002 : Step(182): len = 511940, overlap = 122.938
+PHY-3002 : Step(183): len = 511544, overlap = 126.375
+PHY-3002 : Step(184): len = 511943, overlap = 124.969
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00190836
+PHY-3002 : Step(185): len = 513878, overlap = 126.25
+PHY-3002 : Step(186): len = 517370, overlap = 121
+PHY-3002 : Step(187): len = 519367, overlap = 124.062
+PHY-3002 : Step(188): len = 520802, overlap = 123.5
+PHY-3002 : Step(189): len = 521319, overlap = 119.438
+PHY-3002 : Step(190): len = 521767, overlap = 118.5
+PHY-3002 : Step(191): len = 522380, overlap = 116
+PHY-3002 : Step(192): len = 522934, overlap = 118.375
+PHY-3002 : Step(193): len = 523397, overlap = 116.625
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.010670s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20638.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 717528, over cnt = 1582(4%), over = 7482, worst = 42
+PHY-1001 : End global iterations; 0.679620s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (135.6%)
+
+PHY-1001 : Congestion index: top1 = 81.31, top5 = 62.05, top10 = 53.03, top15 = 47.29.
+PHY-3001 : End congestion estimation; 0.923731s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (126.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20460 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.847534s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000138041
+PHY-3002 : Step(194): len = 650426, overlap = 65.6562
+PHY-3002 : Step(195): len = 655484, overlap = 66.25
+PHY-3002 : Step(196): len = 651210, overlap = 64.9062
+PHY-3002 : Step(197): len = 644618, overlap = 64.5938
+PHY-3002 : Step(198): len = 642249, overlap = 56.5938
+PHY-3002 : Step(199): len = 643620, overlap = 48.8438
+PHY-3002 : Step(200): len = 641384, overlap = 47.125
+PHY-3002 : Step(201): len = 639038, overlap = 47.9688
+PHY-3002 : Step(202): len = 638226, overlap = 43.2188
+PHY-3002 : Step(203): len = 639360, overlap = 40.3438
+PHY-3002 : Step(204): len = 638192, overlap = 37.5625
+PHY-3002 : Step(205): len = 635986, overlap = 34.7812
+PHY-3002 : Step(206): len = 633852, overlap = 31.4375
+PHY-3002 : Step(207): len = 635003, overlap = 27.375
+PHY-3002 : Step(208): len = 635360, overlap = 26.5938
+PHY-3002 : Step(209): len = 634253, overlap = 28.9375
+PHY-3002 : Step(210): len = 633628, overlap = 31.4062
+PHY-3002 : Step(211): len = 633352, overlap = 30.2188
+PHY-3002 : Step(212): len = 632050, overlap = 29.25
+PHY-3002 : Step(213): len = 631183, overlap = 29.375
+PHY-3002 : Step(214): len = 631649, overlap = 29.5938
+PHY-3002 : Step(215): len = 629967, overlap = 29.3438
+PHY-3002 : Step(216): len = 628819, overlap = 27.9375
+PHY-3002 : Step(217): len = 628521, overlap = 25.9688
+PHY-3002 : Step(218): len = 627865, overlap = 25.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000276083
+PHY-3002 : Step(219): len = 629500, overlap = 25.8125
+PHY-3002 : Step(220): len = 633405, overlap = 24.0938
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 71/20638.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715776, over cnt = 2630(7%), over = 11390, worst = 47
+PHY-1001 : End global iterations; 1.680166s wall, 2.093750s user + 0.031250s system = 2.125000s CPU (126.5%)
+
+PHY-1001 : Congestion index: top1 = 82.54, top5 = 66.49, top10 = 57.75, top15 = 52.32.
+PHY-3001 : End congestion estimation; 1.939622s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (123.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20460 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.865391s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.57077e-05
+PHY-3002 : Step(221): len = 630627, overlap = 271.312
+PHY-3002 : Step(222): len = 634211, overlap = 199.656
+PHY-3002 : Step(223): len = 633373, overlap = 179.188
+PHY-3002 : Step(224): len = 629147, overlap = 165.094
+PHY-3002 : Step(225): len = 627172, overlap = 146.156
+PHY-3002 : Step(226): len = 627749, overlap = 127.438
+PHY-3002 : Step(227): len = 625428, overlap = 119.125
+PHY-3002 : Step(228): len = 622428, overlap = 118.125
+PHY-3002 : Step(229): len = 620825, overlap = 114.938
+PHY-3002 : Step(230): len = 619527, overlap = 116.062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000191415
+PHY-3002 : Step(231): len = 618133, overlap = 114.562
+PHY-3002 : Step(232): len = 620673, overlap = 107.438
+PHY-3002 : Step(233): len = 622228, overlap = 105.281
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000382831
+PHY-3002 : Step(234): len = 626693, overlap = 94.8125
+PHY-3002 : Step(235): len = 634375, overlap = 84.625
+PHY-3002 : Step(236): len = 640898, overlap = 76.5
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84374, tnet num: 20460, tinst num: 18059, tnode num: 114958, tedge num: 134578.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.438929s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.9%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 564 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 405.41 peak overflow 4.19
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1331/20638.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733720, over cnt = 3028(8%), over = 10608, worst = 24
+PHY-1001 : End global iterations; 1.118525s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 68.10, top5 = 57.44, top10 = 51.41, top15 = 47.76.
+PHY-1001 : End incremental global routing; 1.439884s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (132.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20460 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.890435s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17928 has valid locations, 290 needs to be replaced
+PHY-3001 : design contains 18303 instances, 7752 luts, 9330 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6164 pins
+PHY-3001 : Found 1257 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 662531
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16686/20882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 746384, over cnt = 3050(8%), over = 10679, worst = 24
+PHY-1001 : End global iterations; 0.225859s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (117.6%)
+
+PHY-1001 : Congestion index: top1 = 67.91, top5 = 57.36, top10 = 51.50, top15 = 48.06.
+PHY-3001 : End congestion estimation; 0.476029s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (111.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85343, tnet num: 20704, tinst num: 18303, tnode num: 116399, tedge num: 136028.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.456102s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.8%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 612 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.404968s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(237): len = 661348, overlap = 0.5625
+PHY-3002 : Step(238): len = 660995, overlap = 0.5625
+PHY-3002 : Step(239): len = 660680, overlap = 0.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16775/20882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744560, over cnt = 3048(8%), over = 10731, worst = 24
+PHY-1001 : End global iterations; 0.187044s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (117.0%)
+
+PHY-1001 : Congestion index: top1 = 68.25, top5 = 57.64, top10 = 51.78, top15 = 48.24.
+PHY-3001 : End congestion estimation; 0.437989s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (107.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.916217s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000441751
+PHY-3002 : Step(240): len = 660373, overlap = 78.625
+PHY-3002 : Step(241): len = 660361, overlap = 78.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000883502
+PHY-3002 : Step(242): len = 660563, overlap = 78.0625
+PHY-3002 : Step(243): len = 661040, overlap = 77.9375
+PHY-3001 : Final: Len = 661040, Over = 77.9375
+PHY-3001 : End incremental placement; 4.850772s wall, 5.015625s user + 0.093750s system = 5.109375s CPU (105.3%)
+
+OPT-1001 : Total overflow 410.84 peak overflow 4.19
+OPT-1001 : End high-fanout net optimization; 7.699224s wall, 8.359375s user + 0.093750s system = 8.453125s CPU (109.8%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 732.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16721/20882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 746880, over cnt = 2982(8%), over = 9728, worst = 24
+PHY-1002 : len = 792112, over cnt = 2029(5%), over = 5165, worst = 19
+PHY-1002 : len = 825456, over cnt = 1097(3%), over = 2596, worst = 19
+PHY-1002 : len = 846240, over cnt = 590(1%), over = 1308, worst = 16
+PHY-1002 : len = 867408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.728927s wall, 2.453125s user + 0.015625s system = 2.468750s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 51.70, top10 = 48.10, top15 = 45.69.
+OPT-1001 : End congestion update; 1.985486s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (136.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.795661s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (100.2%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 122 cells processed and 17850 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 50 cells processed and 5450 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 7 cells processed and 550 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 746 slack improved
+OPT-1001 : End bottleneck based optimization; 3.187706s wall, 3.890625s user + 0.031250s system = 3.921875s CPU (123.0%)
+
+OPT-1001 : Current memory(MB): used = 691, reserve = 688, peak = 732.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16721/20886.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 868168, over cnt = 95(0%), over = 147, worst = 4
+PHY-1002 : len = 867808, over cnt = 60(0%), over = 79, worst = 3
+PHY-1002 : len = 868360, over cnt = 8(0%), over = 9, worst = 2
+PHY-1002 : len = 868408, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 868424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.749016s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 58.02, top5 = 51.70, top10 = 48.06, top15 = 45.61.
+OPT-1001 : End congestion update; 1.029351s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (100.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20708 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.785168s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.5%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 22 cells processed and 4100 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.929635s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (99.6%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 699, peak = 732.
+OPT-1001 : End physical optimization; 14.554127s wall, 15.968750s user + 0.171875s system = 16.140625s CPU (110.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7752 LUT to BLE ...
+SYN-4008 : Packed 7752 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6186 remaining SEQ's ...
+SYN-4005 : Packed 3881 SEQ with LUT/SLICE
+SYN-4006 : 1010 single LUT's are left
+SYN-4006 : 2305 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10057/13844 primitive instances ...
+PHY-3001 : End packing; 1.618502s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6814 instances
+RUN-1001 : 3333 mslices, 3333 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17870 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9974 nets have 2 pins
+RUN-1001 : 6550 nets have [3 - 5] pins
+RUN-1001 : 731 nets have [6 - 10] pins
+RUN-1001 : 275 nets have [11 - 20] pins
+RUN-1001 : 305 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6812 instances, 6666 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3598 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 673342, Over = 231.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7716/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 822312, over cnt = 1921(5%), over = 3089, worst = 8
+PHY-1002 : len = 830664, over cnt = 1170(3%), over = 1660, worst = 8
+PHY-1002 : len = 840912, over cnt = 606(1%), over = 846, worst = 6
+PHY-1002 : len = 852072, over cnt = 201(0%), over = 288, worst = 6
+PHY-1002 : len = 858160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.602004s wall, 2.218750s user + 0.000000s system = 2.218750s CPU (138.5%)
+
+PHY-1001 : Congestion index: top1 = 61.40, top5 = 52.96, top10 = 48.46, top15 = 45.63.
+PHY-3001 : End congestion estimation; 1.988810s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (131.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71674, tnet num: 17692, tinst num: 6812, tnode num: 94213, tedge num: 119192.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.585020s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.6%)
+
+RUN-1004 : used memory is 607 MB, reserved memory is 614 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.694629s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.77691e-05
+PHY-3002 : Step(244): len = 660975, overlap = 238.25
+PHY-3002 : Step(245): len = 654729, overlap = 239
+PHY-3002 : Step(246): len = 650520, overlap = 244.75
+PHY-3002 : Step(247): len = 648257, overlap = 248
+PHY-3002 : Step(248): len = 645967, overlap = 255.25
+PHY-3002 : Step(249): len = 644029, overlap = 262.75
+PHY-3002 : Step(250): len = 642371, overlap = 259.75
+PHY-3002 : Step(251): len = 640656, overlap = 260.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000115538
+PHY-3002 : Step(252): len = 644652, overlap = 255
+PHY-3002 : Step(253): len = 646929, overlap = 249.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000231076
+PHY-3002 : Step(254): len = 651343, overlap = 241.75
+PHY-3002 : Step(255): len = 662186, overlap = 217.25
+PHY-3002 : Step(256): len = 664155, overlap = 217.5
+PHY-3002 : Step(257): len = 665462, overlap = 225
+PHY-3002 : Step(258): len = 666695, overlap = 223.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.380259s wall, 0.359375s user + 0.625000s system = 0.984375s CPU (258.9%)
+
+PHY-3001 : Trial Legalized: Len = 753506
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 743/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862368, over cnt = 2671(7%), over = 4459, worst = 7
+PHY-1002 : len = 879784, over cnt = 1563(4%), over = 2260, worst = 6
+PHY-1002 : len = 901544, over cnt = 449(1%), over = 656, worst = 6
+PHY-1002 : len = 910984, over cnt = 62(0%), over = 85, worst = 4
+PHY-1002 : len = 912480, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.360973s wall, 3.484375s user + 0.046875s system = 3.531250s CPU (149.6%)
+
+PHY-1001 : Congestion index: top1 = 57.76, top5 = 51.66, top10 = 48.38, top15 = 46.20.
+PHY-3001 : End congestion estimation; 2.805733s wall, 3.937500s user + 0.046875s system = 3.984375s CPU (142.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.826166s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (98.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00016167
+PHY-3002 : Step(259): len = 725100, overlap = 39.25
+PHY-3002 : Step(260): len = 708231, overlap = 64.5
+PHY-3002 : Step(261): len = 695095, overlap = 91
+PHY-3002 : Step(262): len = 686617, overlap = 113.5
+PHY-3002 : Step(263): len = 679413, overlap = 140.25
+PHY-3002 : Step(264): len = 676163, overlap = 152.5
+PHY-3002 : Step(265): len = 673306, overlap = 163.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000323339
+PHY-3002 : Step(266): len = 677203, overlap = 158
+PHY-3002 : Step(267): len = 681475, overlap = 155.5
+PHY-3002 : Step(268): len = 684564, overlap = 154.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000646678
+PHY-3002 : Step(269): len = 686738, overlap = 151.75
+PHY-3002 : Step(270): len = 693724, overlap = 149
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032479s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (96.2%)
+
+PHY-3001 : Legalized: Len = 724144, Over = 0
+PHY-3001 : Spreading special nets. 462 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.101479s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (107.8%)
+
+PHY-3001 : 675 instances has been re-located, deltaX = 234, deltaY = 387, maxDist = 3.
+PHY-3001 : Final: Len = 735254, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71674, tnet num: 17692, tinst num: 6815, tnode num: 94213, tedge num: 119192.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.796791s wall, 1.765625s user + 0.031250s system = 1.796875s CPU (100.0%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 637 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4450/17870.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 857064, over cnt = 2432(6%), over = 3891, worst = 6
+PHY-1002 : len = 869928, over cnt = 1491(4%), over = 2109, worst = 6
+PHY-1002 : len = 887016, over cnt = 529(1%), over = 723, worst = 5
+PHY-1002 : len = 895848, over cnt = 84(0%), over = 118, worst = 4
+PHY-1002 : len = 897936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.981129s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (144.3%)
+
+PHY-1001 : Congestion index: top1 = 54.70, top5 = 49.82, top10 = 46.83, top15 = 44.73.
+PHY-1001 : End incremental global routing; 2.342406s wall, 3.203125s user + 0.015625s system = 3.218750s CPU (137.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17692 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.889661s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6723 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6834 instances, 6685 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3673 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 739882
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16180/17890.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903048, over cnt = 94(0%), over = 112, worst = 4
+PHY-1002 : len = 903168, over cnt = 29(0%), over = 32, worst = 4
+PHY-1002 : len = 903456, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 903456, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 903600, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.728016s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 54.74, top5 = 49.88, top10 = 46.91, top15 = 44.83.
+PHY-3001 : End congestion estimation; 1.029535s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (103.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71839, tnet num: 17712, tinst num: 6834, tnode num: 94415, tedge num: 119410.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.808323s wall, 1.781250s user + 0.031250s system = 1.812500s CPU (100.2%)
+
+RUN-1004 : used memory is 650 MB, reserved memory is 644 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17712 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.662865s wall, 2.609375s user + 0.046875s system = 2.656250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(271): len = 738548, overlap = 0
+PHY-3002 : Step(272): len = 737943, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16165/17890.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900608, over cnt = 68(0%), over = 83, worst = 3
+PHY-1002 : len = 900632, over cnt = 26(0%), over = 28, worst = 3
+PHY-1002 : len = 900872, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 901016, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 901064, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.746718s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (108.8%)
+
+PHY-1001 : Congestion index: top1 = 54.66, top5 = 49.87, top10 = 46.90, top15 = 44.79.
+PHY-3001 : End congestion estimation; 1.047925s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (105.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17712 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.826617s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155499
+PHY-3002 : Step(273): len = 737813, overlap = 1.75
+PHY-3002 : Step(274): len = 737880, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005284s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 737946, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057899s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.9%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 737992, Over = 0
+PHY-3001 : End incremental placement; 6.028793s wall, 6.296875s user + 0.156250s system = 6.453125s CPU (107.0%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.867228s wall, 10.968750s user + 0.187500s system = 11.156250s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 728, reserve = 727, peak = 732.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16151/17890.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901728, over cnt = 46(0%), over = 64, worst = 4
+PHY-1002 : len = 901920, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 902080, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 902192, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.562244s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (108.4%)
+
+PHY-1001 : Congestion index: top1 = 54.83, top5 = 49.89, top10 = 46.94, top15 = 44.84.
+OPT-1001 : End congestion update; 0.858730s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (105.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17712 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.694093s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.3%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6746 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6834 instances, 6685 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3673 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 743230, Over = 0
+PHY-3001 : Spreading special nets. 26 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065719s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.1%)
+
+PHY-3001 : 32 instances has been re-located, deltaX = 9, deltaY = 28, maxDist = 2.
+PHY-3001 : Final: Len = 744170, Over = 0
+PHY-3001 : End incremental legalization; 0.415212s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 59 cells processed and 22418 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6746 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6834 instances, 6685 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3673 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744322, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064449s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.0%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 6, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 744740, Over = 0
+PHY-3001 : End incremental legalization; 0.441824s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.0%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 28 cells processed and 3253 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6746 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6834 instances, 6685 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3673 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744396, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058459s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.9%)
+
+PHY-3001 : 20 instances has been re-located, deltaX = 8, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 744952, Over = 0
+PHY-3001 : End incremental legalization; 0.370811s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.1%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 24 cells processed and 1590 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6753 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6841 instances, 6692 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 745224, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058138s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.5%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 9, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 745452, Over = 0
+PHY-3001 : End incremental legalization; 0.368133s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.6%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 6 cells processed and 979 slack improved
+OPT-1001 : End bottleneck based optimization; 3.751335s wall, 3.906250s user + 0.000000s system = 3.906250s CPU (104.1%)
+
+OPT-1001 : Current memory(MB): used = 728, reserve = 728, peak = 732.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15685/17894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909264, over cnt = 217(0%), over = 267, worst = 4
+PHY-1002 : len = 909544, over cnt = 108(0%), over = 117, worst = 3
+PHY-1002 : len = 910272, over cnt = 36(0%), over = 39, worst = 2
+PHY-1002 : len = 910896, over cnt = 11(0%), over = 12, worst = 2
+PHY-1002 : len = 911208, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.845830s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (114.5%)
+
+PHY-1001 : Congestion index: top1 = 55.06, top5 = 49.93, top10 = 47.05, top15 = 44.98.
+OPT-1001 : End congestion update; 1.149366s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (111.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.698217s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.7%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6753 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6841 instances, 6692 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 745808, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058627s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.6%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 3, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 745754, Over = 0
+PHY-3001 : End incremental legalization; 0.369065s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (131.2%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 1450 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.337129s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (110.3%)
+
+OPT-1001 : Current memory(MB): used = 728, reserve = 728, peak = 732.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.696101s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16172/17894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911344, over cnt = 25(0%), over = 27, worst = 3
+PHY-1002 : len = 911400, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 911472, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 911520, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 911592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.890020s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (103.6%)
+
+PHY-1001 : Congestion index: top1 = 55.06, top5 = 49.95, top10 = 47.06, top15 = 44.99.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.697821s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.620690
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 221ps with logic level 1
+OPT-1001 : End physical optimization; 20.578001s wall, 22.171875s user + 0.218750s system = 22.390625s CPU (108.8%)
+
+RUN-1003 : finish command "place" in 61.762634s wall, 84.546875s user + 5.390625s system = 89.937500s CPU (145.6%)
+
+RUN-1004 : used memory is 675 MB, reserved memory is 679 MB, peak memory is 732 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.668152s wall, 2.843750s user + 0.046875s system = 2.890625s CPU (173.3%)
+
+RUN-1004 : used memory is 675 MB, reserved memory is 679 MB, peak memory is 732 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6843 instances
+RUN-1001 : 3350 mslices, 3342 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17894 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 6552 nets have [3 - 5] pins
+RUN-1001 : 746 nets have [6 - 10] pins
+RUN-1001 : 274 nets have [11 - 20] pins
+RUN-1001 : 322 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71910, tnet num: 17716, tinst num: 6841, tnode num: 94508, tedge num: 119502.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.603485s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.4%)
+
+RUN-1004 : used memory is 656 MB, reserved memory is 655 MB, peak memory is 732 MB
+PHY-1001 : 3350 mslices, 3342 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[18] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844024, over cnt = 2658(7%), over = 4420, worst = 7
+PHY-1002 : len = 862992, over cnt = 1551(4%), over = 2182, worst = 6
+PHY-1002 : len = 877680, over cnt = 789(2%), over = 1078, worst = 6
+PHY-1002 : len = 895360, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 895488, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.869403s wall, 3.906250s user + 0.031250s system = 3.937500s CPU (137.2%)
+
+PHY-1001 : Congestion index: top1 = 55.28, top5 = 49.98, top10 = 46.77, top15 = 44.63.
+PHY-1001 : End global routing; 3.187785s wall, 4.203125s user + 0.046875s system = 4.250000s CPU (133.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 705, reserve = 705, peak = 732.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 977, reserve = 979, peak = 977.
+PHY-1001 : End build detailed router design. 4.147953s wall, 4.109375s user + 0.031250s system = 4.140625s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266936, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.199688s wall, 5.203125s user + 0.000000s system = 5.203125s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266992, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.437096s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1013, reserve = 1016, peak = 1013.
+PHY-1001 : End phase 1; 5.649601s wall, 5.656250s user + 0.000000s system = 5.656250s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.29407e+06, over cnt = 1580(0%), over = 1582, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1028, reserve = 1030, peak = 1028.
+PHY-1001 : End initial routed; 27.012048s wall, 56.734375s user + 0.312500s system = 57.046875s CPU (211.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16812(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.172639s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1040, peak = 1038.
+PHY-1001 : End phase 2; 30.184755s wall, 59.906250s user + 0.312500s system = 60.218750s CPU (199.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.132728s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.2%)
+
+PHY-1022 : len = 2.29407e+06, over cnt = 1580(0%), over = 1582, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.400650s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.27185e+06, over cnt = 551(0%), over = 552, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 0.993174s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (174.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.26998e+06, over cnt = 122(0%), over = 122, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.472811s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (148.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.27037e+06, over cnt = 30(0%), over = 30, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.303214s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2708e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 4; 0.208944s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16812(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.210434s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 466 feed throughs used by 379 nets
+PHY-1001 : End commit to database; 2.213331s wall, 2.156250s user + 0.046875s system = 2.203125s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1141, reserve = 1146, peak = 1141.
+PHY-1001 : End phase 3; 8.185395s wall, 9.109375s user + 0.062500s system = 9.171875s CPU (112.1%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.133299s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.5%)
+
+PHY-1022 : len = 2.2708e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.392706s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16812(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.232460s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 466 feed throughs used by 379 nets
+PHY-1001 : End commit to database; 2.286612s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1149, reserve = 1155, peak = 1149.
+PHY-1001 : End phase 4; 5.939245s wall, 5.937500s user + 0.000000s system = 5.937500s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.2708e+06
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1157, peak = 1151.
+PHY-1001 : End export database. 0.059034s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.9%)
+
+PHY-1001 : End detail routing; 54.555625s wall, 85.156250s user + 0.406250s system = 85.562500s CPU (156.8%)
+
+RUN-1003 : finish command "route" in 60.431339s wall, 92.062500s user + 0.453125s system = 92.515625s CPU (153.1%)
+
+RUN-1004 : used memory is 1079 MB, reserved memory is 1082 MB, peak memory is 1151 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10207 out of 19600 52.08%
+#reg 9515 out of 19600 48.55%
+#le 12479
+ #lut only 2964 out of 12479 23.75%
+ #reg only 2272 out of 12479 18.21%
+ #lut® 7243 out of 12479 58.04%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1773
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1440
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1320
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 952
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice BUSY_MIPI_sync_d1_reg_syn_12.q0 138
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg1_syn_160.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_537.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P15 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P39 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P32 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P146 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P16 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12479 |9180 |1027 |9547 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |527 |434 |23 |443 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |90 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |35 |35 |0 |20 |0 |0 |
+| U_ecc_gen |ecc_gen |8 |8 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |756 |387 |96 |576 |0 |0 |
+| u_ADconfig |AD_config |193 |107 |25 |147 |0 |0 |
+| u_gen_sp |gen_sp |250 |159 |71 |116 |0 |0 |
+| exdev_ctl_b |exdev_ctl |748 |360 |96 |567 |0 |0 |
+| u_ADconfig |AD_config |170 |125 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |261 |144 |71 |124 |0 |0 |
+| sampling_fe_a |sampling_fe |3027 |2462 |306 |2070 |25 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |107 |17 |160 |0 |0 |
+| u0_soft_n |cdc_sync |8 |3 |0 |8 |0 |0 |
+| u_sort |sort |2810 |2352 |289 |1883 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |1 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2399 |2050 |253 |1534 |22 |0 |
+| channelPart |channel_part_8478 |129 |124 |3 |124 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1922 |1643 |197 |1156 |0 |0 |
+| adc_addr_gen |adc_addr_gen |228 |201 |27 |124 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |19 |16 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| insert |insert |954 |702 |170 |653 |0 |0 |
+| ram_switch_state |ram_switch_state |740 |740 |0 |379 |0 |0 |
+| read_ram_i |read_ram |264 |212 |44 |185 |0 |0 |
+| read_ram_addr |read_ram_addr |220 |180 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |43 |31 |4 |33 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |308 |221 |36 |275 |3 |0 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3221 |2567 |349 |2059 |25 |1 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |186 |105 |17 |155 |0 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_sort |sort_rev |3001 |2436 |332 |1870 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2629 |2157 |290 |1536 |22 |1 |
+| channelPart |channel_part_8478 |148 |145 |3 |125 |0 |0 |
+| fifo_adc |fifo_adc |64 |55 |9 |44 |0 |1 |
+| ram_switch |ram_switch |2029 |1687 |197 |1125 |0 |0 |
+| adc_addr_gen |adc_addr_gen |216 |189 |27 |101 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |17 |14 |3 |7 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |21 |18 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |28 |25 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| insert |insert |966 |651 |170 |661 |0 |0 |
+| ram_switch_state |ram_switch_state |847 |847 |0 |363 |0 |0 |
+| read_ram_i |read_ram_rev |357 |246 |81 |211 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |292 |212 |73 |161 |0 |0 |
+| read_ram_data |read_ram_data_rev |65 |34 |8 |50 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9907
+ #2 2 4287
+ #3 3 1702
+ #4 4 560
+ #5 5-10 779
+ #6 11-50 549
+ #7 51-100 11
+ #8 >500 1
+ Average 2.73
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.072446s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (172.7%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1084 MB, peak memory is 1151 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71910, tnet num: 17716, tinst num: 6841, tnode num: 94508, tedge num: 119502.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.554920s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.5%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1088 MB, peak memory is 1151 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.420365s wall, 1.390625s user + 0.031250s system = 1.421875s CPU (100.1%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1090 MB, peak memory is 1151 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6841
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17894, pip num: 168435
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 466
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 469601 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.820943s wall, 67.031250s user + 0.203125s system = 67.234375s CPU (684.6%)
+
+RUN-1004 : used memory is 1246 MB, reserved memory is 1249 MB, peak memory is 1361 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_093416.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_094538.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_094538.log
new file mode 100644
index 0000000..3a3c18b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_094538.log
@@ -0,0 +1,2138 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 09:45:38 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.343118s wall, 2.218750s user + 0.125000s system = 2.343750s CPU (100.0%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 316 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2951 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2279 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2120 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18054 instances
+RUN-0007 : 7652 luts, 9179 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20631 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13142 nets have 2 pins
+RUN-1001 : 6454 nets have [3 - 5] pins
+RUN-1001 : 616 nets have [6 - 10] pins
+RUN-1001 : 180 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 798
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3579
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18052 instances, 7652 luts, 9179 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6052 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84343, tnet num: 20453, tinst num: 18052, tnode num: 114933, tedge num: 134530.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.220236s wall, 1.187500s user + 0.031250s system = 1.218750s CPU (99.9%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 515 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20453 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.106086s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (100.2%)
+
+PHY-3001 : Found 1247 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.1543e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18052.
+PHY-3001 : Level 1 #clusters 2047.
+PHY-3001 : End clustering; 0.157676s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (138.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.30083e+06, overlap = 485.344
+PHY-3002 : Step(2): len = 1.20608e+06, overlap = 526.125
+PHY-3002 : Step(3): len = 871975, overlap = 589.5
+PHY-3002 : Step(4): len = 787027, overlap = 634.406
+PHY-3002 : Step(5): len = 621935, overlap = 765.125
+PHY-3002 : Step(6): len = 556850, overlap = 838.625
+PHY-3002 : Step(7): len = 471440, overlap = 931.531
+PHY-3002 : Step(8): len = 429365, overlap = 954.688
+PHY-3002 : Step(9): len = 390405, overlap = 1033.59
+PHY-3002 : Step(10): len = 354783, overlap = 1087.53
+PHY-3002 : Step(11): len = 322927, overlap = 1164.31
+PHY-3002 : Step(12): len = 287897, overlap = 1234.38
+PHY-3002 : Step(13): len = 265999, overlap = 1262.06
+PHY-3002 : Step(14): len = 236159, overlap = 1296.28
+PHY-3002 : Step(15): len = 222374, overlap = 1336.66
+PHY-3002 : Step(16): len = 204863, overlap = 1377.06
+PHY-3002 : Step(17): len = 189072, overlap = 1388.81
+PHY-3002 : Step(18): len = 170662, overlap = 1421.28
+PHY-3002 : Step(19): len = 163163, overlap = 1455.44
+PHY-3002 : Step(20): len = 147660, overlap = 1462.28
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.00628e-06
+PHY-3002 : Step(21): len = 146959, overlap = 1419.28
+PHY-3002 : Step(22): len = 178805, overlap = 1315.97
+PHY-3002 : Step(23): len = 190614, overlap = 1264.22
+PHY-3002 : Step(24): len = 197728, overlap = 1217.53
+PHY-3002 : Step(25): len = 197852, overlap = 1188
+PHY-3002 : Step(26): len = 196041, overlap = 1181.22
+PHY-3002 : Step(27): len = 193216, overlap = 1155
+PHY-3002 : Step(28): len = 190474, overlap = 1181.81
+PHY-3002 : Step(29): len = 187374, overlap = 1174.5
+PHY-3002 : Step(30): len = 185793, overlap = 1162.66
+PHY-3002 : Step(31): len = 184094, overlap = 1156.44
+PHY-3002 : Step(32): len = 181893, overlap = 1146.25
+PHY-3002 : Step(33): len = 179642, overlap = 1134.88
+PHY-3002 : Step(34): len = 179240, overlap = 1134.28
+PHY-3002 : Step(35): len = 178616, overlap = 1136.81
+PHY-3002 : Step(36): len = 178377, overlap = 1129.53
+PHY-3002 : Step(37): len = 177241, overlap = 1113.59
+PHY-3002 : Step(38): len = 177310, overlap = 1105.66
+PHY-3002 : Step(39): len = 176866, overlap = 1125.78
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.01257e-06
+PHY-3002 : Step(40): len = 181428, overlap = 1090.22
+PHY-3002 : Step(41): len = 197744, overlap = 1028.34
+PHY-3002 : Step(42): len = 202925, overlap = 994.5
+PHY-3002 : Step(43): len = 207625, overlap = 978.031
+PHY-3002 : Step(44): len = 210108, overlap = 963.875
+PHY-3002 : Step(45): len = 211274, overlap = 961.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.02513e-06
+PHY-3002 : Step(46): len = 219608, overlap = 945.969
+PHY-3002 : Step(47): len = 234659, overlap = 892.875
+PHY-3002 : Step(48): len = 240748, overlap = 821.688
+PHY-3002 : Step(49): len = 246463, overlap = 774.156
+PHY-3002 : Step(50): len = 248568, overlap = 754.094
+PHY-3002 : Step(51): len = 250745, overlap = 746.094
+PHY-3002 : Step(52): len = 249711, overlap = 733.969
+PHY-3002 : Step(53): len = 250272, overlap = 730.406
+PHY-3002 : Step(54): len = 249467, overlap = 723.969
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.05026e-06
+PHY-3002 : Step(55): len = 264958, overlap = 702.5
+PHY-3002 : Step(56): len = 283415, overlap = 654.375
+PHY-3002 : Step(57): len = 292051, overlap = 569.281
+PHY-3002 : Step(58): len = 297635, overlap = 550.125
+PHY-3002 : Step(59): len = 299267, overlap = 528.719
+PHY-3002 : Step(60): len = 300698, overlap = 515.531
+PHY-3002 : Step(61): len = 300962, overlap = 519.844
+PHY-3002 : Step(62): len = 300431, overlap = 515.094
+PHY-3002 : Step(63): len = 298068, overlap = 505
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.61005e-05
+PHY-3002 : Step(64): len = 315075, overlap = 483.125
+PHY-3002 : Step(65): len = 331837, overlap = 456.906
+PHY-3002 : Step(66): len = 338608, overlap = 397.844
+PHY-3002 : Step(67): len = 341942, overlap = 386.438
+PHY-3002 : Step(68): len = 341871, overlap = 380.375
+PHY-3002 : Step(69): len = 341934, overlap = 366.312
+PHY-3002 : Step(70): len = 340294, overlap = 358.438
+PHY-3002 : Step(71): len = 340678, overlap = 358.625
+PHY-3002 : Step(72): len = 340408, overlap = 337.969
+PHY-3002 : Step(73): len = 340930, overlap = 338.281
+PHY-3002 : Step(74): len = 340146, overlap = 328.438
+PHY-3002 : Step(75): len = 340303, overlap = 336.875
+PHY-3002 : Step(76): len = 341239, overlap = 334.031
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.22011e-05
+PHY-3002 : Step(77): len = 356584, overlap = 312.625
+PHY-3002 : Step(78): len = 370482, overlap = 302.188
+PHY-3002 : Step(79): len = 374233, overlap = 313.594
+PHY-3002 : Step(80): len = 376625, overlap = 307.188
+PHY-3002 : Step(81): len = 377612, overlap = 295.719
+PHY-3002 : Step(82): len = 379491, overlap = 277.344
+PHY-3002 : Step(83): len = 379363, overlap = 260.781
+PHY-3002 : Step(84): len = 377863, overlap = 251.188
+PHY-3002 : Step(85): len = 377274, overlap = 261.844
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.44021e-05
+PHY-3002 : Step(86): len = 393753, overlap = 262.5
+PHY-3002 : Step(87): len = 405868, overlap = 255.438
+PHY-3002 : Step(88): len = 406836, overlap = 252.094
+PHY-3002 : Step(89): len = 408710, overlap = 250.469
+PHY-3002 : Step(90): len = 410907, overlap = 252.656
+PHY-3002 : Step(91): len = 415166, overlap = 241.312
+PHY-3002 : Step(92): len = 413944, overlap = 251.188
+PHY-3002 : Step(93): len = 414761, overlap = 234.156
+PHY-3002 : Step(94): len = 415486, overlap = 233.25
+PHY-3002 : Step(95): len = 416247, overlap = 231.719
+PHY-3002 : Step(96): len = 415767, overlap = 228.594
+PHY-3002 : Step(97): len = 417161, overlap = 225
+PHY-3002 : Step(98): len = 416381, overlap = 224.281
+PHY-3002 : Step(99): len = 417297, overlap = 233.344
+PHY-3002 : Step(100): len = 416239, overlap = 228.812
+PHY-3002 : Step(101): len = 416279, overlap = 219.344
+PHY-3002 : Step(102): len = 415584, overlap = 212.469
+PHY-3002 : Step(103): len = 415762, overlap = 212.344
+PHY-3002 : Step(104): len = 414808, overlap = 207.781
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000128804
+PHY-3002 : Step(105): len = 430577, overlap = 209.125
+PHY-3002 : Step(106): len = 440389, overlap = 203.875
+PHY-3002 : Step(107): len = 439757, overlap = 195.094
+PHY-3002 : Step(108): len = 441048, overlap = 183.781
+PHY-3002 : Step(109): len = 444890, overlap = 182.219
+PHY-3002 : Step(110): len = 448034, overlap = 179.406
+PHY-3002 : Step(111): len = 447025, overlap = 176.25
+PHY-3002 : Step(112): len = 447463, overlap = 180.969
+PHY-3002 : Step(113): len = 447985, overlap = 186.938
+PHY-3002 : Step(114): len = 448939, overlap = 183.438
+PHY-3002 : Step(115): len = 448313, overlap = 182.219
+PHY-3002 : Step(116): len = 450910, overlap = 204.656
+PHY-3002 : Step(117): len = 452114, overlap = 189.312
+PHY-3002 : Step(118): len = 453508, overlap = 174.344
+PHY-3002 : Step(119): len = 451016, overlap = 189.812
+PHY-3002 : Step(120): len = 450969, overlap = 180.188
+PHY-3002 : Step(121): len = 451347, overlap = 181.312
+PHY-3002 : Step(122): len = 452572, overlap = 182.031
+PHY-3002 : Step(123): len = 450631, overlap = 188.969
+PHY-3002 : Step(124): len = 450311, overlap = 193.781
+PHY-3002 : Step(125): len = 450029, overlap = 190.812
+PHY-3002 : Step(126): len = 450883, overlap = 187
+PHY-3002 : Step(127): len = 448698, overlap = 191.469
+PHY-3002 : Step(128): len = 448885, overlap = 185.469
+PHY-3002 : Step(129): len = 449116, overlap = 186.312
+PHY-3002 : Step(130): len = 449629, overlap = 178.5
+PHY-3002 : Step(131): len = 448084, overlap = 179.125
+PHY-3002 : Step(132): len = 448189, overlap = 185.562
+PHY-3002 : Step(133): len = 448724, overlap = 176.75
+PHY-3002 : Step(134): len = 449147, overlap = 176.906
+PHY-3002 : Step(135): len = 447919, overlap = 183.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000254325
+PHY-3002 : Step(136): len = 458703, overlap = 177.938
+PHY-3002 : Step(137): len = 467262, overlap = 170.656
+PHY-3002 : Step(138): len = 466766, overlap = 172.438
+PHY-3002 : Step(139): len = 467656, overlap = 170.719
+PHY-3002 : Step(140): len = 470107, overlap = 166.406
+PHY-3002 : Step(141): len = 471966, overlap = 162.281
+PHY-3002 : Step(142): len = 471776, overlap = 170.219
+PHY-3002 : Step(143): len = 472711, overlap = 163.531
+PHY-3002 : Step(144): len = 475398, overlap = 160.5
+PHY-3002 : Step(145): len = 477624, overlap = 159.156
+PHY-3002 : Step(146): len = 476395, overlap = 159.688
+PHY-3002 : Step(147): len = 476225, overlap = 164.625
+PHY-3002 : Step(148): len = 476797, overlap = 161.125
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000508649
+PHY-3002 : Step(149): len = 484015, overlap = 152.531
+PHY-3002 : Step(150): len = 491099, overlap = 146.938
+PHY-3002 : Step(151): len = 492805, overlap = 140.156
+PHY-3002 : Step(152): len = 495023, overlap = 143.906
+PHY-3002 : Step(153): len = 497514, overlap = 141.625
+PHY-3002 : Step(154): len = 499531, overlap = 139.562
+PHY-3002 : Step(155): len = 499668, overlap = 144.469
+PHY-3002 : Step(156): len = 500160, overlap = 145.875
+PHY-3002 : Step(157): len = 501623, overlap = 149.25
+PHY-3002 : Step(158): len = 503217, overlap = 147.938
+PHY-3002 : Step(159): len = 502371, overlap = 147.688
+PHY-3002 : Step(160): len = 502338, overlap = 144
+PHY-3002 : Step(161): len = 503042, overlap = 145.156
+PHY-3002 : Step(162): len = 503627, overlap = 144.906
+PHY-3002 : Step(163): len = 503376, overlap = 146.5
+PHY-3002 : Step(164): len = 503422, overlap = 137.625
+PHY-3002 : Step(165): len = 503760, overlap = 137.25
+PHY-3002 : Step(166): len = 503882, overlap = 138.375
+PHY-3002 : Step(167): len = 503735, overlap = 138.312
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00092552
+PHY-3002 : Step(168): len = 506864, overlap = 138.656
+PHY-3002 : Step(169): len = 511608, overlap = 130.812
+PHY-3002 : Step(170): len = 513962, overlap = 133.312
+PHY-3002 : Step(171): len = 515358, overlap = 130.844
+PHY-3002 : Step(172): len = 516586, overlap = 124.906
+PHY-3002 : Step(173): len = 517312, overlap = 126.688
+PHY-3002 : Step(174): len = 517270, overlap = 124.094
+PHY-3002 : Step(175): len = 517583, overlap = 125.125
+PHY-3002 : Step(176): len = 518403, overlap = 123.531
+PHY-3002 : Step(177): len = 518743, overlap = 119.969
+PHY-3002 : Step(178): len = 518594, overlap = 116.094
+PHY-3002 : Step(179): len = 518924, overlap = 116.469
+PHY-3002 : Step(180): len = 519534, overlap = 119.844
+PHY-3002 : Step(181): len = 519678, overlap = 119.594
+PHY-3002 : Step(182): len = 519267, overlap = 115.781
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00152419
+PHY-3002 : Step(183): len = 521590, overlap = 114.938
+PHY-3002 : Step(184): len = 525312, overlap = 119.562
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013688s wall, 0.000000s user + 0.015625s system = 0.015625s CPU (114.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20631.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 706472, over cnt = 1628(4%), over = 7828, worst = 44
+PHY-1001 : End global iterations; 0.738337s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (133.3%)
+
+PHY-1001 : Congestion index: top1 = 88.81, top5 = 65.71, top10 = 55.16, top15 = 48.85.
+PHY-3001 : End congestion estimation; 0.975166s wall, 1.187500s user + 0.031250s system = 1.218750s CPU (125.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20453 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.918001s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000139376
+PHY-3002 : Step(185): len = 643920, overlap = 74.625
+PHY-3002 : Step(186): len = 646110, overlap = 58.7188
+PHY-3002 : Step(187): len = 641274, overlap = 60
+PHY-3002 : Step(188): len = 638116, overlap = 58.75
+PHY-3002 : Step(189): len = 638434, overlap = 54.5938
+PHY-3002 : Step(190): len = 639993, overlap = 48.7188
+PHY-3002 : Step(191): len = 638573, overlap = 45.6875
+PHY-3002 : Step(192): len = 636603, overlap = 44.125
+PHY-3002 : Step(193): len = 634453, overlap = 46.5312
+PHY-3002 : Step(194): len = 632225, overlap = 46.3125
+PHY-3002 : Step(195): len = 632163, overlap = 37.3125
+PHY-3002 : Step(196): len = 630291, overlap = 38.5312
+PHY-3002 : Step(197): len = 628680, overlap = 37.75
+PHY-3002 : Step(198): len = 626975, overlap = 42.25
+PHY-3002 : Step(199): len = 626483, overlap = 39.25
+PHY-3002 : Step(200): len = 625947, overlap = 37.25
+PHY-3002 : Step(201): len = 624365, overlap = 37.7188
+PHY-3002 : Step(202): len = 623717, overlap = 39.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000278752
+PHY-3002 : Step(203): len = 625291, overlap = 40.5625
+PHY-3002 : Step(204): len = 630194, overlap = 40.1562
+PHY-3002 : Step(205): len = 635092, overlap = 41.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000557505
+PHY-3002 : Step(206): len = 640757, overlap = 42.7188
+PHY-3002 : Step(207): len = 652121, overlap = 43.5
+PHY-3002 : Step(208): len = 665721, overlap = 44.1875
+PHY-3002 : Step(209): len = 666533, overlap = 45.5938
+PHY-3002 : Step(210): len = 665606, overlap = 45.375
+PHY-3002 : Step(211): len = 665498, overlap = 46.0938
+PHY-3002 : Step(212): len = 665625, overlap = 46.0938
+PHY-3002 : Step(213): len = 667620, overlap = 46.1562
+PHY-3002 : Step(214): len = 670742, overlap = 50.9062
+PHY-3002 : Step(215): len = 672920, overlap = 54.5312
+PHY-3002 : Step(216): len = 671630, overlap = 53.5625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00111501
+PHY-3002 : Step(217): len = 676705, overlap = 53.5
+PHY-3002 : Step(218): len = 686352, overlap = 53.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00196954
+PHY-3002 : Step(219): len = 688879, overlap = 55.75
+PHY-3002 : Step(220): len = 706557, overlap = 63.8438
+PHY-3002 : Step(221): len = 716308, overlap = 68.7188
+PHY-3002 : Step(222): len = 716313, overlap = 71.7188
+PHY-3002 : Step(223): len = 718280, overlap = 75.8438
+PHY-3002 : Step(224): len = 721851, overlap = 75.875
+PHY-3002 : Step(225): len = 722020, overlap = 77.3125
+PHY-3002 : Step(226): len = 722491, overlap = 78.0938
+PHY-3002 : Step(227): len = 723668, overlap = 74.8438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 58/20631.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 803840, over cnt = 2656(7%), over = 14159, worst = 56
+PHY-1001 : End global iterations; 1.623071s wall, 2.265625s user + 0.046875s system = 2.312500s CPU (142.5%)
+
+PHY-1001 : Congestion index: top1 = 108.15, top5 = 79.28, top10 = 67.46, top15 = 60.55.
+PHY-3001 : End congestion estimation; 1.934722s wall, 2.562500s user + 0.062500s system = 2.625000s CPU (135.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20453 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.456866s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000125312
+PHY-3002 : Step(228): len = 711824, overlap = 322.438
+PHY-3002 : Step(229): len = 706253, overlap = 238.688
+PHY-3002 : Step(230): len = 694040, overlap = 217.125
+PHY-3002 : Step(231): len = 682310, overlap = 192.125
+PHY-3002 : Step(232): len = 671746, overlap = 158.719
+PHY-3002 : Step(233): len = 665101, overlap = 156.312
+PHY-3002 : Step(234): len = 658038, overlap = 146.5
+PHY-3002 : Step(235): len = 654304, overlap = 138.156
+PHY-3002 : Step(236): len = 650354, overlap = 142.062
+PHY-3002 : Step(237): len = 644949, overlap = 146.312
+PHY-3002 : Step(238): len = 642371, overlap = 149.406
+PHY-3002 : Step(239): len = 638918, overlap = 154.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000250624
+PHY-3002 : Step(240): len = 639104, overlap = 144.844
+PHY-3002 : Step(241): len = 641617, overlap = 137.344
+PHY-3002 : Step(242): len = 643025, overlap = 131.594
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000501247
+PHY-3002 : Step(243): len = 650376, overlap = 124.219
+PHY-3002 : Step(244): len = 658282, overlap = 113.406
+PHY-3002 : Step(245): len = 662553, overlap = 104.625
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84343, tnet num: 20453, tinst num: 18052, tnode num: 114933, tedge num: 134530.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.489626s wall, 1.421875s user + 0.062500s system = 1.484375s CPU (99.6%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 564 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 422.91 peak overflow 2.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 588/20631.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 757632, over cnt = 3034(8%), over = 11157, worst = 24
+PHY-1001 : End global iterations; 1.496261s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (134.7%)
+
+PHY-1001 : Congestion index: top1 = 78.25, top5 = 59.89, top10 = 52.71, top15 = 48.78.
+PHY-1001 : End incremental global routing; 1.851109s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (129.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20453 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.931443s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.0%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17920 has valid locations, 323 needs to be replaced
+PHY-3001 : design contains 18328 instances, 7756 luts, 9351 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6179 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 686148
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16994/20907.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 774040, over cnt = 3073(8%), over = 11270, worst = 24
+PHY-1001 : End global iterations; 0.347837s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (134.8%)
+
+PHY-1001 : Congestion index: top1 = 77.74, top5 = 60.03, top10 = 53.06, top15 = 49.12.
+PHY-3001 : End congestion estimation; 0.619775s wall, 0.718750s user + 0.015625s system = 0.734375s CPU (118.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85453, tnet num: 20729, tinst num: 18328, tnode num: 116582, tedge num: 136198.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.498279s wall, 1.468750s user + 0.031250s system = 1.500000s CPU (100.1%)
+
+RUN-1004 : used memory is 630 MB, reserved memory is 637 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20729 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.469714s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(246): len = 685085, overlap = 0.125
+PHY-3002 : Step(247): len = 684636, overlap = 0.125
+PHY-3002 : Step(248): len = 684527, overlap = 0.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17089/20907.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 772072, over cnt = 3102(8%), over = 11355, worst = 24
+PHY-1001 : End global iterations; 0.215783s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (144.8%)
+
+PHY-1001 : Congestion index: top1 = 78.15, top5 = 60.45, top10 = 53.25, top15 = 49.33.
+PHY-3001 : End congestion estimation; 0.492105s wall, 0.562500s user + 0.031250s system = 0.593750s CPU (120.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20729 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.959796s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000373241
+PHY-3002 : Step(249): len = 684334, overlap = 107.812
+PHY-3002 : Step(250): len = 684455, overlap = 107.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000746481
+PHY-3002 : Step(251): len = 684723, overlap = 107.594
+PHY-3002 : Step(252): len = 685299, overlap = 106.719
+PHY-3001 : Final: Len = 685299, Over = 106.719
+PHY-3001 : End incremental placement; 5.287005s wall, 5.484375s user + 0.234375s system = 5.718750s CPU (108.2%)
+
+OPT-1001 : Total overflow 427.94 peak overflow 2.97
+OPT-1001 : End high-fanout net optimization; 8.622950s wall, 9.437500s user + 0.250000s system = 9.687500s CPU (112.3%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 712, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17035/20907.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 774504, over cnt = 3017(8%), over = 10262, worst = 24
+PHY-1002 : len = 819160, over cnt = 2235(6%), over = 6034, worst = 22
+PHY-1002 : len = 863296, over cnt = 1066(3%), over = 2622, worst = 21
+PHY-1002 : len = 896960, over cnt = 184(0%), over = 376, worst = 14
+PHY-1002 : len = 903864, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.011140s wall, 2.718750s user + 0.031250s system = 2.750000s CPU (136.7%)
+
+PHY-1001 : Congestion index: top1 = 59.22, top5 = 51.76, top10 = 47.97, top15 = 45.49.
+OPT-1001 : End congestion update; 2.310288s wall, 3.015625s user + 0.031250s system = 3.046875s CPU (131.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20729 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.890003s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.1%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 117 cells processed and 14800 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 42 cells processed and 4900 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 14 cells processed and 750 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 700 slack improved
+OPT-1001 : End bottleneck based optimization; 3.635642s wall, 4.343750s user + 0.031250s system = 4.375000s CPU (120.3%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 697, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17085/20912.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904384, over cnt = 102(0%), over = 131, worst = 5
+PHY-1002 : len = 903992, over cnt = 49(0%), over = 52, worst = 2
+PHY-1002 : len = 904240, over cnt = 14(0%), over = 15, worst = 2
+PHY-1002 : len = 904312, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 904464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.794555s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (104.2%)
+
+PHY-1001 : Congestion index: top1 = 58.84, top5 = 51.67, top10 = 47.87, top15 = 45.42.
+OPT-1001 : End congestion update; 1.113785s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20734 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.914950s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (100.8%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 4150 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.152947s wall, 2.156250s user + 0.031250s system = 2.187500s CPU (101.6%)
+
+OPT-1001 : Current memory(MB): used = 701, reserve = 696, peak = 735.
+OPT-1001 : End physical optimization; 16.233818s wall, 17.796875s user + 0.375000s system = 18.171875s CPU (111.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7756 LUT to BLE ...
+SYN-4008 : Packed 7756 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6208 remaining SEQ's ...
+SYN-4005 : Packed 4023 SEQ with LUT/SLICE
+SYN-4006 : 909 single LUT's are left
+SYN-4006 : 2185 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9941/13728 primitive instances ...
+PHY-3001 : End packing; 1.809094s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6712 instances
+RUN-1001 : 3282 mslices, 3282 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17901 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10045 nets have 2 pins
+RUN-1001 : 6485 nets have [3 - 5] pins
+RUN-1001 : 732 nets have [6 - 10] pins
+RUN-1001 : 303 nets have [11 - 20] pins
+RUN-1001 : 304 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6710 instances, 6564 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3574 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 697892, Over = 253.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7625/17901.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 850296, over cnt = 1965(5%), over = 3165, worst = 9
+PHY-1002 : len = 857720, over cnt = 1252(3%), over = 1818, worst = 9
+PHY-1002 : len = 876376, over cnt = 238(0%), over = 289, worst = 4
+PHY-1002 : len = 880776, over cnt = 31(0%), over = 31, worst = 1
+PHY-1002 : len = 881944, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.951940s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (140.1%)
+
+PHY-1001 : Congestion index: top1 = 59.48, top5 = 51.72, top10 = 47.68, top15 = 45.02.
+PHY-3001 : End congestion estimation; 2.391615s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (132.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71567, tnet num: 17723, tinst num: 6710, tnode num: 94072, tedge num: 118988.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.794704s wall, 1.734375s user + 0.046875s system = 1.781250s CPU (99.3%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 614 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.720532s wall, 2.640625s user + 0.062500s system = 2.703125s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.52777e-05
+PHY-3002 : Step(253): len = 685669, overlap = 250.5
+PHY-3002 : Step(254): len = 678553, overlap = 247.5
+PHY-3002 : Step(255): len = 673721, overlap = 250.25
+PHY-3002 : Step(256): len = 669753, overlap = 255.75
+PHY-3002 : Step(257): len = 666463, overlap = 265.5
+PHY-3002 : Step(258): len = 663715, overlap = 266.25
+PHY-3002 : Step(259): len = 661316, overlap = 267.25
+PHY-3002 : Step(260): len = 659368, overlap = 270
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000110555
+PHY-3002 : Step(261): len = 663534, overlap = 254.25
+PHY-3002 : Step(262): len = 667431, overlap = 245.5
+PHY-3002 : Step(263): len = 666802, overlap = 242
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000221111
+PHY-3002 : Step(264): len = 676270, overlap = 237.75
+PHY-3002 : Step(265): len = 682034, overlap = 228.5
+PHY-3002 : Step(266): len = 680195, overlap = 229.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.387641s wall, 0.343750s user + 0.546875s system = 0.890625s CPU (229.8%)
+
+PHY-3001 : Trial Legalized: Len = 765592
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 805/17901.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 877600, over cnt = 2632(7%), over = 4371, worst = 8
+PHY-1002 : len = 893480, over cnt = 1643(4%), over = 2374, worst = 7
+PHY-1002 : len = 906216, over cnt = 965(2%), over = 1390, worst = 5
+PHY-1002 : len = 920328, over cnt = 371(1%), over = 547, worst = 4
+PHY-1002 : len = 927872, over cnt = 80(0%), over = 121, worst = 4
+PHY-1001 : End global iterations; 2.826701s wall, 4.250000s user + 0.015625s system = 4.265625s CPU (150.9%)
+
+PHY-1001 : Congestion index: top1 = 54.38, top5 = 49.58, top10 = 46.87, top15 = 44.98.
+PHY-3001 : End congestion estimation; 3.365964s wall, 4.781250s user + 0.015625s system = 4.796875s CPU (142.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.006349s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000167994
+PHY-3002 : Step(267): len = 737128, overlap = 39.5
+PHY-3002 : Step(268): len = 721421, overlap = 60.75
+PHY-3002 : Step(269): len = 709448, overlap = 81.75
+PHY-3002 : Step(270): len = 701553, overlap = 105.75
+PHY-3002 : Step(271): len = 694729, overlap = 136.75
+PHY-3002 : Step(272): len = 691614, overlap = 156.25
+PHY-3002 : Step(273): len = 689513, overlap = 162.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000335988
+PHY-3002 : Step(274): len = 693586, overlap = 157.75
+PHY-3002 : Step(275): len = 697990, overlap = 148.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000671975
+PHY-3002 : Step(276): len = 703172, overlap = 142.5
+PHY-3002 : Step(277): len = 710786, overlap = 134.75
+PHY-3002 : Step(278): len = 711484, overlap = 137
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.039132s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (79.9%)
+
+PHY-3001 : Legalized: Len = 740668, Over = 0
+PHY-3001 : Spreading special nets. 451 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.133227s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.6%)
+
+PHY-3001 : 671 instances has been re-located, deltaX = 208, deltaY = 379, maxDist = 2.
+PHY-3001 : Final: Len = 750724, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71567, tnet num: 17723, tinst num: 6713, tnode num: 94072, tedge num: 118988.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.019229s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (99.8%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 642 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3687/17901.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 877456, over cnt = 2432(6%), over = 3916, worst = 6
+PHY-1002 : len = 890336, over cnt = 1467(4%), over = 2132, worst = 6
+PHY-1002 : len = 905888, over cnt = 624(1%), over = 901, worst = 6
+PHY-1002 : len = 916864, over cnt = 137(0%), over = 202, worst = 5
+PHY-1002 : len = 920336, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 1.990501s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (146.0%)
+
+PHY-1001 : Congestion index: top1 = 54.35, top5 = 48.86, top10 = 45.90, top15 = 43.97.
+PHY-1001 : End incremental global routing; 2.392208s wall, 3.296875s user + 0.031250s system = 3.328125s CPU (139.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.200169s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (98.9%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6619 has valid locations, 37 needs to be replaced
+PHY-3001 : design contains 6744 instances, 6595 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3654 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 755730
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16301/17947.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928024, over cnt = 139(0%), over = 158, worst = 4
+PHY-1002 : len = 928120, over cnt = 59(0%), over = 63, worst = 2
+PHY-1002 : len = 928512, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 928712, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 928872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.905789s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 54.76, top5 = 49.12, top10 = 46.17, top15 = 44.22.
+PHY-3001 : End congestion estimation; 1.250661s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (107.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71929, tnet num: 17769, tinst num: 6744, tnode num: 94530, tedge num: 119494.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.020017s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (99.8%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 660 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17769 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.956228s wall, 2.921875s user + 0.031250s system = 2.953125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(279): len = 754882, overlap = 0
+PHY-3002 : Step(280): len = 754458, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16304/17947.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926952, over cnt = 91(0%), over = 105, worst = 4
+PHY-1002 : len = 927056, over cnt = 51(0%), over = 54, worst = 2
+PHY-1002 : len = 927432, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 927608, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 927688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.871167s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (107.6%)
+
+PHY-1001 : Congestion index: top1 = 54.46, top5 = 49.03, top10 = 46.08, top15 = 44.16.
+PHY-3001 : End congestion estimation; 1.203961s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (105.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17769 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.269285s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000662955
+PHY-3002 : Step(281): len = 754321, overlap = 2
+PHY-3002 : Step(282): len = 754356, overlap = 2.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00132591
+PHY-3002 : Step(283): len = 754446, overlap = 2.25
+PHY-3002 : Step(284): len = 754552, overlap = 2
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00263735
+PHY-3002 : Step(285): len = 754910, overlap = 2.5
+PHY-3002 : Step(286): len = 755085, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005711s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (273.6%)
+
+PHY-3001 : Legalized: Len = 755213, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062441s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 1, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 755345, Over = 0
+PHY-3001 : End incremental placement; 7.269391s wall, 7.609375s user + 0.296875s system = 7.906250s CPU (108.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.400925s wall, 12.640625s user + 0.328125s system = 12.968750s CPU (113.8%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 733, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16242/17947.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928400, over cnt = 139(0%), over = 164, worst = 4
+PHY-1002 : len = 928664, over cnt = 51(0%), over = 56, worst = 3
+PHY-1002 : len = 929200, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 929280, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 929424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.875552s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (110.6%)
+
+PHY-1001 : Congestion index: top1 = 54.16, top5 = 49.08, top10 = 46.07, top15 = 44.11.
+OPT-1001 : End congestion update; 1.220981s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (107.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17769 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.788295s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (101.1%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6656 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6744 instances, 6595 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3654 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 763197, Over = 0
+PHY-3001 : Spreading special nets. 35 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070000s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.6%)
+
+PHY-3001 : 50 instances has been re-located, deltaX = 31, deltaY = 34, maxDist = 3.
+PHY-3001 : Final: Len = 764741, Over = 0
+PHY-3001 : End incremental legalization; 0.424225s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 60 cells processed and 20850 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6656 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6744 instances, 6595 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3654 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 763989, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065896s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.8%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 12, deltaY = 18, maxDist = 4.
+PHY-3001 : Final: Len = 764705, Over = 0
+PHY-3001 : End incremental legalization; 0.469352s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (109.9%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 26 cells processed and 2058 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 765622, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.084399s wall, 0.062500s user + 0.015625s system = 0.078125s CPU (92.6%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 6, deltaY = 4, maxDist = 3.
+PHY-3001 : Final: Len = 765532, Over = 0
+PHY-3001 : End incremental legalization; 0.518495s wall, 0.515625s user + 0.031250s system = 0.546875s CPU (105.5%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 8 cells processed and 1073 slack improved
+OPT-1001 : End bottleneck based optimization; 4.012735s wall, 4.312500s user + 0.062500s system = 4.375000s CPU (109.0%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 733, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15910/17950.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 939808, over cnt = 169(0%), over = 213, worst = 3
+PHY-1002 : len = 940128, over cnt = 68(0%), over = 70, worst = 2
+PHY-1002 : len = 940608, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 940856, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 940856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.006268s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (104.0%)
+
+PHY-1001 : Congestion index: top1 = 53.92, top5 = 48.86, top10 = 45.96, top15 = 44.11.
+OPT-1001 : End congestion update; 1.366685s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (101.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.825383s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.3%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 765576, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064219s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.3%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 3, deltaY = 5, maxDist = 4.
+PHY-3001 : Final: Len = 765702, Over = 0
+PHY-3001 : End incremental legalization; 0.454094s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.8%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 12 cells processed and 1496 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.779544s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (101.2%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 733, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.763487s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (100.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16299/17950.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 941104, over cnt = 22(0%), over = 26, worst = 3
+PHY-1002 : len = 941200, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 941256, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 941272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.634943s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (100.9%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.83, top10 = 45.92, top15 = 44.09.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.755085s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 71 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.448276
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 71ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 765702, Over = 0
+PHY-3001 : End spreading; 0.058619s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.6%)
+
+PHY-3001 : Final: Len = 765702, Over = 0
+PHY-3001 : End incremental legalization; 0.440346s wall, 0.406250s user + 0.031250s system = 0.437500s CPU (99.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.761957s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.5%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16332/17950.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 941272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.131348s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.1%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.83, top10 = 45.92, top15 = 44.09.
+OPT-1001 : End congestion update; 0.461521s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.781568s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.0%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 765662, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065319s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.7%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 765702, Over = 0
+PHY-3001 : End incremental legalization; 0.448381s wall, 0.593750s user + 0.031250s system = 0.625000s CPU (139.4%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.811906s wall, 1.953125s user + 0.031250s system = 1.984375s CPU (109.5%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 733, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16332/17950.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 941272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.142229s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.9%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.83, top10 = 45.92, top15 = 44.09.
+OPT-1001 : End congestion update; 0.472629s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.800469s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.6%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 765662, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060371s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.5%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 765702, Over = 0
+PHY-3001 : End incremental legalization; 0.400063s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.6%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6664 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6752 instances, 6603 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 493 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 765662, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.071291s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (109.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 765702, Over = 0
+PHY-3001 : End incremental legalization; 0.443673s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.1%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.421573s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 733, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.770396s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (97.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 733, reserve = 733, peak = 737.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.780994s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (96.0%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16332/17950.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 941272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139560s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.8%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.83, top10 = 45.92, top15 = 44.09.
+RUN-1001 : End congestion update; 0.483296s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.2%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.267899s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (97.4%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 733, peak = 737.
+OPT-1001 : End physical optimization; 30.612817s wall, 32.187500s user + 0.500000s system = 32.687500s CPU (106.8%)
+
+RUN-1003 : finish command "place" in 79.152602s wall, 110.781250s user + 6.796875s system = 117.578125s CPU (148.5%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 643 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.848807s wall, 3.156250s user + 0.000000s system = 3.156250s CPU (170.7%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 644 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6754 instances
+RUN-1001 : 3301 mslices, 3302 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17950 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10040 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 741 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 315 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72007, tnet num: 17772, tinst num: 6752, tnode num: 94638, tedge num: 119614.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.769313s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (100.7%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 658 MB, peak memory is 737 MB
+PHY-1001 : 3301 mslices, 3302 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874680, over cnt = 2680(7%), over = 4400, worst = 7
+PHY-1002 : len = 891632, over cnt = 1612(4%), over = 2316, worst = 7
+PHY-1002 : len = 910648, over cnt = 602(1%), over = 851, worst = 6
+PHY-1002 : len = 924456, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 924664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.589874s wall, 4.656250s user + 0.015625s system = 4.671875s CPU (130.1%)
+
+PHY-1001 : Congestion index: top1 = 53.56, top5 = 48.57, top10 = 45.72, top15 = 43.86.
+PHY-1001 : End global routing; 3.994116s wall, 5.046875s user + 0.015625s system = 5.062500s CPU (126.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 714, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 980, reserve = 984, peak = 980.
+PHY-1001 : End build detailed router design. 4.251446s wall, 4.218750s user + 0.031250s system = 4.250000s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271096, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.951325s wall, 5.953125s user + 0.000000s system = 5.953125s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271152, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.595475s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1015, reserve = 1019, peak = 1015.
+PHY-1001 : End phase 1; 6.565469s wall, 6.562500s user + 0.000000s system = 6.562500s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.32107e+06, over cnt = 1663(0%), over = 1668, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1033, peak = 1031.
+PHY-1001 : End initial routed; 38.401655s wall, 79.203125s user + 0.453125s system = 79.656250s CPU (207.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16873(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.821 | -0.821 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.437882s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1043, reserve = 1046, peak = 1043.
+PHY-1001 : End phase 2; 41.839607s wall, 82.640625s user + 0.453125s system = 83.093750s CPU (198.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.811ns STNS -0.811ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.154058s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.4%)
+
+PHY-1022 : len = 2.32107e+06, over cnt = 1664(0%), over = 1669, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.460079s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29213e+06, over cnt = 516(0%), over = 519, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.548457s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (191.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.29129e+06, over cnt = 123(0%), over = 123, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.625373s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (152.4%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.29163e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.451342s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (110.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.29177e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 4; 0.252033s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16873(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.811 | -0.811 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.430981s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 480 feed throughs used by 357 nets
+PHY-1001 : End commit to database; 2.346952s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1152, peak = 1146.
+PHY-1001 : End phase 3; 9.547156s wall, 11.296875s user + 0.031250s system = 11.328125s CPU (118.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.811ns STNS -0.811ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.162702s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.0%)
+
+PHY-1022 : len = 2.29177e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.457919s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (95.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.811ns, -0.811ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16873(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.811 | -0.811 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.415780s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 480 feed throughs used by 357 nets
+PHY-1001 : End commit to database; 3.281209s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1160, peak = 1154.
+PHY-1001 : End phase 4; 7.184191s wall, 7.171875s user + 0.000000s system = 7.171875s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.29177e+06
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1164, peak = 1157.
+PHY-1001 : End export database. 0.067857s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (115.1%)
+
+PHY-1001 : End detail routing; 69.881083s wall, 112.390625s user + 0.515625s system = 112.906250s CPU (161.6%)
+
+RUN-1003 : finish command "route" in 76.857209s wall, 120.406250s user + 0.546875s system = 120.953125s CPU (157.4%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1087 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10205 out of 19600 52.07%
+#reg 9562 out of 19600 48.79%
+#le 12355
+ #lut only 2793 out of 12355 22.61%
+ #reg only 2150 out of 12355 17.40%
+ #lut® 7412 out of 12355 59.99%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1789
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1406
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1309
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 965
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 134
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg48_syn_230.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg48_syn_203.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P15 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P39 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P32 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P118 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P106 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12355 |9178 |1027 |9596 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |527 |416 |23 |443 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |90 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |34 |34 |0 |15 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |10 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |757 |404 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |198 |121 |25 |151 |0 |0 |
+| u_gen_sp |gen_sp |251 |149 |71 |114 |0 |0 |
+| exdev_ctl_b |exdev_ctl |727 |369 |96 |543 |0 |0 |
+| u_ADconfig |AD_config |154 |117 |25 |111 |0 |0 |
+| u_gen_sp |gen_sp |265 |178 |71 |124 |0 |0 |
+| sampling_fe_a |sampling_fe |3034 |2490 |306 |2107 |25 |0 |
+| u0_soft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |181 |132 |17 |153 |0 |0 |
+| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_sort |sort |2820 |2357 |289 |1921 |25 |0 |
+| rddpram_ctl |rddpram_ctl |7 |2 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2346 |1956 |253 |1566 |22 |0 |
+| channelPart |channel_part_8478 |146 |143 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |56 |47 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1844 |1527 |197 |1170 |0 |0 |
+| adc_addr_gen |adc_addr_gen |209 |181 |27 |128 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |10 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |29 |26 |3 |19 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |19 |16 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| insert |insert |986 |697 |170 |684 |0 |0 |
+| ram_switch_state |ram_switch_state |649 |649 |0 |358 |0 |0 |
+| read_ram_i |read_ram |267 |209 |44 |191 |0 |0 |
+| read_ram_addr |read_ram_addr |220 |180 |40 |153 |0 |0 |
+| read_ram_data |read_ram_data |46 |29 |4 |37 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |314 |250 |36 |261 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3123 |2429 |349 |2109 |25 |1 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |187 |96 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_sort |sort_rev |2909 |2321 |332 |1924 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |0 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |0 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2445 |1948 |290 |1570 |22 |1 |
+| channelPart |channel_part_8478 |144 |136 |3 |137 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |41 |0 |1 |
+| ram_switch |ram_switch |1846 |1475 |197 |1150 |0 |0 |
+| adc_addr_gen |adc_addr_gen |209 |182 |27 |118 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |15 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| insert |insert |972 |630 |170 |677 |0 |0 |
+| ram_switch_state |ram_switch_state |665 |663 |0 |355 |0 |0 |
+| read_ram_i |read_ram_rev |370 |269 |81 |217 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |301 |218 |73 |163 |0 |0 |
+| read_ram_data |read_ram_data_rev |69 |51 |8 |54 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9978
+ #2 2 4237
+ #3 3 1698
+ #4 4 570
+ #5 5-10 784
+ #6 11-50 578
+ #7 51-100 9
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.062551s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (172.0%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1090 MB, peak memory is 1157 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72007, tnet num: 17772, tinst num: 6752, tnode num: 94638, tedge num: 119614.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.616916s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (99.5%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1093 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17772 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.481353s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (100.2%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1098 MB, peak memory is 1157 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6752
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17950, pip num: 169485
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 480
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3262 valid insts, and 471411 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.935593s wall, 67.078125s user + 0.125000s system = 67.203125s CPU (676.4%)
+
+RUN-1004 : used memory is 1247 MB, reserved memory is 1250 MB, peak memory is 1362 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_094538.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_095232.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_095232.log
new file mode 100644
index 0000000..1b9470b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_095232.log
@@ -0,0 +1,3288 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 09:52:32 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.346799s wall, 2.265625s user + 0.078125s system = 2.343750s CPU (99.9%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2951 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18102 instances
+RUN-0007 : 7652 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20679 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13190 nets have 2 pins
+RUN-1001 : 6454 nets have [3 - 5] pins
+RUN-1001 : 616 nets have [6 - 10] pins
+RUN-1001 : 180 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 798
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3627
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18100 instances, 7652 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6052 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84535, tnet num: 20501, tinst num: 18100, tnode num: 115269, tedge num: 134818.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.271569s wall, 1.234375s user + 0.046875s system = 1.281250s CPU (100.8%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 516 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.113706s wall, 2.062500s user + 0.062500s system = 2.125000s CPU (100.5%)
+
+PHY-3001 : Found 1247 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.12437e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18100.
+PHY-3001 : Level 1 #clusters 2047.
+PHY-3001 : End clustering; 0.129006s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (121.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32055e+06, overlap = 484.562
+PHY-3002 : Step(2): len = 1.2281e+06, overlap = 494.688
+PHY-3002 : Step(3): len = 886277, overlap = 588.031
+PHY-3002 : Step(4): len = 800942, overlap = 635.969
+PHY-3002 : Step(5): len = 625464, overlap = 795.344
+PHY-3002 : Step(6): len = 578197, overlap = 846.375
+PHY-3002 : Step(7): len = 478550, overlap = 945.531
+PHY-3002 : Step(8): len = 437944, overlap = 995.125
+PHY-3002 : Step(9): len = 389134, overlap = 1041.44
+PHY-3002 : Step(10): len = 362920, overlap = 1072.03
+PHY-3002 : Step(11): len = 320039, overlap = 1151.75
+PHY-3002 : Step(12): len = 297063, overlap = 1226.91
+PHY-3002 : Step(13): len = 269402, overlap = 1291.16
+PHY-3002 : Step(14): len = 246718, overlap = 1298.66
+PHY-3002 : Step(15): len = 223200, overlap = 1343.59
+PHY-3002 : Step(16): len = 208144, overlap = 1368.62
+PHY-3002 : Step(17): len = 188780, overlap = 1409.16
+PHY-3002 : Step(18): len = 176665, overlap = 1432.25
+PHY-3002 : Step(19): len = 159076, overlap = 1460.47
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.16373e-06
+PHY-3002 : Step(20): len = 163558, overlap = 1428.22
+PHY-3002 : Step(21): len = 207152, overlap = 1309.12
+PHY-3002 : Step(22): len = 214405, overlap = 1228.44
+PHY-3002 : Step(23): len = 216384, overlap = 1127.72
+PHY-3002 : Step(24): len = 208818, overlap = 1103.91
+PHY-3002 : Step(25): len = 206198, overlap = 1114.53
+PHY-3002 : Step(26): len = 200716, overlap = 1087.25
+PHY-3002 : Step(27): len = 198941, overlap = 1068.16
+PHY-3002 : Step(28): len = 193027, overlap = 1054.59
+PHY-3002 : Step(29): len = 190292, overlap = 1043.91
+PHY-3002 : Step(30): len = 186589, overlap = 1053.72
+PHY-3002 : Step(31): len = 185683, overlap = 1065.84
+PHY-3002 : Step(32): len = 183694, overlap = 1078.81
+PHY-3002 : Step(33): len = 182313, overlap = 1086.22
+PHY-3002 : Step(34): len = 181093, overlap = 1096.66
+PHY-3002 : Step(35): len = 180029, overlap = 1114.06
+PHY-3002 : Step(36): len = 178528, overlap = 1124.44
+PHY-3002 : Step(37): len = 177679, overlap = 1118.06
+PHY-3002 : Step(38): len = 176992, overlap = 1103.34
+PHY-3002 : Step(39): len = 174958, overlap = 1100.97
+PHY-3002 : Step(40): len = 173667, overlap = 1084.28
+PHY-3002 : Step(41): len = 172425, overlap = 1086.06
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.32745e-06
+PHY-3002 : Step(42): len = 174945, overlap = 1070.38
+PHY-3002 : Step(43): len = 185230, overlap = 1035.31
+PHY-3002 : Step(44): len = 190021, overlap = 1034
+PHY-3002 : Step(45): len = 194853, overlap = 1046.88
+PHY-3002 : Step(46): len = 196819, overlap = 1033.44
+PHY-3002 : Step(47): len = 198591, overlap = 992.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.6549e-06
+PHY-3002 : Step(48): len = 206972, overlap = 975.688
+PHY-3002 : Step(49): len = 230011, overlap = 914.875
+PHY-3002 : Step(50): len = 240222, overlap = 864.375
+PHY-3002 : Step(51): len = 247037, overlap = 835.969
+PHY-3002 : Step(52): len = 248039, overlap = 801.031
+PHY-3002 : Step(53): len = 248628, overlap = 775.688
+PHY-3002 : Step(54): len = 247787, overlap = 777.375
+PHY-3002 : Step(55): len = 245448, overlap = 776.188
+PHY-3002 : Step(56): len = 244806, overlap = 781.906
+PHY-3002 : Step(57): len = 244878, overlap = 764.031
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.3098e-06
+PHY-3002 : Step(58): len = 260260, overlap = 717.188
+PHY-3002 : Step(59): len = 275128, overlap = 656.188
+PHY-3002 : Step(60): len = 280317, overlap = 588.75
+PHY-3002 : Step(61): len = 286273, overlap = 571.188
+PHY-3002 : Step(62): len = 287673, overlap = 565.75
+PHY-3002 : Step(63): len = 288488, overlap = 523.719
+PHY-3002 : Step(64): len = 288070, overlap = 520.938
+PHY-3002 : Step(65): len = 287424, overlap = 520.219
+PHY-3002 : Step(66): len = 287576, overlap = 516.062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.86196e-05
+PHY-3002 : Step(67): len = 303883, overlap = 470.875
+PHY-3002 : Step(68): len = 316445, overlap = 439.375
+PHY-3002 : Step(69): len = 319423, overlap = 410.656
+PHY-3002 : Step(70): len = 325278, overlap = 375.312
+PHY-3002 : Step(71): len = 327234, overlap = 394.094
+PHY-3002 : Step(72): len = 329689, overlap = 391
+PHY-3002 : Step(73): len = 327745, overlap = 394.219
+PHY-3002 : Step(74): len = 328670, overlap = 405.312
+PHY-3002 : Step(75): len = 329328, overlap = 398.875
+PHY-3002 : Step(76): len = 329639, overlap = 399.406
+PHY-3002 : Step(77): len = 328186, overlap = 392.375
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.72392e-05
+PHY-3002 : Step(78): len = 343858, overlap = 384.281
+PHY-3002 : Step(79): len = 356117, overlap = 367.406
+PHY-3002 : Step(80): len = 359922, overlap = 336.188
+PHY-3002 : Step(81): len = 362176, overlap = 332.219
+PHY-3002 : Step(82): len = 364358, overlap = 325.281
+PHY-3002 : Step(83): len = 368308, overlap = 315.156
+PHY-3002 : Step(84): len = 367249, overlap = 323.75
+PHY-3002 : Step(85): len = 368153, overlap = 306.75
+PHY-3002 : Step(86): len = 370375, overlap = 297.781
+PHY-3002 : Step(87): len = 372937, overlap = 293.625
+PHY-3002 : Step(88): len = 373507, overlap = 287.156
+PHY-3002 : Step(89): len = 376560, overlap = 266.625
+PHY-3002 : Step(90): len = 376615, overlap = 250.031
+PHY-3002 : Step(91): len = 377494, overlap = 251.281
+PHY-3002 : Step(92): len = 375602, overlap = 254.812
+PHY-3002 : Step(93): len = 375700, overlap = 266.562
+PHY-3002 : Step(94): len = 375700, overlap = 271.344
+PHY-3002 : Step(95): len = 373903, overlap = 275.406
+PHY-3002 : Step(96): len = 372360, overlap = 279.812
+PHY-3002 : Step(97): len = 372111, overlap = 289.469
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.44784e-05
+PHY-3002 : Step(98): len = 387919, overlap = 270.062
+PHY-3002 : Step(99): len = 400052, overlap = 255.812
+PHY-3002 : Step(100): len = 400196, overlap = 225.344
+PHY-3002 : Step(101): len = 401020, overlap = 227.375
+PHY-3002 : Step(102): len = 404169, overlap = 218.969
+PHY-3002 : Step(103): len = 406435, overlap = 226.625
+PHY-3002 : Step(104): len = 404724, overlap = 225.344
+PHY-3002 : Step(105): len = 405887, overlap = 223.75
+PHY-3002 : Step(106): len = 406317, overlap = 225.594
+PHY-3002 : Step(107): len = 407372, overlap = 230.156
+PHY-3002 : Step(108): len = 406738, overlap = 220.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000145268
+PHY-3002 : Step(109): len = 420393, overlap = 218.25
+PHY-3002 : Step(110): len = 429581, overlap = 216
+PHY-3002 : Step(111): len = 429625, overlap = 205.625
+PHY-3002 : Step(112): len = 431282, overlap = 203.938
+PHY-3002 : Step(113): len = 433467, overlap = 215.5
+PHY-3002 : Step(114): len = 435858, overlap = 210.469
+PHY-3002 : Step(115): len = 434802, overlap = 206.375
+PHY-3002 : Step(116): len = 436768, overlap = 204.875
+PHY-3002 : Step(117): len = 439403, overlap = 207.188
+PHY-3002 : Step(118): len = 441893, overlap = 205.469
+PHY-3002 : Step(119): len = 439914, overlap = 202.25
+PHY-3002 : Step(120): len = 440357, overlap = 209.031
+PHY-3002 : Step(121): len = 442184, overlap = 207.094
+PHY-3002 : Step(122): len = 443390, overlap = 211.969
+PHY-3002 : Step(123): len = 441297, overlap = 212.625
+PHY-3002 : Step(124): len = 441230, overlap = 211.344
+PHY-3002 : Step(125): len = 442568, overlap = 214.031
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000290535
+PHY-3002 : Step(126): len = 454960, overlap = 206.25
+PHY-3002 : Step(127): len = 465186, overlap = 212.25
+PHY-3002 : Step(128): len = 467424, overlap = 216.812
+PHY-3002 : Step(129): len = 469566, overlap = 204.031
+PHY-3002 : Step(130): len = 471770, overlap = 209.094
+PHY-3002 : Step(131): len = 475845, overlap = 204.438
+PHY-3002 : Step(132): len = 475567, overlap = 205.094
+PHY-3002 : Step(133): len = 476778, overlap = 206.531
+PHY-3002 : Step(134): len = 478468, overlap = 210.438
+PHY-3002 : Step(135): len = 480488, overlap = 212.312
+PHY-3002 : Step(136): len = 479627, overlap = 195.438
+PHY-3002 : Step(137): len = 479346, overlap = 194.125
+PHY-3002 : Step(138): len = 479405, overlap = 194.312
+PHY-3002 : Step(139): len = 479946, overlap = 192.344
+PHY-3002 : Step(140): len = 478689, overlap = 179.5
+PHY-3002 : Step(141): len = 478398, overlap = 173.219
+PHY-3002 : Step(142): len = 478878, overlap = 181.219
+PHY-3002 : Step(143): len = 479873, overlap = 183.531
+PHY-3002 : Step(144): len = 478911, overlap = 185.406
+PHY-3002 : Step(145): len = 479176, overlap = 180.969
+PHY-3002 : Step(146): len = 479143, overlap = 183.656
+PHY-3002 : Step(147): len = 479311, overlap = 187.812
+PHY-3002 : Step(148): len = 478406, overlap = 192.75
+PHY-3002 : Step(149): len = 478872, overlap = 189.188
+PHY-3002 : Step(150): len = 479265, overlap = 180.812
+PHY-3002 : Step(151): len = 479571, overlap = 181.531
+PHY-3002 : Step(152): len = 478968, overlap = 186.25
+PHY-3002 : Step(153): len = 479064, overlap = 186.469
+PHY-3002 : Step(154): len = 479607, overlap = 182.625
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000555082
+PHY-3002 : Step(155): len = 487014, overlap = 184.5
+PHY-3002 : Step(156): len = 495954, overlap = 174.125
+PHY-3002 : Step(157): len = 496012, overlap = 167.375
+PHY-3002 : Step(158): len = 496226, overlap = 169.219
+PHY-3002 : Step(159): len = 497996, overlap = 170.062
+PHY-3002 : Step(160): len = 499244, overlap = 168.031
+PHY-3002 : Step(161): len = 498310, overlap = 161.438
+PHY-3002 : Step(162): len = 498434, overlap = 166.344
+PHY-3002 : Step(163): len = 500808, overlap = 164.75
+PHY-3002 : Step(164): len = 502439, overlap = 164.031
+PHY-3002 : Step(165): len = 500929, overlap = 170.344
+PHY-3002 : Step(166): len = 500699, overlap = 170.531
+PHY-3002 : Step(167): len = 501774, overlap = 167.688
+PHY-3002 : Step(168): len = 502732, overlap = 166.812
+PHY-3002 : Step(169): len = 502015, overlap = 167.656
+PHY-3002 : Step(170): len = 502259, overlap = 170.938
+PHY-3002 : Step(171): len = 503804, overlap = 172.312
+PHY-3002 : Step(172): len = 504495, overlap = 171.062
+PHY-3002 : Step(173): len = 503662, overlap = 170.25
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000983845
+PHY-3002 : Step(174): len = 508000, overlap = 168.281
+PHY-3002 : Step(175): len = 513606, overlap = 161.969
+PHY-3002 : Step(176): len = 513934, overlap = 158.531
+PHY-3002 : Step(177): len = 514517, overlap = 155.562
+PHY-3002 : Step(178): len = 517247, overlap = 159.25
+PHY-3002 : Step(179): len = 519236, overlap = 154.844
+PHY-3002 : Step(180): len = 518908, overlap = 156.031
+PHY-3002 : Step(181): len = 519280, overlap = 156.844
+PHY-3002 : Step(182): len = 521024, overlap = 154.938
+PHY-3002 : Step(183): len = 521626, overlap = 156.594
+PHY-3002 : Step(184): len = 520735, overlap = 155.281
+PHY-3002 : Step(185): len = 520589, overlap = 156.844
+PHY-3002 : Step(186): len = 521271, overlap = 154.5
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00178944
+PHY-3002 : Step(187): len = 524777, overlap = 156.312
+PHY-3002 : Step(188): len = 533149, overlap = 155.375
+PHY-3002 : Step(189): len = 537180, overlap = 158.094
+PHY-3002 : Step(190): len = 541386, overlap = 148.156
+PHY-3002 : Step(191): len = 544657, overlap = 146.625
+PHY-3002 : Step(192): len = 546860, overlap = 147.312
+PHY-3002 : Step(193): len = 547214, overlap = 141.094
+PHY-3002 : Step(194): len = 547719, overlap = 136.844
+PHY-3002 : Step(195): len = 548793, overlap = 136.438
+PHY-3002 : Step(196): len = 549388, overlap = 137.844
+PHY-3002 : Step(197): len = 549398, overlap = 140.094
+PHY-3002 : Step(198): len = 549459, overlap = 139.656
+PHY-3002 : Step(199): len = 549720, overlap = 139.75
+PHY-3002 : Step(200): len = 549794, overlap = 138.625
+PHY-3002 : Step(201): len = 549635, overlap = 139.906
+PHY-3002 : Step(202): len = 549605, overlap = 138.656
+PHY-3002 : Step(203): len = 549730, overlap = 135.688
+PHY-3002 : Step(204): len = 549685, overlap = 137.25
+PHY-3002 : Step(205): len = 549553, overlap = 137.969
+PHY-3002 : Step(206): len = 549978, overlap = 143.094
+PHY-3002 : Step(207): len = 550431, overlap = 139.031
+PHY-3002 : Step(208): len = 550588, overlap = 141.094
+PHY-3002 : Step(209): len = 550400, overlap = 142.625
+PHY-3002 : Step(210): len = 550388, overlap = 145.906
+PHY-3002 : Step(211): len = 550426, overlap = 138.938
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00308123
+PHY-3002 : Step(212): len = 552041, overlap = 144.438
+PHY-3002 : Step(213): len = 555876, overlap = 148.344
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013405s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (116.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738664, over cnt = 1630(4%), over = 7564, worst = 40
+PHY-1001 : End global iterations; 0.841712s wall, 1.140625s user + 0.062500s system = 1.203125s CPU (142.9%)
+
+PHY-1001 : Congestion index: top1 = 86.06, top5 = 63.68, top10 = 53.87, top15 = 48.14.
+PHY-3001 : End congestion estimation; 1.104995s wall, 1.406250s user + 0.062500s system = 1.468750s CPU (132.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.981521s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164242
+PHY-3002 : Step(214): len = 664123, overlap = 105.406
+PHY-3002 : Step(215): len = 662767, overlap = 101
+PHY-3002 : Step(216): len = 657618, overlap = 100.75
+PHY-3002 : Step(217): len = 653087, overlap = 93.9688
+PHY-3002 : Step(218): len = 649500, overlap = 90.2812
+PHY-3002 : Step(219): len = 648259, overlap = 80.9062
+PHY-3002 : Step(220): len = 648327, overlap = 72.0312
+PHY-3002 : Step(221): len = 647400, overlap = 55.0938
+PHY-3002 : Step(222): len = 647216, overlap = 47.125
+PHY-3002 : Step(223): len = 643980, overlap = 48.1562
+PHY-3002 : Step(224): len = 640075, overlap = 49.0625
+PHY-3002 : Step(225): len = 636663, overlap = 53.5
+PHY-3002 : Step(226): len = 634478, overlap = 52.5312
+PHY-3002 : Step(227): len = 631968, overlap = 55.375
+PHY-3002 : Step(228): len = 630350, overlap = 56.9062
+PHY-3002 : Step(229): len = 630830, overlap = 52.8125
+PHY-3002 : Step(230): len = 630460, overlap = 45.1562
+PHY-3002 : Step(231): len = 628617, overlap = 44.4375
+PHY-3002 : Step(232): len = 626471, overlap = 39.0625
+PHY-3002 : Step(233): len = 626144, overlap = 37.1875
+PHY-3002 : Step(234): len = 625495, overlap = 37
+PHY-3002 : Step(235): len = 624561, overlap = 37.0312
+PHY-3002 : Step(236): len = 623933, overlap = 36.2812
+PHY-3002 : Step(237): len = 624147, overlap = 36.3438
+PHY-3002 : Step(238): len = 622229, overlap = 40.1875
+PHY-3002 : Step(239): len = 621527, overlap = 40.5938
+PHY-3002 : Step(240): len = 619595, overlap = 41.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328484
+PHY-3002 : Step(241): len = 622911, overlap = 40.7812
+PHY-3002 : Step(242): len = 629450, overlap = 37.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000581853
+PHY-3002 : Step(243): len = 632368, overlap = 35.6562
+PHY-3002 : Step(244): len = 650684, overlap = 27.8438
+PHY-3002 : Step(245): len = 664020, overlap = 25.0938
+PHY-3002 : Step(246): len = 662482, overlap = 25.8125
+PHY-3002 : Step(247): len = 660184, overlap = 26.7812
+PHY-3002 : Step(248): len = 658672, overlap = 27.9688
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 58/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744984, over cnt = 2745(7%), over = 12282, worst = 52
+PHY-1001 : End global iterations; 1.854661s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (134.0%)
+
+PHY-1001 : Congestion index: top1 = 88.04, top5 = 68.45, top10 = 59.50, top15 = 54.10.
+PHY-3001 : End congestion estimation; 2.144705s wall, 2.750000s user + 0.015625s system = 2.765625s CPU (129.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.957151s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000115161
+PHY-3002 : Step(249): len = 652893, overlap = 229.938
+PHY-3002 : Step(250): len = 653455, overlap = 168.781
+PHY-3002 : Step(251): len = 644741, overlap = 158.75
+PHY-3002 : Step(252): len = 638622, overlap = 149.125
+PHY-3002 : Step(253): len = 632705, overlap = 136.281
+PHY-3002 : Step(254): len = 630061, overlap = 134.125
+PHY-3002 : Step(255): len = 625936, overlap = 130.375
+PHY-3002 : Step(256): len = 622826, overlap = 123.469
+PHY-3002 : Step(257): len = 620366, overlap = 123.656
+PHY-3002 : Step(258): len = 616951, overlap = 125.312
+PHY-3002 : Step(259): len = 614701, overlap = 129.906
+PHY-3002 : Step(260): len = 611953, overlap = 130.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000230321
+PHY-3002 : Step(261): len = 612957, overlap = 126.281
+PHY-3002 : Step(262): len = 615310, overlap = 121.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00041086
+PHY-3002 : Step(263): len = 617508, overlap = 117.344
+PHY-3002 : Step(264): len = 626941, overlap = 109.969
+PHY-3002 : Step(265): len = 632450, overlap = 101
+PHY-3002 : Step(266): len = 629929, overlap = 101.438
+PHY-3002 : Step(267): len = 629154, overlap = 99.375
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84535, tnet num: 20501, tinst num: 18100, tnode num: 115269, tedge num: 134818.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.553988s wall, 1.500000s user + 0.046875s system = 1.546875s CPU (99.5%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 566 MB, peak memory is 712 MB
+OPT-1001 : Total overflow 406.16 peak overflow 2.44
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 808/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725272, over cnt = 3025(8%), over = 11076, worst = 25
+PHY-1001 : End global iterations; 1.417343s wall, 2.140625s user + 0.031250s system = 2.171875s CPU (153.2%)
+
+PHY-1001 : Congestion index: top1 = 73.79, top5 = 59.50, top10 = 52.83, top15 = 48.61.
+PHY-1001 : End incremental global routing; 1.780988s wall, 2.500000s user + 0.031250s system = 2.531250s CPU (142.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.977179s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (100.7%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17968 has valid locations, 322 needs to be replaced
+PHY-3001 : design contains 18375 instances, 7748 luts, 9406 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6180 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 653301
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16955/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 739968, over cnt = 3025(8%), over = 11100, worst = 25
+PHY-1001 : End global iterations; 0.259766s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (168.4%)
+
+PHY-1001 : Congestion index: top1 = 73.66, top5 = 59.49, top10 = 52.95, top15 = 48.83.
+PHY-3001 : End congestion estimation; 0.538175s wall, 0.687500s user + 0.031250s system = 0.718750s CPU (133.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85643, tnet num: 20776, tinst num: 18375, tnode num: 116935, tedge num: 136484.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.584113s wall, 1.500000s user + 0.078125s system = 1.578125s CPU (99.6%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 616 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.609452s wall, 2.531250s user + 0.078125s system = 2.609375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(268): len = 652215, overlap = 0.6875
+PHY-3002 : Step(269): len = 651836, overlap = 0.5
+PHY-3002 : Step(270): len = 651526, overlap = 0.625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17067/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737056, over cnt = 3010(8%), over = 11181, worst = 25
+PHY-1001 : End global iterations; 0.193556s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (113.0%)
+
+PHY-1001 : Congestion index: top1 = 75.26, top5 = 60.25, top10 = 53.39, top15 = 49.17.
+PHY-3001 : End congestion estimation; 0.472622s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (105.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.015025s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000405864
+PHY-3002 : Step(271): len = 651305, overlap = 102.531
+PHY-3002 : Step(272): len = 651498, overlap = 101.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000811728
+PHY-3002 : Step(273): len = 651724, overlap = 101.562
+PHY-3002 : Step(274): len = 652385, overlap = 101.656
+PHY-3001 : Final: Len = 652385, Over = 101.656
+PHY-3001 : End incremental placement; 5.355730s wall, 5.515625s user + 0.250000s system = 5.765625s CPU (107.7%)
+
+OPT-1001 : Total overflow 411.00 peak overflow 2.44
+OPT-1001 : End high-fanout net optimization; 8.733678s wall, 9.687500s user + 0.312500s system = 10.000000s CPU (114.5%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 712, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16991/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740008, over cnt = 2967(8%), over = 10176, worst = 25
+PHY-1002 : len = 789176, over cnt = 2183(6%), over = 5794, worst = 22
+PHY-1002 : len = 825536, over cnt = 1138(3%), over = 2907, worst = 18
+PHY-1002 : len = 855968, over cnt = 402(1%), over = 957, worst = 15
+PHY-1002 : len = 873832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.932821s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (135.8%)
+
+PHY-1001 : Congestion index: top1 = 59.05, top5 = 51.57, top10 = 48.02, top15 = 45.66.
+OPT-1001 : End congestion update; 2.243664s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (131.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.875103s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (100.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 122 cells processed and 16800 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 47 cells processed and 3816 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 950 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 546 slack improved
+OPT-1001 : End bottleneck based optimization; 3.572091s wall, 4.265625s user + 0.015625s system = 4.281250s CPU (119.9%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 698, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17004/20960.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 873200, over cnt = 92(0%), over = 133, worst = 6
+PHY-1002 : len = 872760, over cnt = 47(0%), over = 55, worst = 3
+PHY-1002 : len = 873200, over cnt = 12(0%), over = 13, worst = 2
+PHY-1002 : len = 873368, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 873432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.810113s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.3%)
+
+PHY-1001 : Congestion index: top1 = 58.19, top5 = 51.38, top10 = 47.83, top15 = 45.53.
+OPT-1001 : End congestion update; 1.111257s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20782 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.848308s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.5%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 19 cells processed and 2400 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.092032s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 707, reserve = 703, peak = 733.
+OPT-1001 : End physical optimization; 16.276503s wall, 17.937500s user + 0.406250s system = 18.343750s CPU (112.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7748 LUT to BLE ...
+SYN-4008 : Packed 7748 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6264 remaining SEQ's ...
+SYN-4005 : Packed 3844 SEQ with LUT/SLICE
+SYN-4006 : 1037 single LUT's are left
+SYN-4006 : 2420 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10168/13955 primitive instances ...
+PHY-3001 : End packing; 1.808792s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6813 instances
+RUN-1001 : 3333 mslices, 3332 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17948 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10081 nets have 2 pins
+RUN-1001 : 6499 nets have [3 - 5] pins
+RUN-1001 : 727 nets have [6 - 10] pins
+RUN-1001 : 301 nets have [11 - 20] pins
+RUN-1001 : 307 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6811 instances, 6665 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3574 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 667405, Over = 241.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7875/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 822024, over cnt = 1977(5%), over = 3247, worst = 7
+PHY-1002 : len = 830000, over cnt = 1265(3%), over = 1842, worst = 7
+PHY-1002 : len = 844840, over cnt = 519(1%), over = 679, worst = 7
+PHY-1002 : len = 852032, over cnt = 198(0%), over = 258, worst = 5
+PHY-1002 : len = 855216, over cnt = 65(0%), over = 95, worst = 5
+PHY-1001 : End global iterations; 1.742715s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (141.7%)
+
+PHY-1001 : Congestion index: top1 = 60.11, top5 = 51.96, top10 = 47.75, top15 = 45.02.
+PHY-3001 : End congestion estimation; 2.172114s wall, 2.859375s user + 0.046875s system = 2.906250s CPU (133.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71716, tnet num: 17770, tinst num: 6811, tnode num: 94357, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.735934s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (100.8%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 615 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.684468s wall, 2.656250s user + 0.031250s system = 2.687500s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.83007e-05
+PHY-3002 : Step(275): len = 656675, overlap = 244.75
+PHY-3002 : Step(276): len = 650608, overlap = 251.5
+PHY-3002 : Step(277): len = 646620, overlap = 249
+PHY-3002 : Step(278): len = 644497, overlap = 251
+PHY-3002 : Step(279): len = 642642, overlap = 256.25
+PHY-3002 : Step(280): len = 640541, overlap = 253.75
+PHY-3002 : Step(281): len = 638212, overlap = 253.75
+PHY-3002 : Step(282): len = 635889, overlap = 261.25
+PHY-3002 : Step(283): len = 633912, overlap = 268.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000116601
+PHY-3002 : Step(284): len = 637437, overlap = 258.5
+PHY-3002 : Step(285): len = 642182, overlap = 247.5
+PHY-3002 : Step(286): len = 642980, overlap = 249
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000233203
+PHY-3002 : Step(287): len = 648904, overlap = 237.5
+PHY-3002 : Step(288): len = 656435, overlap = 224.75
+PHY-3002 : Step(289): len = 657109, overlap = 221.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.380374s wall, 0.390625s user + 0.718750s system = 1.109375s CPU (291.7%)
+
+PHY-3001 : Trial Legalized: Len = 744393
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 737/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853208, over cnt = 2629(7%), over = 4442, worst = 10
+PHY-1002 : len = 871096, over cnt = 1484(4%), over = 2208, worst = 10
+PHY-1002 : len = 889744, over cnt = 580(1%), over = 813, worst = 7
+PHY-1002 : len = 901464, over cnt = 105(0%), over = 119, worst = 3
+PHY-1002 : len = 904776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.449467s wall, 3.687500s user + 0.000000s system = 3.687500s CPU (150.5%)
+
+PHY-1001 : Congestion index: top1 = 58.32, top5 = 51.56, top10 = 48.13, top15 = 45.89.
+PHY-3001 : End congestion estimation; 2.948370s wall, 4.171875s user + 0.015625s system = 4.187500s CPU (142.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.892958s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000168532
+PHY-3002 : Step(290): len = 716812, overlap = 41.75
+PHY-3002 : Step(291): len = 700044, overlap = 70.5
+PHY-3002 : Step(292): len = 685429, overlap = 96.5
+PHY-3002 : Step(293): len = 676006, overlap = 118.25
+PHY-3002 : Step(294): len = 669316, overlap = 136.25
+PHY-3002 : Step(295): len = 665792, overlap = 156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000337064
+PHY-3002 : Step(296): len = 669538, overlap = 148.75
+PHY-3002 : Step(297): len = 673272, overlap = 149
+PHY-3002 : Step(298): len = 674649, overlap = 149
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000651401
+PHY-3002 : Step(299): len = 677829, overlap = 148
+PHY-3002 : Step(300): len = 684052, overlap = 147.25
+PHY-3002 : Step(301): len = 688577, overlap = 146.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037605s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (124.7%)
+
+PHY-3001 : Legalized: Len = 717794, Over = 0
+PHY-3001 : Spreading special nets. 462 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.114743s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (108.9%)
+
+PHY-3001 : 681 instances has been re-located, deltaX = 227, deltaY = 445, maxDist = 3.
+PHY-3001 : Final: Len = 728023, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71716, tnet num: 17770, tinst num: 6814, tnode num: 94357, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.942157s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (99.8%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 624 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4049/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 849976, over cnt = 2400(6%), over = 3979, worst = 8
+PHY-1002 : len = 863616, over cnt = 1477(4%), over = 2175, worst = 8
+PHY-1002 : len = 883984, over cnt = 405(1%), over = 561, worst = 5
+PHY-1002 : len = 890344, over cnt = 101(0%), over = 131, worst = 5
+PHY-1002 : len = 891720, over cnt = 23(0%), over = 32, worst = 4
+PHY-1001 : End global iterations; 2.311202s wall, 3.265625s user + 0.031250s system = 3.296875s CPU (142.6%)
+
+PHY-1001 : Congestion index: top1 = 55.17, top5 = 49.77, top10 = 46.46, top15 = 44.24.
+PHY-1001 : End incremental global routing; 2.706087s wall, 3.656250s user + 0.031250s system = 3.687500s CPU (136.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.929199s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (99.2%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6721 has valid locations, 30 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 733753
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16289/17980.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898856, over cnt = 138(0%), over = 171, worst = 6
+PHY-1002 : len = 899064, over cnt = 61(0%), over = 64, worst = 2
+PHY-1002 : len = 899664, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 899768, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 899944, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.881064s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (106.4%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.86, top10 = 46.57, top15 = 44.42.
+PHY-3001 : End congestion estimation; 1.221065s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (103.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71976, tnet num: 17802, tinst num: 6839, tnode num: 94686, tedge num: 119550.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.936349s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (100.1%)
+
+RUN-1004 : used memory is 649 MB, reserved memory is 644 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17802 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.904689s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(302): len = 733238, overlap = 0
+PHY-3002 : Step(303): len = 732200, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16275/17980.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 897928, over cnt = 97(0%), over = 116, worst = 4
+PHY-1002 : len = 898200, over cnt = 43(0%), over = 43, worst = 1
+PHY-1002 : len = 898520, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 898888, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 898936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.865675s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (110.1%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 50.03, top10 = 46.71, top15 = 44.46.
+PHY-3001 : End congestion estimation; 1.206621s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (106.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17802 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.994504s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000561432
+PHY-3002 : Step(304): len = 732161, overlap = 2.75
+PHY-3002 : Step(305): len = 732249, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005492s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 732503, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069969s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (89.3%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 4, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 732617, Over = 0
+PHY-3001 : End incremental placement; 6.860680s wall, 6.937500s user + 0.187500s system = 7.125000s CPU (103.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.013959s wall, 12.093750s user + 0.250000s system = 12.343750s CPU (112.1%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 730, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16255/17980.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898768, over cnt = 81(0%), over = 102, worst = 4
+PHY-1002 : len = 898752, over cnt = 40(0%), over = 44, worst = 3
+PHY-1002 : len = 899144, over cnt = 5(0%), over = 6, worst = 2
+PHY-1002 : len = 899192, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 899256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.880175s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (110.1%)
+
+PHY-1001 : Congestion index: top1 = 55.17, top5 = 50.00, top10 = 46.62, top15 = 44.45.
+OPT-1001 : End congestion update; 1.241100s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (105.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17802 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.756740s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.1%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6751 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 742293, Over = 0
+PHY-3001 : Spreading special nets. 34 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069139s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.4%)
+
+PHY-3001 : 44 instances has been re-located, deltaX = 26, deltaY = 23, maxDist = 4.
+PHY-3001 : Final: Len = 742891, Over = 0
+PHY-3001 : End incremental legalization; 0.458097s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (122.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 58 cells processed and 24398 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6751 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 742975, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067590s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (115.6%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 20, deltaY = 19, maxDist = 3.
+PHY-3001 : Final: Len = 743763, Over = 0
+PHY-3001 : End incremental legalization; 0.418111s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 33 cells processed and 3192 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6761 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6849 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744116, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065614s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.3%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 744592, Over = 0
+PHY-3001 : End incremental legalization; 0.419912s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.5%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 9 cells processed and 1486 slack improved
+OPT-1001 : End bottleneck based optimization; 3.747559s wall, 3.921875s user + 0.000000s system = 3.921875s CPU (104.7%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 730, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15861/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910424, over cnt = 200(0%), over = 242, worst = 7
+PHY-1002 : len = 910816, over cnt = 80(0%), over = 83, worst = 2
+PHY-1002 : len = 911392, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 911904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 912000, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.933621s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (105.4%)
+
+PHY-1001 : Congestion index: top1 = 55.82, top5 = 50.26, top10 = 46.76, top15 = 44.64.
+OPT-1001 : End congestion update; 1.276214s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (104.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.770519s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6761 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6849 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744522, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067407s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.7%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 17, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 744948, Over = 0
+PHY-3001 : End incremental legalization; 0.418075s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 12 cells processed and 1450 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.597426s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (102.3%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 730, peak = 733.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.767996s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16253/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912224, over cnt = 48(0%), over = 59, worst = 4
+PHY-1002 : len = 912368, over cnt = 25(0%), over = 25, worst = 1
+PHY-1002 : len = 912480, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 912512, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 912600, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.858347s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 55.93, top5 = 50.17, top10 = 46.70, top15 = 44.61.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.767958s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.482759
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.303150s wall, 23.718750s user + 0.296875s system = 24.015625s CPU (107.7%)
+
+RUN-1003 : finish command "place" in 69.065970s wall, 99.812500s user + 6.546875s system = 106.359375s CPU (154.0%)
+
+RUN-1004 : used memory is 606 MB, reserved memory is 598 MB, peak memory is 733 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.864845s wall, 3.140625s user + 0.031250s system = 3.171875s CPU (170.1%)
+
+RUN-1004 : used memory is 606 MB, reserved memory is 600 MB, peak memory is 733 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72045, tnet num: 17805, tinst num: 6849, tnode num: 94791, tedge num: 119669.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.712492s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.5%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 635 MB, peak memory is 733 MB
+PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 846032, over cnt = 2656(7%), over = 4489, worst = 9
+PHY-1002 : len = 864952, over cnt = 1635(4%), over = 2372, worst = 9
+PHY-1002 : len = 888664, over cnt = 404(1%), over = 544, worst = 7
+PHY-1002 : len = 896896, over cnt = 21(0%), over = 32, worst = 7
+PHY-1002 : len = 897232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.320815s wall, 4.343750s user + 0.015625s system = 4.359375s CPU (131.3%)
+
+PHY-1001 : Congestion index: top1 = 55.52, top5 = 50.19, top10 = 46.84, top15 = 44.60.
+PHY-1001 : End global routing; 3.673096s wall, 4.703125s user + 0.015625s system = 4.718750s CPU (128.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 712, reserve = 716, peak = 733.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 985, reserve = 988, peak = 985.
+PHY-1001 : End build detailed router design. 4.323836s wall, 4.281250s user + 0.046875s system = 4.328125s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267368, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.692200s wall, 5.671875s user + 0.015625s system = 5.687500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267424, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.480922s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.7%)
+
+PHY-1001 : Current memory(MB): used = 1020, reserve = 1025, peak = 1020.
+PHY-1001 : End phase 1; 6.185386s wall, 6.156250s user + 0.015625s system = 6.171875s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1040, peak = 1036.
+PHY-1001 : End initial routed; 29.219928s wall, 63.828125s user + 0.281250s system = 64.109375s CPU (219.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.523266s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1049, reserve = 1052, peak = 1049.
+PHY-1001 : End phase 2; 32.743260s wall, 67.328125s user + 0.281250s system = 67.609375s CPU (206.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.146147s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.9%)
+
+PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.435352s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (96.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.21014e+06, over cnt = 712(0%), over = 713, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.008738s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (168.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.20853e+06, over cnt = 179(0%), over = 179, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.857565s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (158.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.20974e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.490465s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (124.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.21006e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.332954s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (112.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.238055s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (124.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.357844s wall, 0.359375s user + 0.031250s system = 0.390625s CPU (109.2%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.649156s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.188354s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.209143s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.226816s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.239825s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.344112s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (95.4%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.197264s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.195085s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.224122s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.6%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.233932s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.364859s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.409024s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.196064s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (111.6%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.198123s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.245694s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.4%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.273218s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.439423s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.415746s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.175474s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.184889s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.191744s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.8%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.217506s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (107.8%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.239720s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (110.8%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.368072s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.410042s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.142484s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.155094s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.182607s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.184916s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (92.9%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.224559s wall, 0.250000s user + 0.031250s system = 0.281250s CPU (125.2%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.236257s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.363511s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.407714s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.147339s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.199470s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.256262s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.191891s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.193794s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.223810s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.241476s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.363843s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.402525s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.148407s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.146312s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.218310s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.143017s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.186917s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.192999s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.229384s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (109.0%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.238619s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.365665s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.402305s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.316840s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.163221s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.141594s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.139179s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.132169s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.177709s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.183715s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (119.1%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.223149s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.238558s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.353538s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.400578s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.133155s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.143087s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.231367s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.231552s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.114589s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.125102s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.476601s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1059, reserve = 1063, peak = 1059.
+PHY-1001 : End phase 3; 46.567518s wall, 48.625000s user + 0.156250s system = 48.781250s CPU (104.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.145250s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.8%)
+
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.445811s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.185392s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.215255s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.288982s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (102.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.185332s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 5 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.184543s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.222321s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.237058s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.364096s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.7%)
+
+PHY-1001 : ===== DR Iter 9 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.195802s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.209746s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (111.7%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.252137s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.263657s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.393100s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.395993s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (94.7%)
+
+PHY-1001 : ===== DR Iter 15 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.186133s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.191549s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.225726s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.232661s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (107.5%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.363531s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.403188s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 1.119150s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 22 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.182469s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.186089s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.220742s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.235184s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.356141s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.402242s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 1.115816s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 1.125035s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 30 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.181304s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.4%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.181951s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.224272s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.235007s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.359505s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.403127s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 1.325326s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 1.109476s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.120576s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 39 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.182041s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (111.6%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.193338s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (105.1%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.226150s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.237365s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.350567s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.411698s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 1.130241s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.136144s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.135363s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.139008s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 49 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.191811s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.8%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.192796s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (113.5%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.218918s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.266705s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.438092s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.461423s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 1.139386s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 1.137763s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.142859s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.129279s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.146220s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 60 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.182752s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.182499s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.224488s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.238745s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.360079s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.405787s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 1.149130s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 1.408368s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.152321s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.145255s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.166037s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.168032s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.559008s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1061, reserve = 1065, peak = 1061.
+PHY-1001 : End phase 4; 41.779690s wall, 41.796875s user + 0.046875s system = 41.843750s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.2102e+06
+PHY-1001 : 589 feed throughs used by 430 nets
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1168, peak = 1160.
+PHY-1001 : End export database. 2.490493s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (100.4%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
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+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
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+PHY-3001 : eco cells: (1 17 2) is for feedthrough
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+PHY-3001 : eco cells: (11 5 3) is for feedthrough
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+PHY-3001 : eco cells: (34 33 2) is for feedthrough
+PHY-3001 : eco cells: (34 34 0) is for feedthrough
+PHY-3001 : eco cells: (34 36 0) is for feedthrough
+PHY-3001 : eco cells: (34 36 3) is for feedthrough
+PHY-3001 : eco cells: (34 37 0) is for feedthrough
+PHY-3001 : eco cells: (34 38 1) is for feedthrough
+PHY-3001 : eco cells: (34 38 3) is for feedthrough
+PHY-3001 : eco cells: (34 39 1) is for feedthrough
+PHY-3001 : eco cells: (34 58 1) is for feedthrough
+PHY-3001 : eco cells: (35 9 2) is for feedthrough
+PHY-3001 : eco cells: (35 18 0) is for feedthrough
+PHY-3001 : eco cells: (35 20 3) is for feedthrough
+PHY-3001 : eco cells: (35 21 2) is for feedthrough
+PHY-3001 : eco cells: (35 22 0) is for feedthrough
+PHY-3001 : eco cells: (35 22 1) is for feedthrough
+PHY-3001 : eco cells: (35 23 1) is for feedthrough
+PHY-3001 : eco cells: (35 24 0) is for feedthrough
+PHY-3001 : eco cells: (35 24 3) is for feedthrough
+PHY-3001 : eco cells: (35 25 0) is for feedthrough
+PHY-3001 : eco cells: (35 25 1) is for feedthrough
+PHY-3001 : eco cells: (35 28 2) is for feedthrough
+PHY-3001 : eco cells: (35 29 2) is for feedthrough
+PHY-3001 : eco cells: (35 30 1) is for feedthrough
+PHY-3001 : eco cells: (35 31 0) is for feedthrough
+PHY-3001 : eco cells: (35 31 1) is for feedthrough
+PHY-3001 : eco cells: (35 32 1) is for feedthrough
+PHY-3001 : eco cells: (35 33 1) is for feedthrough
+PHY-3001 : eco cells: (35 33 3) is for feedthrough
+PHY-3001 : eco cells: (35 34 0) is for feedthrough
+PHY-3001 : eco cells: (35 34 2) is for feedthrough
+PHY-3001 : eco cells: (35 34 3) is for feedthrough
+PHY-3001 : eco cells: (35 35 0) is for feedthrough
+PHY-3001 : eco cells: (35 37 0) is for feedthrough
+PHY-3001 : eco cells: (35 38 0) is for feedthrough
+PHY-3001 : eco cells: (35 42 2) is for feedthrough
+PHY-3001 : eco cells: (35 42 3) is for feedthrough
+PHY-3001 : eco cells: (35 44 2) is for feedthrough
+PHY-3001 : eco cells: (35 46 3) is for feedthrough
+PHY-3001 : eco cells: (35 53 1) is for feedthrough
+PHY-3001 : eco cells: (36 2 0) is for feedthrough
+PHY-3001 : eco cells: (36 3 0) is for feedthrough
+PHY-3001 : eco cells: (36 12 2) is for feedthrough
+PHY-3001 : eco cells: (36 15 1) is for feedthrough
+PHY-3001 : eco cells: (36 15 3) is for feedthrough
+PHY-3001 : eco cells: (36 17 0) is for feedthrough
+PHY-3001 : eco cells: (36 20 3) is for feedthrough
+PHY-3001 : eco cells: (36 21 0) is for feedthrough
+PHY-3001 : eco cells: (36 22 0) is for feedthrough
+PHY-3001 : eco cells: (36 22 3) is for feedthrough
+PHY-3001 : eco cells: (36 26 3) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 1) is for feedthrough
+PHY-3001 : eco cells: (36 28 3) is for feedthrough
+PHY-3001 : eco cells: (36 29 0) is for feedthrough
+PHY-3001 : eco cells: (36 30 0) is for feedthrough
+PHY-3001 : eco cells: (36 30 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 2) is for feedthrough
+PHY-3001 : eco cells: (36 32 0) is for feedthrough
+PHY-3001 : eco cells: (36 32 1) is for feedthrough
+PHY-3001 : eco cells: (36 32 3) is for feedthrough
+PHY-3001 : eco cells: (36 36 0) is for feedthrough
+PHY-3001 : eco cells: (36 36 3) is for feedthrough
+PHY-3001 : eco cells: (36 37 0) is for feedthrough
+PHY-3001 : eco cells: (36 38 1) is for feedthrough
+PHY-3001 : eco cells: (36 38 2) is for feedthrough
+PHY-3001 : eco cells: (36 39 3) is for feedthrough
+PHY-3001 : eco cells: (36 42 0) is for feedthrough
+PHY-3001 : eco cells: (36 43 3) is for feedthrough
+PHY-3001 : eco cells: (36 44 3) is for feedthrough
+PHY-3001 : eco cells: (36 46 2) is for feedthrough
+PHY-3001 : eco cells: (36 69 1) is for feedthrough
+PHY-3001 : eco cells: (37 3 1) is for feedthrough
+PHY-3001 : eco cells: (37 12 0) is for feedthrough
+PHY-3001 : eco cells: (37 23 2) is for feedthrough
+PHY-3001 : eco cells: (37 27 0) is for feedthrough
+PHY-3001 : eco cells: (37 30 2) is for feedthrough
+PHY-3001 : eco cells: (37 31 0) is for feedthrough
+PHY-3001 : eco cells: (37 31 3) is for feedthrough
+PHY-3001 : eco cells: (37 32 1) is for feedthrough
+PHY-3001 : eco cells: (37 32 2) is for feedthrough
+PHY-3001 : eco cells: (37 33 0) is for feedthrough
+PHY-3001 : eco cells: (37 34 0) is for feedthrough
+PHY-3001 : eco cells: (37 34 3) is for feedthrough
+PHY-3001 : eco cells: (37 35 0) is for feedthrough
+PHY-3001 : eco cells: (37 35 2) is for feedthrough
+PHY-3001 : eco cells: (37 36 2) is for feedthrough
+PHY-3001 : eco cells: (37 39 0) is for feedthrough
+PHY-3001 : eco cells: (37 46 1) is for feedthrough
+PHY-3001 : eco cells: (37 55 0) is for feedthrough
+PHY-3001 : eco cells: (37 62 2) is for feedthrough
+PHY-3001 : eco cells: (38 1 1) is for feedthrough
+PHY-3001 : eco cells: (38 3 2) is for feedthrough
+PHY-3001 : eco cells: (38 27 0) is for feedthrough
+PHY-3001 : eco cells: (38 30 2) is for feedthrough
+PHY-3001 : eco cells: (38 47 2) is for feedthrough
+PHY-3001 : eco cells: (38 67 1) is for feedthrough
+PHY-3001 : eco cells: (39 4 2) is for feedthrough
+PHY-3001 : eco cells: (39 10 3) is for feedthrough
+PHY-3001 : eco cells: (39 30 3) is for feedthrough
+PHY-3001 : eco cells: (39 50 2) is for feedthrough
+PHY-3001 : eco cells: 6761 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6849 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.861453s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%)
+
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.352104s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (100.5%)
+
+RUN-1004 : used memory is 1157 MB, reserved memory is 1164 MB, peak memory is 1160 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1165, peak = 1160.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1182, peak = 1175.
+PHY-1001 : End build detailed router design. 2.014773s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.023571s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (66.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.030687s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (101.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.030187s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (103.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.031089s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.031281s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.031306s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1182, peak = 1175.
+PHY-1001 : End phase 1; 0.218012s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.3%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1182, peak = 1175.
+PHY-1001 : End initial routed; 0.146947s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.432802s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1182, peak = 1175.
+PHY-1001 : End phase 2; 3.579814s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.121103s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (103.2%)
+
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.378664s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.143105s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (109.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.137888s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (113.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.155401s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.137651s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.133124s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.133066s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.9%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.136082s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.9%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.141861s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.151729s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.134646s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.8%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.132555s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.1%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.142569s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.133024s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.7%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.132001s wall, 0.109375s user + 0.015625s system = 0.125000s CPU (94.7%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.133047s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.7%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.140454s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.133784s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.4%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.139617s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.136436s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (114.5%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.134311s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.131730s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.133149s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.6%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.135913s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.0%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.134924s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.6%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.135658s wall, 0.171875s user + 0.031250s system = 0.203125s CPU (149.7%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.132260s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.3%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.133317s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.135766s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.141341s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.152185s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.148262s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.8%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.159909s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.7%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.153775s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.138545s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.2%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.149945s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (114.6%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.151391s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.9%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.149589s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.0%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.169320s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.136173s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.138134s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.131906s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.8%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.135115s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (115.6%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.133221s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.6%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.131363s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.2%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.131101s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.133037s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.7%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.132877s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.131174s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.2%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.132791s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.133871s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.0%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.132510s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.3%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.138699s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.133015s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.0%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.131755s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.7%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.133549s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.6%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.216539s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.132809s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.132414s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (129.8%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.133171s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.9%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.135827s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.131784s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.7%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.131984s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.7%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.137532s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (125.0%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.131303s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.137713s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.8%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.141510s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (110.4%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.136262s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.136225s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.148367s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.8%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.145135s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.7%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.138008s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.139799s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (89.4%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.143427s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (119.8%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.134037s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.510550s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (98.4%)
+
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1182, peak = 1176.
+PHY-1001 : End phase 3; 14.304394s wall, 14.312500s user + 0.125000s system = 14.437500s CPU (100.9%)
+
+PHY-1001 : 589 feed throughs used by 430 nets
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1182, peak = 1176.
+PHY-1001 : End export database. 2.441441s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (98.6%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y24_n2beg4), nets: BUSY_MIPI_i_syn_3 sampling_fe_a/u_sort/u_transfer_300_to_200/mux16_syn_16
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 23.809428s wall, 23.750000s user + 0.140625s system = 23.890625s CPU (100.3%)
+
+RUN-1004 : used memory is 1160 MB, reserved memory is 1166 MB, peak memory is 1176 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y24_n2beg4), nets: BUSY_MIPI_i_syn_3 sampling_fe_a/u_sort/u_transfer_300_to_200/mux16_syn_16
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 165.959244s wall, 203.515625s user + 0.718750s system = 204.234375s CPU (123.1%)
+
+RUN-1004 : used memory is 1160 MB, reserved memory is 1166 MB, peak memory is 1176 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_095232.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_095821.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_095821.log
new file mode 100644
index 0000000..3c3b659
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_095821.log
@@ -0,0 +1,2194 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 09:58:21 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.302635s wall, 2.187500s user + 0.125000s system = 2.312500s CPU (100.4%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 316 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2951 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2255 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2096 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18026 instances
+RUN-0007 : 7672 luts, 9131 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20603 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13084 nets have 2 pins
+RUN-1001 : 6479 nets have [3 - 5] pins
+RUN-1001 : 623 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 804
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3525
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 55
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 140
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18024 instances, 7672 luts, 9131 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6056 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84226, tnet num: 20425, tinst num: 18024, tnode num: 114666, tedge num: 134352.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.248289s wall, 1.203125s user + 0.046875s system = 1.250000s CPU (100.1%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 515 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.098999s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (100.5%)
+
+PHY-3001 : Found 1253 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.26818e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18024.
+PHY-3001 : Level 1 #clusters 2054.
+PHY-3001 : End clustering; 0.140764s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (133.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.34754e+06, overlap = 507.594
+PHY-3002 : Step(2): len = 1.22219e+06, overlap = 557.062
+PHY-3002 : Step(3): len = 876994, overlap = 595.094
+PHY-3002 : Step(4): len = 801224, overlap = 646.844
+PHY-3002 : Step(5): len = 613404, overlap = 805
+PHY-3002 : Step(6): len = 550507, overlap = 857.781
+PHY-3002 : Step(7): len = 464962, overlap = 967.344
+PHY-3002 : Step(8): len = 421501, overlap = 965.125
+PHY-3002 : Step(9): len = 386168, overlap = 1015.53
+PHY-3002 : Step(10): len = 347965, overlap = 1095.84
+PHY-3002 : Step(11): len = 317819, overlap = 1126.16
+PHY-3002 : Step(12): len = 288017, overlap = 1176.69
+PHY-3002 : Step(13): len = 263854, overlap = 1219.28
+PHY-3002 : Step(14): len = 238272, overlap = 1283.03
+PHY-3002 : Step(15): len = 226336, overlap = 1333.19
+PHY-3002 : Step(16): len = 200326, overlap = 1390.91
+PHY-3002 : Step(17): len = 186506, overlap = 1437.75
+PHY-3002 : Step(18): len = 168030, overlap = 1457.06
+PHY-3002 : Step(19): len = 155405, overlap = 1472.91
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.32636e-06
+PHY-3002 : Step(20): len = 157154, overlap = 1425.56
+PHY-3002 : Step(21): len = 196270, overlap = 1263.84
+PHY-3002 : Step(22): len = 207765, overlap = 1196.62
+PHY-3002 : Step(23): len = 216530, overlap = 1101.62
+PHY-3002 : Step(24): len = 215746, overlap = 1091.84
+PHY-3002 : Step(25): len = 215120, overlap = 1084.38
+PHY-3002 : Step(26): len = 211450, overlap = 1104.59
+PHY-3002 : Step(27): len = 208888, overlap = 1098.41
+PHY-3002 : Step(28): len = 205267, overlap = 1078
+PHY-3002 : Step(29): len = 203829, overlap = 1084.91
+PHY-3002 : Step(30): len = 201298, overlap = 1076.72
+PHY-3002 : Step(31): len = 198893, overlap = 1074.16
+PHY-3002 : Step(32): len = 196865, overlap = 1079.72
+PHY-3002 : Step(33): len = 195919, overlap = 1075.44
+PHY-3002 : Step(34): len = 194251, overlap = 1067.03
+PHY-3002 : Step(35): len = 193524, overlap = 1054.91
+PHY-3002 : Step(36): len = 192736, overlap = 1044.59
+PHY-3002 : Step(37): len = 191757, overlap = 1047.19
+PHY-3002 : Step(38): len = 191225, overlap = 1050.72
+PHY-3002 : Step(39): len = 190681, overlap = 1055.78
+PHY-3002 : Step(40): len = 189977, overlap = 1054.41
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.65273e-06
+PHY-3002 : Step(41): len = 195392, overlap = 1054.25
+PHY-3002 : Step(42): len = 208545, overlap = 1023.66
+PHY-3002 : Step(43): len = 214311, overlap = 985
+PHY-3002 : Step(44): len = 218849, overlap = 958.25
+PHY-3002 : Step(45): len = 218649, overlap = 959.719
+PHY-3002 : Step(46): len = 218878, overlap = 924.438
+PHY-3002 : Step(47): len = 217815, overlap = 930
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.30546e-06
+PHY-3002 : Step(48): len = 229290, overlap = 905.781
+PHY-3002 : Step(49): len = 251738, overlap = 839.781
+PHY-3002 : Step(50): len = 265365, overlap = 738.125
+PHY-3002 : Step(51): len = 271645, overlap = 698.312
+PHY-3002 : Step(52): len = 271413, overlap = 632.5
+PHY-3002 : Step(53): len = 274063, overlap = 624.5
+PHY-3002 : Step(54): len = 272651, overlap = 612.469
+PHY-3002 : Step(55): len = 271558, overlap = 598.062
+PHY-3002 : Step(56): len = 270741, overlap = 612.531
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.06109e-05
+PHY-3002 : Step(57): len = 287262, overlap = 589.25
+PHY-3002 : Step(58): len = 308127, overlap = 556.875
+PHY-3002 : Step(59): len = 315340, overlap = 517.719
+PHY-3002 : Step(60): len = 316747, overlap = 497.344
+PHY-3002 : Step(61): len = 315628, overlap = 499.531
+PHY-3002 : Step(62): len = 315099, overlap = 497.719
+PHY-3002 : Step(63): len = 314316, overlap = 483.281
+PHY-3002 : Step(64): len = 313763, overlap = 479.594
+PHY-3002 : Step(65): len = 313464, overlap = 467.062
+PHY-3002 : Step(66): len = 313138, overlap = 468.906
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.12218e-05
+PHY-3002 : Step(67): len = 330071, overlap = 402.438
+PHY-3002 : Step(68): len = 346200, overlap = 356.469
+PHY-3002 : Step(69): len = 353054, overlap = 350.719
+PHY-3002 : Step(70): len = 355858, overlap = 372.5
+PHY-3002 : Step(71): len = 355892, overlap = 362.875
+PHY-3002 : Step(72): len = 358137, overlap = 376.969
+PHY-3002 : Step(73): len = 357748, overlap = 377.219
+PHY-3002 : Step(74): len = 359390, overlap = 362.406
+PHY-3002 : Step(75): len = 359268, overlap = 355.312
+PHY-3002 : Step(76): len = 359393, overlap = 338.906
+PHY-3002 : Step(77): len = 357173, overlap = 329.188
+PHY-3002 : Step(78): len = 356919, overlap = 319.688
+PHY-3002 : Step(79): len = 356227, overlap = 322.031
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.24436e-05
+PHY-3002 : Step(80): len = 377513, overlap = 293.906
+PHY-3002 : Step(81): len = 390287, overlap = 289.469
+PHY-3002 : Step(82): len = 389413, overlap = 273.656
+PHY-3002 : Step(83): len = 388728, overlap = 272.156
+PHY-3002 : Step(84): len = 389201, overlap = 267.469
+PHY-3002 : Step(85): len = 391712, overlap = 257.438
+PHY-3002 : Step(86): len = 389847, overlap = 250.125
+PHY-3002 : Step(87): len = 392748, overlap = 256.875
+PHY-3002 : Step(88): len = 395021, overlap = 258.125
+PHY-3002 : Step(89): len = 395975, overlap = 260.406
+PHY-3002 : Step(90): len = 392592, overlap = 272.5
+PHY-3002 : Step(91): len = 392778, overlap = 259.688
+PHY-3002 : Step(92): len = 393802, overlap = 253.312
+PHY-3002 : Step(93): len = 394540, overlap = 257.469
+PHY-3002 : Step(94): len = 392451, overlap = 260.719
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.48873e-05
+PHY-3002 : Step(95): len = 408748, overlap = 251.969
+PHY-3002 : Step(96): len = 417297, overlap = 253.438
+PHY-3002 : Step(97): len = 416089, overlap = 243.344
+PHY-3002 : Step(98): len = 416455, overlap = 246.094
+PHY-3002 : Step(99): len = 418889, overlap = 230.156
+PHY-3002 : Step(100): len = 422192, overlap = 219.656
+PHY-3002 : Step(101): len = 423102, overlap = 225.406
+PHY-3002 : Step(102): len = 426924, overlap = 222.812
+PHY-3002 : Step(103): len = 428994, overlap = 215.344
+PHY-3002 : Step(104): len = 431929, overlap = 201.312
+PHY-3002 : Step(105): len = 429040, overlap = 210.781
+PHY-3002 : Step(106): len = 429605, overlap = 214.938
+PHY-3002 : Step(107): len = 430754, overlap = 204.656
+PHY-3002 : Step(108): len = 432934, overlap = 197.312
+PHY-3002 : Step(109): len = 430258, overlap = 196.219
+PHY-3002 : Step(110): len = 430525, overlap = 198.25
+PHY-3002 : Step(111): len = 430693, overlap = 190.781
+PHY-3002 : Step(112): len = 431874, overlap = 190.406
+PHY-3002 : Step(113): len = 429505, overlap = 192.938
+PHY-3002 : Step(114): len = 429359, overlap = 195.5
+PHY-3002 : Step(115): len = 429754, overlap = 190.312
+PHY-3002 : Step(116): len = 431050, overlap = 193.594
+PHY-3002 : Step(117): len = 429130, overlap = 204.562
+PHY-3002 : Step(118): len = 429441, overlap = 215.156
+PHY-3002 : Step(119): len = 429928, overlap = 220.219
+PHY-3002 : Step(120): len = 430778, overlap = 218.438
+PHY-3002 : Step(121): len = 429119, overlap = 213.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000166472
+PHY-3002 : Step(122): len = 441125, overlap = 220.656
+PHY-3002 : Step(123): len = 447932, overlap = 219.469
+PHY-3002 : Step(124): len = 447463, overlap = 218.812
+PHY-3002 : Step(125): len = 447708, overlap = 215.812
+PHY-3002 : Step(126): len = 448786, overlap = 214.688
+PHY-3002 : Step(127): len = 451470, overlap = 209.812
+PHY-3002 : Step(128): len = 452724, overlap = 201.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000330494
+PHY-3002 : Step(129): len = 459634, overlap = 207.531
+PHY-3002 : Step(130): len = 467853, overlap = 192.562
+PHY-3002 : Step(131): len = 471457, overlap = 188.406
+PHY-3002 : Step(132): len = 476006, overlap = 190.875
+PHY-3002 : Step(133): len = 477901, overlap = 188.844
+PHY-3002 : Step(134): len = 479571, overlap = 190.406
+PHY-3002 : Step(135): len = 479251, overlap = 185.75
+PHY-3002 : Step(136): len = 479772, overlap = 185.656
+PHY-3002 : Step(137): len = 479893, overlap = 187.938
+PHY-3002 : Step(138): len = 480211, overlap = 185.125
+PHY-3002 : Step(139): len = 480261, overlap = 183.688
+PHY-3002 : Step(140): len = 480589, overlap = 184.531
+PHY-3002 : Step(141): len = 480701, overlap = 182.375
+PHY-3002 : Step(142): len = 481068, overlap = 181.219
+PHY-3002 : Step(143): len = 480376, overlap = 175.844
+PHY-3002 : Step(144): len = 480310, overlap = 172.375
+PHY-3002 : Step(145): len = 480532, overlap = 178.188
+PHY-3002 : Step(146): len = 481014, overlap = 178.625
+PHY-3002 : Step(147): len = 480550, overlap = 174
+PHY-3002 : Step(148): len = 480926, overlap = 177.906
+PHY-3002 : Step(149): len = 481270, overlap = 176.406
+PHY-3002 : Step(150): len = 481637, overlap = 178.156
+PHY-3002 : Step(151): len = 481574, overlap = 174.844
+PHY-3002 : Step(152): len = 482352, overlap = 175.219
+PHY-3002 : Step(153): len = 483263, overlap = 176.281
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000648515
+PHY-3002 : Step(154): len = 487332, overlap = 176.5
+PHY-3002 : Step(155): len = 493462, overlap = 176.312
+PHY-3002 : Step(156): len = 496073, overlap = 173.594
+PHY-3002 : Step(157): len = 497973, overlap = 170.875
+PHY-3002 : Step(158): len = 499145, overlap = 171.781
+PHY-3002 : Step(159): len = 500130, overlap = 165.781
+PHY-3002 : Step(160): len = 500109, overlap = 165.656
+PHY-3002 : Step(161): len = 500300, overlap = 165.375
+PHY-3002 : Step(162): len = 501290, overlap = 163
+PHY-3002 : Step(163): len = 503188, overlap = 154.938
+PHY-3002 : Step(164): len = 503421, overlap = 153.312
+PHY-3002 : Step(165): len = 503673, overlap = 147.75
+PHY-3002 : Step(166): len = 504111, overlap = 147.719
+PHY-3002 : Step(167): len = 504763, overlap = 148.656
+PHY-3002 : Step(168): len = 505037, overlap = 147.719
+PHY-3002 : Step(169): len = 505320, overlap = 144.781
+PHY-3002 : Step(170): len = 506025, overlap = 147.812
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00119673
+PHY-3002 : Step(171): len = 509160, overlap = 143.875
+PHY-3002 : Step(172): len = 513677, overlap = 135.344
+PHY-3002 : Step(173): len = 515260, overlap = 131.531
+PHY-3002 : Step(174): len = 516637, overlap = 128.156
+PHY-3002 : Step(175): len = 518219, overlap = 134.969
+PHY-3002 : Step(176): len = 519874, overlap = 132.625
+PHY-3002 : Step(177): len = 520427, overlap = 130.5
+PHY-3002 : Step(178): len = 521048, overlap = 133.781
+PHY-3002 : Step(179): len = 522137, overlap = 131.719
+PHY-3002 : Step(180): len = 522827, overlap = 131.094
+PHY-3002 : Step(181): len = 522963, overlap = 135.469
+PHY-3002 : Step(182): len = 523373, overlap = 134
+PHY-3002 : Step(183): len = 524080, overlap = 134.375
+PHY-3002 : Step(184): len = 524362, overlap = 133.219
+PHY-3002 : Step(185): len = 524202, overlap = 133.625
+PHY-3002 : Step(186): len = 524255, overlap = 132.25
+PHY-3002 : Step(187): len = 524626, overlap = 132.219
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00211699
+PHY-3002 : Step(188): len = 526862, overlap = 128.938
+PHY-3002 : Step(189): len = 530555, overlap = 127.719
+PHY-3002 : Step(190): len = 532099, overlap = 126.844
+PHY-3002 : Step(191): len = 533281, overlap = 121.188
+PHY-3002 : Step(192): len = 534745, overlap = 120.656
+PHY-3002 : Step(193): len = 535579, overlap = 120.156
+PHY-3002 : Step(194): len = 535383, overlap = 117.312
+PHY-3002 : Step(195): len = 535246, overlap = 119.812
+PHY-3002 : Step(196): len = 535408, overlap = 116.281
+PHY-3002 : Step(197): len = 535659, overlap = 115.562
+PHY-3002 : Step(198): len = 535865, overlap = 117
+PHY-3002 : Step(199): len = 536150, overlap = 114.25
+PHY-3002 : Step(200): len = 536640, overlap = 113.312
+PHY-3002 : Step(201): len = 537126, overlap = 117.469
+PHY-3002 : Step(202): len = 537705, overlap = 121.156
+PHY-3002 : Step(203): len = 538645, overlap = 121.438
+PHY-3002 : Step(204): len = 539303, overlap = 123.25
+PHY-3002 : Step(205): len = 539577, overlap = 123.25
+PHY-3002 : Step(206): len = 539664, overlap = 123.25
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00351386
+PHY-3002 : Step(207): len = 540907, overlap = 121.188
+PHY-3002 : Step(208): len = 543217, overlap = 120.938
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.011697s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710024, over cnt = 1615(4%), over = 7624, worst = 54
+PHY-1001 : End global iterations; 0.759986s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (139.8%)
+
+PHY-1001 : Congestion index: top1 = 90.24, top5 = 64.55, top10 = 53.74, top15 = 47.58.
+PHY-3001 : End congestion estimation; 0.999804s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (129.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.915815s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000136147
+PHY-3002 : Step(209): len = 646390, overlap = 57.0938
+PHY-3002 : Step(210): len = 647727, overlap = 55.9062
+PHY-3002 : Step(211): len = 642701, overlap = 57.25
+PHY-3002 : Step(212): len = 638874, overlap = 51.4688
+PHY-3002 : Step(213): len = 636224, overlap = 48
+PHY-3002 : Step(214): len = 634116, overlap = 46.2812
+PHY-3002 : Step(215): len = 631858, overlap = 45.0625
+PHY-3002 : Step(216): len = 629213, overlap = 44.5
+PHY-3002 : Step(217): len = 626749, overlap = 41.0625
+PHY-3002 : Step(218): len = 624793, overlap = 36.9688
+PHY-3002 : Step(219): len = 623997, overlap = 31.1875
+PHY-3002 : Step(220): len = 623043, overlap = 31.0938
+PHY-3002 : Step(221): len = 620927, overlap = 32
+PHY-3002 : Step(222): len = 618993, overlap = 31.5938
+PHY-3002 : Step(223): len = 618363, overlap = 30.9688
+PHY-3002 : Step(224): len = 616853, overlap = 31.9062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000272295
+PHY-3002 : Step(225): len = 620433, overlap = 31.7812
+PHY-3002 : Step(226): len = 626070, overlap = 35.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000544589
+PHY-3002 : Step(227): len = 628545, overlap = 39
+PHY-3002 : Step(228): len = 646372, overlap = 40.375
+PHY-3002 : Step(229): len = 657458, overlap = 44.625
+PHY-3002 : Step(230): len = 654264, overlap = 45.1562
+PHY-3002 : Step(231): len = 652488, overlap = 47.3125
+PHY-3002 : Step(232): len = 649114, overlap = 46.2812
+PHY-3002 : Step(233): len = 650138, overlap = 45.9062
+PHY-3002 : Step(234): len = 653971, overlap = 46.625
+PHY-3002 : Step(235): len = 658039, overlap = 45.9688
+PHY-3002 : Step(236): len = 657659, overlap = 44.8438
+PHY-3002 : Step(237): len = 656130, overlap = 45.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00107512
+PHY-3002 : Step(238): len = 663633, overlap = 43.1875
+PHY-3002 : Step(239): len = 669336, overlap = 44.2812
+PHY-3002 : Step(240): len = 674912, overlap = 43.8125
+PHY-3002 : Step(241): len = 676369, overlap = 43.625
+PHY-3002 : Step(242): len = 680067, overlap = 39.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 116/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 763448, over cnt = 2677(7%), over = 12114, worst = 42
+PHY-1001 : End global iterations; 1.823894s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (141.4%)
+
+PHY-1001 : Congestion index: top1 = 91.59, top5 = 69.15, top10 = 59.59, top15 = 54.09.
+PHY-3001 : End congestion estimation; 2.147556s wall, 2.875000s user + 0.015625s system = 2.890625s CPU (134.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.947826s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000118102
+PHY-3002 : Step(243): len = 671436, overlap = 261.156
+PHY-3002 : Step(244): len = 670077, overlap = 200
+PHY-3002 : Step(245): len = 658966, overlap = 176.406
+PHY-3002 : Step(246): len = 651119, overlap = 162.844
+PHY-3002 : Step(247): len = 645233, overlap = 150.062
+PHY-3002 : Step(248): len = 639586, overlap = 146
+PHY-3002 : Step(249): len = 637941, overlap = 140.531
+PHY-3002 : Step(250): len = 633654, overlap = 140.062
+PHY-3002 : Step(251): len = 630487, overlap = 131.562
+PHY-3002 : Step(252): len = 627120, overlap = 133.438
+PHY-3002 : Step(253): len = 623785, overlap = 142.812
+PHY-3002 : Step(254): len = 619973, overlap = 144.688
+PHY-3002 : Step(255): len = 618779, overlap = 148.406
+PHY-3002 : Step(256): len = 615366, overlap = 145.438
+PHY-3002 : Step(257): len = 612568, overlap = 140.562
+PHY-3002 : Step(258): len = 609868, overlap = 137.531
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000236205
+PHY-3002 : Step(259): len = 611364, overlap = 136.344
+PHY-3002 : Step(260): len = 614077, overlap = 130.812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000439571
+PHY-3002 : Step(261): len = 617809, overlap = 123.219
+PHY-3002 : Step(262): len = 628204, overlap = 112.781
+PHY-3002 : Step(263): len = 634881, overlap = 103.75
+PHY-3002 : Step(264): len = 631451, overlap = 105.469
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000879142
+PHY-3002 : Step(265): len = 635446, overlap = 99.9375
+PHY-3002 : Step(266): len = 644120, overlap = 88.375
+PHY-3002 : Step(267): len = 654306, overlap = 80.3125
+PHY-3002 : Step(268): len = 652232, overlap = 77.7188
+PHY-3002 : Step(269): len = 650816, overlap = 80.25
+PHY-3002 : Step(270): len = 650492, overlap = 79.7812
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84226, tnet num: 20425, tinst num: 18024, tnode num: 114666, tedge num: 134352.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.534421s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (99.8%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 565 MB, peak memory is 710 MB
+OPT-1001 : Total overflow 390.81 peak overflow 3.16
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 727/20603.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749008, over cnt = 3032(8%), over = 11044, worst = 24
+PHY-1001 : End global iterations; 1.367335s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (149.7%)
+
+PHY-1001 : Congestion index: top1 = 74.05, top5 = 59.11, top10 = 52.45, top15 = 48.36.
+PHY-1001 : End incremental global routing; 1.730119s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (140.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20425 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.215704s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.3%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17892 has valid locations, 297 needs to be replaced
+PHY-3001 : design contains 18274 instances, 7764 luts, 9289 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6162 pins
+PHY-3001 : Found 1262 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 674059
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17111/20853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 762952, over cnt = 3095(8%), over = 11044, worst = 24
+PHY-1001 : End global iterations; 0.257526s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (151.7%)
+
+PHY-1001 : Congestion index: top1 = 73.69, top5 = 59.26, top10 = 52.56, top15 = 48.58.
+PHY-3001 : End congestion estimation; 0.530192s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (123.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85224, tnet num: 20675, tinst num: 18274, tnode num: 116157, tedge num: 135848.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.544007s wall, 1.500000s user + 0.046875s system = 1.546875s CPU (100.2%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 612 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.568783s wall, 2.515625s user + 0.062500s system = 2.578125s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(271): len = 672836, overlap = 0
+PHY-3002 : Step(272): len = 672374, overlap = 0
+PHY-3002 : Step(273): len = 672036, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17189/20853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 761008, over cnt = 3084(8%), over = 11081, worst = 24
+PHY-1001 : End global iterations; 0.315635s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (128.7%)
+
+PHY-1001 : Congestion index: top1 = 74.50, top5 = 59.56, top10 = 52.93, top15 = 48.91.
+PHY-3001 : End congestion estimation; 0.595160s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (115.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.992445s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000462282
+PHY-3002 : Step(274): len = 671850, overlap = 82.2188
+PHY-3002 : Step(275): len = 671983, overlap = 82.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000924563
+PHY-3002 : Step(276): len = 672082, overlap = 82.3438
+PHY-3002 : Step(277): len = 672668, overlap = 82.5312
+PHY-3001 : Final: Len = 672668, Over = 82.5312
+PHY-3001 : End incremental placement; 5.364686s wall, 5.812500s user + 0.234375s system = 6.046875s CPU (112.7%)
+
+OPT-1001 : Total overflow 396.53 peak overflow 3.16
+OPT-1001 : End high-fanout net optimization; 8.875342s wall, 10.093750s user + 0.250000s system = 10.343750s CPU (116.5%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 731.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17167/20853.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 763984, over cnt = 3032(8%), over = 10041, worst = 24
+PHY-1002 : len = 814560, over cnt = 2109(5%), over = 5440, worst = 21
+PHY-1002 : len = 859704, over cnt = 889(2%), over = 2061, worst = 17
+PHY-1002 : len = 876704, over cnt = 362(1%), over = 822, worst = 17
+PHY-1002 : len = 887880, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.903486s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 60.62, top5 = 52.31, top10 = 48.25, top15 = 45.52.
+OPT-1001 : End congestion update; 2.182204s wall, 2.968750s user + 0.000000s system = 2.968750s CPU (136.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20675 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.849015s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.4%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 130 cells processed and 19100 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 25 cells processed and 3000 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 1200 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 150 slack improved
+OPT-1001 : End bottleneck based optimization; 3.479335s wall, 4.250000s user + 0.015625s system = 4.265625s CPU (122.6%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 694, peak = 731.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17173/20855.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 888016, over cnt = 92(0%), over = 130, worst = 3
+PHY-1002 : len = 887808, over cnt = 50(0%), over = 57, worst = 2
+PHY-1002 : len = 888056, over cnt = 26(0%), over = 29, worst = 2
+PHY-1002 : len = 888440, over cnt = 6(0%), over = 8, worst = 2
+PHY-1002 : len = 888616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.796036s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (108.0%)
+
+PHY-1001 : Congestion index: top1 = 60.04, top5 = 52.11, top10 = 48.12, top15 = 45.39.
+OPT-1001 : End congestion update; 1.098338s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (103.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20677 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.843731s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.0%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 5150 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.067918s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (102.0%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 702, peak = 731.
+OPT-1001 : End physical optimization; 16.283600s wall, 18.359375s user + 0.312500s system = 18.671875s CPU (114.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7764 LUT to BLE ...
+SYN-4008 : Packed 7764 LUT and 3153 SEQ to BLE.
+SYN-4003 : Packing 6138 remaining SEQ's ...
+SYN-4005 : Packed 4069 SEQ with LUT/SLICE
+SYN-4006 : 840 single LUT's are left
+SYN-4006 : 2069 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9833/13620 primitive instances ...
+PHY-3001 : End packing; 1.806620s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6711 instances
+RUN-1001 : 3281 mslices, 3282 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17837 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9941 nets have 2 pins
+RUN-1001 : 6540 nets have [3 - 5] pins
+RUN-1001 : 729 nets have [6 - 10] pins
+RUN-1001 : 295 nets have [11 - 20] pins
+RUN-1001 : 300 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6709 instances, 6563 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3591 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 681753, Over = 225.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7588/17837.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 832000, over cnt = 1995(5%), over = 3224, worst = 7
+PHY-1002 : len = 840528, over cnt = 1129(3%), over = 1566, worst = 6
+PHY-1002 : len = 850128, over cnt = 470(1%), over = 646, worst = 5
+PHY-1002 : len = 857624, over cnt = 132(0%), over = 158, worst = 5
+PHY-1002 : len = 861064, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations; 2.008309s wall, 2.843750s user + 0.062500s system = 2.906250s CPU (144.7%)
+
+PHY-1001 : Congestion index: top1 = 58.79, top5 = 51.68, top10 = 47.32, top15 = 44.48.
+PHY-3001 : End congestion estimation; 2.440790s wall, 3.265625s user + 0.062500s system = 3.328125s CPU (136.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71474, tnet num: 17659, tinst num: 6709, tnode num: 93874, tedge num: 118861.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.700614s wall, 1.687500s user + 0.015625s system = 1.703125s CPU (100.1%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 608 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17659 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.614011s wall, 2.578125s user + 0.031250s system = 2.609375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.72015e-05
+PHY-3002 : Step(278): len = 670300, overlap = 231
+PHY-3002 : Step(279): len = 664243, overlap = 239.25
+PHY-3002 : Step(280): len = 660120, overlap = 239.5
+PHY-3002 : Step(281): len = 657251, overlap = 241.25
+PHY-3002 : Step(282): len = 654886, overlap = 242.25
+PHY-3002 : Step(283): len = 652414, overlap = 249.75
+PHY-3002 : Step(284): len = 649996, overlap = 244.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000114403
+PHY-3002 : Step(285): len = 652237, overlap = 238
+PHY-3002 : Step(286): len = 655649, overlap = 231.25
+PHY-3002 : Step(287): len = 655538, overlap = 230.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000228806
+PHY-3002 : Step(288): len = 660614, overlap = 228.5
+PHY-3002 : Step(289): len = 666015, overlap = 218.5
+PHY-3002 : Step(290): len = 666757, overlap = 216.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.398225s wall, 0.359375s user + 0.718750s system = 1.078125s CPU (270.7%)
+
+PHY-3001 : Trial Legalized: Len = 752703
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 815/17837.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861304, over cnt = 2624(7%), over = 4373, worst = 9
+PHY-1002 : len = 876432, over cnt = 1585(4%), over = 2392, worst = 9
+PHY-1002 : len = 898600, over cnt = 486(1%), over = 705, worst = 9
+PHY-1002 : len = 908344, over cnt = 118(0%), over = 165, worst = 4
+PHY-1002 : len = 911048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.725864s wall, 3.812500s user + 0.046875s system = 3.859375s CPU (141.6%)
+
+PHY-1001 : Congestion index: top1 = 57.52, top5 = 51.61, top10 = 48.11, top15 = 45.73.
+PHY-3001 : End congestion estimation; 3.228562s wall, 4.296875s user + 0.046875s system = 4.343750s CPU (134.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17659 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.985225s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000176664
+PHY-3002 : Step(291): len = 724847, overlap = 41
+PHY-3002 : Step(292): len = 708464, overlap = 61.25
+PHY-3002 : Step(293): len = 696857, overlap = 81.25
+PHY-3002 : Step(294): len = 688096, overlap = 99.25
+PHY-3002 : Step(295): len = 683262, overlap = 115.25
+PHY-3002 : Step(296): len = 680030, overlap = 131.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000353329
+PHY-3002 : Step(297): len = 683561, overlap = 131.25
+PHY-3002 : Step(298): len = 687240, overlap = 125.75
+PHY-3002 : Step(299): len = 687026, overlap = 128
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000706658
+PHY-3002 : Step(300): len = 690167, overlap = 124
+PHY-3002 : Step(301): len = 697466, overlap = 125.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.035636s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (131.5%)
+
+PHY-3001 : Legalized: Len = 724377, Over = 0
+PHY-3001 : Spreading special nets. 471 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.110151s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.3%)
+
+PHY-3001 : 677 instances has been re-located, deltaX = 193, deltaY = 367, maxDist = 2.
+PHY-3001 : Final: Len = 733715, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71474, tnet num: 17659, tinst num: 6712, tnode num: 93874, tedge num: 118861.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.952748s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (100.0%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 633 MB, peak memory is 731 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4252/17837.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 854048, over cnt = 2422(6%), over = 3887, worst = 7
+PHY-1002 : len = 866672, over cnt = 1528(4%), over = 2144, worst = 6
+PHY-1002 : len = 884960, over cnt = 470(1%), over = 645, worst = 6
+PHY-1002 : len = 893536, over cnt = 76(0%), over = 88, worst = 3
+PHY-1002 : len = 895056, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.126746s wall, 3.140625s user + 0.046875s system = 3.187500s CPU (149.9%)
+
+PHY-1001 : Congestion index: top1 = 58.23, top5 = 50.37, top10 = 46.65, top15 = 44.52.
+PHY-1001 : End incremental global routing; 2.552564s wall, 3.562500s user + 0.046875s system = 3.609375s CPU (141.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17659 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.934686s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.3%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6619 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3670 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 738351
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16224/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900696, over cnt = 91(0%), over = 105, worst = 5
+PHY-1002 : len = 900792, over cnt = 47(0%), over = 52, worst = 3
+PHY-1002 : len = 901112, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 901216, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 901312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.842877s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 58.34, top5 = 50.43, top10 = 46.73, top15 = 44.60.
+PHY-3001 : End congestion estimation; 1.173976s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71675, tnet num: 17678, tinst num: 6733, tnode num: 94116, tedge num: 119103.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.927346s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (99.7%)
+
+RUN-1004 : used memory is 680 MB, reserved memory is 676 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.846735s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(302): len = 737349, overlap = 0
+PHY-3002 : Step(303): len = 736503, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16206/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898512, over cnt = 73(0%), over = 88, worst = 3
+PHY-1002 : len = 898712, over cnt = 22(0%), over = 22, worst = 1
+PHY-1002 : len = 898888, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 898968, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 899160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.809167s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 58.30, top5 = 50.41, top10 = 46.71, top15 = 44.61.
+PHY-3001 : End congestion estimation; 1.142358s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (102.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.900663s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000429163
+PHY-3002 : Step(304): len = 736331, overlap = 0.5
+PHY-3002 : Step(305): len = 736175, overlap = 0.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.008738s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 736196, Over = 0
+PHY-3001 : End spreading; 0.063748s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.0%)
+
+PHY-3001 : Final: Len = 736196, Over = 0
+PHY-3001 : End incremental placement; 6.586007s wall, 6.640625s user + 0.187500s system = 6.828125s CPU (103.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.585931s wall, 11.656250s user + 0.234375s system = 11.890625s CPU (112.3%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 729, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16209/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898368, over cnt = 39(0%), over = 56, worst = 6
+PHY-1002 : len = 898544, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 898600, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 898648, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.612254s wall, 0.671875s user + 0.015625s system = 0.687500s CPU (112.3%)
+
+PHY-1001 : Congestion index: top1 = 58.15, top5 = 50.33, top10 = 46.61, top15 = 44.50.
+OPT-1001 : End congestion update; 0.950336s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (108.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.781712s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3670 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 742167, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070408s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.0%)
+
+PHY-3001 : 38 instances has been re-located, deltaX = 25, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 742725, Over = 0
+PHY-3001 : End incremental legalization; 0.451118s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 62 cells processed and 21571 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6645 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6733 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3670 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 743149, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063894s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.8%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 8, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 743595, Over = 0
+PHY-3001 : End incremental legalization; 0.412385s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.3%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 19 cells processed and 3012 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6647 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6735 instances, 6586 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 743669, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061986s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 743661, Over = 0
+PHY-3001 : End incremental legalization; 0.432069s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.6%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 2 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.539985s wall, 3.703125s user + 0.015625s system = 3.718750s CPU (105.0%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15828/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906072, over cnt = 165(0%), over = 219, worst = 4
+PHY-1002 : len = 906704, over cnt = 71(0%), over = 81, worst = 3
+PHY-1002 : len = 907560, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 907728, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 907776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.916695s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 57.11, top5 = 49.90, top10 = 46.44, top15 = 44.35.
+OPT-1001 : End congestion update; 1.262132s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (104.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.760851s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.6%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6647 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6735 instances, 6586 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 743689, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063384s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.6%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 743797, Over = 0
+PHY-3001 : End incremental legalization; 0.412058s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (94.8%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 10 cells processed and 1400 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.567137s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (104.1%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.761599s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16207/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 907760, over cnt = 36(0%), over = 42, worst = 4
+PHY-1002 : len = 907816, over cnt = 25(0%), over = 25, worst = 1
+PHY-1002 : len = 908024, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 908088, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 908088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.801682s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 49.86, top10 = 46.43, top15 = 44.39.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.762273s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (98.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.586207
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6647 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6735 instances, 6586 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 743797, Over = 0
+PHY-3001 : End spreading; 0.063726s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.1%)
+
+PHY-3001 : Final: Len = 743797, Over = 0
+PHY-3001 : End incremental legalization; 0.409299s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.754820s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.4%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16247/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.137060s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.6%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 49.86, top10 = 46.43, top15 = 44.39.
+OPT-1001 : End congestion update; 0.471675s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.765602s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6647 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6735 instances, 6586 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 743775, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067762s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 743797, Over = 0
+PHY-3001 : End incremental legalization; 0.444823s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (115.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.809231s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (108.8%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16247/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.141955s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.1%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 49.86, top10 = 46.43, top15 = 44.39.
+OPT-1001 : End congestion update; 0.496287s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (100.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.759728s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (100.8%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6647 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6735 instances, 6586 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 743775, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063249s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 743797, Over = 0
+PHY-3001 : End incremental legalization; 0.448160s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (94.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6647 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6735 instances, 6586 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 510 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 743775, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059951s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 743797, Over = 0
+PHY-3001 : End incremental legalization; 0.411250s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (121.6%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.413568s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (112.0%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.762138s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 735.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.771086s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.3%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16247/17856.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.136943s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 49.86, top10 = 46.43, top15 = 44.39.
+RUN-1001 : End congestion update; 0.485584s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (99.8%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.259892s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (99.2%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 735.
+OPT-1001 : End physical optimization; 29.124569s wall, 31.031250s user + 0.296875s system = 31.328125s CPU (107.6%)
+
+RUN-1003 : finish command "place" in 76.954842s wall, 111.640625s user + 6.281250s system = 117.921875s CPU (153.2%)
+
+RUN-1004 : used memory is 676 MB, reserved memory is 679 MB, peak memory is 735 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.801910s wall, 3.078125s user + 0.000000s system = 3.078125s CPU (170.8%)
+
+RUN-1004 : used memory is 676 MB, reserved memory is 680 MB, peak memory is 735 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6737 instances
+RUN-1001 : 3286 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17856 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9926 nets have 2 pins
+RUN-1001 : 6552 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 302 nets have [11 - 20] pins
+RUN-1001 : 313 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71690, tnet num: 17678, tinst num: 6735, tnode num: 94138, tedge num: 119125.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.684446s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.2%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 655 MB, peak memory is 735 MB
+PHY-1001 : 3286 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841976, over cnt = 2604(7%), over = 4297, worst = 8
+PHY-1002 : len = 860296, over cnt = 1485(4%), over = 2105, worst = 7
+PHY-1002 : len = 879872, over cnt = 391(1%), over = 548, worst = 6
+PHY-1002 : len = 888664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.296671s wall, 4.359375s user + 0.015625s system = 4.375000s CPU (132.7%)
+
+PHY-1001 : Congestion index: top1 = 56.16, top5 = 49.46, top10 = 45.78, top15 = 43.65.
+PHY-1001 : End global routing; 3.651317s wall, 4.718750s user + 0.015625s system = 4.734375s CPU (129.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 707, peak = 735.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 980, reserve = 982, peak = 980.
+PHY-1001 : End build detailed router design. 4.289677s wall, 4.218750s user + 0.062500s system = 4.281250s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267552, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.716176s wall, 5.687500s user + 0.031250s system = 5.718750s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267608, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.494436s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.1%)
+
+PHY-1001 : Current memory(MB): used = 1016, reserve = 1019, peak = 1016.
+PHY-1001 : End phase 1; 6.223112s wall, 6.203125s user + 0.031250s system = 6.234375s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.26383e+06, over cnt = 1782(0%), over = 1791, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1035, peak = 1032.
+PHY-1001 : End initial routed; 35.962976s wall, 66.000000s user + 0.281250s system = 66.281250s CPU (184.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16779(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.947 | -0.947 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.473432s wall, 3.468750s user + 0.015625s system = 3.484375s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1047, peak = 1042.
+PHY-1001 : End phase 2; 39.436471s wall, 69.468750s user + 0.296875s system = 69.765625s CPU (176.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.166764s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.7%)
+
+PHY-1022 : len = 2.26385e+06, over cnt = 1782(0%), over = 1791, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.446070s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.23066e+06, over cnt = 667(0%), over = 668, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.662864s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (190.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.22906e+06, over cnt = 119(0%), over = 119, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.967081s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (143.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.22983e+06, over cnt = 19(0%), over = 19, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.455037s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (113.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.23009e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.282421s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (110.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.240791s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (103.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.229038s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.3%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.262539s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.205626s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.196836s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.215277s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.276433s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.307246s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (101.7%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.23022e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.190923s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (139.1%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.23023e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.175933s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16779(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.805 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.650704s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (99.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 554 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.474584s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (98.5%)
+
+PHY-1001 : Current memory(MB): used = 1143, reserve = 1152, peak = 1143.
+PHY-1001 : End phase 3; 12.701012s wall, 14.718750s user + 0.015625s system = 14.734375s CPU (116.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.805ns STNS -0.805ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.184120s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.8%)
+
+PHY-1022 : len = 2.23023e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.528562s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.805ns, -0.805ns, 1}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.23022e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.181118s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16779(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.947 | -0.947 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.606594s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1160, peak = 1151.
+PHY-1001 : End phase 4; 4.382005s wall, 4.343750s user + 0.000000s system = 4.343750s CPU (99.1%)
+
+PHY-1003 : Routed, final wirelength = 2.23022e+06
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1160, peak = 1151.
+PHY-1001 : End export database. 0.066433s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.6%)
+
+PHY-1001 : End detail routing; 67.515422s wall, 99.437500s user + 0.406250s system = 99.843750s CPU (147.9%)
+
+RUN-1003 : finish command "route" in 73.968123s wall, 106.921875s user + 0.453125s system = 107.375000s CPU (145.2%)
+
+RUN-1004 : used memory is 1077 MB, reserved memory is 1084 MB, peak memory is 1151 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10198 out of 19600 52.03%
+#reg 9470 out of 19600 48.32%
+#le 12240
+ #lut only 2770 out of 12240 22.63%
+ #reg only 2042 out of 12240 16.68%
+ #lut® 7428 out of 12240 60.69%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1769
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1404
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1309
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 957
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/reg6_syn_49.q0 135
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg11_syn_135.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice reg34_syn_174.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P82 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P104 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P15 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P39 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P32 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P163 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P109 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P107 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12240 |9171 |1027 |9504 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |507 |387 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |97 |86 |4 |85 |4 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |9 |0 |0 |
+| U_crc16_24b |crc16_24b |24 |24 |0 |16 |0 |0 |
+| exdev_ctl_a |exdev_ctl |770 |365 |96 |592 |0 |0 |
+| u_ADconfig |AD_config |189 |122 |25 |146 |0 |0 |
+| u_gen_sp |gen_sp |257 |139 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |735 |390 |96 |561 |0 |0 |
+| u_ADconfig |AD_config |169 |120 |25 |127 |0 |0 |
+| u_gen_sp |gen_sp |258 |141 |71 |126 |0 |0 |
+| sampling_fe_a |sampling_fe |2928 |2402 |306 |2033 |25 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |146 |17 |143 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |2713 |2252 |289 |1859 |25 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2339 |1946 |253 |1539 |22 |0 |
+| channelPart |channel_part_8478 |117 |112 |3 |112 |0 |0 |
+| fifo_adc |fifo_adc |56 |47 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1885 |1561 |197 |1177 |0 |0 |
+| adc_addr_gen |adc_addr_gen |224 |197 |27 |109 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |9 |6 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |32 |29 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| insert |insert |970 |673 |170 |680 |0 |0 |
+| ram_switch_state |ram_switch_state |691 |691 |0 |388 |0 |0 |
+| read_ram_i |read_ram |253 |204 |44 |180 |0 |0 |
+| read_ram_addr |read_ram_addr |209 |169 |40 |145 |0 |0 |
+| read_ram_data |read_ram_data |44 |35 |4 |35 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |309 |243 |36 |271 |3 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3134 |2488 |349 |2068 |25 |1 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |186 |99 |17 |157 |0 |0 |
+| u_sort |sort_rev |2914 |2369 |332 |1877 |25 |1 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2522 |2068 |290 |1548 |22 |1 |
+| channelPart |channel_part_8478 |144 |135 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1937 |1608 |197 |1134 |0 |0 |
+| adc_addr_gen |adc_addr_gen |213 |186 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |23 |20 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |28 |25 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| insert |insert |976 |676 |170 |670 |0 |0 |
+| ram_switch_state |ram_switch_state |748 |746 |0 |359 |0 |0 |
+| read_ram_i |read_ram_rev |350 |251 |81 |202 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |209 |73 |159 |0 |0 |
+| read_ram_data |read_ram_data_rev |59 |42 |8 |43 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9864
+ #2 2 4288
+ #3 3 1694
+ #4 4 567
+ #5 5-10 776
+ #6 11-50 562
+ #7 51-100 9
+ #8 >500 1
+ Average 2.73
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.080096s wall, 3.578125s user + 0.031250s system = 3.609375s CPU (173.5%)
+
+RUN-1004 : used memory is 1078 MB, reserved memory is 1085 MB, peak memory is 1151 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71690, tnet num: 17678, tinst num: 6735, tnode num: 94138, tedge num: 119125.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.644247s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.8%)
+
+RUN-1004 : used memory is 1082 MB, reserved memory is 1089 MB, peak memory is 1151 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17678 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.489266s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (100.7%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1091 MB, peak memory is 1151 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6735
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17856, pip num: 167489
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 554
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3253 valid insts, and 468209 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.465093s wall, 59.000000s user + 0.265625s system = 59.265625s CPU (626.1%)
+
+RUN-1004 : used memory is 1234 MB, reserved memory is 1236 MB, peak memory is 1349 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_095821.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_100526.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_100526.log
new file mode 100644
index 0000000..33be5c8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_100526.log
@@ -0,0 +1,3293 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 10:05:26 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.343046s wall, 2.203125s user + 0.140625s system = 2.343750s CPU (100.0%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2951 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18102 instances
+RUN-0007 : 7652 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20679 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13190 nets have 2 pins
+RUN-1001 : 6454 nets have [3 - 5] pins
+RUN-1001 : 616 nets have [6 - 10] pins
+RUN-1001 : 180 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 798
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3627
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18100 instances, 7652 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6052 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84535, tnet num: 20501, tinst num: 18100, tnode num: 115269, tedge num: 134818.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.245313s wall, 1.203125s user + 0.031250s system = 1.234375s CPU (99.1%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 517 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.086180s wall, 2.031250s user + 0.046875s system = 2.078125s CPU (99.6%)
+
+PHY-3001 : Found 1247 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.12437e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18100.
+PHY-3001 : Level 1 #clusters 2047.
+PHY-3001 : End clustering; 0.143585s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (119.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32055e+06, overlap = 484.562
+PHY-3002 : Step(2): len = 1.2281e+06, overlap = 494.688
+PHY-3002 : Step(3): len = 886277, overlap = 588.031
+PHY-3002 : Step(4): len = 800942, overlap = 635.969
+PHY-3002 : Step(5): len = 625464, overlap = 795.344
+PHY-3002 : Step(6): len = 578197, overlap = 846.375
+PHY-3002 : Step(7): len = 478550, overlap = 945.531
+PHY-3002 : Step(8): len = 437944, overlap = 995.125
+PHY-3002 : Step(9): len = 389134, overlap = 1041.44
+PHY-3002 : Step(10): len = 362920, overlap = 1072.03
+PHY-3002 : Step(11): len = 320039, overlap = 1151.75
+PHY-3002 : Step(12): len = 297063, overlap = 1226.91
+PHY-3002 : Step(13): len = 269402, overlap = 1291.16
+PHY-3002 : Step(14): len = 246718, overlap = 1298.66
+PHY-3002 : Step(15): len = 223200, overlap = 1343.59
+PHY-3002 : Step(16): len = 208144, overlap = 1368.62
+PHY-3002 : Step(17): len = 188780, overlap = 1409.16
+PHY-3002 : Step(18): len = 176665, overlap = 1432.25
+PHY-3002 : Step(19): len = 159076, overlap = 1460.47
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.16373e-06
+PHY-3002 : Step(20): len = 163558, overlap = 1428.22
+PHY-3002 : Step(21): len = 207152, overlap = 1309.12
+PHY-3002 : Step(22): len = 214405, overlap = 1228.44
+PHY-3002 : Step(23): len = 216384, overlap = 1127.72
+PHY-3002 : Step(24): len = 208818, overlap = 1103.91
+PHY-3002 : Step(25): len = 206198, overlap = 1114.53
+PHY-3002 : Step(26): len = 200716, overlap = 1087.25
+PHY-3002 : Step(27): len = 198941, overlap = 1068.16
+PHY-3002 : Step(28): len = 193027, overlap = 1054.59
+PHY-3002 : Step(29): len = 190292, overlap = 1043.91
+PHY-3002 : Step(30): len = 186589, overlap = 1053.72
+PHY-3002 : Step(31): len = 185683, overlap = 1065.84
+PHY-3002 : Step(32): len = 183694, overlap = 1078.81
+PHY-3002 : Step(33): len = 182313, overlap = 1086.22
+PHY-3002 : Step(34): len = 181093, overlap = 1096.66
+PHY-3002 : Step(35): len = 180029, overlap = 1114.06
+PHY-3002 : Step(36): len = 178528, overlap = 1124.44
+PHY-3002 : Step(37): len = 177679, overlap = 1118.06
+PHY-3002 : Step(38): len = 176992, overlap = 1103.34
+PHY-3002 : Step(39): len = 174958, overlap = 1100.97
+PHY-3002 : Step(40): len = 173667, overlap = 1084.28
+PHY-3002 : Step(41): len = 172425, overlap = 1086.06
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.32745e-06
+PHY-3002 : Step(42): len = 174945, overlap = 1070.38
+PHY-3002 : Step(43): len = 185230, overlap = 1035.31
+PHY-3002 : Step(44): len = 190021, overlap = 1034
+PHY-3002 : Step(45): len = 194853, overlap = 1046.88
+PHY-3002 : Step(46): len = 196819, overlap = 1033.44
+PHY-3002 : Step(47): len = 198591, overlap = 992.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.6549e-06
+PHY-3002 : Step(48): len = 206972, overlap = 975.688
+PHY-3002 : Step(49): len = 230011, overlap = 914.875
+PHY-3002 : Step(50): len = 240222, overlap = 864.375
+PHY-3002 : Step(51): len = 247037, overlap = 835.969
+PHY-3002 : Step(52): len = 248039, overlap = 801.031
+PHY-3002 : Step(53): len = 248628, overlap = 775.688
+PHY-3002 : Step(54): len = 247787, overlap = 777.375
+PHY-3002 : Step(55): len = 245448, overlap = 776.188
+PHY-3002 : Step(56): len = 244806, overlap = 781.906
+PHY-3002 : Step(57): len = 244878, overlap = 764.031
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.3098e-06
+PHY-3002 : Step(58): len = 260260, overlap = 717.188
+PHY-3002 : Step(59): len = 275128, overlap = 656.188
+PHY-3002 : Step(60): len = 280317, overlap = 588.75
+PHY-3002 : Step(61): len = 286273, overlap = 571.188
+PHY-3002 : Step(62): len = 287673, overlap = 565.75
+PHY-3002 : Step(63): len = 288488, overlap = 523.719
+PHY-3002 : Step(64): len = 288070, overlap = 520.938
+PHY-3002 : Step(65): len = 287424, overlap = 520.219
+PHY-3002 : Step(66): len = 287576, overlap = 516.062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.86196e-05
+PHY-3002 : Step(67): len = 303883, overlap = 470.875
+PHY-3002 : Step(68): len = 316445, overlap = 439.375
+PHY-3002 : Step(69): len = 319423, overlap = 410.656
+PHY-3002 : Step(70): len = 325278, overlap = 375.312
+PHY-3002 : Step(71): len = 327234, overlap = 394.094
+PHY-3002 : Step(72): len = 329689, overlap = 391
+PHY-3002 : Step(73): len = 327745, overlap = 394.219
+PHY-3002 : Step(74): len = 328670, overlap = 405.312
+PHY-3002 : Step(75): len = 329328, overlap = 398.875
+PHY-3002 : Step(76): len = 329639, overlap = 399.406
+PHY-3002 : Step(77): len = 328186, overlap = 392.375
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.72392e-05
+PHY-3002 : Step(78): len = 343858, overlap = 384.281
+PHY-3002 : Step(79): len = 356117, overlap = 367.406
+PHY-3002 : Step(80): len = 359922, overlap = 336.188
+PHY-3002 : Step(81): len = 362176, overlap = 332.219
+PHY-3002 : Step(82): len = 364358, overlap = 325.281
+PHY-3002 : Step(83): len = 368308, overlap = 315.156
+PHY-3002 : Step(84): len = 367249, overlap = 323.75
+PHY-3002 : Step(85): len = 368153, overlap = 306.75
+PHY-3002 : Step(86): len = 370375, overlap = 297.781
+PHY-3002 : Step(87): len = 372937, overlap = 293.625
+PHY-3002 : Step(88): len = 373507, overlap = 287.156
+PHY-3002 : Step(89): len = 376560, overlap = 266.625
+PHY-3002 : Step(90): len = 376615, overlap = 250.031
+PHY-3002 : Step(91): len = 377494, overlap = 251.281
+PHY-3002 : Step(92): len = 375602, overlap = 254.812
+PHY-3002 : Step(93): len = 375700, overlap = 266.562
+PHY-3002 : Step(94): len = 375700, overlap = 271.344
+PHY-3002 : Step(95): len = 373903, overlap = 275.406
+PHY-3002 : Step(96): len = 372360, overlap = 279.812
+PHY-3002 : Step(97): len = 372111, overlap = 289.469
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.44784e-05
+PHY-3002 : Step(98): len = 387919, overlap = 270.062
+PHY-3002 : Step(99): len = 400052, overlap = 255.812
+PHY-3002 : Step(100): len = 400196, overlap = 225.344
+PHY-3002 : Step(101): len = 401020, overlap = 227.375
+PHY-3002 : Step(102): len = 404169, overlap = 218.969
+PHY-3002 : Step(103): len = 406435, overlap = 226.625
+PHY-3002 : Step(104): len = 404724, overlap = 225.344
+PHY-3002 : Step(105): len = 405887, overlap = 223.75
+PHY-3002 : Step(106): len = 406317, overlap = 225.594
+PHY-3002 : Step(107): len = 407372, overlap = 230.156
+PHY-3002 : Step(108): len = 406738, overlap = 220.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000145268
+PHY-3002 : Step(109): len = 420393, overlap = 218.25
+PHY-3002 : Step(110): len = 429581, overlap = 216
+PHY-3002 : Step(111): len = 429625, overlap = 205.625
+PHY-3002 : Step(112): len = 431282, overlap = 203.938
+PHY-3002 : Step(113): len = 433467, overlap = 215.5
+PHY-3002 : Step(114): len = 435858, overlap = 210.469
+PHY-3002 : Step(115): len = 434802, overlap = 206.375
+PHY-3002 : Step(116): len = 436768, overlap = 204.875
+PHY-3002 : Step(117): len = 439403, overlap = 207.188
+PHY-3002 : Step(118): len = 441893, overlap = 205.469
+PHY-3002 : Step(119): len = 439914, overlap = 202.25
+PHY-3002 : Step(120): len = 440357, overlap = 209.031
+PHY-3002 : Step(121): len = 442184, overlap = 207.094
+PHY-3002 : Step(122): len = 443390, overlap = 211.969
+PHY-3002 : Step(123): len = 441297, overlap = 212.625
+PHY-3002 : Step(124): len = 441230, overlap = 211.344
+PHY-3002 : Step(125): len = 442568, overlap = 214.031
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000290535
+PHY-3002 : Step(126): len = 454960, overlap = 206.25
+PHY-3002 : Step(127): len = 465186, overlap = 212.25
+PHY-3002 : Step(128): len = 467424, overlap = 216.812
+PHY-3002 : Step(129): len = 469566, overlap = 204.031
+PHY-3002 : Step(130): len = 471770, overlap = 209.094
+PHY-3002 : Step(131): len = 475845, overlap = 204.438
+PHY-3002 : Step(132): len = 475567, overlap = 205.094
+PHY-3002 : Step(133): len = 476778, overlap = 206.531
+PHY-3002 : Step(134): len = 478468, overlap = 210.438
+PHY-3002 : Step(135): len = 480488, overlap = 212.312
+PHY-3002 : Step(136): len = 479627, overlap = 195.438
+PHY-3002 : Step(137): len = 479346, overlap = 194.125
+PHY-3002 : Step(138): len = 479405, overlap = 194.312
+PHY-3002 : Step(139): len = 479946, overlap = 192.344
+PHY-3002 : Step(140): len = 478689, overlap = 179.5
+PHY-3002 : Step(141): len = 478398, overlap = 173.219
+PHY-3002 : Step(142): len = 478878, overlap = 181.219
+PHY-3002 : Step(143): len = 479873, overlap = 183.531
+PHY-3002 : Step(144): len = 478911, overlap = 185.406
+PHY-3002 : Step(145): len = 479176, overlap = 180.969
+PHY-3002 : Step(146): len = 479143, overlap = 183.656
+PHY-3002 : Step(147): len = 479311, overlap = 187.812
+PHY-3002 : Step(148): len = 478406, overlap = 192.75
+PHY-3002 : Step(149): len = 478872, overlap = 189.188
+PHY-3002 : Step(150): len = 479265, overlap = 180.812
+PHY-3002 : Step(151): len = 479571, overlap = 181.531
+PHY-3002 : Step(152): len = 478968, overlap = 186.25
+PHY-3002 : Step(153): len = 479064, overlap = 186.469
+PHY-3002 : Step(154): len = 479607, overlap = 182.625
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000555082
+PHY-3002 : Step(155): len = 487014, overlap = 184.5
+PHY-3002 : Step(156): len = 495954, overlap = 174.125
+PHY-3002 : Step(157): len = 496012, overlap = 167.375
+PHY-3002 : Step(158): len = 496226, overlap = 169.219
+PHY-3002 : Step(159): len = 497996, overlap = 170.062
+PHY-3002 : Step(160): len = 499244, overlap = 168.031
+PHY-3002 : Step(161): len = 498310, overlap = 161.438
+PHY-3002 : Step(162): len = 498434, overlap = 166.344
+PHY-3002 : Step(163): len = 500808, overlap = 164.75
+PHY-3002 : Step(164): len = 502439, overlap = 164.031
+PHY-3002 : Step(165): len = 500929, overlap = 170.344
+PHY-3002 : Step(166): len = 500699, overlap = 170.531
+PHY-3002 : Step(167): len = 501774, overlap = 167.688
+PHY-3002 : Step(168): len = 502732, overlap = 166.812
+PHY-3002 : Step(169): len = 502015, overlap = 167.656
+PHY-3002 : Step(170): len = 502259, overlap = 170.938
+PHY-3002 : Step(171): len = 503804, overlap = 172.312
+PHY-3002 : Step(172): len = 504495, overlap = 171.062
+PHY-3002 : Step(173): len = 503662, overlap = 170.25
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000983845
+PHY-3002 : Step(174): len = 508000, overlap = 168.281
+PHY-3002 : Step(175): len = 513606, overlap = 161.969
+PHY-3002 : Step(176): len = 513934, overlap = 158.531
+PHY-3002 : Step(177): len = 514517, overlap = 155.562
+PHY-3002 : Step(178): len = 517247, overlap = 159.25
+PHY-3002 : Step(179): len = 519236, overlap = 154.844
+PHY-3002 : Step(180): len = 518908, overlap = 156.031
+PHY-3002 : Step(181): len = 519280, overlap = 156.844
+PHY-3002 : Step(182): len = 521024, overlap = 154.938
+PHY-3002 : Step(183): len = 521626, overlap = 156.594
+PHY-3002 : Step(184): len = 520735, overlap = 155.281
+PHY-3002 : Step(185): len = 520589, overlap = 156.844
+PHY-3002 : Step(186): len = 521271, overlap = 154.5
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00178944
+PHY-3002 : Step(187): len = 524777, overlap = 156.312
+PHY-3002 : Step(188): len = 533149, overlap = 155.375
+PHY-3002 : Step(189): len = 537180, overlap = 158.094
+PHY-3002 : Step(190): len = 541386, overlap = 148.156
+PHY-3002 : Step(191): len = 544657, overlap = 146.625
+PHY-3002 : Step(192): len = 546860, overlap = 147.312
+PHY-3002 : Step(193): len = 547214, overlap = 141.094
+PHY-3002 : Step(194): len = 547719, overlap = 136.844
+PHY-3002 : Step(195): len = 548793, overlap = 136.438
+PHY-3002 : Step(196): len = 549388, overlap = 137.844
+PHY-3002 : Step(197): len = 549398, overlap = 140.094
+PHY-3002 : Step(198): len = 549459, overlap = 139.656
+PHY-3002 : Step(199): len = 549720, overlap = 139.75
+PHY-3002 : Step(200): len = 549794, overlap = 138.625
+PHY-3002 : Step(201): len = 549635, overlap = 139.906
+PHY-3002 : Step(202): len = 549605, overlap = 138.656
+PHY-3002 : Step(203): len = 549730, overlap = 135.688
+PHY-3002 : Step(204): len = 549685, overlap = 137.25
+PHY-3002 : Step(205): len = 549553, overlap = 137.969
+PHY-3002 : Step(206): len = 549978, overlap = 143.094
+PHY-3002 : Step(207): len = 550431, overlap = 139.031
+PHY-3002 : Step(208): len = 550588, overlap = 141.094
+PHY-3002 : Step(209): len = 550400, overlap = 142.625
+PHY-3002 : Step(210): len = 550388, overlap = 145.906
+PHY-3002 : Step(211): len = 550426, overlap = 138.938
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00308123
+PHY-3002 : Step(212): len = 552041, overlap = 144.438
+PHY-3002 : Step(213): len = 555876, overlap = 148.344
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.016324s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (95.7%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738664, over cnt = 1630(4%), over = 7564, worst = 40
+PHY-1001 : End global iterations; 0.790954s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (136.3%)
+
+PHY-1001 : Congestion index: top1 = 86.06, top5 = 63.68, top10 = 53.87, top15 = 48.14.
+PHY-3001 : End congestion estimation; 1.072708s wall, 1.328125s user + 0.031250s system = 1.359375s CPU (126.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.925080s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164242
+PHY-3002 : Step(214): len = 664123, overlap = 105.406
+PHY-3002 : Step(215): len = 662767, overlap = 101
+PHY-3002 : Step(216): len = 657618, overlap = 100.75
+PHY-3002 : Step(217): len = 653087, overlap = 93.9688
+PHY-3002 : Step(218): len = 649500, overlap = 90.2812
+PHY-3002 : Step(219): len = 648259, overlap = 80.9062
+PHY-3002 : Step(220): len = 648327, overlap = 72.0312
+PHY-3002 : Step(221): len = 647400, overlap = 55.0938
+PHY-3002 : Step(222): len = 647216, overlap = 47.125
+PHY-3002 : Step(223): len = 643980, overlap = 48.1562
+PHY-3002 : Step(224): len = 640075, overlap = 49.0625
+PHY-3002 : Step(225): len = 636663, overlap = 53.5
+PHY-3002 : Step(226): len = 634478, overlap = 52.5312
+PHY-3002 : Step(227): len = 631968, overlap = 55.375
+PHY-3002 : Step(228): len = 630350, overlap = 56.9062
+PHY-3002 : Step(229): len = 630830, overlap = 52.8125
+PHY-3002 : Step(230): len = 630460, overlap = 45.1562
+PHY-3002 : Step(231): len = 628617, overlap = 44.4375
+PHY-3002 : Step(232): len = 626471, overlap = 39.0625
+PHY-3002 : Step(233): len = 626144, overlap = 37.1875
+PHY-3002 : Step(234): len = 625495, overlap = 37
+PHY-3002 : Step(235): len = 624561, overlap = 37.0312
+PHY-3002 : Step(236): len = 623933, overlap = 36.2812
+PHY-3002 : Step(237): len = 624147, overlap = 36.3438
+PHY-3002 : Step(238): len = 622229, overlap = 40.1875
+PHY-3002 : Step(239): len = 621527, overlap = 40.5938
+PHY-3002 : Step(240): len = 619595, overlap = 41.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328484
+PHY-3002 : Step(241): len = 622911, overlap = 40.7812
+PHY-3002 : Step(242): len = 629450, overlap = 37.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000581853
+PHY-3002 : Step(243): len = 632368, overlap = 35.6562
+PHY-3002 : Step(244): len = 650684, overlap = 27.8438
+PHY-3002 : Step(245): len = 664020, overlap = 25.0938
+PHY-3002 : Step(246): len = 662482, overlap = 25.8125
+PHY-3002 : Step(247): len = 660184, overlap = 26.7812
+PHY-3002 : Step(248): len = 658672, overlap = 27.9688
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 58/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744984, over cnt = 2745(7%), over = 12282, worst = 52
+PHY-1001 : End global iterations; 1.852224s wall, 2.484375s user + 0.015625s system = 2.500000s CPU (135.0%)
+
+PHY-1001 : Congestion index: top1 = 88.04, top5 = 68.45, top10 = 59.50, top15 = 54.10.
+PHY-3001 : End congestion estimation; 2.149218s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (130.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.397796s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000115161
+PHY-3002 : Step(249): len = 652893, overlap = 229.938
+PHY-3002 : Step(250): len = 653455, overlap = 168.781
+PHY-3002 : Step(251): len = 644741, overlap = 158.75
+PHY-3002 : Step(252): len = 638622, overlap = 149.125
+PHY-3002 : Step(253): len = 632705, overlap = 136.281
+PHY-3002 : Step(254): len = 630061, overlap = 134.125
+PHY-3002 : Step(255): len = 625936, overlap = 130.375
+PHY-3002 : Step(256): len = 622826, overlap = 123.469
+PHY-3002 : Step(257): len = 620366, overlap = 123.656
+PHY-3002 : Step(258): len = 616951, overlap = 125.312
+PHY-3002 : Step(259): len = 614701, overlap = 129.906
+PHY-3002 : Step(260): len = 611953, overlap = 130.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000230321
+PHY-3002 : Step(261): len = 612957, overlap = 126.281
+PHY-3002 : Step(262): len = 615310, overlap = 121.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00041086
+PHY-3002 : Step(263): len = 617508, overlap = 117.344
+PHY-3002 : Step(264): len = 626941, overlap = 109.969
+PHY-3002 : Step(265): len = 632450, overlap = 101
+PHY-3002 : Step(266): len = 629929, overlap = 101.438
+PHY-3002 : Step(267): len = 629154, overlap = 99.375
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84535, tnet num: 20501, tinst num: 18100, tnode num: 115269, tedge num: 134818.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.561821s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.0%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 566 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 406.16 peak overflow 2.44
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 808/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725272, over cnt = 3025(8%), over = 11076, worst = 25
+PHY-1001 : End global iterations; 1.399806s wall, 1.953125s user + 0.031250s system = 1.984375s CPU (141.8%)
+
+PHY-1001 : Congestion index: top1 = 73.79, top5 = 59.50, top10 = 52.83, top15 = 48.61.
+PHY-1001 : End incremental global routing; 1.771795s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (134.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.377060s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (99.9%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17968 has valid locations, 322 needs to be replaced
+PHY-3001 : design contains 18375 instances, 7748 luts, 9406 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6180 pins
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 653301
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16955/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 739968, over cnt = 3025(8%), over = 11100, worst = 25
+PHY-1001 : End global iterations; 0.370075s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (135.1%)
+
+PHY-1001 : Congestion index: top1 = 73.66, top5 = 59.49, top10 = 52.95, top15 = 48.83.
+PHY-3001 : End congestion estimation; 0.648865s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (120.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85643, tnet num: 20776, tinst num: 18375, tnode num: 116935, tedge num: 136484.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.591656s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.1%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 614 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.662234s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(268): len = 652215, overlap = 0.6875
+PHY-3002 : Step(269): len = 651836, overlap = 0.5
+PHY-3002 : Step(270): len = 651526, overlap = 0.625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17067/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737056, over cnt = 3010(8%), over = 11181, worst = 25
+PHY-1001 : End global iterations; 0.196041s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (95.6%)
+
+PHY-1001 : Congestion index: top1 = 75.26, top5 = 60.25, top10 = 53.39, top15 = 49.17.
+PHY-3001 : End congestion estimation; 0.486168s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.025836s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000405864
+PHY-3002 : Step(271): len = 651305, overlap = 102.531
+PHY-3002 : Step(272): len = 651498, overlap = 101.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000811728
+PHY-3002 : Step(273): len = 651724, overlap = 101.562
+PHY-3002 : Step(274): len = 652385, overlap = 101.656
+PHY-3001 : Final: Len = 652385, Over = 101.656
+PHY-3001 : End incremental placement; 5.571652s wall, 5.921875s user + 0.328125s system = 6.250000s CPU (112.2%)
+
+OPT-1001 : Total overflow 411.00 peak overflow 2.44
+OPT-1001 : End high-fanout net optimization; 9.297213s wall, 10.265625s user + 0.390625s system = 10.656250s CPU (114.6%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 712, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16991/20954.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740008, over cnt = 2967(8%), over = 10176, worst = 25
+PHY-1002 : len = 789176, over cnt = 2183(6%), over = 5794, worst = 22
+PHY-1002 : len = 825536, over cnt = 1138(3%), over = 2907, worst = 18
+PHY-1002 : len = 855968, over cnt = 402(1%), over = 957, worst = 15
+PHY-1002 : len = 873832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.935567s wall, 2.781250s user + 0.031250s system = 2.812500s CPU (145.3%)
+
+PHY-1001 : Congestion index: top1 = 59.05, top5 = 51.57, top10 = 48.02, top15 = 45.66.
+OPT-1001 : End congestion update; 2.227519s wall, 3.078125s user + 0.031250s system = 3.109375s CPU (139.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20776 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.869479s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.6%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 122 cells processed and 16800 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 47 cells processed and 3816 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 950 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 546 slack improved
+OPT-1001 : End bottleneck based optimization; 3.557058s wall, 4.406250s user + 0.031250s system = 4.437500s CPU (124.8%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 695, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17004/20960.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 873200, over cnt = 92(0%), over = 133, worst = 6
+PHY-1002 : len = 872760, over cnt = 47(0%), over = 55, worst = 3
+PHY-1002 : len = 873200, over cnt = 12(0%), over = 13, worst = 2
+PHY-1002 : len = 873368, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 873432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.817093s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 58.19, top5 = 51.38, top10 = 47.83, top15 = 45.53.
+OPT-1001 : End congestion update; 1.114224s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20782 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.860339s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.9%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 19 cells processed and 2400 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.103185s wall, 2.140625s user + 0.000000s system = 2.140625s CPU (101.8%)
+
+OPT-1001 : Current memory(MB): used = 707, reserve = 702, peak = 734.
+OPT-1001 : End physical optimization; 16.855366s wall, 18.796875s user + 0.437500s system = 19.234375s CPU (114.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7748 LUT to BLE ...
+SYN-4008 : Packed 7748 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6264 remaining SEQ's ...
+SYN-4005 : Packed 3844 SEQ with LUT/SLICE
+SYN-4006 : 1037 single LUT's are left
+SYN-4006 : 2420 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10168/13955 primitive instances ...
+PHY-3001 : End packing; 1.877419s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6813 instances
+RUN-1001 : 3333 mslices, 3332 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17948 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10081 nets have 2 pins
+RUN-1001 : 6499 nets have [3 - 5] pins
+RUN-1001 : 727 nets have [6 - 10] pins
+RUN-1001 : 301 nets have [11 - 20] pins
+RUN-1001 : 307 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6811 instances, 6665 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3574 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 667405, Over = 241.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7875/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 822024, over cnt = 1977(5%), over = 3247, worst = 7
+PHY-1002 : len = 830000, over cnt = 1265(3%), over = 1842, worst = 7
+PHY-1002 : len = 844840, over cnt = 519(1%), over = 679, worst = 7
+PHY-1002 : len = 852032, over cnt = 198(0%), over = 258, worst = 5
+PHY-1002 : len = 855216, over cnt = 65(0%), over = 95, worst = 5
+PHY-1001 : End global iterations; 1.760356s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 60.11, top5 = 51.96, top10 = 47.75, top15 = 45.02.
+PHY-3001 : End congestion estimation; 2.206468s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (133.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71716, tnet num: 17770, tinst num: 6811, tnode num: 94357, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.752824s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (99.8%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 616 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.759687s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.83007e-05
+PHY-3002 : Step(275): len = 656675, overlap = 244.75
+PHY-3002 : Step(276): len = 650608, overlap = 251.5
+PHY-3002 : Step(277): len = 646620, overlap = 249
+PHY-3002 : Step(278): len = 644497, overlap = 251
+PHY-3002 : Step(279): len = 642642, overlap = 256.25
+PHY-3002 : Step(280): len = 640541, overlap = 253.75
+PHY-3002 : Step(281): len = 638212, overlap = 253.75
+PHY-3002 : Step(282): len = 635889, overlap = 261.25
+PHY-3002 : Step(283): len = 633912, overlap = 268.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000116601
+PHY-3002 : Step(284): len = 637437, overlap = 258.5
+PHY-3002 : Step(285): len = 642182, overlap = 247.5
+PHY-3002 : Step(286): len = 642980, overlap = 249
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000233203
+PHY-3002 : Step(287): len = 648904, overlap = 237.5
+PHY-3002 : Step(288): len = 656435, overlap = 224.75
+PHY-3002 : Step(289): len = 657109, overlap = 221.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.389963s wall, 0.343750s user + 0.562500s system = 0.906250s CPU (232.4%)
+
+PHY-3001 : Trial Legalized: Len = 744393
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 737/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853208, over cnt = 2629(7%), over = 4442, worst = 10
+PHY-1002 : len = 871096, over cnt = 1484(4%), over = 2208, worst = 10
+PHY-1002 : len = 889744, over cnt = 580(1%), over = 813, worst = 7
+PHY-1002 : len = 901464, over cnt = 105(0%), over = 119, worst = 3
+PHY-1002 : len = 904776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.462310s wall, 3.765625s user + 0.015625s system = 3.781250s CPU (153.6%)
+
+PHY-1001 : Congestion index: top1 = 58.32, top5 = 51.56, top10 = 48.13, top15 = 45.89.
+PHY-3001 : End congestion estimation; 2.969777s wall, 4.281250s user + 0.015625s system = 4.296875s CPU (144.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.043796s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000168532
+PHY-3002 : Step(290): len = 716812, overlap = 41.75
+PHY-3002 : Step(291): len = 700044, overlap = 70.5
+PHY-3002 : Step(292): len = 685429, overlap = 96.5
+PHY-3002 : Step(293): len = 676006, overlap = 118.25
+PHY-3002 : Step(294): len = 669316, overlap = 136.25
+PHY-3002 : Step(295): len = 665792, overlap = 156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000337064
+PHY-3002 : Step(296): len = 669538, overlap = 148.75
+PHY-3002 : Step(297): len = 673272, overlap = 149
+PHY-3002 : Step(298): len = 674649, overlap = 149
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000651401
+PHY-3002 : Step(299): len = 677829, overlap = 148
+PHY-3002 : Step(300): len = 684052, overlap = 147.25
+PHY-3002 : Step(301): len = 688577, overlap = 146.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.042072s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (111.4%)
+
+PHY-3001 : Legalized: Len = 717794, Over = 0
+PHY-3001 : Spreading special nets. 462 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.114530s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (95.5%)
+
+PHY-3001 : 681 instances has been re-located, deltaX = 227, deltaY = 445, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 728023, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71716, tnet num: 17770, tinst num: 6814, tnode num: 94357, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.002463s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (100.7%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 652 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4049/17948.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 849976, over cnt = 2400(6%), over = 3979, worst = 8
+PHY-1002 : len = 863616, over cnt = 1477(4%), over = 2175, worst = 8
+PHY-1002 : len = 883984, over cnt = 405(1%), over = 561, worst = 5
+PHY-1002 : len = 890344, over cnt = 101(0%), over = 131, worst = 5
+PHY-1002 : len = 891720, over cnt = 23(0%), over = 32, worst = 4
+PHY-1001 : End global iterations; 2.355443s wall, 3.265625s user + 0.031250s system = 3.296875s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 55.17, top5 = 49.77, top10 = 46.46, top15 = 44.24.
+PHY-1001 : End incremental global routing; 2.762005s wall, 3.671875s user + 0.031250s system = 3.703125s CPU (134.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17770 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.966320s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (98.6%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6721 has valid locations, 30 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 733753
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16289/17980.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898856, over cnt = 138(0%), over = 171, worst = 6
+PHY-1002 : len = 899064, over cnt = 61(0%), over = 64, worst = 2
+PHY-1002 : len = 899664, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 899768, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 899944, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.004532s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.86, top10 = 46.57, top15 = 44.42.
+PHY-3001 : End congestion estimation; 1.360073s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (102.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71976, tnet num: 17802, tinst num: 6839, tnode num: 94686, tedge num: 119550.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.022525s wall, 2.015625s user + 0.015625s system = 2.031250s CPU (100.4%)
+
+RUN-1004 : used memory is 680 MB, reserved memory is 685 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17802 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.022609s wall, 3.000000s user + 0.015625s system = 3.015625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(302): len = 733238, overlap = 0
+PHY-3002 : Step(303): len = 732200, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16275/17980.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 897928, over cnt = 97(0%), over = 116, worst = 4
+PHY-1002 : len = 898200, over cnt = 43(0%), over = 43, worst = 1
+PHY-1002 : len = 898520, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 898888, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 898936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.955098s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.8%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 50.03, top10 = 46.71, top15 = 44.46.
+PHY-3001 : End congestion estimation; 1.330700s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (99.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17802 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.989028s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (97.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000561432
+PHY-3002 : Step(304): len = 732161, overlap = 2.75
+PHY-3002 : Step(305): len = 732249, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006700s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (233.2%)
+
+PHY-3001 : Legalized: Len = 732503, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070791s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (110.4%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 4, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 732617, Over = 0
+PHY-3001 : End incremental placement; 7.242863s wall, 7.343750s user + 0.093750s system = 7.437500s CPU (102.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.524197s wall, 12.515625s user + 0.140625s system = 12.656250s CPU (109.8%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 730, peak = 736.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16255/17980.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898768, over cnt = 81(0%), over = 102, worst = 4
+PHY-1002 : len = 898752, over cnt = 40(0%), over = 44, worst = 3
+PHY-1002 : len = 899144, over cnt = 5(0%), over = 6, worst = 2
+PHY-1002 : len = 899192, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 899256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.971437s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (107.8%)
+
+PHY-1001 : Congestion index: top1 = 55.17, top5 = 50.00, top10 = 46.62, top15 = 44.45.
+OPT-1001 : End congestion update; 1.349951s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (104.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17802 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.922084s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (96.6%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6751 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 742293, Over = 0
+PHY-3001 : Spreading special nets. 34 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.076115s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (102.6%)
+
+PHY-3001 : 44 instances has been re-located, deltaX = 26, deltaY = 23, maxDist = 4.
+PHY-3001 : Final: Len = 742891, Over = 0
+PHY-3001 : End incremental legalization; 0.496510s wall, 0.453125s user + 0.031250s system = 0.484375s CPU (97.6%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 58 cells processed and 24398 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6751 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 742975, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062295s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.3%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 20, deltaY = 19, maxDist = 3.
+PHY-3001 : Final: Len = 743763, Over = 0
+PHY-3001 : End incremental legalization; 0.455508s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (96.0%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 33 cells processed and 3192 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6761 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6849 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744116, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064036s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.6%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 744592, Over = 0
+PHY-3001 : End incremental legalization; 0.428863s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.4%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 9 cells processed and 1486 slack improved
+OPT-1001 : End bottleneck based optimization; 4.137273s wall, 4.156250s user + 0.046875s system = 4.203125s CPU (101.6%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15861/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910424, over cnt = 200(0%), over = 242, worst = 7
+PHY-1002 : len = 910816, over cnt = 80(0%), over = 83, worst = 2
+PHY-1002 : len = 911392, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 911904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 912000, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.038234s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (106.9%)
+
+PHY-1001 : Congestion index: top1 = 55.82, top5 = 50.26, top10 = 46.76, top15 = 44.64.
+OPT-1001 : End congestion update; 1.415440s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (103.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.843762s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6761 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6849 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744522, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.086517s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (108.4%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 17, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 744948, Over = 0
+PHY-3001 : End incremental legalization; 0.534850s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (99.3%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 12 cells processed and 1450 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.978628s wall, 3.031250s user + 0.000000s system = 3.031250s CPU (101.8%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.898374s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (93.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16253/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912224, over cnt = 48(0%), over = 59, worst = 4
+PHY-1002 : len = 912368, over cnt = 25(0%), over = 25, worst = 1
+PHY-1002 : len = 912480, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 912512, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 912600, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.916089s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (104.0%)
+
+PHY-1001 : Congestion index: top1 = 55.93, top5 = 50.17, top10 = 46.70, top15 = 44.61.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779468s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.482759
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 23.877258s wall, 24.937500s user + 0.187500s system = 25.125000s CPU (105.2%)
+
+RUN-1003 : finish command "place" in 72.590005s wall, 101.453125s user + 6.984375s system = 108.437500s CPU (149.4%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 635 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.747074s wall, 3.000000s user + 0.031250s system = 3.031250s CPU (173.5%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 636 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72045, tnet num: 17805, tinst num: 6849, tnode num: 94791, tedge num: 119669.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.777100s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (99.4%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 656 MB, peak memory is 737 MB
+PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 846032, over cnt = 2656(7%), over = 4489, worst = 9
+PHY-1002 : len = 864952, over cnt = 1635(4%), over = 2372, worst = 9
+PHY-1002 : len = 888664, over cnt = 404(1%), over = 544, worst = 7
+PHY-1002 : len = 896896, over cnt = 21(0%), over = 32, worst = 7
+PHY-1002 : len = 897232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.390343s wall, 4.593750s user + 0.000000s system = 4.593750s CPU (135.5%)
+
+PHY-1001 : Congestion index: top1 = 55.52, top5 = 50.19, top10 = 46.84, top15 = 44.60.
+PHY-1001 : End global routing; 3.800166s wall, 4.984375s user + 0.015625s system = 5.000000s CPU (131.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 710, reserve = 713, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 987, reserve = 989, peak = 987.
+PHY-1001 : End build detailed router design. 4.396946s wall, 4.343750s user + 0.031250s system = 4.375000s CPU (99.5%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267368, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.798060s wall, 5.734375s user + 0.000000s system = 5.734375s CPU (98.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267424, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.465347s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.7%)
+
+PHY-1001 : Current memory(MB): used = 1022, reserve = 1025, peak = 1022.
+PHY-1001 : End phase 1; 6.275817s wall, 6.218750s user + 0.000000s system = 6.218750s CPU (99.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1036, peak = 1034.
+PHY-1001 : End initial routed; 30.502175s wall, 65.828125s user + 0.203125s system = 66.031250s CPU (216.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.452870s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1049, peak = 1046.
+PHY-1001 : End phase 2; 33.955115s wall, 69.265625s user + 0.203125s system = 69.468750s CPU (204.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.142608s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.6%)
+
+PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.433934s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.21014e+06, over cnt = 712(0%), over = 713, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.185285s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (165.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.20853e+06, over cnt = 179(0%), over = 179, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.840403s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (156.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.20974e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.484044s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (119.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.21006e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.327123s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (105.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.236489s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (118.9%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.373625s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.654604s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.188205s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.213075s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.228888s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.238625s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.363301s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.9%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.191480s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (106.1%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.186211s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.219781s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.228236s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.354223s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.399872s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.186547s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.190676s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.216093s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (122.9%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.228544s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (109.4%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.356720s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.409412s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.150444s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.186495s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (92.2%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.198200s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.6%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.247520s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.247747s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (107.2%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.357987s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.408541s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.134735s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.116690s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.173868s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.184461s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.216421s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (93.9%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.232649s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (107.5%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.356265s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.401224s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.113275s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.133690s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.115801s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.183228s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.186297s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.214568s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (116.5%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.232743s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.386727s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.483004s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.157226s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.120359s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.206134s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.144747s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.185998s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (92.4%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.190471s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.213610s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.227622s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.358483s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.403171s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.112213s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.153914s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.195134s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.241510s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.134286s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.6%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.180605s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (121.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.181224s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (120.7%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.219680s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.232717s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.348518s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.403060s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.156011s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.137746s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.123501s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.129444s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.137981s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.336772s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (100.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.445426s wall, 3.421875s user + 0.015625s system = 3.437500s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1057, peak = 1053.
+PHY-1001 : End phase 3; 46.167186s wall, 48.328125s user + 0.093750s system = 48.421875s CPU (104.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.139900s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.5%)
+
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.400037s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.188074s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.205378s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.288230s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (103.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.181923s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (111.7%)
+
+PHY-1001 : ==== DR Iter 5 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.184782s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.216224s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.232817s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.351182s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.9%)
+
+PHY-1001 : ===== DR Iter 9 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.183920s wall, 0.187500s user + 0.031250s system = 0.218750s CPU (118.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.188415s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.218390s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (107.3%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.227470s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.353746s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.399139s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (105.7%)
+
+PHY-1001 : ===== DR Iter 15 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.190831s wall, 0.203125s user + 0.031250s system = 0.234375s CPU (122.8%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.182468s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.2%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.219106s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (107.0%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.231090s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (114.9%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.361631s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.446947s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 1.262288s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 22 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.175397s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.184920s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (126.7%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.224513s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.233565s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.354033s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.410149s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 1.143904s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 1.144315s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 30 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.176821s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.181744s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.6%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.222885s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.230395s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (108.5%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.353400s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.408654s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 1.148609s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 1.143858s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.242511s wall, 1.218750s user + 0.015625s system = 1.234375s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 39 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.200165s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.201731s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (108.4%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.229006s wall, 0.265625s user + 0.031250s system = 0.296875s CPU (129.6%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.244365s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.386024s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.436501s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 1.201237s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.235756s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.303778s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.516822s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (95.8%)
+
+PHY-1001 : ===== DR Iter 49 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.218294s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.236324s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (119.0%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.231038s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (94.7%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.248956s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (106.7%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.414416s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.449337s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 1.391677s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 1.448773s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.342433s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.371853s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.345963s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 60 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.190705s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (106.5%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.207260s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.234520s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.268370s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.423254s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.445992s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 1.359477s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 1.431302s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.160159s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.257981s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.242737s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.237025s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.459527s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1055, reserve = 1059, peak = 1055.
+PHY-1001 : End phase 4; 44.379838s wall, 44.515625s user + 0.156250s system = 44.671875s CPU (100.7%)
+
+PHY-1003 : Routed, final wirelength = 2.2102e+06
+PHY-1001 : 589 feed throughs used by 430 nets
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1160, peak = 1153.
+PHY-1001 : End export database. 2.482622s wall, 2.421875s user + 0.062500s system = 2.484375s CPU (100.1%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 11 3) is for feedthrough
+PHY-3001 : eco cells: (1 17 2) is for feedthrough
+PHY-3001 : eco cells: (1 26 3) is for feedthrough
+PHY-3001 : eco cells: (1 53 1) is for feedthrough
+PHY-3001 : eco cells: (2 6 3) is for feedthrough
+PHY-3001 : eco cells: (2 8 3) is for feedthrough
+PHY-3001 : eco cells: (2 11 2) is for feedthrough
+PHY-3001 : eco cells: (2 12 1) is for feedthrough
+PHY-3001 : eco cells: (2 13 1) is for feedthrough
+PHY-3001 : eco cells: (2 14 0) is for feedthrough
+PHY-3001 : eco cells: (2 14 1) is for feedthrough
+PHY-3001 : eco cells: (2 14 3) is for feedthrough
+PHY-3001 : eco cells: (2 16 3) is for feedthrough
+PHY-3001 : eco cells: (2 18 2) is for feedthrough
+PHY-3001 : eco cells: (2 23 3) is for feedthrough
+PHY-3001 : eco cells: (2 25 1) is for feedthrough
+PHY-3001 : eco cells: (2 25 2) is for feedthrough
+PHY-3001 : eco cells: (2 27 3) is for feedthrough
+PHY-3001 : eco cells: (2 29 2) is for feedthrough
+PHY-3001 : eco cells: (2 34 2) is for feedthrough
+PHY-3001 : eco cells: (2 44 0) is for feedthrough
+PHY-3001 : eco cells: (2 45 0) is for feedthrough
+PHY-3001 : eco cells: (3 4 2) is for feedthrough
+PHY-3001 : eco cells: (3 6 1) is for feedthrough
+PHY-3001 : eco cells: (3 7 3) is for feedthrough
+PHY-3001 : eco cells: (3 8 0) is for feedthrough
+PHY-3001 : eco cells: (3 14 2) is for feedthrough
+PHY-3001 : eco cells: (3 15 3) is for feedthrough
+PHY-3001 : eco cells: (3 18 1) is for feedthrough
+PHY-3001 : eco cells: (3 20 2) is for feedthrough
+PHY-3001 : eco cells: (3 21 1) is for feedthrough
+PHY-3001 : eco cells: (3 23 2) is for feedthrough
+PHY-3001 : eco cells: (3 46 0) is for feedthrough
+PHY-3001 : eco cells: (3 49 2) is for feedthrough
+PHY-3001 : eco cells: (3 50 1) is for feedthrough
+PHY-3001 : eco cells: (3 51 0) is for feedthrough
+PHY-3001 : eco cells: (3 51 2) is for feedthrough
+PHY-3001 : eco cells: (3 55 3) is for feedthrough
+PHY-3001 : eco cells: (3 56 0) is for feedthrough
+PHY-3001 : eco cells: (3 61 1) is for feedthrough
+PHY-3001 : eco cells: (3 67 1) is for feedthrough
+PHY-3001 : eco cells: (4 4 0) is for feedthrough
+PHY-3001 : eco cells: (4 5 3) is for feedthrough
+PHY-3001 : eco cells: (4 6 3) is for feedthrough
+PHY-3001 : eco cells: (4 7 3) is for feedthrough
+PHY-3001 : eco cells: (4 8 3) is for feedthrough
+PHY-3001 : eco cells: (4 10 1) is for feedthrough
+PHY-3001 : eco cells: (4 11 0) is for feedthrough
+PHY-3001 : eco cells: (4 15 2) is for feedthrough
+PHY-3001 : eco cells: (4 17 3) is for feedthrough
+PHY-3001 : eco cells: (4 18 3) is for feedthrough
+PHY-3001 : eco cells: (4 19 2) is for feedthrough
+PHY-3001 : eco cells: (4 25 2) is for feedthrough
+PHY-3001 : eco cells: (4 33 0) is for feedthrough
+PHY-3001 : eco cells: (4 34 1) is for feedthrough
+PHY-3001 : eco cells: (4 48 0) is for feedthrough
+PHY-3001 : eco cells: (4 49 3) is for feedthrough
+PHY-3001 : eco cells: (4 50 0) is for feedthrough
+PHY-3001 : eco cells: (4 51 2) is for feedthrough
+PHY-3001 : eco cells: (4 52 1) is for feedthrough
+PHY-3001 : eco cells: (4 52 2) is for feedthrough
+PHY-3001 : eco cells: (4 53 3) is for feedthrough
+PHY-3001 : eco cells: (5 3 3) is for feedthrough
+PHY-3001 : eco cells: (5 5 1) is for feedthrough
+PHY-3001 : eco cells: (5 7 0) is for feedthrough
+PHY-3001 : eco cells: (5 12 2) is for feedthrough
+PHY-3001 : eco cells: (5 14 2) is for feedthrough
+PHY-3001 : eco cells: (5 15 3) is for feedthrough
+PHY-3001 : eco cells: (5 17 3) is for feedthrough
+PHY-3001 : eco cells: (5 19 1) is for feedthrough
+PHY-3001 : eco cells: (5 24 2) is for feedthrough
+PHY-3001 : eco cells: (5 24 3) is for feedthrough
+PHY-3001 : eco cells: (5 31 1) is for feedthrough
+PHY-3001 : eco cells: (5 46 3) is for feedthrough
+PHY-3001 : eco cells: (5 49 3) is for feedthrough
+PHY-3001 : eco cells: (5 52 2) is for feedthrough
+PHY-3001 : eco cells: (5 54 2) is for feedthrough
+PHY-3001 : eco cells: (5 67 3) is for feedthrough
+PHY-3001 : eco cells: (6 6 3) is for feedthrough
+PHY-3001 : eco cells: (6 8 2) is for feedthrough
+PHY-3001 : eco cells: (6 8 3) is for feedthrough
+PHY-3001 : eco cells: (6 14 0) is for feedthrough
+PHY-3001 : eco cells: (6 14 1) is for feedthrough
+PHY-3001 : eco cells: (6 14 3) is for feedthrough
+PHY-3001 : eco cells: (6 19 3) is for feedthrough
+PHY-3001 : eco cells: (6 23 2) is for feedthrough
+PHY-3001 : eco cells: (6 23 3) is for feedthrough
+PHY-3001 : eco cells: (6 26 0) is for feedthrough
+PHY-3001 : eco cells: (6 27 2) is for feedthrough
+PHY-3001 : eco cells: (6 33 0) is for feedthrough
+PHY-3001 : eco cells: (6 48 1) is for feedthrough
+PHY-3001 : eco cells: (6 50 0) is for feedthrough
+PHY-3001 : eco cells: (6 51 3) is for feedthrough
+PHY-3001 : eco cells: (6 58 2) is for feedthrough
+PHY-3001 : eco cells: (6 60 1) is for feedthrough
+PHY-3001 : eco cells: (7 9 2) is for feedthrough
+PHY-3001 : eco cells: (7 10 1) is for feedthrough
+PHY-3001 : eco cells: (7 16 1) is for feedthrough
+PHY-3001 : eco cells: (7 16 2) is for feedthrough
+PHY-3001 : eco cells: (7 18 2) is for feedthrough
+PHY-3001 : eco cells: (7 20 1) is for feedthrough
+PHY-3001 : eco cells: (7 51 0) is for feedthrough
+PHY-3001 : eco cells: (7 52 0) is for feedthrough
+PHY-3001 : eco cells: (7 54 1) is for feedthrough
+PHY-3001 : eco cells: (7 54 3) is for feedthrough
+PHY-3001 : eco cells: (7 58 2) is for feedthrough
+PHY-3001 : eco cells: (7 59 2) is for feedthrough
+PHY-3001 : eco cells: (9 7 0) is for feedthrough
+PHY-3001 : eco cells: (9 7 1) is for feedthrough
+PHY-3001 : eco cells: (9 9 3) is for feedthrough
+PHY-3001 : eco cells: (9 10 3) is for feedthrough
+PHY-3001 : eco cells: (9 13 2) is for feedthrough
+PHY-3001 : eco cells: (9 18 1) is for feedthrough
+PHY-3001 : eco cells: (9 38 1) is for feedthrough
+PHY-3001 : eco cells: (9 38 2) is for feedthrough
+PHY-3001 : eco cells: (9 53 1) is for feedthrough
+PHY-3001 : eco cells: (10 2 1) is for feedthrough
+PHY-3001 : eco cells: (10 10 0) is for feedthrough
+PHY-3001 : eco cells: (10 16 1) is for feedthrough
+PHY-3001 : eco cells: (10 17 3) is for feedthrough
+PHY-3001 : eco cells: (10 20 1) is for feedthrough
+PHY-3001 : eco cells: (10 21 2) is for feedthrough
+PHY-3001 : eco cells: (10 22 3) is for feedthrough
+PHY-3001 : eco cells: (10 24 0) is for feedthrough
+PHY-3001 : eco cells: (10 36 1) is for feedthrough
+PHY-3001 : eco cells: (10 38 2) is for feedthrough
+PHY-3001 : eco cells: (10 44 1) is for feedthrough
+PHY-3001 : eco cells: (10 45 3) is for feedthrough
+PHY-3001 : eco cells: (10 49 0) is for feedthrough
+PHY-3001 : eco cells: (10 54 3) is for feedthrough
+PHY-3001 : eco cells: (10 69 1) is for feedthrough
+PHY-3001 : eco cells: (11 5 3) is for feedthrough
+PHY-3001 : eco cells: (11 14 2) is for feedthrough
+PHY-3001 : eco cells: (11 17 1) is for feedthrough
+PHY-3001 : eco cells: (11 18 1) is for feedthrough
+PHY-3001 : eco cells: (11 19 1) is for feedthrough
+PHY-3001 : eco cells: (11 27 2) is for feedthrough
+PHY-3001 : eco cells: (11 39 1) is for feedthrough
+PHY-3001 : eco cells: (11 40 0) is for feedthrough
+PHY-3001 : eco cells: (11 40 3) is for feedthrough
+PHY-3001 : eco cells: (11 41 3) is for feedthrough
+PHY-3001 : eco cells: (11 42 3) is for feedthrough
+PHY-3001 : eco cells: (11 54 0) is for feedthrough
+PHY-3001 : eco cells: (11 67 3) is for feedthrough
+PHY-3001 : eco cells: (11 69 0) is for feedthrough
+PHY-3001 : eco cells: (12 6 2) is for feedthrough
+PHY-3001 : eco cells: (12 6 3) is for feedthrough
+PHY-3001 : eco cells: (12 10 3) is for feedthrough
+PHY-3001 : eco cells: (12 15 3) is for feedthrough
+PHY-3001 : eco cells: (12 16 1) is for feedthrough
+PHY-3001 : eco cells: (12 18 2) is for feedthrough
+PHY-3001 : eco cells: (12 23 3) is for feedthrough
+PHY-3001 : eco cells: (12 28 3) is for feedthrough
+PHY-3001 : eco cells: (12 38 2) is for feedthrough
+PHY-3001 : eco cells: (12 39 1) is for feedthrough
+PHY-3001 : eco cells: (12 41 2) is for feedthrough
+PHY-3001 : eco cells: (12 66 1) is for feedthrough
+PHY-3001 : eco cells: (12 66 3) is for feedthrough
+PHY-3001 : eco cells: (13 5 2) is for feedthrough
+PHY-3001 : eco cells: (13 7 1) is for feedthrough
+PHY-3001 : eco cells: (13 12 0) is for feedthrough
+PHY-3001 : eco cells: (13 23 1) is for feedthrough
+PHY-3001 : eco cells: (13 33 0) is for feedthrough
+PHY-3001 : eco cells: (13 37 1) is for feedthrough
+PHY-3001 : eco cells: (13 38 1) is for feedthrough
+PHY-3001 : eco cells: (13 38 3) is for feedthrough
+PHY-3001 : eco cells: (13 39 2) is for feedthrough
+PHY-3001 : eco cells: (13 54 3) is for feedthrough
+PHY-3001 : eco cells: (13 61 2) is for feedthrough
+PHY-3001 : eco cells: (14 2 0) is for feedthrough
+PHY-3001 : eco cells: (14 6 0) is for feedthrough
+PHY-3001 : eco cells: (14 8 1) is for feedthrough
+PHY-3001 : eco cells: (14 8 2) is for feedthrough
+PHY-3001 : eco cells: (14 10 3) is for feedthrough
+PHY-3001 : eco cells: (14 11 2) is for feedthrough
+PHY-3001 : eco cells: (14 12 3) is for feedthrough
+PHY-3001 : eco cells: (14 27 0) is for feedthrough
+PHY-3001 : eco cells: (14 32 0) is for feedthrough
+PHY-3001 : eco cells: (14 38 3) is for feedthrough
+PHY-3001 : eco cells: (14 39 0) is for feedthrough
+PHY-3001 : eco cells: (14 42 0) is for feedthrough
+PHY-3001 : eco cells: (15 5 0) is for feedthrough
+PHY-3001 : eco cells: (15 5 1) is for feedthrough
+PHY-3001 : eco cells: (15 6 3) is for feedthrough
+PHY-3001 : eco cells: (15 8 0) is for feedthrough
+PHY-3001 : eco cells: (15 9 3) is for feedthrough
+PHY-3001 : eco cells: (15 10 1) is for feedthrough
+PHY-3001 : eco cells: (15 17 0) is for feedthrough
+PHY-3001 : eco cells: (15 19 3) is for feedthrough
+PHY-3001 : eco cells: (15 29 2) is for feedthrough
+PHY-3001 : eco cells: (15 38 3) is for feedthrough
+PHY-3001 : eco cells: (15 39 2) is for feedthrough
+PHY-3001 : eco cells: (15 41 1) is for feedthrough
+PHY-3001 : eco cells: (15 42 0) is for feedthrough
+PHY-3001 : eco cells: (15 43 2) is for feedthrough
+PHY-3001 : eco cells: (15 44 3) is for feedthrough
+PHY-3001 : eco cells: (15 53 3) is for feedthrough
+PHY-3001 : eco cells: (15 54 3) is for feedthrough
+PHY-3001 : eco cells: (15 55 3) is for feedthrough
+PHY-3001 : eco cells: (15 62 2) is for feedthrough
+PHY-3001 : eco cells: (15 67 2) is for feedthrough
+PHY-3001 : eco cells: (15 68 0) is for feedthrough
+PHY-3001 : eco cells: (17 7 0) is for feedthrough
+PHY-3001 : eco cells: (17 7 3) is for feedthrough
+PHY-3001 : eco cells: (17 8 2) is for feedthrough
+PHY-3001 : eco cells: (17 10 1) is for feedthrough
+PHY-3001 : eco cells: (17 12 1) is for feedthrough
+PHY-3001 : eco cells: (17 13 0) is for feedthrough
+PHY-3001 : eco cells: (17 20 0) is for feedthrough
+PHY-3001 : eco cells: (17 22 3) is for feedthrough
+PHY-3001 : eco cells: (17 26 3) is for feedthrough
+PHY-3001 : eco cells: (17 27 3) is for feedthrough
+PHY-3001 : eco cells: (17 30 3) is for feedthrough
+PHY-3001 : eco cells: (17 31 3) is for feedthrough
+PHY-3001 : eco cells: (17 33 3) is for feedthrough
+PHY-3001 : eco cells: (17 47 3) is for feedthrough
+PHY-3001 : eco cells: (17 52 3) is for feedthrough
+PHY-3001 : eco cells: (17 54 3) is for feedthrough
+PHY-3001 : eco cells: (17 56 3) is for feedthrough
+PHY-3001 : eco cells: (18 2 3) is for feedthrough
+PHY-3001 : eco cells: (18 3 1) is for feedthrough
+PHY-3001 : eco cells: (18 5 0) is for feedthrough
+PHY-3001 : eco cells: (18 6 3) is for feedthrough
+PHY-3001 : eco cells: (18 10 0) is for feedthrough
+PHY-3001 : eco cells: (18 19 3) is for feedthrough
+PHY-3001 : eco cells: (18 20 3) is for feedthrough
+PHY-3001 : eco cells: (18 21 2) is for feedthrough
+PHY-3001 : eco cells: (18 22 2) is for feedthrough
+PHY-3001 : eco cells: (18 24 1) is for feedthrough
+PHY-3001 : eco cells: (18 27 2) is for feedthrough
+PHY-3001 : eco cells: (18 29 0) is for feedthrough
+PHY-3001 : eco cells: (18 32 2) is for feedthrough
+PHY-3001 : eco cells: (18 55 1) is for feedthrough
+PHY-3001 : eco cells: (18 62 3) is for feedthrough
+PHY-3001 : eco cells: (19 1 1) is for feedthrough
+PHY-3001 : eco cells: (19 2 0) is for feedthrough
+PHY-3001 : eco cells: (19 6 3) is for feedthrough
+PHY-3001 : eco cells: (19 19 3) is for feedthrough
+PHY-3001 : eco cells: (19 20 3) is for feedthrough
+PHY-3001 : eco cells: (19 21 1) is for feedthrough
+PHY-3001 : eco cells: (19 22 1) is for feedthrough
+PHY-3001 : eco cells: (19 22 3) is for feedthrough
+PHY-3001 : eco cells: (19 23 2) is for feedthrough
+PHY-3001 : eco cells: (19 24 3) is for feedthrough
+PHY-3001 : eco cells: (19 25 3) is for feedthrough
+PHY-3001 : eco cells: (19 26 2) is for feedthrough
+PHY-3001 : eco cells: (19 28 0) is for feedthrough
+PHY-3001 : eco cells: (19 28 1) is for feedthrough
+PHY-3001 : eco cells: (19 29 0) is for feedthrough
+PHY-3001 : eco cells: (19 29 1) is for feedthrough
+PHY-3001 : eco cells: (19 31 0) is for feedthrough
+PHY-3001 : eco cells: (19 33 0) is for feedthrough
+PHY-3001 : eco cells: (19 34 3) is for feedthrough
+PHY-3001 : eco cells: (19 36 2) is for feedthrough
+PHY-3001 : eco cells: (19 53 3) is for feedthrough
+PHY-3001 : eco cells: (19 54 0) is for feedthrough
+PHY-3001 : eco cells: (19 54 1) is for feedthrough
+PHY-3001 : eco cells: (19 56 2) is for feedthrough
+PHY-3001 : eco cells: (20 3 1) is for feedthrough
+PHY-3001 : eco cells: (20 6 1) is for feedthrough
+PHY-3001 : eco cells: (20 7 1) is for feedthrough
+PHY-3001 : eco cells: (20 7 3) is for feedthrough
+PHY-3001 : eco cells: (20 20 0) is for feedthrough
+PHY-3001 : eco cells: (20 22 0) is for feedthrough
+PHY-3001 : eco cells: (20 24 0) is for feedthrough
+PHY-3001 : eco cells: (20 24 2) is for feedthrough
+PHY-3001 : eco cells: (20 24 3) is for feedthrough
+PHY-3001 : eco cells: (20 25 3) is for feedthrough
+PHY-3001 : eco cells: (20 27 0) is for feedthrough
+PHY-3001 : eco cells: (20 32 0) is for feedthrough
+PHY-3001 : eco cells: (20 35 0) is for feedthrough
+PHY-3001 : eco cells: (20 36 1) is for feedthrough
+PHY-3001 : eco cells: (20 46 1) is for feedthrough
+PHY-3001 : eco cells: (20 54 3) is for feedthrough
+PHY-3001 : eco cells: (20 55 2) is for feedthrough
+PHY-3001 : eco cells: (20 62 1) is for feedthrough
+PHY-3001 : eco cells: (21 2 1) is for feedthrough
+PHY-3001 : eco cells: (21 8 0) is for feedthrough
+PHY-3001 : eco cells: (21 22 1) is for feedthrough
+PHY-3001 : eco cells: (21 26 2) is for feedthrough
+PHY-3001 : eco cells: (21 36 2) is for feedthrough
+PHY-3001 : eco cells: (21 55 2) is for feedthrough
+PHY-3001 : eco cells: (21 57 1) is for feedthrough
+PHY-3001 : eco cells: (21 59 0) is for feedthrough
+PHY-3001 : eco cells: (21 59 1) is for feedthrough
+PHY-3001 : eco cells: (21 61 2) is for feedthrough
+PHY-3001 : eco cells: (21 63 0) is for feedthrough
+PHY-3001 : eco cells: (22 1 0) is for feedthrough
+PHY-3001 : eco cells: (22 20 0) is for feedthrough
+PHY-3001 : eco cells: (22 23 3) is for feedthrough
+PHY-3001 : eco cells: (22 25 1) is for feedthrough
+PHY-3001 : eco cells: (22 25 3) is for feedthrough
+PHY-3001 : eco cells: (22 26 1) is for feedthrough
+PHY-3001 : eco cells: (22 31 1) is for feedthrough
+PHY-3001 : eco cells: (22 45 0) is for feedthrough
+PHY-3001 : eco cells: (22 55 0) is for feedthrough
+PHY-3001 : eco cells: (22 56 1) is for feedthrough
+PHY-3001 : eco cells: (22 57 1) is for feedthrough
+PHY-3001 : eco cells: (22 68 2) is for feedthrough
+PHY-3001 : eco cells: (23 4 3) is for feedthrough
+PHY-3001 : eco cells: (23 21 2) is for feedthrough
+PHY-3001 : eco cells: (23 22 2) is for feedthrough
+PHY-3001 : eco cells: (23 27 3) is for feedthrough
+PHY-3001 : eco cells: (23 55 0) is for feedthrough
+PHY-3001 : eco cells: (23 56 1) is for feedthrough
+PHY-3001 : eco cells: (23 56 3) is for feedthrough
+PHY-3001 : eco cells: (23 57 0) is for feedthrough
+PHY-3001 : eco cells: (25 5 1) is for feedthrough
+PHY-3001 : eco cells: (25 24 1) is for feedthrough
+PHY-3001 : eco cells: (25 24 2) is for feedthrough
+PHY-3001 : eco cells: (25 41 1) is for feedthrough
+PHY-3001 : eco cells: (25 55 0) is for feedthrough
+PHY-3001 : eco cells: (25 58 3) is for feedthrough
+PHY-3001 : eco cells: (26 58 1) is for feedthrough
+PHY-3001 : eco cells: (26 69 2) is for feedthrough
+PHY-3001 : eco cells: (27 1 3) is for feedthrough
+PHY-3001 : eco cells: (27 3 3) is for feedthrough
+PHY-3001 : eco cells: (27 26 3) is for feedthrough
+PHY-3001 : eco cells: (27 31 2) is for feedthrough
+PHY-3001 : eco cells: (27 36 3) is for feedthrough
+PHY-3001 : eco cells: (27 41 1) is for feedthrough
+PHY-3001 : eco cells: (27 41 2) is for feedthrough
+PHY-3001 : eco cells: (27 43 2) is for feedthrough
+PHY-3001 : eco cells: (27 44 0) is for feedthrough
+PHY-3001 : eco cells: (27 44 1) is for feedthrough
+PHY-3001 : eco cells: (27 56 1) is for feedthrough
+PHY-3001 : eco cells: (27 56 3) is for feedthrough
+PHY-3001 : eco cells: (27 57 3) is for feedthrough
+PHY-3001 : eco cells: (27 58 0) is for feedthrough
+PHY-3001 : eco cells: (27 67 0) is for feedthrough
+PHY-3001 : eco cells: (27 68 3) is for feedthrough
+PHY-3001 : eco cells: (28 20 1) is for feedthrough
+PHY-3001 : eco cells: (28 21 1) is for feedthrough
+PHY-3001 : eco cells: (28 26 0) is for feedthrough
+PHY-3001 : eco cells: (28 30 2) is for feedthrough
+PHY-3001 : eco cells: (28 30 3) is for feedthrough
+PHY-3001 : eco cells: (28 31 1) is for feedthrough
+PHY-3001 : eco cells: (28 31 3) is for feedthrough
+PHY-3001 : eco cells: (28 33 3) is for feedthrough
+PHY-3001 : eco cells: (28 35 2) is for feedthrough
+PHY-3001 : eco cells: (28 35 3) is for feedthrough
+PHY-3001 : eco cells: (28 36 1) is for feedthrough
+PHY-3001 : eco cells: (28 42 3) is for feedthrough
+PHY-3001 : eco cells: (28 60 0) is for feedthrough
+PHY-3001 : eco cells: (28 62 0) is for feedthrough
+PHY-3001 : eco cells: (29 7 0) is for feedthrough
+PHY-3001 : eco cells: (29 25 0) is for feedthrough
+PHY-3001 : eco cells: (29 30 0) is for feedthrough
+PHY-3001 : eco cells: (29 31 0) is for feedthrough
+PHY-3001 : eco cells: (29 31 1) is for feedthrough
+PHY-3001 : eco cells: (29 33 0) is for feedthrough
+PHY-3001 : eco cells: (29 35 3) is for feedthrough
+PHY-3001 : eco cells: (29 39 0) is for feedthrough
+PHY-3001 : eco cells: (29 41 1) is for feedthrough
+PHY-3001 : eco cells: (29 43 2) is for feedthrough
+PHY-3001 : eco cells: (29 44 1) is for feedthrough
+PHY-3001 : eco cells: (29 45 1) is for feedthrough
+PHY-3001 : eco cells: (29 58 0) is for feedthrough
+PHY-3001 : eco cells: (29 59 3) is for feedthrough
+PHY-3001 : eco cells: (30 5 0) is for feedthrough
+PHY-3001 : eco cells: (30 9 3) is for feedthrough
+PHY-3001 : eco cells: (30 24 1) is for feedthrough
+PHY-3001 : eco cells: (30 28 0) is for feedthrough
+PHY-3001 : eco cells: (30 29 1) is for feedthrough
+PHY-3001 : eco cells: (30 31 3) is for feedthrough
+PHY-3001 : eco cells: (30 36 0) is for feedthrough
+PHY-3001 : eco cells: (30 40 0) is for feedthrough
+PHY-3001 : eco cells: (30 45 3) is for feedthrough
+PHY-3001 : eco cells: (30 50 3) is for feedthrough
+PHY-3001 : eco cells: (30 57 0) is for feedthrough
+PHY-3001 : eco cells: (31 7 0) is for feedthrough
+PHY-3001 : eco cells: (31 31 2) is for feedthrough
+PHY-3001 : eco cells: (31 31 3) is for feedthrough
+PHY-3001 : eco cells: (31 32 3) is for feedthrough
+PHY-3001 : eco cells: (31 33 2) is for feedthrough
+PHY-3001 : eco cells: (31 40 2) is for feedthrough
+PHY-3001 : eco cells: (31 66 1) is for feedthrough
+PHY-3001 : eco cells: (33 21 2) is for feedthrough
+PHY-3001 : eco cells: (33 22 2) is for feedthrough
+PHY-3001 : eco cells: (33 27 0) is for feedthrough
+PHY-3001 : eco cells: (33 28 3) is for feedthrough
+PHY-3001 : eco cells: (33 30 3) is for feedthrough
+PHY-3001 : eco cells: (33 32 2) is for feedthrough
+PHY-3001 : eco cells: (33 34 0) is for feedthrough
+PHY-3001 : eco cells: (33 36 0) is for feedthrough
+PHY-3001 : eco cells: (33 38 3) is for feedthrough
+PHY-3001 : eco cells: (33 40 0) is for feedthrough
+PHY-3001 : eco cells: (33 41 3) is for feedthrough
+PHY-3001 : eco cells: (34 18 3) is for feedthrough
+PHY-3001 : eco cells: (34 21 2) is for feedthrough
+PHY-3001 : eco cells: (34 22 2) is for feedthrough
+PHY-3001 : eco cells: (34 23 1) is for feedthrough
+PHY-3001 : eco cells: (34 23 2) is for feedthrough
+PHY-3001 : eco cells: (34 25 2) is for feedthrough
+PHY-3001 : eco cells: (34 26 2) is for feedthrough
+PHY-3001 : eco cells: (34 27 3) is for feedthrough
+PHY-3001 : eco cells: (34 28 1) is for feedthrough
+PHY-3001 : eco cells: (34 28 3) is for feedthrough
+PHY-3001 : eco cells: (34 31 1) is for feedthrough
+PHY-3001 : eco cells: (34 32 2) is for feedthrough
+PHY-3001 : eco cells: (34 33 2) is for feedthrough
+PHY-3001 : eco cells: (34 34 0) is for feedthrough
+PHY-3001 : eco cells: (34 36 0) is for feedthrough
+PHY-3001 : eco cells: (34 36 3) is for feedthrough
+PHY-3001 : eco cells: (34 37 0) is for feedthrough
+PHY-3001 : eco cells: (34 38 1) is for feedthrough
+PHY-3001 : eco cells: (34 38 3) is for feedthrough
+PHY-3001 : eco cells: (34 39 1) is for feedthrough
+PHY-3001 : eco cells: (34 58 1) is for feedthrough
+PHY-3001 : eco cells: (35 9 2) is for feedthrough
+PHY-3001 : eco cells: (35 18 0) is for feedthrough
+PHY-3001 : eco cells: (35 20 3) is for feedthrough
+PHY-3001 : eco cells: (35 21 2) is for feedthrough
+PHY-3001 : eco cells: (35 22 0) is for feedthrough
+PHY-3001 : eco cells: (35 22 1) is for feedthrough
+PHY-3001 : eco cells: (35 23 1) is for feedthrough
+PHY-3001 : eco cells: (35 24 0) is for feedthrough
+PHY-3001 : eco cells: (35 24 3) is for feedthrough
+PHY-3001 : eco cells: (35 25 0) is for feedthrough
+PHY-3001 : eco cells: (35 25 1) is for feedthrough
+PHY-3001 : eco cells: (35 28 2) is for feedthrough
+PHY-3001 : eco cells: (35 29 2) is for feedthrough
+PHY-3001 : eco cells: (35 30 1) is for feedthrough
+PHY-3001 : eco cells: (35 31 0) is for feedthrough
+PHY-3001 : eco cells: (35 31 1) is for feedthrough
+PHY-3001 : eco cells: (35 32 1) is for feedthrough
+PHY-3001 : eco cells: (35 33 1) is for feedthrough
+PHY-3001 : eco cells: (35 33 3) is for feedthrough
+PHY-3001 : eco cells: (35 34 0) is for feedthrough
+PHY-3001 : eco cells: (35 34 2) is for feedthrough
+PHY-3001 : eco cells: (35 34 3) is for feedthrough
+PHY-3001 : eco cells: (35 35 0) is for feedthrough
+PHY-3001 : eco cells: (35 37 0) is for feedthrough
+PHY-3001 : eco cells: (35 38 0) is for feedthrough
+PHY-3001 : eco cells: (35 42 2) is for feedthrough
+PHY-3001 : eco cells: (35 42 3) is for feedthrough
+PHY-3001 : eco cells: (35 44 2) is for feedthrough
+PHY-3001 : eco cells: (35 46 3) is for feedthrough
+PHY-3001 : eco cells: (35 53 1) is for feedthrough
+PHY-3001 : eco cells: (36 2 0) is for feedthrough
+PHY-3001 : eco cells: (36 3 0) is for feedthrough
+PHY-3001 : eco cells: (36 12 2) is for feedthrough
+PHY-3001 : eco cells: (36 15 1) is for feedthrough
+PHY-3001 : eco cells: (36 15 3) is for feedthrough
+PHY-3001 : eco cells: (36 17 0) is for feedthrough
+PHY-3001 : eco cells: (36 20 3) is for feedthrough
+PHY-3001 : eco cells: (36 21 0) is for feedthrough
+PHY-3001 : eco cells: (36 22 0) is for feedthrough
+PHY-3001 : eco cells: (36 22 3) is for feedthrough
+PHY-3001 : eco cells: (36 26 3) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 1) is for feedthrough
+PHY-3001 : eco cells: (36 28 3) is for feedthrough
+PHY-3001 : eco cells: (36 29 0) is for feedthrough
+PHY-3001 : eco cells: (36 30 0) is for feedthrough
+PHY-3001 : eco cells: (36 30 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 2) is for feedthrough
+PHY-3001 : eco cells: (36 32 0) is for feedthrough
+PHY-3001 : eco cells: (36 32 1) is for feedthrough
+PHY-3001 : eco cells: (36 32 3) is for feedthrough
+PHY-3001 : eco cells: (36 36 0) is for feedthrough
+PHY-3001 : eco cells: (36 36 3) is for feedthrough
+PHY-3001 : eco cells: (36 37 0) is for feedthrough
+PHY-3001 : eco cells: (36 38 1) is for feedthrough
+PHY-3001 : eco cells: (36 38 2) is for feedthrough
+PHY-3001 : eco cells: (36 39 3) is for feedthrough
+PHY-3001 : eco cells: (36 42 0) is for feedthrough
+PHY-3001 : eco cells: (36 43 3) is for feedthrough
+PHY-3001 : eco cells: (36 44 3) is for feedthrough
+PHY-3001 : eco cells: (36 46 2) is for feedthrough
+PHY-3001 : eco cells: (36 69 1) is for feedthrough
+PHY-3001 : eco cells: (37 3 1) is for feedthrough
+PHY-3001 : eco cells: (37 12 0) is for feedthrough
+PHY-3001 : eco cells: (37 23 2) is for feedthrough
+PHY-3001 : eco cells: (37 27 0) is for feedthrough
+PHY-3001 : eco cells: (37 30 2) is for feedthrough
+PHY-3001 : eco cells: (37 31 0) is for feedthrough
+PHY-3001 : eco cells: (37 31 3) is for feedthrough
+PHY-3001 : eco cells: (37 32 1) is for feedthrough
+PHY-3001 : eco cells: (37 32 2) is for feedthrough
+PHY-3001 : eco cells: (37 33 0) is for feedthrough
+PHY-3001 : eco cells: (37 34 0) is for feedthrough
+PHY-3001 : eco cells: (37 34 3) is for feedthrough
+PHY-3001 : eco cells: (37 35 0) is for feedthrough
+PHY-3001 : eco cells: (37 35 2) is for feedthrough
+PHY-3001 : eco cells: (37 36 2) is for feedthrough
+PHY-3001 : eco cells: (37 39 0) is for feedthrough
+PHY-3001 : eco cells: (37 46 1) is for feedthrough
+PHY-3001 : eco cells: (37 55 0) is for feedthrough
+PHY-3001 : eco cells: (37 62 2) is for feedthrough
+PHY-3001 : eco cells: (38 1 1) is for feedthrough
+PHY-3001 : eco cells: (38 3 2) is for feedthrough
+PHY-3001 : eco cells: (38 27 0) is for feedthrough
+PHY-3001 : eco cells: (38 30 2) is for feedthrough
+PHY-3001 : eco cells: (38 47 2) is for feedthrough
+PHY-3001 : eco cells: (38 67 1) is for feedthrough
+PHY-3001 : eco cells: (39 4 2) is for feedthrough
+PHY-3001 : eco cells: (39 10 3) is for feedthrough
+PHY-3001 : eco cells: (39 30 3) is for feedthrough
+PHY-3001 : eco cells: (39 50 2) is for feedthrough
+PHY-3001 : eco cells: 6761 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6849 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.837281s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (98.9%)
+
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.312595s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (100.0%)
+
+RUN-1004 : used memory is 1149 MB, reserved memory is 1156 MB, peak memory is 1153 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1158, peak = 1153.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End build detailed router design. 1.966478s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.024038s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (65.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.031220s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.032288s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (96.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.033398s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (93.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.035601s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (87.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.031776s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (98.3%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End phase 1; 0.226854s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.4%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End initial routed; 0.154007s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.487280s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1177, peak = 1170.
+PHY-1001 : End phase 2; 3.641353s wall, 3.640625s user + 0.000000s system = 3.640625s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.131834s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.7%)
+
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.410068s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.151414s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.147780s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.141976s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.143699s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.142843s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.4%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.147077s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.148717s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (115.6%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.139374s wall, 0.109375s user + 0.015625s system = 0.125000s CPU (89.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.142707s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (142.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.143431s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.140026s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.143083s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.150341s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (114.3%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.264634s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (53.1%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.141605s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.137309s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.137226s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.5%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.154455s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (91.0%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.137796s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.138023s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.6%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.148360s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (115.8%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.142864s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.139695s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.136600s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.146158s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.139212s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (112.2%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.137881s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (113.3%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.137617s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.156469s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.155023s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.142916s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.143209s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.2%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.150896s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.143544s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.145775s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (117.9%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.144687s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.142278s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.145447s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.144204s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.4%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.143318s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.147248s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.5%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.148624s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (105.1%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.146656s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (117.2%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.144649s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (118.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.141113s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.146833s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.144940s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.139227s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (112.2%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.147514s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.9%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.142857s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.140540s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.151820s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.142101s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.145201s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.142768s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (109.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.144312s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.140185s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.146613s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.145257s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.6%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.140217s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (89.1%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.146207s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (117.6%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.143597s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.9%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.153618s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (91.5%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.143318s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.150626s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (114.1%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.148415s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.3%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.155175s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (90.6%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.149457s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.153463s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.151139s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.4%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.153608s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (91.5%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.141163s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.141386s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.147924s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.571950s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1177, peak = 1170.
+PHY-1001 : End phase 3; 14.939906s wall, 14.890625s user + 0.156250s system = 15.046875s CPU (100.7%)
+
+PHY-1001 : 589 feed throughs used by 430 nets
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1177, peak = 1170.
+PHY-1001 : End export database. 2.496090s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (100.2%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y24_n2beg4), nets: BUSY_MIPI_i_syn_3 sampling_fe_a/u_sort/u_transfer_300_to_200/mux16_syn_16
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 24.514648s wall, 24.421875s user + 0.171875s system = 24.593750s CPU (100.3%)
+
+RUN-1004 : used memory is 1147 MB, reserved memory is 1153 MB, peak memory is 1170 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y24_n2beg4), nets: BUSY_MIPI_i_syn_3 sampling_fe_a/u_sort/u_transfer_300_to_200/mux16_syn_16
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 170.452026s wall, 208.984375s user + 0.734375s system = 209.718750s CPU (123.0%)
+
+RUN-1004 : used memory is 1147 MB, reserved memory is 1153 MB, peak memory is 1170 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_100526.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101138.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101138.log
new file mode 100644
index 0000000..efe11ac
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101138.log
@@ -0,0 +1,696 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 10:11:38 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db hg_anlogic_place.db" in 2.742081s wall, 2.609375s user + 0.140625s system = 2.750000s CPU (100.3%)
+
+RUN-1004 : used memory is 374 MB, reserved memory is 353 MB, peak memory is 379 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param route opt_timing high"
+RUN-1002 : start command "set_param route priority routability"
+RUN-1001 : Print Route Property
+RUN-1001 : ----------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ----------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | routability | timing | *
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : ----------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72045, tnet num: 17805, tinst num: 6849, tnode num: 94791, tedge num: 119669.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.661386s wall, 1.625000s user + 0.031250s system = 1.656250s CPU (99.7%)
+
+RUN-1004 : used memory is 501 MB, reserved memory is 484 MB, peak memory is 501 MB
+PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+PHY-1001 : Routability prioritized.
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 846032, over cnt = 2656(7%), over = 4489, worst = 9
+PHY-1002 : len = 864952, over cnt = 1635(4%), over = 2372, worst = 9
+PHY-1002 : len = 888664, over cnt = 404(1%), over = 544, worst = 7
+PHY-1002 : len = 896896, over cnt = 21(0%), over = 32, worst = 7
+PHY-1002 : len = 897232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.414847s wall, 4.468750s user + 0.062500s system = 4.531250s CPU (132.7%)
+
+PHY-1001 : Congestion index: top1 = 55.52, top5 = 50.19, top10 = 46.84, top15 = 44.60.
+PHY-1001 : End global routing; 3.712590s wall, 4.734375s user + 0.078125s system = 4.812500s CPU (129.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Routability prioritized.
+PHY-1001 : Current memory(MB): used = 668, reserve = 656, peak = 668.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 964, reserve = 958, peak = 964.
+PHY-1001 : End build detailed router design. 4.327209s wall, 4.281250s user + 0.046875s system = 4.328125s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267368, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.235930s wall, 6.187500s user + 0.031250s system = 6.218750s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267424, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.523152s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (101.5%)
+
+PHY-1001 : Current memory(MB): used = 1001, reserve = 995, peak = 1001.
+PHY-1001 : End phase 1; 6.771743s wall, 6.718750s user + 0.031250s system = 6.750000s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1016, peak = 1021.
+PHY-1001 : End initial routed; 32.520606s wall, 69.328125s user + 0.359375s system = 69.687500s CPU (214.3%)
+
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1016, peak = 1021.
+PHY-1001 : End phase 2; 32.520650s wall, 69.328125s user + 0.359375s system = 69.687500s CPU (214.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.21129e+06, over cnt = 697(0%), over = 697, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.084650s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (167.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.21005e+06, over cnt = 197(0%), over = 197, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.783919s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (155.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.20993e+06, over cnt = 61(0%), over = 61, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.519143s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (129.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.21079e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.275660s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (119.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.21089e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.279901s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (122.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.21089e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.266985s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.21089e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.428085s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.2109e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.196943s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (111.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.21091e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.206867s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 588 feed throughs used by 424 nets
+PHY-1001 : End commit to database; 2.337004s wall, 2.265625s user + 0.062500s system = 2.328125s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1123, reserve = 1122, peak = 1123.
+PHY-1001 : End phase 3; 7.824634s wall, 9.890625s user + 0.062500s system = 9.953125s CPU (127.2%)
+
+PHY-1003 : Routed, final wirelength = 2.21091e+06
+PHY-1001 : Current memory(MB): used = 1127, reserve = 1127, peak = 1127.
+PHY-1001 : End export database. 0.065240s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.8%)
+
+PHY-1001 : End detail routing; 51.877298s wall, 90.640625s user + 0.515625s system = 91.156250s CPU (175.7%)
+
+RUN-1003 : finish command "route" in 58.331756s wall, 98.031250s user + 0.671875s system = 98.703125s CPU (169.2%)
+
+RUN-1004 : used memory is 888 MB, reserved memory is 893 MB, peak memory is 1127 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10176 out of 19600 51.92%
+#reg 9605 out of 19600 49.01%
+#le 12565
+ #lut only 2960 out of 12565 23.56%
+ #reg only 2389 out of 12565 19.01%
+ #lut® 7216 out of 12565 57.43%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1801
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1451
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1331
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 929
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/current_state[0]_syn_405.q0 136
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg2_syn_159.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_eot_min/reg1_syn_320.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P15 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P39 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P32 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P118 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P106 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12565 |9149 |1027 |9639 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |539 |450 |23 |441 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |92 |4 |87 |4 |0 |
+| U_crc16_24b |crc16_24b |50 |50 |0 |24 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |8 |0 |0 |
+| exdev_ctl_a |exdev_ctl |763 |389 |96 |582 |0 |0 |
+| u_ADconfig |AD_config |188 |124 |25 |146 |0 |0 |
+| u_gen_sp |gen_sp |257 |152 |71 |118 |0 |0 |
+| exdev_ctl_b |exdev_ctl |732 |367 |96 |543 |0 |0 |
+| u_ADconfig |AD_config |161 |110 |25 |116 |0 |0 |
+| u_gen_sp |gen_sp |264 |168 |71 |120 |0 |0 |
+| sampling_fe_a |sampling_fe |3081 |2437 |306 |2126 |25 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |99 |17 |162 |0 |0 |
+| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_sort |sort |2856 |2326 |289 |1929 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2406 |2021 |253 |1556 |22 |0 |
+| channelPart |channel_part_8478 |147 |135 |3 |142 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1880 |1574 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |114 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |17 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |17 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |23 |20 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| insert |insert |946 |667 |170 |639 |0 |0 |
+| ram_switch_state |ram_switch_state |713 |713 |0 |396 |0 |0 |
+| read_ram_i |read_ram |287 |234 |44 |192 |0 |0 |
+| read_ram_addr |read_ram_addr |229 |189 |40 |150 |0 |0 |
+| read_ram_data |read_ram_data |55 |42 |4 |39 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |328 |226 |36 |270 |3 |0 |
+| u0_soft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3256 |2498 |349 |2115 |25 |1 |
+| u0_soft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |106 |17 |160 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort_rev |3034 |2385 |332 |1922 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2579 |2042 |290 |1557 |22 |1 |
+| channelPart |channel_part_8478 |135 |125 |3 |128 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1988 |1585 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |203 |176 |27 |98 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |14 |11 |3 |6 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |16 |13 |3 |6 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| insert |insert |971 |598 |170 |682 |0 |0 |
+| ram_switch_state |ram_switch_state |814 |811 |0 |369 |0 |0 |
+| read_ram_i |read_ram_rev |370 |263 |81 |210 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |314 |229 |73 |169 |0 |0 |
+| read_ram_data |read_ram_data_rev |56 |34 |8 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10013
+ #2 2 4263
+ #3 3 1670
+ #4 4 572
+ #5 5-10 791
+ #6 11-50 565
+ #7 51-100 12
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.205464s wall, 3.718750s user + 0.015625s system = 3.734375s CPU (169.3%)
+
+RUN-1004 : used memory is 910 MB, reserved memory is 915 MB, peak memory is 1127 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72045, tnet num: 17805, tinst num: 6849, tnode num: 94791, tedge num: 119669.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.689250s wall, 1.671875s user + 0.015625s system = 1.687500s CPU (99.9%)
+
+RUN-1004 : used memory is 955 MB, reserved memory is 953 MB, peak memory is 1127 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.581854s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.8%)
+
+RUN-1004 : used memory is 1046 MB, reserved memory is 1046 MB, peak memory is 1127 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_101138.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101250.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101250.log
new file mode 100644
index 0000000..f414c21
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101250.log
@@ -0,0 +1,257 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 10:12:51 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 588 feed throughs used by 424 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db hg_anlogic_pr.db" in 12.902920s wall, 12.468750s user + 0.218750s system = 12.687500s CPU (98.3%)
+
+RUN-1004 : used memory is 792 MB, reserved memory is 785 MB, peak memory is 819 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6849
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17983, pip num: 167676
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 588
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 468383 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.289372s wall, 65.015625s user + 0.453125s system = 65.468750s CPU (636.3%)
+
+RUN-1004 : used memory is 815 MB, reserved memory is 824 MB, peak memory is 1085 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_101250.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101657.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101657.log
new file mode 100644
index 0000000..7d67b36
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_101657.log
@@ -0,0 +1,2043 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 10:16:57 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db hg_anlogic_place.db" in 2.729693s wall, 2.593750s user + 0.125000s system = 2.718750s CPU (99.6%)
+
+RUN-1004 : used memory is 374 MB, reserved memory is 353 MB, peak memory is 379 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param route opt_timing high"
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72045, tnet num: 17805, tinst num: 6849, tnode num: 94791, tedge num: 119669.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.669018s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.2%)
+
+RUN-1004 : used memory is 501 MB, reserved memory is 484 MB, peak memory is 501 MB
+PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[0] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 846032, over cnt = 2656(7%), over = 4489, worst = 9
+PHY-1002 : len = 864952, over cnt = 1635(4%), over = 2372, worst = 9
+PHY-1002 : len = 888664, over cnt = 404(1%), over = 544, worst = 7
+PHY-1002 : len = 896896, over cnt = 21(0%), over = 32, worst = 7
+PHY-1002 : len = 897232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.315814s wall, 4.265625s user + 0.000000s system = 4.265625s CPU (128.6%)
+
+PHY-1001 : Congestion index: top1 = 55.52, top5 = 50.19, top10 = 46.84, top15 = 44.60.
+PHY-1001 : End global routing; 3.619058s wall, 4.546875s user + 0.000000s system = 4.546875s CPU (125.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 667, reserve = 656, peak = 667.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 963, reserve = 957, peak = 963.
+PHY-1001 : End build detailed router design. 4.319054s wall, 4.281250s user + 0.046875s system = 4.328125s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267368, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.832705s wall, 5.828125s user + 0.000000s system = 5.828125s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267424, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.590066s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (98.0%)
+
+PHY-1001 : Current memory(MB): used = 999, reserve = 994, peak = 999.
+PHY-1001 : End phase 1; 6.438646s wall, 6.421875s user + 0.000000s system = 6.421875s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1016, peak = 1021.
+PHY-1001 : End initial routed; 31.564489s wall, 67.578125s user + 0.218750s system = 67.796875s CPU (214.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.467919s wall, 3.390625s user + 0.078125s system = 3.468750s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1031, peak = 1030.
+PHY-1001 : End phase 2; 35.032491s wall, 70.968750s user + 0.296875s system = 71.265625s CPU (203.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.140862s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.8%)
+
+PHY-1022 : len = 2.24534e+06, over cnt = 1885(0%), over = 1894, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.431631s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.21014e+06, over cnt = 712(0%), over = 713, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.069162s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (166.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.20853e+06, over cnt = 179(0%), over = 179, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.875456s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (149.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.20974e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.519476s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (123.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.21006e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.379142s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (111.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.265939s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (117.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.394150s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.676631s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.21018e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.184666s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.207263s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.5%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.229472s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.239128s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.374298s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (96.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.193659s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.194057s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.228442s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.237894s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (105.1%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.370457s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.423832s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.182579s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (111.3%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.189365s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.226256s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.239499s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.370893s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.426621s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.188335s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.176133s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.188365s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.218933s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (107.1%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.233078s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (127.4%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.369900s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.419442s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.330004s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.384059s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.179071s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.188756s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.243204s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (122.1%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.237398s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.385576s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.421663s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.240106s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.222144s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.213779s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.181638s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (111.8%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.191035s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.223224s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (112.0%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.238666s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.369784s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.418422s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.268844s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.355527s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.272058s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.259938s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (98.0%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.194177s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.6%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.193648s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.231721s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (94.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.242398s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (109.6%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.387066s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.436943s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.220320s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.186522s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.186682s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.345178s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.224395s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.178718s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.182869s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.242014s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.244415s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (108.7%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.384093s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.443161s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.362050s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.226564s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.205795s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.187639s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.194034s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.376989s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (99.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.509816s wall, 3.468750s user + 0.046875s system = 3.515625s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1036, peak = 1037.
+PHY-1001 : End phase 3; 48.823821s wall, 50.937500s user + 0.109375s system = 51.046875s CPU (104.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.140619s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.0%)
+
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.404733s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.189480s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.216109s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.284701s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (104.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.177068s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 5 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.182614s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.224414s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (118.4%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.232942s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.364217s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.7%)
+
+PHY-1001 : ===== DR Iter 9 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.183390s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.197801s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.225700s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.241151s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.387307s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.433479s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.3%)
+
+PHY-1001 : ===== DR Iter 15 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.193871s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.8%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.243785s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.257991s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.248643s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.399091s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.534657s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 1.283675s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 22 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.177945s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.187085s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.232684s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (94.0%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.239620s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (110.9%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.398664s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.455965s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 1.236170s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 1.226370s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 30 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.179365s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (113.2%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.190183s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.225311s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.0%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.242127s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.399172s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.445706s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 1.212857s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 1.241440s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.354764s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 39 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.187922s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.191667s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.227259s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (96.3%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.236721s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.373264s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.432581s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 1.194378s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.200264s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.203669s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.200677s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 49 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.197819s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.198352s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.228141s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.248723s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.376317s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.431119s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 1.430508s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 1.279756s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.203095s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.210790s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.234104s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 60 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.180136s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.1%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.197627s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.236807s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (112.2%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.245900s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.373284s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.444908s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 1.213515s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 1.236405s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.365112s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.224042s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.215763s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.207988s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.580443s wall, 3.515625s user + 0.046875s system = 3.562500s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1038, peak = 1039.
+PHY-1001 : End phase 4; 44.069064s wall, 44.015625s user + 0.125000s system = 44.140625s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.2102e+06
+PHY-1001 : 589 feed throughs used by 430 nets
+PHY-1001 : Current memory(MB): used = 1140, reserve = 1147, peak = 1140.
+PHY-1001 : End export database. 2.466165s wall, 2.453125s user + 0.015625s system = 2.468750s CPU (100.1%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 11 3) is for feedthrough
+PHY-3001 : eco cells: (1 17 2) is for feedthrough
+PHY-3001 : eco cells: (1 26 3) is for feedthrough
+PHY-3001 : eco cells: (1 53 1) is for feedthrough
+PHY-3001 : eco cells: (2 6 3) is for feedthrough
+PHY-3001 : eco cells: (2 8 3) is for feedthrough
+PHY-3001 : eco cells: (2 11 2) is for feedthrough
+PHY-3001 : eco cells: (2 12 1) is for feedthrough
+PHY-3001 : eco cells: (2 13 1) is for feedthrough
+PHY-3001 : eco cells: (2 14 0) is for feedthrough
+PHY-3001 : eco cells: (2 14 1) is for feedthrough
+PHY-3001 : eco cells: (2 14 3) is for feedthrough
+PHY-3001 : eco cells: (2 16 3) is for feedthrough
+PHY-3001 : eco cells: (2 18 2) is for feedthrough
+PHY-3001 : eco cells: (2 23 3) is for feedthrough
+PHY-3001 : eco cells: (2 25 1) is for feedthrough
+PHY-3001 : eco cells: (2 25 2) is for feedthrough
+PHY-3001 : eco cells: (2 27 3) is for feedthrough
+PHY-3001 : eco cells: (2 29 2) is for feedthrough
+PHY-3001 : eco cells: (2 34 2) is for feedthrough
+PHY-3001 : eco cells: (2 44 0) is for feedthrough
+PHY-3001 : eco cells: (2 45 0) is for feedthrough
+PHY-3001 : eco cells: (3 4 2) is for feedthrough
+PHY-3001 : eco cells: (3 6 1) is for feedthrough
+PHY-3001 : eco cells: (3 7 3) is for feedthrough
+PHY-3001 : eco cells: (3 8 0) is for feedthrough
+PHY-3001 : eco cells: (3 14 2) is for feedthrough
+PHY-3001 : eco cells: (3 15 3) is for feedthrough
+PHY-3001 : eco cells: (3 18 1) is for feedthrough
+PHY-3001 : eco cells: (3 20 2) is for feedthrough
+PHY-3001 : eco cells: (3 21 1) is for feedthrough
+PHY-3001 : eco cells: (3 23 2) is for feedthrough
+PHY-3001 : eco cells: (3 46 0) is for feedthrough
+PHY-3001 : eco cells: (3 49 2) is for feedthrough
+PHY-3001 : eco cells: (3 50 1) is for feedthrough
+PHY-3001 : eco cells: (3 51 0) is for feedthrough
+PHY-3001 : eco cells: (3 51 2) is for feedthrough
+PHY-3001 : eco cells: (3 55 3) is for feedthrough
+PHY-3001 : eco cells: (3 56 0) is for feedthrough
+PHY-3001 : eco cells: (3 61 1) is for feedthrough
+PHY-3001 : eco cells: (3 67 1) is for feedthrough
+PHY-3001 : eco cells: (4 4 0) is for feedthrough
+PHY-3001 : eco cells: (4 5 3) is for feedthrough
+PHY-3001 : eco cells: (4 6 3) is for feedthrough
+PHY-3001 : eco cells: (4 7 3) is for feedthrough
+PHY-3001 : eco cells: (4 8 3) is for feedthrough
+PHY-3001 : eco cells: (4 10 1) is for feedthrough
+PHY-3001 : eco cells: (4 11 0) is for feedthrough
+PHY-3001 : eco cells: (4 15 2) is for feedthrough
+PHY-3001 : eco cells: (4 17 3) is for feedthrough
+PHY-3001 : eco cells: (4 18 3) is for feedthrough
+PHY-3001 : eco cells: (4 19 2) is for feedthrough
+PHY-3001 : eco cells: (4 25 2) is for feedthrough
+PHY-3001 : eco cells: (4 33 0) is for feedthrough
+PHY-3001 : eco cells: (4 34 1) is for feedthrough
+PHY-3001 : eco cells: (4 48 0) is for feedthrough
+PHY-3001 : eco cells: (4 49 3) is for feedthrough
+PHY-3001 : eco cells: (4 50 0) is for feedthrough
+PHY-3001 : eco cells: (4 51 2) is for feedthrough
+PHY-3001 : eco cells: (4 52 1) is for feedthrough
+PHY-3001 : eco cells: (4 52 2) is for feedthrough
+PHY-3001 : eco cells: (4 53 3) is for feedthrough
+PHY-3001 : eco cells: (5 3 3) is for feedthrough
+PHY-3001 : eco cells: (5 5 1) is for feedthrough
+PHY-3001 : eco cells: (5 7 0) is for feedthrough
+PHY-3001 : eco cells: (5 12 2) is for feedthrough
+PHY-3001 : eco cells: (5 14 2) is for feedthrough
+PHY-3001 : eco cells: (5 15 3) is for feedthrough
+PHY-3001 : eco cells: (5 17 3) is for feedthrough
+PHY-3001 : eco cells: (5 19 1) is for feedthrough
+PHY-3001 : eco cells: (5 24 2) is for feedthrough
+PHY-3001 : eco cells: (5 24 3) is for feedthrough
+PHY-3001 : eco cells: (5 31 1) is for feedthrough
+PHY-3001 : eco cells: (5 46 3) is for feedthrough
+PHY-3001 : eco cells: (5 49 3) is for feedthrough
+PHY-3001 : eco cells: (5 52 2) is for feedthrough
+PHY-3001 : eco cells: (5 54 2) is for feedthrough
+PHY-3001 : eco cells: (5 67 3) is for feedthrough
+PHY-3001 : eco cells: (6 6 3) is for feedthrough
+PHY-3001 : eco cells: (6 8 2) is for feedthrough
+PHY-3001 : eco cells: (6 8 3) is for feedthrough
+PHY-3001 : eco cells: (6 14 0) is for feedthrough
+PHY-3001 : eco cells: (6 14 1) is for feedthrough
+PHY-3001 : eco cells: (6 14 3) is for feedthrough
+PHY-3001 : eco cells: (6 19 3) is for feedthrough
+PHY-3001 : eco cells: (6 23 2) is for feedthrough
+PHY-3001 : eco cells: (6 23 3) is for feedthrough
+PHY-3001 : eco cells: (6 26 0) is for feedthrough
+PHY-3001 : eco cells: (6 27 2) is for feedthrough
+PHY-3001 : eco cells: (6 33 0) is for feedthrough
+PHY-3001 : eco cells: (6 48 1) is for feedthrough
+PHY-3001 : eco cells: (6 50 0) is for feedthrough
+PHY-3001 : eco cells: (6 51 3) is for feedthrough
+PHY-3001 : eco cells: (6 58 2) is for feedthrough
+PHY-3001 : eco cells: (6 60 1) is for feedthrough
+PHY-3001 : eco cells: (7 9 2) is for feedthrough
+PHY-3001 : eco cells: (7 10 1) is for feedthrough
+PHY-3001 : eco cells: (7 16 1) is for feedthrough
+PHY-3001 : eco cells: (7 16 2) is for feedthrough
+PHY-3001 : eco cells: (7 18 2) is for feedthrough
+PHY-3001 : eco cells: (7 20 1) is for feedthrough
+PHY-3001 : eco cells: (7 51 0) is for feedthrough
+PHY-3001 : eco cells: (7 52 0) is for feedthrough
+PHY-3001 : eco cells: (7 54 1) is for feedthrough
+PHY-3001 : eco cells: (7 54 3) is for feedthrough
+PHY-3001 : eco cells: (7 58 2) is for feedthrough
+PHY-3001 : eco cells: (7 59 2) is for feedthrough
+PHY-3001 : eco cells: (9 7 0) is for feedthrough
+PHY-3001 : eco cells: (9 7 1) is for feedthrough
+PHY-3001 : eco cells: (9 9 3) is for feedthrough
+PHY-3001 : eco cells: (9 10 3) is for feedthrough
+PHY-3001 : eco cells: (9 13 2) is for feedthrough
+PHY-3001 : eco cells: (9 18 1) is for feedthrough
+PHY-3001 : eco cells: (9 38 1) is for feedthrough
+PHY-3001 : eco cells: (9 38 2) is for feedthrough
+PHY-3001 : eco cells: (9 53 1) is for feedthrough
+PHY-3001 : eco cells: (10 2 1) is for feedthrough
+PHY-3001 : eco cells: (10 10 0) is for feedthrough
+PHY-3001 : eco cells: (10 16 1) is for feedthrough
+PHY-3001 : eco cells: (10 17 3) is for feedthrough
+PHY-3001 : eco cells: (10 20 1) is for feedthrough
+PHY-3001 : eco cells: (10 21 2) is for feedthrough
+PHY-3001 : eco cells: (10 22 3) is for feedthrough
+PHY-3001 : eco cells: (10 24 0) is for feedthrough
+PHY-3001 : eco cells: (10 36 1) is for feedthrough
+PHY-3001 : eco cells: (10 38 2) is for feedthrough
+PHY-3001 : eco cells: (10 44 1) is for feedthrough
+PHY-3001 : eco cells: (10 45 3) is for feedthrough
+PHY-3001 : eco cells: (10 49 0) is for feedthrough
+PHY-3001 : eco cells: (10 54 3) is for feedthrough
+PHY-3001 : eco cells: (10 69 1) is for feedthrough
+PHY-3001 : eco cells: (11 5 3) is for feedthrough
+PHY-3001 : eco cells: (11 14 2) is for feedthrough
+PHY-3001 : eco cells: (11 17 1) is for feedthrough
+PHY-3001 : eco cells: (11 18 1) is for feedthrough
+PHY-3001 : eco cells: (11 19 1) is for feedthrough
+PHY-3001 : eco cells: (11 27 2) is for feedthrough
+PHY-3001 : eco cells: (11 39 1) is for feedthrough
+PHY-3001 : eco cells: (11 40 0) is for feedthrough
+PHY-3001 : eco cells: (11 40 3) is for feedthrough
+PHY-3001 : eco cells: (11 41 3) is for feedthrough
+PHY-3001 : eco cells: (11 42 3) is for feedthrough
+PHY-3001 : eco cells: (11 54 0) is for feedthrough
+PHY-3001 : eco cells: (11 67 3) is for feedthrough
+PHY-3001 : eco cells: (11 69 0) is for feedthrough
+PHY-3001 : eco cells: (12 6 2) is for feedthrough
+PHY-3001 : eco cells: (12 6 3) is for feedthrough
+PHY-3001 : eco cells: (12 10 3) is for feedthrough
+PHY-3001 : eco cells: (12 15 3) is for feedthrough
+PHY-3001 : eco cells: (12 16 1) is for feedthrough
+PHY-3001 : eco cells: (12 18 2) is for feedthrough
+PHY-3001 : eco cells: (12 23 3) is for feedthrough
+PHY-3001 : eco cells: (12 28 3) is for feedthrough
+PHY-3001 : eco cells: (12 38 2) is for feedthrough
+PHY-3001 : eco cells: (12 39 1) is for feedthrough
+PHY-3001 : eco cells: (12 41 2) is for feedthrough
+PHY-3001 : eco cells: (12 66 1) is for feedthrough
+PHY-3001 : eco cells: (12 66 3) is for feedthrough
+PHY-3001 : eco cells: (13 5 2) is for feedthrough
+PHY-3001 : eco cells: (13 7 1) is for feedthrough
+PHY-3001 : eco cells: (13 12 0) is for feedthrough
+PHY-3001 : eco cells: (13 23 1) is for feedthrough
+PHY-3001 : eco cells: (13 33 0) is for feedthrough
+PHY-3001 : eco cells: (13 37 1) is for feedthrough
+PHY-3001 : eco cells: (13 38 1) is for feedthrough
+PHY-3001 : eco cells: (13 38 3) is for feedthrough
+PHY-3001 : eco cells: (13 39 2) is for feedthrough
+PHY-3001 : eco cells: (13 54 3) is for feedthrough
+PHY-3001 : eco cells: (13 61 2) is for feedthrough
+PHY-3001 : eco cells: (14 2 0) is for feedthrough
+PHY-3001 : eco cells: (14 6 0) is for feedthrough
+PHY-3001 : eco cells: (14 8 1) is for feedthrough
+PHY-3001 : eco cells: (14 8 2) is for feedthrough
+PHY-3001 : eco cells: (14 10 3) is for feedthrough
+PHY-3001 : eco cells: (14 11 2) is for feedthrough
+PHY-3001 : eco cells: (14 12 3) is for feedthrough
+PHY-3001 : eco cells: (14 27 0) is for feedthrough
+PHY-3001 : eco cells: (14 32 0) is for feedthrough
+PHY-3001 : eco cells: (14 38 3) is for feedthrough
+PHY-3001 : eco cells: (14 39 0) is for feedthrough
+PHY-3001 : eco cells: (14 42 0) is for feedthrough
+PHY-3001 : eco cells: (15 5 0) is for feedthrough
+PHY-3001 : eco cells: (15 5 1) is for feedthrough
+PHY-3001 : eco cells: (15 6 3) is for feedthrough
+PHY-3001 : eco cells: (15 8 0) is for feedthrough
+PHY-3001 : eco cells: (15 9 3) is for feedthrough
+PHY-3001 : eco cells: (15 10 1) is for feedthrough
+PHY-3001 : eco cells: (15 17 0) is for feedthrough
+PHY-3001 : eco cells: (15 19 3) is for feedthrough
+PHY-3001 : eco cells: (15 29 2) is for feedthrough
+PHY-3001 : eco cells: (15 38 3) is for feedthrough
+PHY-3001 : eco cells: (15 39 2) is for feedthrough
+PHY-3001 : eco cells: (15 41 1) is for feedthrough
+PHY-3001 : eco cells: (15 42 0) is for feedthrough
+PHY-3001 : eco cells: (15 43 2) is for feedthrough
+PHY-3001 : eco cells: (15 44 3) is for feedthrough
+PHY-3001 : eco cells: (15 53 3) is for feedthrough
+PHY-3001 : eco cells: (15 54 3) is for feedthrough
+PHY-3001 : eco cells: (15 55 3) is for feedthrough
+PHY-3001 : eco cells: (15 62 2) is for feedthrough
+PHY-3001 : eco cells: (15 67 2) is for feedthrough
+PHY-3001 : eco cells: (15 68 0) is for feedthrough
+PHY-3001 : eco cells: (17 7 0) is for feedthrough
+PHY-3001 : eco cells: (17 7 3) is for feedthrough
+PHY-3001 : eco cells: (17 8 2) is for feedthrough
+PHY-3001 : eco cells: (17 10 1) is for feedthrough
+PHY-3001 : eco cells: (17 12 1) is for feedthrough
+PHY-3001 : eco cells: (17 13 0) is for feedthrough
+PHY-3001 : eco cells: (17 20 0) is for feedthrough
+PHY-3001 : eco cells: (17 22 3) is for feedthrough
+PHY-3001 : eco cells: (17 26 3) is for feedthrough
+PHY-3001 : eco cells: (17 27 3) is for feedthrough
+PHY-3001 : eco cells: (17 30 3) is for feedthrough
+PHY-3001 : eco cells: (17 31 3) is for feedthrough
+PHY-3001 : eco cells: (17 33 3) is for feedthrough
+PHY-3001 : eco cells: (17 47 3) is for feedthrough
+PHY-3001 : eco cells: (17 52 3) is for feedthrough
+PHY-3001 : eco cells: (17 54 3) is for feedthrough
+PHY-3001 : eco cells: (17 56 3) is for feedthrough
+PHY-3001 : eco cells: (18 2 3) is for feedthrough
+PHY-3001 : eco cells: (18 3 1) is for feedthrough
+PHY-3001 : eco cells: (18 5 0) is for feedthrough
+PHY-3001 : eco cells: (18 6 3) is for feedthrough
+PHY-3001 : eco cells: (18 10 0) is for feedthrough
+PHY-3001 : eco cells: (18 19 3) is for feedthrough
+PHY-3001 : eco cells: (18 20 3) is for feedthrough
+PHY-3001 : eco cells: (18 21 2) is for feedthrough
+PHY-3001 : eco cells: (18 22 2) is for feedthrough
+PHY-3001 : eco cells: (18 24 1) is for feedthrough
+PHY-3001 : eco cells: (18 27 2) is for feedthrough
+PHY-3001 : eco cells: (18 29 0) is for feedthrough
+PHY-3001 : eco cells: (18 32 2) is for feedthrough
+PHY-3001 : eco cells: (18 55 1) is for feedthrough
+PHY-3001 : eco cells: (18 62 3) is for feedthrough
+PHY-3001 : eco cells: (19 1 1) is for feedthrough
+PHY-3001 : eco cells: (19 2 0) is for feedthrough
+PHY-3001 : eco cells: (19 6 3) is for feedthrough
+PHY-3001 : eco cells: (19 19 3) is for feedthrough
+PHY-3001 : eco cells: (19 20 3) is for feedthrough
+PHY-3001 : eco cells: (19 21 1) is for feedthrough
+PHY-3001 : eco cells: (19 22 1) is for feedthrough
+PHY-3001 : eco cells: (19 22 3) is for feedthrough
+PHY-3001 : eco cells: (19 23 2) is for feedthrough
+PHY-3001 : eco cells: (19 24 3) is for feedthrough
+PHY-3001 : eco cells: (19 25 3) is for feedthrough
+PHY-3001 : eco cells: (19 26 2) is for feedthrough
+PHY-3001 : eco cells: (19 28 0) is for feedthrough
+PHY-3001 : eco cells: (19 28 1) is for feedthrough
+PHY-3001 : eco cells: (19 29 0) is for feedthrough
+PHY-3001 : eco cells: (19 29 1) is for feedthrough
+PHY-3001 : eco cells: (19 31 0) is for feedthrough
+PHY-3001 : eco cells: (19 33 0) is for feedthrough
+PHY-3001 : eco cells: (19 34 3) is for feedthrough
+PHY-3001 : eco cells: (19 36 2) is for feedthrough
+PHY-3001 : eco cells: (19 53 3) is for feedthrough
+PHY-3001 : eco cells: (19 54 0) is for feedthrough
+PHY-3001 : eco cells: (19 54 1) is for feedthrough
+PHY-3001 : eco cells: (19 56 2) is for feedthrough
+PHY-3001 : eco cells: (20 3 1) is for feedthrough
+PHY-3001 : eco cells: (20 6 1) is for feedthrough
+PHY-3001 : eco cells: (20 7 1) is for feedthrough
+PHY-3001 : eco cells: (20 7 3) is for feedthrough
+PHY-3001 : eco cells: (20 20 0) is for feedthrough
+PHY-3001 : eco cells: (20 22 0) is for feedthrough
+PHY-3001 : eco cells: (20 24 0) is for feedthrough
+PHY-3001 : eco cells: (20 24 2) is for feedthrough
+PHY-3001 : eco cells: (20 24 3) is for feedthrough
+PHY-3001 : eco cells: (20 25 3) is for feedthrough
+PHY-3001 : eco cells: (20 27 0) is for feedthrough
+PHY-3001 : eco cells: (20 32 0) is for feedthrough
+PHY-3001 : eco cells: (20 35 0) is for feedthrough
+PHY-3001 : eco cells: (20 36 1) is for feedthrough
+PHY-3001 : eco cells: (20 46 1) is for feedthrough
+PHY-3001 : eco cells: (20 54 3) is for feedthrough
+PHY-3001 : eco cells: (20 55 2) is for feedthrough
+PHY-3001 : eco cells: (20 62 1) is for feedthrough
+PHY-3001 : eco cells: (21 2 1) is for feedthrough
+PHY-3001 : eco cells: (21 8 0) is for feedthrough
+PHY-3001 : eco cells: (21 22 1) is for feedthrough
+PHY-3001 : eco cells: (21 26 2) is for feedthrough
+PHY-3001 : eco cells: (21 36 2) is for feedthrough
+PHY-3001 : eco cells: (21 55 2) is for feedthrough
+PHY-3001 : eco cells: (21 57 1) is for feedthrough
+PHY-3001 : eco cells: (21 59 0) is for feedthrough
+PHY-3001 : eco cells: (21 59 1) is for feedthrough
+PHY-3001 : eco cells: (21 61 2) is for feedthrough
+PHY-3001 : eco cells: (21 63 0) is for feedthrough
+PHY-3001 : eco cells: (22 1 0) is for feedthrough
+PHY-3001 : eco cells: (22 20 0) is for feedthrough
+PHY-3001 : eco cells: (22 23 3) is for feedthrough
+PHY-3001 : eco cells: (22 25 1) is for feedthrough
+PHY-3001 : eco cells: (22 25 3) is for feedthrough
+PHY-3001 : eco cells: (22 26 1) is for feedthrough
+PHY-3001 : eco cells: (22 31 1) is for feedthrough
+PHY-3001 : eco cells: (22 45 0) is for feedthrough
+PHY-3001 : eco cells: (22 55 0) is for feedthrough
+PHY-3001 : eco cells: (22 56 1) is for feedthrough
+PHY-3001 : eco cells: (22 57 1) is for feedthrough
+PHY-3001 : eco cells: (22 68 2) is for feedthrough
+PHY-3001 : eco cells: (23 4 3) is for feedthrough
+PHY-3001 : eco cells: (23 21 2) is for feedthrough
+PHY-3001 : eco cells: (23 22 2) is for feedthrough
+PHY-3001 : eco cells: (23 27 3) is for feedthrough
+PHY-3001 : eco cells: (23 55 0) is for feedthrough
+PHY-3001 : eco cells: (23 56 1) is for feedthrough
+PHY-3001 : eco cells: (23 56 3) is for feedthrough
+PHY-3001 : eco cells: (23 57 0) is for feedthrough
+PHY-3001 : eco cells: (25 5 1) is for feedthrough
+PHY-3001 : eco cells: (25 24 1) is for feedthrough
+PHY-3001 : eco cells: (25 24 2) is for feedthrough
+PHY-3001 : eco cells: (25 41 1) is for feedthrough
+PHY-3001 : eco cells: (25 55 0) is for feedthrough
+PHY-3001 : eco cells: (25 58 3) is for feedthrough
+PHY-3001 : eco cells: (26 58 1) is for feedthrough
+PHY-3001 : eco cells: (26 69 2) is for feedthrough
+PHY-3001 : eco cells: (27 1 3) is for feedthrough
+PHY-3001 : eco cells: (27 3 3) is for feedthrough
+PHY-3001 : eco cells: (27 26 3) is for feedthrough
+PHY-3001 : eco cells: (27 31 2) is for feedthrough
+PHY-3001 : eco cells: (27 36 3) is for feedthrough
+PHY-3001 : eco cells: (27 41 1) is for feedthrough
+PHY-3001 : eco cells: (27 41 2) is for feedthrough
+PHY-3001 : eco cells: (27 43 2) is for feedthrough
+PHY-3001 : eco cells: (27 44 0) is for feedthrough
+PHY-3001 : eco cells: (27 44 1) is for feedthrough
+PHY-3001 : eco cells: (27 56 1) is for feedthrough
+PHY-3001 : eco cells: (27 56 3) is for feedthrough
+PHY-3001 : eco cells: (27 57 3) is for feedthrough
+PHY-3001 : eco cells: (27 58 0) is for feedthrough
+PHY-3001 : eco cells: (27 67 0) is for feedthrough
+PHY-3001 : eco cells: (27 68 3) is for feedthrough
+PHY-3001 : eco cells: (28 20 1) is for feedthrough
+PHY-3001 : eco cells: (28 21 1) is for feedthrough
+PHY-3001 : eco cells: (28 26 0) is for feedthrough
+PHY-3001 : eco cells: (28 30 2) is for feedthrough
+PHY-3001 : eco cells: (28 30 3) is for feedthrough
+PHY-3001 : eco cells: (28 31 1) is for feedthrough
+PHY-3001 : eco cells: (28 31 3) is for feedthrough
+PHY-3001 : eco cells: (28 33 3) is for feedthrough
+PHY-3001 : eco cells: (28 35 2) is for feedthrough
+PHY-3001 : eco cells: (28 35 3) is for feedthrough
+PHY-3001 : eco cells: (28 36 1) is for feedthrough
+PHY-3001 : eco cells: (28 42 3) is for feedthrough
+PHY-3001 : eco cells: (28 60 0) is for feedthrough
+PHY-3001 : eco cells: (28 62 0) is for feedthrough
+PHY-3001 : eco cells: (29 7 0) is for feedthrough
+PHY-3001 : eco cells: (29 25 0) is for feedthrough
+PHY-3001 : eco cells: (29 30 0) is for feedthrough
+PHY-3001 : eco cells: (29 31 0) is for feedthrough
+PHY-3001 : eco cells: (29 31 1) is for feedthrough
+PHY-3001 : eco cells: (29 33 0) is for feedthrough
+PHY-3001 : eco cells: (29 35 3) is for feedthrough
+PHY-3001 : eco cells: (29 39 0) is for feedthrough
+PHY-3001 : eco cells: (29 41 1) is for feedthrough
+PHY-3001 : eco cells: (29 43 2) is for feedthrough
+PHY-3001 : eco cells: (29 44 1) is for feedthrough
+PHY-3001 : eco cells: (29 45 1) is for feedthrough
+PHY-3001 : eco cells: (29 58 0) is for feedthrough
+PHY-3001 : eco cells: (29 59 3) is for feedthrough
+PHY-3001 : eco cells: (30 5 0) is for feedthrough
+PHY-3001 : eco cells: (30 9 3) is for feedthrough
+PHY-3001 : eco cells: (30 24 1) is for feedthrough
+PHY-3001 : eco cells: (30 28 0) is for feedthrough
+PHY-3001 : eco cells: (30 29 1) is for feedthrough
+PHY-3001 : eco cells: (30 31 3) is for feedthrough
+PHY-3001 : eco cells: (30 36 0) is for feedthrough
+PHY-3001 : eco cells: (30 40 0) is for feedthrough
+PHY-3001 : eco cells: (30 45 3) is for feedthrough
+PHY-3001 : eco cells: (30 50 3) is for feedthrough
+PHY-3001 : eco cells: (30 57 0) is for feedthrough
+PHY-3001 : eco cells: (31 7 0) is for feedthrough
+PHY-3001 : eco cells: (31 31 2) is for feedthrough
+PHY-3001 : eco cells: (31 31 3) is for feedthrough
+PHY-3001 : eco cells: (31 32 3) is for feedthrough
+PHY-3001 : eco cells: (31 33 2) is for feedthrough
+PHY-3001 : eco cells: (31 40 2) is for feedthrough
+PHY-3001 : eco cells: (31 66 1) is for feedthrough
+PHY-3001 : eco cells: (33 21 2) is for feedthrough
+PHY-3001 : eco cells: (33 22 2) is for feedthrough
+PHY-3001 : eco cells: (33 27 0) is for feedthrough
+PHY-3001 : eco cells: (33 28 3) is for feedthrough
+PHY-3001 : eco cells: (33 30 3) is for feedthrough
+PHY-3001 : eco cells: (33 32 2) is for feedthrough
+PHY-3001 : eco cells: (33 34 0) is for feedthrough
+PHY-3001 : eco cells: (33 36 0) is for feedthrough
+PHY-3001 : eco cells: (33 38 3) is for feedthrough
+PHY-3001 : eco cells: (33 40 0) is for feedthrough
+PHY-3001 : eco cells: (33 41 3) is for feedthrough
+PHY-3001 : eco cells: (34 18 3) is for feedthrough
+PHY-3001 : eco cells: (34 21 2) is for feedthrough
+PHY-3001 : eco cells: (34 22 2) is for feedthrough
+PHY-3001 : eco cells: (34 23 1) is for feedthrough
+PHY-3001 : eco cells: (34 23 2) is for feedthrough
+PHY-3001 : eco cells: (34 25 2) is for feedthrough
+PHY-3001 : eco cells: (34 26 2) is for feedthrough
+PHY-3001 : eco cells: (34 27 3) is for feedthrough
+PHY-3001 : eco cells: (34 28 1) is for feedthrough
+PHY-3001 : eco cells: (34 28 3) is for feedthrough
+PHY-3001 : eco cells: (34 31 1) is for feedthrough
+PHY-3001 : eco cells: (34 32 2) is for feedthrough
+PHY-3001 : eco cells: (34 33 2) is for feedthrough
+PHY-3001 : eco cells: (34 34 0) is for feedthrough
+PHY-3001 : eco cells: (34 36 0) is for feedthrough
+PHY-3001 : eco cells: (34 36 3) is for feedthrough
+PHY-3001 : eco cells: (34 37 0) is for feedthrough
+PHY-3001 : eco cells: (34 38 1) is for feedthrough
+PHY-3001 : eco cells: (34 38 3) is for feedthrough
+PHY-3001 : eco cells: (34 39 1) is for feedthrough
+PHY-3001 : eco cells: (34 58 1) is for feedthrough
+PHY-3001 : eco cells: (35 9 2) is for feedthrough
+PHY-3001 : eco cells: (35 18 0) is for feedthrough
+PHY-3001 : eco cells: (35 20 3) is for feedthrough
+PHY-3001 : eco cells: (35 21 2) is for feedthrough
+PHY-3001 : eco cells: (35 22 0) is for feedthrough
+PHY-3001 : eco cells: (35 22 1) is for feedthrough
+PHY-3001 : eco cells: (35 23 1) is for feedthrough
+PHY-3001 : eco cells: (35 24 0) is for feedthrough
+PHY-3001 : eco cells: (35 24 3) is for feedthrough
+PHY-3001 : eco cells: (35 25 0) is for feedthrough
+PHY-3001 : eco cells: (35 25 1) is for feedthrough
+PHY-3001 : eco cells: (35 28 2) is for feedthrough
+PHY-3001 : eco cells: (35 29 2) is for feedthrough
+PHY-3001 : eco cells: (35 30 1) is for feedthrough
+PHY-3001 : eco cells: (35 31 0) is for feedthrough
+PHY-3001 : eco cells: (35 31 1) is for feedthrough
+PHY-3001 : eco cells: (35 32 1) is for feedthrough
+PHY-3001 : eco cells: (35 33 1) is for feedthrough
+PHY-3001 : eco cells: (35 33 3) is for feedthrough
+PHY-3001 : eco cells: (35 34 0) is for feedthrough
+PHY-3001 : eco cells: (35 34 2) is for feedthrough
+PHY-3001 : eco cells: (35 34 3) is for feedthrough
+PHY-3001 : eco cells: (35 35 0) is for feedthrough
+PHY-3001 : eco cells: (35 37 0) is for feedthrough
+PHY-3001 : eco cells: (35 38 0) is for feedthrough
+PHY-3001 : eco cells: (35 42 2) is for feedthrough
+PHY-3001 : eco cells: (35 42 3) is for feedthrough
+PHY-3001 : eco cells: (35 44 2) is for feedthrough
+PHY-3001 : eco cells: (35 46 3) is for feedthrough
+PHY-3001 : eco cells: (35 53 1) is for feedthrough
+PHY-3001 : eco cells: (36 2 0) is for feedthrough
+PHY-3001 : eco cells: (36 3 0) is for feedthrough
+PHY-3001 : eco cells: (36 12 2) is for feedthrough
+PHY-3001 : eco cells: (36 15 1) is for feedthrough
+PHY-3001 : eco cells: (36 15 3) is for feedthrough
+PHY-3001 : eco cells: (36 17 0) is for feedthrough
+PHY-3001 : eco cells: (36 20 3) is for feedthrough
+PHY-3001 : eco cells: (36 21 0) is for feedthrough
+PHY-3001 : eco cells: (36 22 0) is for feedthrough
+PHY-3001 : eco cells: (36 22 3) is for feedthrough
+PHY-3001 : eco cells: (36 26 3) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 1) is for feedthrough
+PHY-3001 : eco cells: (36 28 3) is for feedthrough
+PHY-3001 : eco cells: (36 29 0) is for feedthrough
+PHY-3001 : eco cells: (36 30 0) is for feedthrough
+PHY-3001 : eco cells: (36 30 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 2) is for feedthrough
+PHY-3001 : eco cells: (36 32 0) is for feedthrough
+PHY-3001 : eco cells: (36 32 1) is for feedthrough
+PHY-3001 : eco cells: (36 32 3) is for feedthrough
+PHY-3001 : eco cells: (36 36 0) is for feedthrough
+PHY-3001 : eco cells: (36 36 3) is for feedthrough
+PHY-3001 : eco cells: (36 37 0) is for feedthrough
+PHY-3001 : eco cells: (36 38 1) is for feedthrough
+PHY-3001 : eco cells: (36 38 2) is for feedthrough
+PHY-3001 : eco cells: (36 39 3) is for feedthrough
+PHY-3001 : eco cells: (36 42 0) is for feedthrough
+PHY-3001 : eco cells: (36 43 3) is for feedthrough
+PHY-3001 : eco cells: (36 44 3) is for feedthrough
+PHY-3001 : eco cells: (36 46 2) is for feedthrough
+PHY-3001 : eco cells: (36 69 1) is for feedthrough
+PHY-3001 : eco cells: (37 3 1) is for feedthrough
+PHY-3001 : eco cells: (37 12 0) is for feedthrough
+PHY-3001 : eco cells: (37 23 2) is for feedthrough
+PHY-3001 : eco cells: (37 27 0) is for feedthrough
+PHY-3001 : eco cells: (37 30 2) is for feedthrough
+PHY-3001 : eco cells: (37 31 0) is for feedthrough
+PHY-3001 : eco cells: (37 31 3) is for feedthrough
+PHY-3001 : eco cells: (37 32 1) is for feedthrough
+PHY-3001 : eco cells: (37 32 2) is for feedthrough
+PHY-3001 : eco cells: (37 33 0) is for feedthrough
+PHY-3001 : eco cells: (37 34 0) is for feedthrough
+PHY-3001 : eco cells: (37 34 3) is for feedthrough
+PHY-3001 : eco cells: (37 35 0) is for feedthrough
+PHY-3001 : eco cells: (37 35 2) is for feedthrough
+PHY-3001 : eco cells: (37 36 2) is for feedthrough
+PHY-3001 : eco cells: (37 39 0) is for feedthrough
+PHY-3001 : eco cells: (37 46 1) is for feedthrough
+PHY-3001 : eco cells: (37 55 0) is for feedthrough
+PHY-3001 : eco cells: (37 62 2) is for feedthrough
+PHY-3001 : eco cells: (38 1 1) is for feedthrough
+PHY-3001 : eco cells: (38 3 2) is for feedthrough
+PHY-3001 : eco cells: (38 27 0) is for feedthrough
+PHY-3001 : eco cells: (38 30 2) is for feedthrough
+PHY-3001 : eco cells: (38 47 2) is for feedthrough
+PHY-3001 : eco cells: (38 67 1) is for feedthrough
+PHY-3001 : eco cells: (39 4 2) is for feedthrough
+PHY-3001 : eco cells: (39 10 3) is for feedthrough
+PHY-3001 : eco cells: (39 30 3) is for feedthrough
+PHY-3001 : eco cells: (39 50 2) is for feedthrough
+PHY-3001 : eco cells: 6761 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6849 instances, 6700 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3655 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.843604s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.0%)
+
+PHY-3001 : Found 505 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.282748s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (101.1%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1093 MB, peak memory is 1141 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param route opt_timing high"
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6851 instances
+RUN-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6508 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 318 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3352 mslices, 3348 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1081, reserve = 1088, peak = 1141.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1118, reserve = 1123, peak = 1141.
+PHY-1001 : End build detailed router design. 1.900785s wall, 1.890625s user + 0.015625s system = 1.906250s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.021265s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (73.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.031611s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (98.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.034802s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.032359s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (144.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.032091s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.032627s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (95.8%)
+
+PHY-1001 : Current memory(MB): used = 1118, reserve = 1123, peak = 1141.
+PHY-1001 : End phase 1; 0.221329s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1118, reserve = 1123, peak = 1141.
+PHY-1001 : End initial routed; 0.152619s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.459103s wall, 3.406250s user + 0.046875s system = 3.453125s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1119, reserve = 1126, peak = 1141.
+PHY-1001 : End phase 2; 3.611788s wall, 3.562500s user + 0.046875s system = 3.609375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.122769s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.8%)
+
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.383314s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.145136s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (107.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.146856s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.144976s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.146438s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.150657s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.143076s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.3%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.142373s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (131.7%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.135427s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.3%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.136978s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (114.1%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.140835s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.139470s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.141317s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.143499s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (108.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.136642s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.5%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.137563s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (113.6%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.137208s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.137348s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.4%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.140773s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.142809s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.139770s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.136514s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.136991s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.136390s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.6%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.137685s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.145489s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.138220s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.138689s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.136537s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.6%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.139873s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.137598s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.141207s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.139881s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.139987s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.139075s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.140245s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (89.1%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.135257s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (127.1%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.136774s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.136888s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.137412s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.0%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.141166s wall, 0.156250s user + 0.046875s system = 0.203125s CPU (143.9%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.137825s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.7%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.141471s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.137562s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.136574s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.5%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.138704s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.142107s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.140697s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (88.8%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.136917s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.137703s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.138152s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.136113s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.8%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.147215s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.1%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.137330s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.136662s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.136885s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.3%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.142156s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (109.9%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.137612s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.8%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.138360s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.137661s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.138668s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.137205s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.135705s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.1%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.147174s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.2%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.140177s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.136980s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.142790s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.140494s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.139302s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.136623s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.137531s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.9%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.145435s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.4%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.143686s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.145609s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2102e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.147979s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16905(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.521170s wall, 3.453125s user + 0.031250s system = 3.484375s CPU (99.0%)
+
+PHY-1001 : Current memory(MB): used = 1119, reserve = 1130, peak = 1141.
+PHY-1001 : End phase 3; 14.376438s wall, 14.359375s user + 0.140625s system = 14.500000s CPU (100.9%)
+
+PHY-1001 : 589 feed throughs used by 430 nets
+PHY-1001 : Current memory(MB): used = 1127, reserve = 1138, peak = 1141.
+PHY-1001 : End export database. 2.495403s wall, 2.484375s user + 0.015625s system = 2.500000s CPU (100.2%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y24_n2beg4), nets: BUSY_MIPI_i_syn_3 sampling_fe_a/u_sort/u_transfer_300_to_200/mux16_syn_16
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 23.899496s wall, 23.703125s user + 0.218750s system = 23.921875s CPU (100.1%)
+
+RUN-1004 : used memory is 1125 MB, reserved memory is 1137 MB, peak memory is 1141 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y24_n2beg4), nets: BUSY_MIPI_i_syn_3 sampling_fe_a/u_sort/u_transfer_300_to_200/mux16_syn_16
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 172.819789s wall, 211.453125s user + 0.843750s system = 212.296875s CPU (122.8%)
+
+RUN-1004 : used memory is 1125 MB, reserved memory is 1137 MB, peak memory is 1141 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_101657.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_102124.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_102124.log
new file mode 100644
index 0000000..14e8ceb
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_102124.log
@@ -0,0 +1,2063 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 10:21:24 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1739)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2135)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.341212s wall, 2.218750s user + 0.125000s system = 2.343750s CPU (100.1%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2951 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18102 instances
+RUN-0007 : 7652 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20679 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13190 nets have 2 pins
+RUN-1001 : 6454 nets have [3 - 5] pins
+RUN-1001 : 616 nets have [6 - 10] pins
+RUN-1001 : 180 nets have [11 - 20] pins
+RUN-1001 : 168 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 798
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3627
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18100 instances, 7652 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6052 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84535, tnet num: 20501, tinst num: 18100, tnode num: 115269, tedge num: 134818.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.239295s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.6%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 517 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.099684s wall, 2.078125s user + 0.015625s system = 2.093750s CPU (99.7%)
+
+PHY-3001 : Found 1247 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.12437e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18100.
+PHY-3001 : Level 1 #clusters 2047.
+PHY-3001 : End clustering; 0.140870s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (144.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31766e+06, overlap = 472.844
+PHY-3002 : Step(2): len = 1.21125e+06, overlap = 500.75
+PHY-3002 : Step(3): len = 886026, overlap = 597.031
+PHY-3002 : Step(4): len = 795238, overlap = 654.5
+PHY-3002 : Step(5): len = 627441, overlap = 802.812
+PHY-3002 : Step(6): len = 576770, overlap = 859.844
+PHY-3002 : Step(7): len = 474930, overlap = 965.812
+PHY-3002 : Step(8): len = 433221, overlap = 998.031
+PHY-3002 : Step(9): len = 392055, overlap = 1038.44
+PHY-3002 : Step(10): len = 358696, overlap = 1087
+PHY-3002 : Step(11): len = 323213, overlap = 1175.97
+PHY-3002 : Step(12): len = 292319, overlap = 1238.91
+PHY-3002 : Step(13): len = 262891, overlap = 1277.69
+PHY-3002 : Step(14): len = 242361, overlap = 1309.66
+PHY-3002 : Step(15): len = 217506, overlap = 1361.47
+PHY-3002 : Step(16): len = 201202, overlap = 1394.19
+PHY-3002 : Step(17): len = 182266, overlap = 1428.59
+PHY-3002 : Step(18): len = 168694, overlap = 1437.47
+PHY-3002 : Step(19): len = 153236, overlap = 1461.09
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.0416e-06
+PHY-3002 : Step(20): len = 157535, overlap = 1437.91
+PHY-3002 : Step(21): len = 199579, overlap = 1307.84
+PHY-3002 : Step(22): len = 204363, overlap = 1223.75
+PHY-3002 : Step(23): len = 205802, overlap = 1164.25
+PHY-3002 : Step(24): len = 201185, overlap = 1122.81
+PHY-3002 : Step(25): len = 198579, overlap = 1117.22
+PHY-3002 : Step(26): len = 193147, overlap = 1103.66
+PHY-3002 : Step(27): len = 191520, overlap = 1093.12
+PHY-3002 : Step(28): len = 187479, overlap = 1070.53
+PHY-3002 : Step(29): len = 183500, overlap = 1070.28
+PHY-3002 : Step(30): len = 180372, overlap = 1066.5
+PHY-3002 : Step(31): len = 178739, overlap = 1099.69
+PHY-3002 : Step(32): len = 177719, overlap = 1096.62
+PHY-3002 : Step(33): len = 176532, overlap = 1084.09
+PHY-3002 : Step(34): len = 175143, overlap = 1074.34
+PHY-3002 : Step(35): len = 173292, overlap = 1077.62
+PHY-3002 : Step(36): len = 173303, overlap = 1104.62
+PHY-3002 : Step(37): len = 172405, overlap = 1108.56
+PHY-3002 : Step(38): len = 171659, overlap = 1099.09
+PHY-3002 : Step(39): len = 169888, overlap = 1083.41
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.08319e-06
+PHY-3002 : Step(40): len = 174980, overlap = 1083.19
+PHY-3002 : Step(41): len = 185830, overlap = 1071.78
+PHY-3002 : Step(42): len = 189456, overlap = 1027.5
+PHY-3002 : Step(43): len = 194056, overlap = 1014.19
+PHY-3002 : Step(44): len = 194186, overlap = 994.844
+PHY-3002 : Step(45): len = 194901, overlap = 989.625
+PHY-3002 : Step(46): len = 193635, overlap = 999.812
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.16638e-06
+PHY-3002 : Step(47): len = 201148, overlap = 964.438
+PHY-3002 : Step(48): len = 217331, overlap = 900.219
+PHY-3002 : Step(49): len = 226749, overlap = 915.031
+PHY-3002 : Step(50): len = 233469, overlap = 882.625
+PHY-3002 : Step(51): len = 235265, overlap = 881.938
+PHY-3002 : Step(52): len = 236138, overlap = 876.844
+PHY-3002 : Step(53): len = 235039, overlap = 871.5
+PHY-3002 : Step(54): len = 233445, overlap = 869
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.33276e-06
+PHY-3002 : Step(55): len = 246715, overlap = 830.031
+PHY-3002 : Step(56): len = 264221, overlap = 751.438
+PHY-3002 : Step(57): len = 273206, overlap = 701.281
+PHY-3002 : Step(58): len = 280207, overlap = 696.25
+PHY-3002 : Step(59): len = 279948, overlap = 668.5
+PHY-3002 : Step(60): len = 280267, overlap = 642.719
+PHY-3002 : Step(61): len = 279933, overlap = 627.5
+PHY-3002 : Step(62): len = 279939, overlap = 595.406
+PHY-3002 : Step(63): len = 280669, overlap = 594
+PHY-3002 : Step(64): len = 281693, overlap = 585.531
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.66655e-05
+PHY-3002 : Step(65): len = 297111, overlap = 524.062
+PHY-3002 : Step(66): len = 312283, overlap = 490.031
+PHY-3002 : Step(67): len = 319543, overlap = 473.031
+PHY-3002 : Step(68): len = 323637, overlap = 461.719
+PHY-3002 : Step(69): len = 322936, overlap = 450.531
+PHY-3002 : Step(70): len = 323900, overlap = 444.906
+PHY-3002 : Step(71): len = 324315, overlap = 436
+PHY-3002 : Step(72): len = 325544, overlap = 420.125
+PHY-3002 : Step(73): len = 326335, overlap = 417.031
+PHY-3002 : Step(74): len = 326563, overlap = 420.375
+PHY-3002 : Step(75): len = 326028, overlap = 417.594
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.3331e-05
+PHY-3002 : Step(76): len = 343073, overlap = 394.688
+PHY-3002 : Step(77): len = 356677, overlap = 373.062
+PHY-3002 : Step(78): len = 360141, overlap = 347.719
+PHY-3002 : Step(79): len = 362645, overlap = 341.875
+PHY-3002 : Step(80): len = 364428, overlap = 336.781
+PHY-3002 : Step(81): len = 367650, overlap = 326.938
+PHY-3002 : Step(82): len = 367841, overlap = 305.219
+PHY-3002 : Step(83): len = 369865, overlap = 298.062
+PHY-3002 : Step(84): len = 372906, overlap = 295.5
+PHY-3002 : Step(85): len = 375407, overlap = 300.531
+PHY-3002 : Step(86): len = 371793, overlap = 306.562
+PHY-3002 : Step(87): len = 371988, overlap = 304.562
+PHY-3002 : Step(88): len = 372633, overlap = 283.844
+PHY-3002 : Step(89): len = 374957, overlap = 291.406
+PHY-3002 : Step(90): len = 370597, overlap = 286.875
+PHY-3002 : Step(91): len = 371162, overlap = 277.781
+PHY-3002 : Step(92): len = 370835, overlap = 281.812
+PHY-3002 : Step(93): len = 371781, overlap = 275.75
+PHY-3002 : Step(94): len = 369288, overlap = 276.062
+PHY-3002 : Step(95): len = 369267, overlap = 274.875
+PHY-3002 : Step(96): len = 369511, overlap = 260
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.66621e-05
+PHY-3002 : Step(97): len = 385352, overlap = 258.75
+PHY-3002 : Step(98): len = 395553, overlap = 251.406
+PHY-3002 : Step(99): len = 396579, overlap = 234.688
+PHY-3002 : Step(100): len = 398637, overlap = 227.406
+PHY-3002 : Step(101): len = 401742, overlap = 219.906
+PHY-3002 : Step(102): len = 404043, overlap = 238.719
+PHY-3002 : Step(103): len = 402215, overlap = 233.062
+PHY-3002 : Step(104): len = 403080, overlap = 238.312
+PHY-3002 : Step(105): len = 403690, overlap = 236.531
+PHY-3002 : Step(106): len = 404913, overlap = 232.781
+PHY-3002 : Step(107): len = 402624, overlap = 246.656
+PHY-3002 : Step(108): len = 402738, overlap = 262.125
+PHY-3002 : Step(109): len = 403403, overlap = 266.969
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000133324
+PHY-3002 : Step(110): len = 417722, overlap = 261.281
+PHY-3002 : Step(111): len = 427985, overlap = 265.5
+PHY-3002 : Step(112): len = 429106, overlap = 250.406
+PHY-3002 : Step(113): len = 431031, overlap = 246.344
+PHY-3002 : Step(114): len = 433844, overlap = 241.312
+PHY-3002 : Step(115): len = 437123, overlap = 239.062
+PHY-3002 : Step(116): len = 434895, overlap = 247
+PHY-3002 : Step(117): len = 435711, overlap = 250.031
+PHY-3002 : Step(118): len = 437934, overlap = 240.844
+PHY-3002 : Step(119): len = 439710, overlap = 238.656
+PHY-3002 : Step(120): len = 437345, overlap = 237.938
+PHY-3002 : Step(121): len = 438000, overlap = 237.312
+PHY-3002 : Step(122): len = 440225, overlap = 233.469
+PHY-3002 : Step(123): len = 442456, overlap = 233.844
+PHY-3002 : Step(124): len = 439796, overlap = 233.656
+PHY-3002 : Step(125): len = 439744, overlap = 225.812
+PHY-3002 : Step(126): len = 441478, overlap = 225.719
+PHY-3002 : Step(127): len = 442822, overlap = 226.531
+PHY-3002 : Step(128): len = 441536, overlap = 219.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000253817
+PHY-3002 : Step(129): len = 451940, overlap = 222.75
+PHY-3002 : Step(130): len = 459538, overlap = 222.688
+PHY-3002 : Step(131): len = 459123, overlap = 220.719
+PHY-3002 : Step(132): len = 460182, overlap = 222.031
+PHY-3002 : Step(133): len = 464908, overlap = 220.438
+PHY-3002 : Step(134): len = 468124, overlap = 220.188
+PHY-3002 : Step(135): len = 466450, overlap = 216.531
+PHY-3002 : Step(136): len = 467053, overlap = 210.938
+PHY-3002 : Step(137): len = 470265, overlap = 196.531
+PHY-3002 : Step(138): len = 472620, overlap = 193.406
+PHY-3002 : Step(139): len = 470729, overlap = 194
+PHY-3002 : Step(140): len = 471632, overlap = 186.25
+PHY-3002 : Step(141): len = 475105, overlap = 190.844
+PHY-3002 : Step(142): len = 476658, overlap = 185.969
+PHY-3002 : Step(143): len = 475198, overlap = 185.375
+PHY-3002 : Step(144): len = 475377, overlap = 190.562
+PHY-3002 : Step(145): len = 477405, overlap = 184.5
+PHY-3002 : Step(146): len = 477958, overlap = 186.156
+PHY-3002 : Step(147): len = 476166, overlap = 189.094
+PHY-3002 : Step(148): len = 475895, overlap = 186.594
+PHY-3002 : Step(149): len = 477586, overlap = 182.969
+PHY-3002 : Step(150): len = 478838, overlap = 181.594
+PHY-3002 : Step(151): len = 477335, overlap = 177
+PHY-3002 : Step(152): len = 477045, overlap = 177.875
+PHY-3002 : Step(153): len = 479194, overlap = 176
+PHY-3002 : Step(154): len = 481233, overlap = 183.656
+PHY-3002 : Step(155): len = 479286, overlap = 182.906
+PHY-3002 : Step(156): len = 478802, overlap = 182.219
+PHY-3002 : Step(157): len = 479245, overlap = 179.281
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000502169
+PHY-3002 : Step(158): len = 487394, overlap = 178.562
+PHY-3002 : Step(159): len = 496691, overlap = 174.625
+PHY-3002 : Step(160): len = 498170, overlap = 160.062
+PHY-3002 : Step(161): len = 499581, overlap = 151.969
+PHY-3002 : Step(162): len = 502527, overlap = 152.969
+PHY-3002 : Step(163): len = 504504, overlap = 150.531
+PHY-3002 : Step(164): len = 503988, overlap = 148.812
+PHY-3002 : Step(165): len = 505121, overlap = 144.375
+PHY-3002 : Step(166): len = 508633, overlap = 138.094
+PHY-3002 : Step(167): len = 510841, overlap = 135.5
+PHY-3002 : Step(168): len = 510010, overlap = 138.344
+PHY-3002 : Step(169): len = 510164, overlap = 140.344
+PHY-3002 : Step(170): len = 511495, overlap = 135.031
+PHY-3002 : Step(171): len = 511882, overlap = 136.438
+PHY-3002 : Step(172): len = 510040, overlap = 138.531
+PHY-3002 : Step(173): len = 509293, overlap = 139.906
+PHY-3002 : Step(174): len = 510678, overlap = 141.312
+PHY-3002 : Step(175): len = 511916, overlap = 142.5
+PHY-3002 : Step(176): len = 510817, overlap = 144.5
+PHY-3002 : Step(177): len = 510509, overlap = 146.5
+PHY-3002 : Step(178): len = 510847, overlap = 143.344
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00100434
+PHY-3002 : Step(179): len = 515977, overlap = 138.812
+PHY-3002 : Step(180): len = 522053, overlap = 139.25
+PHY-3002 : Step(181): len = 524059, overlap = 134.781
+PHY-3002 : Step(182): len = 525418, overlap = 133.812
+PHY-3002 : Step(183): len = 527160, overlap = 132
+PHY-3002 : Step(184): len = 528748, overlap = 133.312
+PHY-3002 : Step(185): len = 529266, overlap = 132.781
+PHY-3002 : Step(186): len = 529602, overlap = 134.594
+PHY-3002 : Step(187): len = 530518, overlap = 132.281
+PHY-3002 : Step(188): len = 531527, overlap = 133.375
+PHY-3002 : Step(189): len = 531917, overlap = 131
+PHY-3002 : Step(190): len = 532055, overlap = 134.531
+PHY-3002 : Step(191): len = 532227, overlap = 132.312
+PHY-3002 : Step(192): len = 532528, overlap = 126.688
+PHY-3002 : Step(193): len = 532377, overlap = 127.438
+PHY-3002 : Step(194): len = 532224, overlap = 129.344
+PHY-3002 : Step(195): len = 531990, overlap = 127.188
+PHY-3002 : Step(196): len = 531941, overlap = 127
+PHY-3002 : Step(197): len = 531865, overlap = 125.875
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00184623
+PHY-3002 : Step(198): len = 535742, overlap = 127.75
+PHY-3002 : Step(199): len = 542012, overlap = 128.031
+PHY-3002 : Step(200): len = 543639, overlap = 131.562
+PHY-3002 : Step(201): len = 545058, overlap = 129.375
+PHY-3002 : Step(202): len = 547471, overlap = 125.219
+PHY-3002 : Step(203): len = 549592, overlap = 122.812
+PHY-3002 : Step(204): len = 549386, overlap = 123.25
+PHY-3002 : Step(205): len = 549569, overlap = 121.875
+PHY-3002 : Step(206): len = 550860, overlap = 122.344
+PHY-3002 : Step(207): len = 551569, overlap = 123.625
+PHY-3002 : Step(208): len = 550737, overlap = 121.312
+PHY-3002 : Step(209): len = 550163, overlap = 123.938
+PHY-3002 : Step(210): len = 551177, overlap = 127.688
+PHY-3002 : Step(211): len = 551862, overlap = 128.438
+PHY-3002 : Step(212): len = 551372, overlap = 127.25
+PHY-3002 : Step(213): len = 551301, overlap = 129.438
+PHY-3002 : Step(214): len = 552153, overlap = 128.969
+PHY-3002 : Step(215): len = 552369, overlap = 131.969
+PHY-3002 : Step(216): len = 551842, overlap = 130.812
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.018174s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (171.9%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715240, over cnt = 1643(4%), over = 7735, worst = 40
+PHY-1001 : End global iterations; 0.792377s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (138.0%)
+
+PHY-1001 : Congestion index: top1 = 86.31, top5 = 63.64, top10 = 53.31, top15 = 47.39.
+PHY-3001 : End congestion estimation; 1.041639s wall, 1.296875s user + 0.031250s system = 1.328125s CPU (127.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.952478s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (98.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000144038
+PHY-3002 : Step(217): len = 644874, overlap = 82.1562
+PHY-3002 : Step(218): len = 640281, overlap = 81.125
+PHY-3002 : Step(219): len = 633161, overlap = 80.8125
+PHY-3002 : Step(220): len = 630055, overlap = 71.8438
+PHY-3002 : Step(221): len = 632453, overlap = 52.8438
+PHY-3002 : Step(222): len = 632723, overlap = 46.125
+PHY-3002 : Step(223): len = 629191, overlap = 49.125
+PHY-3002 : Step(224): len = 626032, overlap = 57.8125
+PHY-3002 : Step(225): len = 624168, overlap = 48.1875
+PHY-3002 : Step(226): len = 622951, overlap = 44.4375
+PHY-3002 : Step(227): len = 620000, overlap = 40.1875
+PHY-3002 : Step(228): len = 617723, overlap = 34.0312
+PHY-3002 : Step(229): len = 617993, overlap = 31.4688
+PHY-3002 : Step(230): len = 616615, overlap = 36.4375
+PHY-3002 : Step(231): len = 614417, overlap = 38
+PHY-3002 : Step(232): len = 613873, overlap = 39.875
+PHY-3002 : Step(233): len = 614017, overlap = 38.3438
+PHY-3002 : Step(234): len = 614031, overlap = 39.4688
+PHY-3002 : Step(235): len = 613629, overlap = 39.75
+PHY-3002 : Step(236): len = 613313, overlap = 42.0312
+PHY-3002 : Step(237): len = 613078, overlap = 44.9688
+PHY-3002 : Step(238): len = 611497, overlap = 47.0938
+PHY-3002 : Step(239): len = 609606, overlap = 49.4688
+PHY-3002 : Step(240): len = 608647, overlap = 54.2188
+PHY-3002 : Step(241): len = 606828, overlap = 56.3438
+PHY-3002 : Step(242): len = 606043, overlap = 54.9375
+PHY-3002 : Step(243): len = 604284, overlap = 55.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000288075
+PHY-3002 : Step(244): len = 607982, overlap = 54.9062
+PHY-3002 : Step(245): len = 613621, overlap = 56.1875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000526742
+PHY-3002 : Step(246): len = 616463, overlap = 54.9062
+PHY-3002 : Step(247): len = 630014, overlap = 50.1562
+PHY-3002 : Step(248): len = 643002, overlap = 49.9375
+PHY-3002 : Step(249): len = 643321, overlap = 49.9688
+PHY-3002 : Step(250): len = 643455, overlap = 47.5312
+PHY-3002 : Step(251): len = 641817, overlap = 47.5938
+PHY-3002 : Step(252): len = 642027, overlap = 44.6562
+PHY-3002 : Step(253): len = 642631, overlap = 42.2812
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000898412
+PHY-3002 : Step(254): len = 648846, overlap = 42.5625
+PHY-3002 : Step(255): len = 658898, overlap = 42.6875
+PHY-3002 : Step(256): len = 665229, overlap = 42.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00157211
+PHY-3002 : Step(257): len = 667904, overlap = 39.7812
+PHY-3002 : Step(258): len = 678178, overlap = 37.1562
+PHY-3002 : Step(259): len = 696215, overlap = 35.6562
+PHY-3002 : Step(260): len = 699319, overlap = 36.125
+PHY-3002 : Step(261): len = 700123, overlap = 34.5
+PHY-3002 : Step(262): len = 700924, overlap = 32.5938
+PHY-3002 : Step(263): len = 701488, overlap = 34.875
+PHY-3002 : Step(264): len = 701075, overlap = 34.375
+PHY-3002 : Step(265): len = 703217, overlap = 33.9688
+PHY-3002 : Step(266): len = 703545, overlap = 33.2812
+PHY-3002 : Step(267): len = 703010, overlap = 31.375
+PHY-3002 : Step(268): len = 701791, overlap = 28.625
+PHY-3002 : Step(269): len = 700269, overlap = 30.4062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.0025606
+PHY-3002 : Step(270): len = 701690, overlap = 29.4375
+PHY-3002 : Step(271): len = 708117, overlap = 27.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 70/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793104, over cnt = 2860(8%), over = 14126, worst = 55
+PHY-1001 : End global iterations; 1.746229s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 94.35, top5 = 74.01, top10 = 65.08, top15 = 59.36.
+PHY-3001 : End congestion estimation; 2.031709s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (130.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.425463s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000122077
+PHY-3002 : Step(272): len = 691499, overlap = 254.281
+PHY-3002 : Step(273): len = 682070, overlap = 202.656
+PHY-3002 : Step(274): len = 668957, overlap = 186.5
+PHY-3002 : Step(275): len = 658949, overlap = 154.406
+PHY-3002 : Step(276): len = 649850, overlap = 132.562
+PHY-3002 : Step(277): len = 643730, overlap = 126.562
+PHY-3002 : Step(278): len = 636930, overlap = 114.656
+PHY-3002 : Step(279): len = 633090, overlap = 102.438
+PHY-3002 : Step(280): len = 627700, overlap = 96.7188
+PHY-3002 : Step(281): len = 622946, overlap = 98.6562
+PHY-3002 : Step(282): len = 620104, overlap = 99.7188
+PHY-3002 : Step(283): len = 615989, overlap = 103.25
+PHY-3002 : Step(284): len = 609854, overlap = 106.844
+PHY-3002 : Step(285): len = 607911, overlap = 113.5
+PHY-3002 : Step(286): len = 603237, overlap = 123.188
+PHY-3002 : Step(287): len = 599134, overlap = 130.094
+PHY-3002 : Step(288): len = 596951, overlap = 133.594
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000244153
+PHY-3002 : Step(289): len = 598426, overlap = 126.375
+PHY-3002 : Step(290): len = 602389, overlap = 118.281
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000482378
+PHY-3002 : Step(291): len = 609296, overlap = 107.594
+PHY-3002 : Step(292): len = 618358, overlap = 102.75
+PHY-3002 : Step(293): len = 621811, overlap = 95.5938
+PHY-3002 : Step(294): len = 621367, overlap = 94.5
+PHY-3002 : Step(295): len = 621645, overlap = 94.0312
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84535, tnet num: 20501, tinst num: 18100, tnode num: 115269, tedge num: 134818.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.578557s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.0%)
+
+RUN-1004 : used memory is 577 MB, reserved memory is 567 MB, peak memory is 712 MB
+OPT-1001 : Total overflow 430.94 peak overflow 5.31
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 481/20679.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715880, over cnt = 3026(8%), over = 11024, worst = 21
+PHY-1001 : End global iterations; 1.639167s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (137.3%)
+
+PHY-1001 : Congestion index: top1 = 73.43, top5 = 58.57, top10 = 51.86, top15 = 47.89.
+PHY-1001 : End incremental global routing; 1.998220s wall, 2.593750s user + 0.015625s system = 2.609375s CPU (130.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20501 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.205992s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (99.8%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17968 has valid locations, 323 needs to be replaced
+PHY-3001 : design contains 18376 instances, 7754 luts, 9401 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6187 pins
+PHY-3001 : Found 1256 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 646253
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16968/20955.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 732480, over cnt = 3061(8%), over = 11067, worst = 21
+PHY-1001 : End global iterations; 0.251945s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (130.2%)
+
+PHY-1001 : Congestion index: top1 = 73.66, top5 = 58.94, top10 = 52.21, top15 = 48.23.
+PHY-3001 : End congestion estimation; 0.529718s wall, 0.593750s user + 0.015625s system = 0.609375s CPU (115.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85640, tnet num: 20777, tinst num: 18376, tnode num: 116919, tedge num: 136476.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.589285s wall, 1.562500s user + 0.031250s system = 1.593750s CPU (100.3%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 618 MB, peak memory is 717 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20777 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.095027s wall, 3.046875s user + 0.046875s system = 3.093750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(296): len = 645218, overlap = 1.96875
+PHY-3002 : Step(297): len = 644680, overlap = 1.59375
+PHY-3002 : Step(298): len = 644259, overlap = 1.59375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17081/20955.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730256, over cnt = 3063(8%), over = 11146, worst = 21
+PHY-1001 : End global iterations; 0.218432s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (114.5%)
+
+PHY-1001 : Congestion index: top1 = 73.94, top5 = 59.24, top10 = 52.56, top15 = 48.50.
+PHY-3001 : End congestion estimation; 0.510899s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (107.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20777 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.017591s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000332448
+PHY-3002 : Step(299): len = 644254, overlap = 95.9062
+PHY-3002 : Step(300): len = 644478, overlap = 96.125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000664896
+PHY-3002 : Step(301): len = 644449, overlap = 95.8438
+PHY-3002 : Step(302): len = 645072, overlap = 95.8125
+PHY-3001 : Final: Len = 645072, Over = 95.8125
+PHY-3001 : End incremental placement; 5.874487s wall, 5.968750s user + 0.218750s system = 6.187500s CPU (105.3%)
+
+OPT-1001 : Total overflow 437.53 peak overflow 5.31
+OPT-1001 : End high-fanout net optimization; 9.657345s wall, 10.421875s user + 0.265625s system = 10.687500s CPU (110.7%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 713, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17025/20955.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 732200, over cnt = 2994(8%), over = 10167, worst = 21
+PHY-1002 : len = 779464, over cnt = 2201(6%), over = 5756, worst = 21
+PHY-1002 : len = 822440, over cnt = 1058(3%), over = 2466, worst = 17
+PHY-1002 : len = 854176, over cnt = 256(0%), over = 533, worst = 12
+PHY-1002 : len = 863480, over cnt = 4(0%), over = 4, worst = 1
+PHY-1001 : End global iterations; 2.067083s wall, 2.750000s user + 0.015625s system = 2.765625s CPU (133.8%)
+
+PHY-1001 : Congestion index: top1 = 57.89, top5 = 50.97, top10 = 47.43, top15 = 45.15.
+OPT-1001 : End congestion update; 2.359495s wall, 3.046875s user + 0.015625s system = 3.062500s CPU (129.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20777 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.878459s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.6%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 142 cells processed and 18100 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 26 cells processed and 1900 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 4 cells processed and 250 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 546 slack improved
+OPT-1001 : End bottleneck based optimization; 3.695526s wall, 4.375000s user + 0.031250s system = 4.406250s CPU (119.2%)
+
+OPT-1001 : Current memory(MB): used = 696, reserve = 697, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17060/20960.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862672, over cnt = 95(0%), over = 128, worst = 4
+PHY-1002 : len = 861976, over cnt = 45(0%), over = 53, worst = 3
+PHY-1002 : len = 862224, over cnt = 23(0%), over = 24, worst = 2
+PHY-1002 : len = 862648, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 862936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.778834s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (106.3%)
+
+PHY-1001 : Congestion index: top1 = 57.48, top5 = 50.72, top10 = 47.26, top15 = 45.02.
+OPT-1001 : End congestion update; 1.088775s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (103.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20782 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.877469s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.7%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 16 cells processed and 3050 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.096183s wall, 2.140625s user + 0.000000s system = 2.140625s CPU (102.1%)
+
+OPT-1001 : Current memory(MB): used = 707, reserve = 703, peak = 735.
+OPT-1001 : End physical optimization; 17.380269s wall, 18.921875s user + 0.343750s system = 19.265625s CPU (110.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7754 LUT to BLE ...
+SYN-4008 : Packed 7754 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6258 remaining SEQ's ...
+SYN-4005 : Packed 4065 SEQ with LUT/SLICE
+SYN-4006 : 846 single LUT's are left
+SYN-4006 : 2193 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9947/13734 primitive instances ...
+PHY-3001 : End packing; 1.995804s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (98.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6721 instances
+RUN-1001 : 3287 mslices, 3286 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17945 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 10075 nets have 2 pins
+RUN-1001 : 6498 nets have [3 - 5] pins
+RUN-1001 : 723 nets have [6 - 10] pins
+RUN-1001 : 306 nets have [11 - 20] pins
+RUN-1001 : 309 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6719 instances, 6573 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3581 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 656123, Over = 225.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7775/17945.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808760, over cnt = 1987(5%), over = 3267, worst = 8
+PHY-1002 : len = 816800, over cnt = 1297(3%), over = 1876, worst = 7
+PHY-1002 : len = 832664, over cnt = 457(1%), over = 634, worst = 7
+PHY-1002 : len = 842104, over cnt = 71(0%), over = 88, worst = 4
+PHY-1002 : len = 843832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.004597s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 58.21, top5 = 50.84, top10 = 46.89, top15 = 44.38.
+PHY-3001 : End congestion estimation; 2.440736s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (134.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71727, tnet num: 17767, tinst num: 6719, tnode num: 94327, tedge num: 119242.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.784300s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (99.8%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 613 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17767 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.723439s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.68601e-05
+PHY-3002 : Step(303): len = 645159, overlap = 228
+PHY-3002 : Step(304): len = 638911, overlap = 228.25
+PHY-3002 : Step(305): len = 634877, overlap = 241.5
+PHY-3002 : Step(306): len = 631748, overlap = 243
+PHY-3002 : Step(307): len = 629514, overlap = 249.25
+PHY-3002 : Step(308): len = 626492, overlap = 254.25
+PHY-3002 : Step(309): len = 623477, overlap = 255.25
+PHY-3002 : Step(310): len = 620871, overlap = 251.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00011372
+PHY-3002 : Step(311): len = 624430, overlap = 242
+PHY-3002 : Step(312): len = 627942, overlap = 234.75
+PHY-3002 : Step(313): len = 628497, overlap = 230.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00022744
+PHY-3002 : Step(314): len = 637993, overlap = 216.5
+PHY-3002 : Step(315): len = 646207, overlap = 209
+PHY-3002 : Step(316): len = 644551, overlap = 204.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.400436s wall, 0.359375s user + 0.562500s system = 0.921875s CPU (230.2%)
+
+PHY-3001 : Trial Legalized: Len = 728809
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 903/17945.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843464, over cnt = 2704(7%), over = 4415, worst = 6
+PHY-1002 : len = 857176, over cnt = 1753(4%), over = 2576, worst = 6
+PHY-1002 : len = 879016, over cnt = 669(1%), over = 977, worst = 5
+PHY-1002 : len = 889016, over cnt = 304(0%), over = 445, worst = 5
+PHY-1002 : len = 895840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.871680s wall, 3.937500s user + 0.031250s system = 3.968750s CPU (138.2%)
+
+PHY-1001 : Congestion index: top1 = 55.15, top5 = 50.09, top10 = 47.23, top15 = 45.23.
+PHY-3001 : End congestion estimation; 3.374171s wall, 4.437500s user + 0.031250s system = 4.468750s CPU (132.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17767 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.955690s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171208
+PHY-3002 : Step(317): len = 700342, overlap = 34.75
+PHY-3002 : Step(318): len = 683889, overlap = 65.75
+PHY-3002 : Step(319): len = 670754, overlap = 92
+PHY-3002 : Step(320): len = 661603, overlap = 112.5
+PHY-3002 : Step(321): len = 656342, overlap = 130.5
+PHY-3002 : Step(322): len = 652641, overlap = 144.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000342415
+PHY-3002 : Step(323): len = 657381, overlap = 138.25
+PHY-3002 : Step(324): len = 661468, overlap = 133
+PHY-3002 : Step(325): len = 661489, overlap = 134.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00068483
+PHY-3002 : Step(326): len = 665082, overlap = 132.5
+PHY-3002 : Step(327): len = 672970, overlap = 132.25
+PHY-3002 : Step(328): len = 675057, overlap = 131.75
+PHY-3002 : Step(329): len = 676452, overlap = 131
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.036073s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (86.6%)
+
+PHY-3001 : Legalized: Len = 704269, Over = 0
+PHY-3001 : Spreading special nets. 427 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.111977s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (97.7%)
+
+PHY-3001 : 622 instances has been re-located, deltaX = 186, deltaY = 347, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 713011, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71727, tnet num: 17767, tinst num: 6722, tnode num: 94327, tedge num: 119242.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.008960s wall, 1.953125s user + 0.046875s system = 2.000000s CPU (99.6%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 644 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4205/17945.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838328, over cnt = 2462(6%), over = 3896, worst = 6
+PHY-1002 : len = 851816, over cnt = 1429(4%), over = 2001, worst = 6
+PHY-1002 : len = 865008, over cnt = 658(1%), over = 929, worst = 5
+PHY-1002 : len = 873912, over cnt = 290(0%), over = 414, worst = 4
+PHY-1002 : len = 879648, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.143229s wall, 3.328125s user + 0.046875s system = 3.375000s CPU (157.5%)
+
+PHY-1001 : Congestion index: top1 = 55.32, top5 = 48.66, top10 = 45.64, top15 = 43.75.
+PHY-1001 : End incremental global routing; 2.567245s wall, 3.765625s user + 0.046875s system = 3.812500s CPU (148.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17767 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.941349s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (99.6%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6630 has valid locations, 22 needs to be replaced
+PHY-3001 : design contains 6740 instances, 6591 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3649 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 717652
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16285/17965.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 885184, over cnt = 74(0%), over = 89, worst = 6
+PHY-1002 : len = 885352, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 885792, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 885896, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 885944, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.912676s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 55.56, top5 = 48.88, top10 = 45.81, top15 = 43.92.
+PHY-3001 : End congestion estimation; 1.274562s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (101.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71888, tnet num: 17787, tinst num: 6740, tnode num: 94522, tedge num: 119459.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.990556s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (100.5%)
+
+RUN-1004 : used memory is 656 MB, reserved memory is 664 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.949302s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(330): len = 716231, overlap = 0
+PHY-3002 : Step(331): len = 715347, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16270/17965.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 882192, over cnt = 49(0%), over = 65, worst = 5
+PHY-1002 : len = 882280, over cnt = 26(0%), over = 30, worst = 4
+PHY-1002 : len = 882616, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 882616, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 882664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.838849s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (108.0%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 48.70, top10 = 45.69, top15 = 43.83.
+PHY-3001 : End congestion estimation; 1.182891s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (105.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.934461s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000217501
+PHY-3002 : Step(332): len = 715427, overlap = 2
+PHY-3002 : Step(333): len = 715449, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005482s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (285.0%)
+
+PHY-3001 : Legalized: Len = 715510, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064287s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 715544, Over = 0
+PHY-3001 : End incremental placement; 6.874955s wall, 6.921875s user + 0.140625s system = 7.062500s CPU (102.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.914764s wall, 12.250000s user + 0.203125s system = 12.453125s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 736, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16276/17965.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 883496, over cnt = 40(0%), over = 50, worst = 3
+PHY-1002 : len = 883664, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 883904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 883920, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 884016, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.828704s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 55.45, top5 = 48.84, top10 = 45.79, top15 = 43.92.
+OPT-1001 : End congestion update; 1.180220s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (104.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.775958s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.7%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6652 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6740 instances, 6591 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3649 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 724916, Over = 0
+PHY-3001 : Spreading special nets. 34 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.071344s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (87.6%)
+
+PHY-3001 : 51 instances has been re-located, deltaX = 40, deltaY = 29, maxDist = 3.
+PHY-3001 : Final: Len = 726260, Over = 0
+PHY-3001 : End incremental legalization; 0.444613s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (91.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 56 cells processed and 19587 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6652 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6740 instances, 6591 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3649 pins
+PHY-3001 : Found 485 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 725660, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065476s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.5%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 12, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 725724, Over = 0
+PHY-3001 : End incremental legalization; 0.423651s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (99.6%)
+
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 28 cells processed and 1873 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6659 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6747 instances, 6598 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3650 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 726104, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068773s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.9%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 726254, Over = 0
+PHY-3001 : End incremental legalization; 0.425542s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (106.5%)
+
+OPT-0007 : Iter 3: improved WNS 71 TNS 0 NUM_FEPS 0 with 7 cells processed and 1577 slack improved
+OPT-1001 : End bottleneck based optimization; 3.719085s wall, 3.875000s user + 0.015625s system = 3.890625s CPU (104.6%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 735, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15879/17965.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 893928, over cnt = 180(0%), over = 253, worst = 9
+PHY-1002 : len = 894544, over cnt = 109(0%), over = 122, worst = 4
+PHY-1002 : len = 895392, over cnt = 41(0%), over = 42, worst = 2
+PHY-1002 : len = 896224, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 896256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.025318s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (103.6%)
+
+PHY-1001 : Congestion index: top1 = 55.24, top5 = 49.08, top10 = 45.96, top15 = 44.14.
+OPT-1001 : End congestion update; 1.377633s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (102.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.784907s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.5%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6659 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6747 instances, 6598 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3650 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 726598, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067089s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.2%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 13, deltaY = 13, maxDist = 3.
+PHY-3001 : Final: Len = 726980, Over = 0
+PHY-3001 : End incremental legalization; 0.472455s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 18 cells processed and 2150 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.774605s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (101.4%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 735, peak = 738.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779643s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16225/17965.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896840, over cnt = 45(0%), over = 47, worst = 2
+PHY-1002 : len = 896880, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 897008, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 897088, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 897136, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.845502s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 54.76, top5 = 49.10, top10 = 46.04, top15 = 44.18.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.787785s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.344828
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 22.457377s wall, 23.937500s user + 0.281250s system = 24.218750s CPU (107.8%)
+
+RUN-1003 : finish command "place" in 74.966986s wall, 111.281250s user + 7.375000s system = 118.656250s CPU (158.3%)
+
+RUN-1004 : used memory is 604 MB, reserved memory is 612 MB, peak memory is 738 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.831139s wall, 3.125000s user + 0.000000s system = 3.125000s CPU (170.7%)
+
+RUN-1004 : used memory is 604 MB, reserved memory is 613 MB, peak memory is 738 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param route opt_timing high"
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6749 instances
+RUN-1001 : 3300 mslices, 3298 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17965 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 10052 nets have 2 pins
+RUN-1001 : 6517 nets have [3 - 5] pins
+RUN-1001 : 733 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 322 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71951, tnet num: 17787, tinst num: 6747, tnode num: 94611, tedge num: 119541.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.723932s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.7%)
+
+RUN-1004 : used memory is 597 MB, reserved memory is 596 MB, peak memory is 738 MB
+PHY-1001 : 3300 mslices, 3298 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[11] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 829120, over cnt = 2677(7%), over = 4353, worst = 9
+PHY-1002 : len = 846616, over cnt = 1620(4%), over = 2301, worst = 9
+PHY-1002 : len = 865608, over cnt = 614(1%), over = 869, worst = 5
+PHY-1002 : len = 880096, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 880224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.562555s wall, 4.656250s user + 0.046875s system = 4.703125s CPU (132.0%)
+
+PHY-1001 : Congestion index: top1 = 53.81, top5 = 48.65, top10 = 45.60, top15 = 43.63.
+PHY-1001 : End global routing; 3.952402s wall, 5.046875s user + 0.046875s system = 5.093750s CPU (128.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 706, reserve = 712, peak = 738.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 981, reserve = 985, peak = 981.
+PHY-1001 : End build detailed router design. 4.347515s wall, 4.281250s user + 0.046875s system = 4.328125s CPU (99.6%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271936, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.243831s wall, 6.218750s user + 0.000000s system = 6.218750s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271992, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.546289s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1022, peak = 1017.
+PHY-1001 : End phase 1; 6.805408s wall, 6.781250s user + 0.000000s system = 6.781250s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.25895e+06, over cnt = 1663(0%), over = 1672, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1037, peak = 1033.
+PHY-1001 : End initial routed; 25.506034s wall, 61.593750s user + 0.500000s system = 62.093750s CPU (243.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16884(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.565151s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1055, peak = 1051.
+PHY-1001 : End phase 2; 29.071248s wall, 65.140625s user + 0.500000s system = 65.640625s CPU (225.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.144345s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1022 : len = 2.25895e+06, over cnt = 1663(0%), over = 1672, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.442925s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (102.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.231e+06, over cnt = 669(0%), over = 670, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.525221s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (186.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.22819e+06, over cnt = 177(0%), over = 177, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.102920s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (138.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.22887e+06, over cnt = 29(0%), over = 29, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.429893s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (116.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.22926e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.279999s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.22946e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.248317s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.2295e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 6; 0.193480s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (105.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16884(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.548818s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 526 feed throughs used by 380 nets
+PHY-1001 : End commit to database; 2.347652s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1159, peak = 1152.
+PHY-1001 : End phase 3; 10.558762s wall, 12.281250s user + 0.062500s system = 12.343750s CPU (116.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.142894s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.4%)
+
+PHY-1022 : len = 2.2295e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.415569s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16884(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.509964s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 526 feed throughs used by 380 nets
+PHY-1001 : End commit to database; 2.477451s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1167, peak = 1160.
+PHY-1001 : End phase 4; 6.428449s wall, 6.437500s user + 0.000000s system = 6.437500s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.2295e+06
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1172, peak = 1164.
+PHY-1001 : End export database. 0.068586s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.1%)
+
+PHY-1001 : End detail routing; 57.708266s wall, 95.421875s user + 0.609375s system = 96.031250s CPU (166.4%)
+
+RUN-1003 : finish command "route" in 64.581514s wall, 103.375000s user + 0.671875s system = 104.046875s CPU (161.1%)
+
+RUN-1004 : used memory is 1027 MB, reserved memory is 1033 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10183 out of 19600 51.95%
+#reg 9581 out of 19600 48.88%
+#le 12335
+ #lut only 2754 out of 12335 22.33%
+ #reg only 2152 out of 12335 17.45%
+ #lut® 7429 out of 12335 60.23%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1782
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1439
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1334
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 930
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice BUSY_MIPI_sync_d1_reg_syn_12.q0 137
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 67
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/reg1_syn_145.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P91 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P107 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P15 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P39 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P32 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P118 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P106 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12335 |9156 |1027 |9615 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |519 |448 |23 |431 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |100 |86 |4 |92 |4 |0 |
+| U_ecc_gen |ecc_gen |11 |11 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |53 |53 |0 |24 |0 |0 |
+| exdev_ctl_a |exdev_ctl |739 |408 |96 |563 |0 |0 |
+| u_ADconfig |AD_config |177 |121 |25 |135 |0 |0 |
+| u_gen_sp |gen_sp |250 |144 |71 |116 |0 |0 |
+| exdev_ctl_b |exdev_ctl |748 |371 |96 |563 |0 |0 |
+| u_ADconfig |AD_config |173 |117 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |266 |168 |71 |124 |0 |0 |
+| sampling_fe_a |sampling_fe |3003 |2418 |306 |2117 |25 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |103 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2782 |2311 |289 |1927 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2322 |1937 |253 |1550 |22 |0 |
+| channelPart |channel_part_8478 |130 |112 |3 |125 |0 |0 |
+| fifo_adc |fifo_adc |65 |56 |9 |47 |0 |0 |
+| ram_switch |ram_switch |1835 |1524 |197 |1173 |0 |0 |
+| adc_addr_gen |adc_addr_gen |229 |202 |27 |125 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |10 |0 |0 |
+| insert |insert |956 |672 |170 |665 |0 |0 |
+| ram_switch_state |ram_switch_state |650 |650 |0 |383 |0 |0 |
+| read_ram_i |read_ram |273 |227 |44 |186 |0 |0 |
+| read_ram_addr |read_ram_addr |227 |187 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |44 |40 |4 |33 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |307 |243 |36 |259 |3 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3165 |2505 |349 |2123 |25 |1 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |132 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |2943 |2352 |332 |1931 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2494 |2015 |290 |1556 |22 |1 |
+| channelPart |channel_part_8478 |138 |128 |3 |130 |0 |0 |
+| fifo_adc |fifo_adc |65 |56 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1904 |1555 |197 |1149 |0 |0 |
+| adc_addr_gen |adc_addr_gen |204 |177 |27 |108 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| insert |insert |975 |653 |170 |683 |0 |0 |
+| ram_switch_state |ram_switch_state |725 |725 |0 |358 |0 |0 |
+| read_ram_i |read_ram_rev |361 |255 |81 |206 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |303 |218 |73 |166 |0 |0 |
+| read_ram_data |read_ram_data_rev |58 |37 |8 |40 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9990
+ #2 2 4259
+ #3 3 1690
+ #4 4 565
+ #5 5-10 781
+ #6 11-50 569
+ #7 51-100 13
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.175272s wall, 3.734375s user + 0.031250s system = 3.765625s CPU (173.1%)
+
+RUN-1004 : used memory is 1028 MB, reserved memory is 1035 MB, peak memory is 1164 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71951, tnet num: 17787, tinst num: 6747, tnode num: 94611, tedge num: 119541.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.703830s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (100.0%)
+
+RUN-1004 : used memory is 1032 MB, reserved memory is 1038 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17787 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.605744s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (100.2%)
+
+RUN-1004 : used memory is 1067 MB, reserved memory is 1073 MB, peak memory is 1164 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6747
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17965, pip num: 167697
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 526
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3225 valid insts, and 467742 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.359702s wall, 59.515625s user + 0.250000s system = 59.765625s CPU (638.5%)
+
+RUN-1004 : used memory is 1246 MB, reserved memory is 1249 MB, peak memory is 1362 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_102124.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_103050.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_103050.log
new file mode 100644
index 0000000..97aa631
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_103050.log
@@ -0,0 +1,2384 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 10:30:50 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.337944s wall, 2.234375s user + 0.109375s system = 2.343750s CPU (100.2%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18117 instances
+RUN-0007 : 7667 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20694 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13192 nets have 2 pins
+RUN-1001 : 6467 nets have [3 - 5] pins
+RUN-1001 : 617 nets have [6 - 10] pins
+RUN-1001 : 178 nets have [11 - 20] pins
+RUN-1001 : 169 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 798
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3627
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18115 instances, 7667 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6050 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84630, tnet num: 20516, tinst num: 18115, tnode num: 115358, tedge num: 134978.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.254095s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (99.7%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 516 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20516 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.121341s wall, 2.031250s user + 0.078125s system = 2.109375s CPU (99.4%)
+
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.08907e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18115.
+PHY-3001 : Level 1 #clusters 2056.
+PHY-3001 : End clustering; 0.142503s wall, 0.203125s user + 0.031250s system = 0.234375s CPU (164.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35363e+06, overlap = 453.844
+PHY-3002 : Step(2): len = 1.24045e+06, overlap = 500.094
+PHY-3002 : Step(3): len = 888840, overlap = 602.688
+PHY-3002 : Step(4): len = 807151, overlap = 670.375
+PHY-3002 : Step(5): len = 636978, overlap = 784
+PHY-3002 : Step(6): len = 580525, overlap = 819.938
+PHY-3002 : Step(7): len = 480583, overlap = 904.375
+PHY-3002 : Step(8): len = 432962, overlap = 977.875
+PHY-3002 : Step(9): len = 388928, overlap = 1027.28
+PHY-3002 : Step(10): len = 363932, overlap = 1061.94
+PHY-3002 : Step(11): len = 323883, overlap = 1115.72
+PHY-3002 : Step(12): len = 309169, overlap = 1141.19
+PHY-3002 : Step(13): len = 274806, overlap = 1236.38
+PHY-3002 : Step(14): len = 265149, overlap = 1282.03
+PHY-3002 : Step(15): len = 233456, overlap = 1330.66
+PHY-3002 : Step(16): len = 224623, overlap = 1352.09
+PHY-3002 : Step(17): len = 193574, overlap = 1375.38
+PHY-3002 : Step(18): len = 183266, overlap = 1407.25
+PHY-3002 : Step(19): len = 163641, overlap = 1464.16
+PHY-3002 : Step(20): len = 159862, overlap = 1486.53
+PHY-3002 : Step(21): len = 141745, overlap = 1499
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.02822e-06
+PHY-3002 : Step(22): len = 143958, overlap = 1451
+PHY-3002 : Step(23): len = 178760, overlap = 1276.41
+PHY-3002 : Step(24): len = 186721, overlap = 1248.91
+PHY-3002 : Step(25): len = 195078, overlap = 1182.78
+PHY-3002 : Step(26): len = 194959, overlap = 1150.09
+PHY-3002 : Step(27): len = 194711, overlap = 1120.59
+PHY-3002 : Step(28): len = 192016, overlap = 1116.5
+PHY-3002 : Step(29): len = 190835, overlap = 1101.31
+PHY-3002 : Step(30): len = 188882, overlap = 1094.09
+PHY-3002 : Step(31): len = 187233, overlap = 1097.59
+PHY-3002 : Step(32): len = 184924, overlap = 1094.12
+PHY-3002 : Step(33): len = 183670, overlap = 1081.53
+PHY-3002 : Step(34): len = 180996, overlap = 1056.91
+PHY-3002 : Step(35): len = 178143, overlap = 1070.81
+PHY-3002 : Step(36): len = 176411, overlap = 1062.62
+PHY-3002 : Step(37): len = 174777, overlap = 1068.03
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.05644e-06
+PHY-3002 : Step(38): len = 178271, overlap = 1057.72
+PHY-3002 : Step(39): len = 190476, overlap = 1035.09
+PHY-3002 : Step(40): len = 195136, overlap = 1042.81
+PHY-3002 : Step(41): len = 199844, overlap = 1026.56
+PHY-3002 : Step(42): len = 202199, overlap = 1014.72
+PHY-3002 : Step(43): len = 204197, overlap = 1011.75
+PHY-3002 : Step(44): len = 202607, overlap = 1013.44
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.11288e-06
+PHY-3002 : Step(45): len = 208527, overlap = 987.906
+PHY-3002 : Step(46): len = 221863, overlap = 920.5
+PHY-3002 : Step(47): len = 229722, overlap = 851.875
+PHY-3002 : Step(48): len = 238838, overlap = 807.594
+PHY-3002 : Step(49): len = 241958, overlap = 807.25
+PHY-3002 : Step(50): len = 243080, overlap = 770.312
+PHY-3002 : Step(51): len = 243939, overlap = 762.25
+PHY-3002 : Step(52): len = 242790, overlap = 751.438
+PHY-3002 : Step(53): len = 242209, overlap = 768.125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.22576e-06
+PHY-3002 : Step(54): len = 255130, overlap = 723.969
+PHY-3002 : Step(55): len = 276077, overlap = 649.75
+PHY-3002 : Step(56): len = 284942, overlap = 606.719
+PHY-3002 : Step(57): len = 289672, overlap = 561.594
+PHY-3002 : Step(58): len = 288797, overlap = 506.312
+PHY-3002 : Step(59): len = 289011, overlap = 476.625
+PHY-3002 : Step(60): len = 288232, overlap = 485.531
+PHY-3002 : Step(61): len = 289714, overlap = 498.844
+PHY-3002 : Step(62): len = 289884, overlap = 503.219
+PHY-3002 : Step(63): len = 289760, overlap = 512.406
+PHY-3002 : Step(64): len = 289227, overlap = 519.938
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.64515e-05
+PHY-3002 : Step(65): len = 304798, overlap = 504.938
+PHY-3002 : Step(66): len = 318499, overlap = 458.219
+PHY-3002 : Step(67): len = 325094, overlap = 435.406
+PHY-3002 : Step(68): len = 329612, overlap = 432
+PHY-3002 : Step(69): len = 327239, overlap = 430.031
+PHY-3002 : Step(70): len = 327528, overlap = 415.062
+PHY-3002 : Step(71): len = 327201, overlap = 409.094
+PHY-3002 : Step(72): len = 329571, overlap = 398.406
+PHY-3002 : Step(73): len = 329828, overlap = 387.031
+PHY-3002 : Step(74): len = 330421, overlap = 371
+PHY-3002 : Step(75): len = 328534, overlap = 379.875
+PHY-3002 : Step(76): len = 328295, overlap = 399.781
+PHY-3002 : Step(77): len = 327928, overlap = 401.75
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.2903e-05
+PHY-3002 : Step(78): len = 344796, overlap = 375.25
+PHY-3002 : Step(79): len = 358387, overlap = 357.219
+PHY-3002 : Step(80): len = 358769, overlap = 345.125
+PHY-3002 : Step(81): len = 362215, overlap = 330.625
+PHY-3002 : Step(82): len = 364933, overlap = 329.469
+PHY-3002 : Step(83): len = 368411, overlap = 312.656
+PHY-3002 : Step(84): len = 366988, overlap = 288.812
+PHY-3002 : Step(85): len = 369005, overlap = 276.812
+PHY-3002 : Step(86): len = 369236, overlap = 272.562
+PHY-3002 : Step(87): len = 370349, overlap = 262.438
+PHY-3002 : Step(88): len = 368263, overlap = 249.938
+PHY-3002 : Step(89): len = 369280, overlap = 244.188
+PHY-3002 : Step(90): len = 368364, overlap = 270.531
+PHY-3002 : Step(91): len = 369652, overlap = 265.812
+PHY-3002 : Step(92): len = 368205, overlap = 258.375
+PHY-3002 : Step(93): len = 369041, overlap = 262.094
+PHY-3002 : Step(94): len = 368886, overlap = 260.5
+PHY-3002 : Step(95): len = 369264, overlap = 252.031
+PHY-3002 : Step(96): len = 367145, overlap = 260.906
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.58061e-05
+PHY-3002 : Step(97): len = 382775, overlap = 243.5
+PHY-3002 : Step(98): len = 394531, overlap = 230.25
+PHY-3002 : Step(99): len = 393183, overlap = 222.125
+PHY-3002 : Step(100): len = 394609, overlap = 221.906
+PHY-3002 : Step(101): len = 396631, overlap = 201.812
+PHY-3002 : Step(102): len = 399261, overlap = 207.375
+PHY-3002 : Step(103): len = 396515, overlap = 210.156
+PHY-3002 : Step(104): len = 399109, overlap = 222.219
+PHY-3002 : Step(105): len = 402827, overlap = 224.75
+PHY-3002 : Step(106): len = 405608, overlap = 229.812
+PHY-3002 : Step(107): len = 401582, overlap = 226.25
+PHY-3002 : Step(108): len = 401335, overlap = 226.531
+PHY-3002 : Step(109): len = 402647, overlap = 233.125
+PHY-3002 : Step(110): len = 404232, overlap = 230.969
+PHY-3002 : Step(111): len = 401401, overlap = 231
+PHY-3002 : Step(112): len = 401863, overlap = 231.469
+PHY-3002 : Step(113): len = 402901, overlap = 228.25
+PHY-3002 : Step(114): len = 403680, overlap = 222
+PHY-3002 : Step(115): len = 401814, overlap = 221.125
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00012855
+PHY-3002 : Step(116): len = 414862, overlap = 217.219
+PHY-3002 : Step(117): len = 423138, overlap = 215.25
+PHY-3002 : Step(118): len = 423081, overlap = 205.719
+PHY-3002 : Step(119): len = 425442, overlap = 206.438
+PHY-3002 : Step(120): len = 429196, overlap = 207.688
+PHY-3002 : Step(121): len = 432093, overlap = 205.281
+PHY-3002 : Step(122): len = 431035, overlap = 189.781
+PHY-3002 : Step(123): len = 432975, overlap = 185.75
+PHY-3002 : Step(124): len = 435554, overlap = 179.25
+PHY-3002 : Step(125): len = 437871, overlap = 173.938
+PHY-3002 : Step(126): len = 436395, overlap = 189.312
+PHY-3002 : Step(127): len = 436722, overlap = 192.594
+PHY-3002 : Step(128): len = 437318, overlap = 185.719
+PHY-3002 : Step(129): len = 437599, overlap = 184.094
+PHY-3002 : Step(130): len = 435617, overlap = 191.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00024168
+PHY-3002 : Step(131): len = 445349, overlap = 188.969
+PHY-3002 : Step(132): len = 452439, overlap = 178
+PHY-3002 : Step(133): len = 451626, overlap = 182.156
+PHY-3002 : Step(134): len = 452160, overlap = 189.531
+PHY-3002 : Step(135): len = 455801, overlap = 189.406
+PHY-3002 : Step(136): len = 458885, overlap = 194.719
+PHY-3002 : Step(137): len = 457674, overlap = 190.312
+PHY-3002 : Step(138): len = 457731, overlap = 190.562
+PHY-3002 : Step(139): len = 459583, overlap = 194.469
+PHY-3002 : Step(140): len = 461126, overlap = 183.531
+PHY-3002 : Step(141): len = 460166, overlap = 187.469
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000442067
+PHY-3002 : Step(142): len = 465681, overlap = 186.031
+PHY-3002 : Step(143): len = 472910, overlap = 187.031
+PHY-3002 : Step(144): len = 473789, overlap = 182
+PHY-3002 : Step(145): len = 474610, overlap = 180.344
+PHY-3002 : Step(146): len = 477362, overlap = 180.656
+PHY-3002 : Step(147): len = 479954, overlap = 174.875
+PHY-3002 : Step(148): len = 479306, overlap = 172.219
+PHY-3002 : Step(149): len = 479926, overlap = 171.062
+PHY-3002 : Step(150): len = 482550, overlap = 164.594
+PHY-3002 : Step(151): len = 483777, overlap = 168.469
+PHY-3002 : Step(152): len = 482415, overlap = 164.219
+PHY-3002 : Step(153): len = 481733, overlap = 167.094
+PHY-3002 : Step(154): len = 483189, overlap = 167.062
+PHY-3002 : Step(155): len = 484180, overlap = 165.719
+PHY-3002 : Step(156): len = 482827, overlap = 163.469
+PHY-3002 : Step(157): len = 482463, overlap = 162.5
+PHY-3002 : Step(158): len = 484068, overlap = 160.875
+PHY-3002 : Step(159): len = 485958, overlap = 151.375
+PHY-3002 : Step(160): len = 485139, overlap = 149.312
+PHY-3002 : Step(161): len = 485180, overlap = 148.75
+PHY-3002 : Step(162): len = 486441, overlap = 147.969
+PHY-3002 : Step(163): len = 487101, overlap = 145.719
+PHY-3002 : Step(164): len = 486225, overlap = 142.406
+PHY-3002 : Step(165): len = 486482, overlap = 148.938
+PHY-3002 : Step(166): len = 487822, overlap = 143.656
+PHY-3002 : Step(167): len = 488471, overlap = 142.344
+PHY-3002 : Step(168): len = 487522, overlap = 146.938
+PHY-3002 : Step(169): len = 487330, overlap = 147.156
+PHY-3002 : Step(170): len = 488330, overlap = 144.531
+PHY-3002 : Step(171): len = 488985, overlap = 147.688
+PHY-3002 : Step(172): len = 487737, overlap = 151.688
+PHY-3002 : Step(173): len = 487556, overlap = 150.75
+PHY-3002 : Step(174): len = 488039, overlap = 148.719
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000866001
+PHY-3002 : Step(175): len = 492717, overlap = 149.031
+PHY-3002 : Step(176): len = 499850, overlap = 145.75
+PHY-3002 : Step(177): len = 503919, overlap = 131.438
+PHY-3002 : Step(178): len = 506454, overlap = 130.031
+PHY-3002 : Step(179): len = 509108, overlap = 122.344
+PHY-3002 : Step(180): len = 511658, overlap = 125.344
+PHY-3002 : Step(181): len = 510971, overlap = 131.781
+PHY-3002 : Step(182): len = 510979, overlap = 135.281
+PHY-3002 : Step(183): len = 511673, overlap = 135.375
+PHY-3002 : Step(184): len = 511793, overlap = 135.375
+PHY-3002 : Step(185): len = 510887, overlap = 136.031
+PHY-3002 : Step(186): len = 510299, overlap = 135.062
+PHY-3002 : Step(187): len = 510584, overlap = 134.938
+PHY-3002 : Step(188): len = 510602, overlap = 140.281
+PHY-3002 : Step(189): len = 510122, overlap = 138.938
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00148578
+PHY-3002 : Step(190): len = 512640, overlap = 131.719
+PHY-3002 : Step(191): len = 514464, overlap = 133.438
+PHY-3002 : Step(192): len = 515236, overlap = 133.031
+PHY-3002 : Step(193): len = 516125, overlap = 133.094
+PHY-3002 : Step(194): len = 518059, overlap = 130.5
+PHY-3002 : Step(195): len = 519160, overlap = 129.062
+PHY-3002 : Step(196): len = 519248, overlap = 128.469
+PHY-3002 : Step(197): len = 519400, overlap = 128.906
+PHY-3002 : Step(198): len = 519996, overlap = 127.469
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00240399
+PHY-3002 : Step(199): len = 522370, overlap = 129.781
+PHY-3002 : Step(200): len = 530306, overlap = 129.062
+PHY-3002 : Step(201): len = 532776, overlap = 128.562
+PHY-3002 : Step(202): len = 535089, overlap = 128.312
+PHY-3002 : Step(203): len = 536787, overlap = 118.469
+PHY-3002 : Step(204): len = 538292, overlap = 120.031
+PHY-3002 : Step(205): len = 540055, overlap = 114
+PHY-3002 : Step(206): len = 541705, overlap = 122.125
+PHY-3002 : Step(207): len = 542117, overlap = 117.5
+PHY-3002 : Step(208): len = 542364, overlap = 115.531
+PHY-3002 : Step(209): len = 542796, overlap = 121.406
+PHY-3002 : Step(210): len = 543400, overlap = 121.188
+PHY-3002 : Step(211): len = 543463, overlap = 115.812
+PHY-3002 : Step(212): len = 543489, overlap = 115.5
+PHY-3002 : Step(213): len = 543660, overlap = 115.5
+PHY-3002 : Step(214): len = 543856, overlap = 117.812
+PHY-3002 : Step(215): len = 544089, overlap = 116.688
+PHY-3002 : Step(216): len = 544159, overlap = 117.5
+PHY-3002 : Step(217): len = 544070, overlap = 114.812
+PHY-3002 : Step(218): len = 544070, overlap = 114.812
+PHY-3002 : Step(219): len = 544166, overlap = 114.875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.019731s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (237.6%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20694.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 729544, over cnt = 1603(4%), over = 7463, worst = 44
+PHY-1001 : End global iterations; 0.799937s wall, 1.109375s user + 0.078125s system = 1.187500s CPU (148.4%)
+
+PHY-1001 : Congestion index: top1 = 83.08, top5 = 62.83, top10 = 53.44, top15 = 47.48.
+PHY-3001 : End congestion estimation; 1.064748s wall, 1.359375s user + 0.093750s system = 1.453125s CPU (136.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20516 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.944036s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000141221
+PHY-3002 : Step(220): len = 659464, overlap = 79.8438
+PHY-3002 : Step(221): len = 656740, overlap = 79.875
+PHY-3002 : Step(222): len = 649029, overlap = 80.1875
+PHY-3002 : Step(223): len = 645108, overlap = 71.4688
+PHY-3002 : Step(224): len = 645208, overlap = 48.5312
+PHY-3002 : Step(225): len = 645723, overlap = 45.2188
+PHY-3002 : Step(226): len = 643199, overlap = 45.9688
+PHY-3002 : Step(227): len = 641092, overlap = 46.4688
+PHY-3002 : Step(228): len = 639667, overlap = 43.1562
+PHY-3002 : Step(229): len = 636759, overlap = 41.0625
+PHY-3002 : Step(230): len = 634935, overlap = 36.0312
+PHY-3002 : Step(231): len = 633144, overlap = 34.6875
+PHY-3002 : Step(232): len = 632480, overlap = 35.0938
+PHY-3002 : Step(233): len = 630373, overlap = 37.4688
+PHY-3002 : Step(234): len = 628985, overlap = 38.7812
+PHY-3002 : Step(235): len = 628936, overlap = 39.8438
+PHY-3002 : Step(236): len = 626522, overlap = 41.0938
+PHY-3002 : Step(237): len = 625661, overlap = 42.5
+PHY-3002 : Step(238): len = 624467, overlap = 43.6875
+PHY-3002 : Step(239): len = 624465, overlap = 41.2812
+PHY-3002 : Step(240): len = 623493, overlap = 38.0625
+PHY-3002 : Step(241): len = 622585, overlap = 38.9062
+PHY-3002 : Step(242): len = 623120, overlap = 38.0625
+PHY-3002 : Step(243): len = 622895, overlap = 41.5312
+PHY-3002 : Step(244): len = 622246, overlap = 41.3125
+PHY-3002 : Step(245): len = 621798, overlap = 36.8125
+PHY-3002 : Step(246): len = 621936, overlap = 34.0625
+PHY-3002 : Step(247): len = 621546, overlap = 31.9688
+PHY-3002 : Step(248): len = 620384, overlap = 32.5938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000282442
+PHY-3002 : Step(249): len = 623577, overlap = 32.7188
+PHY-3002 : Step(250): len = 626779, overlap = 32.0938
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 47/20694.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 713528, over cnt = 2685(7%), over = 11488, worst = 42
+PHY-1001 : End global iterations; 2.016508s wall, 2.546875s user + 0.031250s system = 2.578125s CPU (127.9%)
+
+PHY-1001 : Congestion index: top1 = 83.12, top5 = 65.76, top10 = 57.73, top15 = 52.30.
+PHY-3001 : End congestion estimation; 2.327576s wall, 2.828125s user + 0.062500s system = 2.890625s CPU (124.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20516 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.969490s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.09758e-05
+PHY-3002 : Step(251): len = 624839, overlap = 249.969
+PHY-3002 : Step(252): len = 629684, overlap = 217.844
+PHY-3002 : Step(253): len = 626104, overlap = 201.906
+PHY-3002 : Step(254): len = 623197, overlap = 188.031
+PHY-3002 : Step(255): len = 623906, overlap = 173.812
+PHY-3002 : Step(256): len = 619521, overlap = 162.312
+PHY-3002 : Step(257): len = 617631, overlap = 155.062
+PHY-3002 : Step(258): len = 615780, overlap = 149.406
+PHY-3002 : Step(259): len = 612654, overlap = 140.875
+PHY-3002 : Step(260): len = 610752, overlap = 134.031
+PHY-3002 : Step(261): len = 607877, overlap = 132.406
+PHY-3002 : Step(262): len = 605296, overlap = 132.281
+PHY-3002 : Step(263): len = 603378, overlap = 124.938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000181952
+PHY-3002 : Step(264): len = 603437, overlap = 122.344
+PHY-3002 : Step(265): len = 605271, overlap = 119.594
+PHY-3002 : Step(266): len = 608870, overlap = 111.688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000363903
+PHY-3002 : Step(267): len = 613857, overlap = 100.438
+PHY-3002 : Step(268): len = 617741, overlap = 96.75
+PHY-3002 : Step(269): len = 623438, overlap = 91.625
+PHY-3002 : Step(270): len = 627444, overlap = 88.6562
+PHY-3002 : Step(271): len = 629407, overlap = 87.375
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84630, tnet num: 20516, tinst num: 18115, tnode num: 115358, tedge num: 134978.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.604335s wall, 1.562500s user + 0.046875s system = 1.609375s CPU (100.3%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 566 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 411.75 peak overflow 3.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1176/20694.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725984, over cnt = 2948(8%), over = 10666, worst = 21
+PHY-1001 : End global iterations; 1.372540s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (142.3%)
+
+PHY-1001 : Congestion index: top1 = 68.73, top5 = 56.74, top10 = 50.81, top15 = 47.26.
+PHY-1001 : End incremental global routing; 1.730789s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (133.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20516 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.956410s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (101.3%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17983 has valid locations, 310 needs to be replaced
+PHY-3001 : design contains 18378 instances, 7769 luts, 9388 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6173 pins
+PHY-3001 : Found 1269 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 652477
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16864/20957.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 739632, over cnt = 3023(8%), over = 10829, worst = 21
+PHY-1001 : End global iterations; 0.271450s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (132.4%)
+
+PHY-1001 : Congestion index: top1 = 68.86, top5 = 56.88, top10 = 51.12, top15 = 47.67.
+PHY-3001 : End congestion estimation; 0.563032s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (113.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85658, tnet num: 20779, tinst num: 18378, tnode num: 116883, tedge num: 136508.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.611613s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (99.9%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 636 MB, peak memory is 716 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20779 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.658406s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(272): len = 651309, overlap = 0.25
+PHY-3002 : Step(273): len = 650678, overlap = 0.1875
+PHY-3002 : Step(274): len = 650213, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16958/20957.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737192, over cnt = 3009(8%), over = 10835, worst = 21
+PHY-1001 : End global iterations; 0.208643s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (112.3%)
+
+PHY-1001 : Congestion index: top1 = 69.42, top5 = 57.16, top10 = 51.25, top15 = 47.71.
+PHY-3001 : End congestion estimation; 0.492024s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (108.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20779 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.114856s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000392831
+PHY-3002 : Step(275): len = 650101, overlap = 89.2812
+PHY-3002 : Step(276): len = 650237, overlap = 90.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000785662
+PHY-3002 : Step(277): len = 650341, overlap = 89.5938
+PHY-3002 : Step(278): len = 650833, overlap = 89.7188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00153861
+PHY-3002 : Step(279): len = 651072, overlap = 90.0938
+PHY-3002 : Step(280): len = 651527, overlap = 90.0938
+PHY-3001 : Final: Len = 651527, Over = 90.0938
+PHY-3001 : End incremental placement; 5.640148s wall, 6.062500s user + 0.250000s system = 6.312500s CPU (111.9%)
+
+OPT-1001 : Total overflow 416.84 peak overflow 3.97
+OPT-1001 : End high-fanout net optimization; 8.908982s wall, 9.984375s user + 0.250000s system = 10.234375s CPU (114.9%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 711, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16879/20957.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740720, over cnt = 2947(8%), over = 9816, worst = 21
+PHY-1002 : len = 787176, over cnt = 2041(5%), over = 5320, worst = 19
+PHY-1002 : len = 828064, over cnt = 946(2%), over = 2281, worst = 19
+PHY-1002 : len = 853520, over cnt = 276(0%), over = 653, worst = 13
+PHY-1002 : len = 863112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.884325s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (141.0%)
+
+PHY-1001 : Congestion index: top1 = 57.59, top5 = 50.66, top10 = 47.21, top15 = 44.83.
+OPT-1001 : End congestion update; 2.177319s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (134.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20779 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.875786s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 122 cells processed and 17200 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 55 cells processed and 7450 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 1018 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.545432s wall, 4.296875s user + 0.015625s system = 4.312500s CPU (121.6%)
+
+OPT-1001 : Current memory(MB): used = 694, reserve = 694, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16944/20960.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863032, over cnt = 81(0%), over = 127, worst = 5
+PHY-1002 : len = 862952, over cnt = 59(0%), over = 72, worst = 3
+PHY-1002 : len = 863360, over cnt = 26(0%), over = 29, worst = 2
+PHY-1002 : len = 863824, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 863920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.795565s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (106.1%)
+
+PHY-1001 : Congestion index: top1 = 57.48, top5 = 50.45, top10 = 47.02, top15 = 44.65.
+OPT-1001 : End congestion update; 1.091883s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (104.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20782 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.911365s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.4%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 26 cells processed and 3950 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.152395s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (101.6%)
+
+OPT-1001 : Current memory(MB): used = 706, reserve = 700, peak = 734.
+OPT-1001 : End physical optimization; 16.558607s wall, 18.359375s user + 0.343750s system = 18.703125s CPU (113.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7769 LUT to BLE ...
+SYN-4008 : Packed 7769 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6243 remaining SEQ's ...
+SYN-4005 : Packed 3924 SEQ with LUT/SLICE
+SYN-4006 : 994 single LUT's are left
+SYN-4006 : 2319 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10088/13875 primitive instances ...
+PHY-3001 : End packing; 1.899374s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6794 instances
+RUN-1001 : 3323 mslices, 3323 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17941 nets
+RUN-6002 WARNING: There are 6 undriven nets.
+RUN-6004 WARNING: There are 26 nets with only 1 pin.
+RUN-1001 : 10047 nets have 2 pins
+RUN-1001 : 6534 nets have [3 - 5] pins
+RUN-1001 : 725 nets have [6 - 10] pins
+RUN-1001 : 287 nets have [11 - 20] pins
+RUN-1001 : 310 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6792 instances, 6646 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3601 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 665032, Over = 229.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7578/17941.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 816240, over cnt = 1906(5%), over = 3231, worst = 10
+PHY-1002 : len = 823792, over cnt = 1181(3%), over = 1757, worst = 8
+PHY-1002 : len = 835944, over cnt = 573(1%), over = 776, worst = 6
+PHY-1002 : len = 843968, over cnt = 220(0%), over = 290, worst = 5
+PHY-1002 : len = 849048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.956261s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (138.2%)
+
+PHY-1001 : Congestion index: top1 = 58.17, top5 = 50.81, top10 = 46.81, top15 = 44.34.
+PHY-3001 : End congestion estimation; 2.393629s wall, 3.125000s user + 0.015625s system = 3.140625s CPU (131.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71863, tnet num: 17763, tinst num: 6792, tnode num: 94484, tedge num: 119487.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.758842s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (99.5%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 611 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17763 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.702534s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.37976e-05
+PHY-3002 : Step(281): len = 653143, overlap = 223.75
+PHY-3002 : Step(282): len = 646766, overlap = 227
+PHY-3002 : Step(283): len = 642868, overlap = 233
+PHY-3002 : Step(284): len = 640329, overlap = 238
+PHY-3002 : Step(285): len = 637546, overlap = 246.5
+PHY-3002 : Step(286): len = 634655, overlap = 255
+PHY-3002 : Step(287): len = 632187, overlap = 261.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000107595
+PHY-3002 : Step(288): len = 635375, overlap = 254.5
+PHY-3002 : Step(289): len = 639515, overlap = 246
+PHY-3002 : Step(290): len = 639983, overlap = 249.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00021519
+PHY-3002 : Step(291): len = 648904, overlap = 228
+PHY-3002 : Step(292): len = 657485, overlap = 208.5
+PHY-3002 : Step(293): len = 656241, overlap = 209
+PHY-3002 : Step(294): len = 654682, overlap = 212
+PHY-3002 : Step(295): len = 654666, overlap = 209.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.380394s wall, 0.328125s user + 0.656250s system = 0.984375s CPU (258.8%)
+
+PHY-3001 : Trial Legalized: Len = 736251
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 1025/17941.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 848712, over cnt = 2610(7%), over = 4340, worst = 8
+PHY-1002 : len = 866680, over cnt = 1465(4%), over = 2113, worst = 8
+PHY-1002 : len = 883416, over cnt = 617(1%), over = 845, worst = 6
+PHY-1002 : len = 891800, over cnt = 197(0%), over = 247, worst = 6
+PHY-1002 : len = 895744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.716205s wall, 3.921875s user + 0.000000s system = 3.921875s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 55.93, top5 = 50.27, top10 = 47.04, top15 = 44.95.
+PHY-3001 : End congestion estimation; 3.229594s wall, 4.437500s user + 0.000000s system = 4.437500s CPU (137.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17763 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.961607s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164813
+PHY-3002 : Step(296): len = 709829, overlap = 44
+PHY-3002 : Step(297): len = 695153, overlap = 67.25
+PHY-3002 : Step(298): len = 682626, overlap = 95.5
+PHY-3002 : Step(299): len = 676231, overlap = 110.25
+PHY-3002 : Step(300): len = 670973, overlap = 131.25
+PHY-3002 : Step(301): len = 668269, overlap = 145
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000329626
+PHY-3002 : Step(302): len = 672559, overlap = 142.25
+PHY-3002 : Step(303): len = 676393, overlap = 137.5
+PHY-3002 : Step(304): len = 679583, overlap = 131.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000659253
+PHY-3002 : Step(305): len = 682900, overlap = 130.25
+PHY-3002 : Step(306): len = 692859, overlap = 127.25
+PHY-3002 : Step(307): len = 699242, overlap = 135.25
+PHY-3002 : Step(308): len = 696449, overlap = 134.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.042475s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (73.6%)
+
+PHY-3001 : Legalized: Len = 723801, Over = 0
+PHY-3001 : Spreading special nets. 489 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.115296s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (94.9%)
+
+PHY-3001 : 706 instances has been re-located, deltaX = 234, deltaY = 399, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 733872, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71863, tnet num: 17763, tinst num: 6795, tnode num: 94484, tedge num: 119487.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.011362s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (100.2%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 644 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3636/17941.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 857552, over cnt = 2500(7%), over = 4004, worst = 6
+PHY-1002 : len = 871768, over cnt = 1376(3%), over = 1949, worst = 6
+PHY-1002 : len = 887520, over cnt = 486(1%), over = 641, worst = 5
+PHY-1002 : len = 894336, over cnt = 160(0%), over = 215, worst = 5
+PHY-1002 : len = 897704, over cnt = 2(0%), over = 5, worst = 4
+PHY-1001 : End global iterations; 2.747352s wall, 3.812500s user + 0.046875s system = 3.859375s CPU (140.5%)
+
+PHY-1001 : Congestion index: top1 = 55.71, top5 = 49.69, top10 = 46.37, top15 = 44.40.
+PHY-1001 : End incremental global routing; 3.182428s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (135.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17763 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.516872s wall, 1.375000s user + 0.031250s system = 1.406250s CPU (92.7%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6702 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6817 instances, 6668 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 739298
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16317/17968.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903856, over cnt = 135(0%), over = 168, worst = 5
+PHY-1002 : len = 904016, over cnt = 66(0%), over = 75, worst = 5
+PHY-1002 : len = 904768, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 904840, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 904968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.134127s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.2%)
+
+PHY-1001 : Congestion index: top1 = 55.54, top5 = 49.79, top10 = 46.56, top15 = 44.58.
+PHY-3001 : End congestion estimation; 1.514701s wall, 1.484375s user + 0.015625s system = 1.500000s CPU (99.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72087, tnet num: 17790, tinst num: 6817, tnode num: 94773, tedge num: 119798.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.038161s wall, 2.031250s user + 0.015625s system = 2.046875s CPU (100.4%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 654 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17790 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.040188s wall, 3.015625s user + 0.031250s system = 3.046875s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(309): len = 738429, overlap = 0
+PHY-3002 : Step(310): len = 737498, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16302/17968.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902336, over cnt = 92(0%), over = 119, worst = 5
+PHY-1002 : len = 902696, over cnt = 35(0%), over = 38, worst = 3
+PHY-1002 : len = 902896, over cnt = 19(0%), over = 20, worst = 2
+PHY-1002 : len = 903104, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 903288, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.895220s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 55.60, top5 = 49.73, top10 = 46.45, top15 = 44.47.
+PHY-3001 : End congestion estimation; 1.289855s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (104.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17790 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.945904s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000592203
+PHY-3002 : Step(311): len = 737164, overlap = 1.75
+PHY-3002 : Step(312): len = 736947, overlap = 2.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005529s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 736989, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066946s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.4%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 737015, Over = 0
+PHY-3001 : End incremental placement; 7.465576s wall, 7.531250s user + 0.093750s system = 7.625000s CPU (102.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 12.826248s wall, 13.906250s user + 0.171875s system = 14.078125s CPU (109.8%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 730, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16302/17968.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903024, over cnt = 78(0%), over = 100, worst = 6
+PHY-1002 : len = 903408, over cnt = 25(0%), over = 29, worst = 3
+PHY-1002 : len = 903528, over cnt = 12(0%), over = 14, worst = 2
+PHY-1002 : len = 903760, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.682373s wall, 0.671875s user + 0.015625s system = 0.687500s CPU (100.8%)
+
+PHY-1001 : Congestion index: top1 = 55.84, top5 = 49.89, top10 = 46.50, top15 = 44.51.
+OPT-1001 : End congestion update; 1.042130s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (100.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17790 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.798307s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.8%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6729 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6817 instances, 6668 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 740905, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066603s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.3%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 8, deltaY = 9, maxDist = 1.
+PHY-3001 : Final: Len = 741275, Over = 0
+PHY-3001 : End incremental legalization; 0.430289s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.0%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 45 cells processed and 10300 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6729 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6817 instances, 6668 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 745361, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.067564s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.5%)
+
+PHY-3001 : 23 instances has been re-located, deltaX = 11, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 745925, Over = 0
+PHY-3001 : End incremental legalization; 0.428100s wall, 0.421875s user + 0.031250s system = 0.453125s CPU (105.8%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 33 cells processed and 10812 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6729 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6817 instances, 6668 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 746397, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068200s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.6%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 3.
+PHY-3001 : Final: Len = 746787, Over = 0
+PHY-3001 : End incremental legalization; 0.426760s wall, 0.531250s user + 0.015625s system = 0.546875s CPU (128.1%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 13 cells processed and 1766 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6732 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6820 instances, 6671 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3685 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 747101, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066442s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.1%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 747113, Over = 0
+PHY-3001 : End incremental legalization; 0.504658s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (102.2%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 471 slack improved
+OPT-1001 : End bottleneck based optimization; 4.309274s wall, 4.437500s user + 0.078125s system = 4.515625s CPU (104.8%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 731, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15963/17970.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912968, over cnt = 162(0%), over = 195, worst = 5
+PHY-1002 : len = 913224, over cnt = 77(0%), over = 81, worst = 3
+PHY-1002 : len = 913680, over cnt = 38(0%), over = 38, worst = 1
+PHY-1002 : len = 914376, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 914440, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.937777s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (113.3%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.05, top10 = 46.62, top15 = 44.60.
+OPT-1001 : End congestion update; 1.323200s wall, 1.390625s user + 0.031250s system = 1.421875s CPU (107.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.792833s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.5%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6732 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6820 instances, 6671 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3685 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 747273, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066909s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (116.8%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 5, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 747583, Over = 0
+PHY-3001 : End incremental legalization; 0.431459s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.4%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 17 cells processed and 1900 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6732 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6820 instances, 6671 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3685 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 747571, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068726s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (113.7%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 1, deltaY = 4, maxDist = 1.
+PHY-3001 : Final: Len = 747647, Over = 0
+PHY-3001 : End incremental legalization; 0.427633s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.7%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 6 cells processed and 250 slack improved
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.266950s wall, 3.343750s user + 0.031250s system = 3.375000s CPU (103.3%)
+
+OPT-1001 : Current memory(MB): used = 729, reserve = 731, peak = 734.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.787481s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (97.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16242/17970.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914848, over cnt = 61(0%), over = 72, worst = 3
+PHY-1002 : len = 914768, over cnt = 29(0%), over = 29, worst = 1
+PHY-1002 : len = 915040, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 915080, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 915192, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.875392s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.99, top10 = 46.60, top15 = 44.59.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.795934s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.586207
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6732 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6820 instances, 6671 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3685 pins
+PHY-3001 : Found 491 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 747647, Over = 0
+PHY-3001 : End spreading; 0.071088s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (87.9%)
+
+PHY-3001 : Final: Len = 747647, Over = 0
+PHY-3001 : End incremental legalization; 0.488494s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.832615s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.5%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16346/17970.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915192, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.142831s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.5%)
+
+PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.99, top10 = 46.60, top15 = 44.59.
+OPT-1001 : End congestion update; 0.489888s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (102.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.777738s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.279921s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 731, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16346/17970.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915192, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.144979s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.0%)
+
+PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.99, top10 = 46.60, top15 = 44.59.
+OPT-1001 : End congestion update; 0.490866s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.773992s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (98.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.437013s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 731, peak = 734.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779935s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 730, reserve = 731, peak = 734.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.797335s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.0%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16346/17970.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915192, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.145021s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.99, top10 = 46.60, top15 = 44.59.
+RUN-1001 : End congestion update; 0.495522s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (100.9%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.296144s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (98.9%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 731, peak = 734.
+OPT-1001 : End physical optimization; 31.827801s wall, 33.093750s user + 0.296875s system = 33.390625s CPU (104.9%)
+
+RUN-1003 : finish command "place" in 80.382691s wall, 113.203125s user + 6.671875s system = 119.875000s CPU (149.1%)
+
+RUN-1004 : used memory is 638 MB, reserved memory is 631 MB, peak memory is 734 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.779527s wall, 3.093750s user + 0.031250s system = 3.125000s CPU (175.6%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 633 MB, peak memory is 734 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param route opt_timing high"
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6822 instances
+RUN-1001 : 3333 mslices, 3338 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17970 nets
+RUN-6002 WARNING: There are 6 undriven nets.
+RUN-6004 WARNING: There are 26 nets with only 1 pin.
+RUN-1001 : 10045 nets have 2 pins
+RUN-1001 : 6541 nets have [3 - 5] pins
+RUN-1001 : 734 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 326 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72109, tnet num: 17792, tinst num: 6820, tnode num: 94802, tedge num: 119828.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.741034s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.6%)
+
+RUN-1004 : used memory is 650 MB, reserved memory is 655 MB, peak memory is 734 MB
+PHY-1001 : 3333 mslices, 3338 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[14] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[2] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 851808, over cnt = 2706(7%), over = 4436, worst = 8
+PHY-1002 : len = 869384, over cnt = 1583(4%), over = 2320, worst = 8
+PHY-1002 : len = 883904, over cnt = 837(2%), over = 1217, worst = 8
+PHY-1002 : len = 902032, over cnt = 43(0%), over = 48, worst = 3
+PHY-1002 : len = 903104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.480602s wall, 4.546875s user + 0.046875s system = 4.593750s CPU (132.0%)
+
+PHY-1001 : Congestion index: top1 = 56.38, top5 = 49.99, top10 = 46.56, top15 = 44.51.
+PHY-1001 : End global routing; 3.853608s wall, 4.937500s user + 0.046875s system = 4.984375s CPU (129.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 708, reserve = 711, peak = 734.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 983, peak = 982.
+PHY-1001 : End build detailed router design. 4.340442s wall, 4.312500s user + 0.031250s system = 4.343750s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 276328, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.949960s wall, 5.953125s user + 0.000000s system = 5.953125s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 276384, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.522489s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (98.7%)
+
+PHY-1001 : Current memory(MB): used = 1016, reserve = 1019, peak = 1016.
+PHY-1001 : End phase 1; 6.485934s wall, 6.484375s user + 0.000000s system = 6.484375s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.32544e+06, over cnt = 1600(0%), over = 1605, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1032, peak = 1031.
+PHY-1001 : End initial routed; 33.447010s wall, 72.093750s user + 0.390625s system = 72.484375s CPU (216.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 31/16887(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.046 | -1.856 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.603255s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1046, peak = 1044.
+PHY-1001 : End phase 2; 37.050338s wall, 75.703125s user + 0.390625s system = 76.093750s CPU (205.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 11 pins with SWNS -1.043ns STNS -1.850ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.171784s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (91.0%)
+
+PHY-1022 : len = 2.32545e+06, over cnt = 1606(0%), over = 1611, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.473116s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (95.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29961e+06, over cnt = 608(0%), over = 608, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.191851s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (166.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.29646e+06, over cnt = 110(0%), over = 110, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.780720s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (160.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.29731e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.311492s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (120.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.29742e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.239905s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (97.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.240081s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (97.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.291805s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (101.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.389489s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.187658s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.184669s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.222456s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.232770s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.308167s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (96.3%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.29746e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.192424s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (105.6%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.29748e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.175763s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (97.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 30/16887(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.043 | -1.850 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.574411s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 486 feed throughs used by 374 nets
+PHY-1001 : End commit to database; 2.469067s wall, 2.406250s user + 0.062500s system = 2.468750s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1144, reserve = 1150, peak = 1144.
+PHY-1001 : End phase 3; 11.927206s wall, 13.140625s user + 0.093750s system = 13.234375s CPU (111.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.914ns STNS -1.721ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.169187s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.6%)
+
+PHY-1022 : len = 2.29748e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.434780s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.914ns, -1.721ns, 2}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29751e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.174022s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 30/16887(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.043 | -1.850 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.541683s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 486 feed throughs used by 374 nets
+PHY-1001 : End commit to database; 2.526594s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1159, peak = 1153.
+PHY-1001 : End phase 4; 6.726580s wall, 6.734375s user + 0.000000s system = 6.734375s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 5 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.914ns STNS -1.721ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.169550s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.2%)
+
+PHY-1022 : len = 2.29751e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.438607s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2975e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.177147s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 32/16887(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.049 | -1.856 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.521623s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1164, peak = 1158.
+PHY-1001 : End phase 5; 4.188571s wall, 4.171875s user + 0.000000s system = 4.171875s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 6 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.914ns STNS -1.721ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.167801s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.4%)
+
+PHY-1022 : len = 2.29751e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.433698s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2975e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.259990s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (102.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 30/16887(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.914 | -1.721 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.502155s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 487 feed throughs used by 375 nets
+PHY-1001 : End commit to database; 2.547175s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1164, peak = 1158.
+PHY-1001 : End phase 6; 6.784940s wall, 6.781250s user + 0.000000s system = 6.781250s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 7 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.914ns STNS -1.721ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.168793s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.8%)
+
+PHY-1022 : len = 2.2975e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.444044s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29748e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.173845s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 32/16887(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.049 | -1.856 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.527767s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1169, peak = 1162.
+PHY-1001 : End phase 7; 4.193208s wall, 4.187500s user + 0.000000s system = 4.187500s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 8 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.914ns STNS -1.721ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.165269s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (104.0%)
+
+PHY-1022 : len = 2.2975e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.438800s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.7%)
+
+PHY-0007 : Phase: 8; Congestion: {, , , }; Timing: {-0.914ns, -1.721ns, 2}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29751e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.172092s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 30/16887(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.914 | -1.721 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.581399s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 487 feed throughs used by 375 nets
+PHY-1001 : End commit to database; 2.514051s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1169, peak = 1163.
+PHY-1001 : End phase 8; 6.759230s wall, 6.765625s user + 0.000000s system = 6.765625s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.29751e+06
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1171, peak = 1164.
+PHY-1001 : End export database. 0.068394s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (91.4%)
+
+PHY-1001 : End detail routing; 88.943195s wall, 128.750000s user + 0.515625s system = 129.265625s CPU (145.3%)
+
+RUN-1003 : finish command "route" in 95.740954s wall, 136.609375s user + 0.578125s system = 137.187500s CPU (143.3%)
+
+RUN-1004 : used memory is 1158 MB, reserved memory is 1165 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10209 out of 19600 52.09%
+#reg 9571 out of 19600 48.83%
+#le 12491
+ #lut only 2920 out of 12491 23.38%
+ #reg only 2282 out of 12491 18.27%
+ #lut® 7289 out of 12491 58.35%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1763
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1442
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1357
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 939
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 138
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 29
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_eot_min/reg1_syn_308.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg0_syn_134.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P72 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P83 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P17 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P114 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P39 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P118 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P148 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P16 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12491 |9182 |1027 |9603 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |535 |424 |23 |433 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |112 |98 |4 |95 |4 |0 |
+| U_ecc_gen |ecc_gen |11 |11 |0 |6 |0 |0 |
+| U_crc16_24b |crc16_24b |37 |37 |0 |19 |0 |0 |
+| exdev_ctl_a |exdev_ctl |737 |377 |96 |559 |0 |0 |
+| u_ADconfig |AD_config |184 |116 |25 |139 |0 |0 |
+| u_gen_sp |gen_sp |251 |141 |71 |118 |0 |0 |
+| exdev_ctl_b |exdev_ctl |742 |363 |96 |569 |0 |0 |
+| u_ADconfig |AD_config |171 |105 |25 |130 |0 |0 |
+| u_gen_sp |gen_sp |253 |148 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |3026 |2476 |306 |2106 |25 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |179 |112 |17 |150 |0 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_sort |sort |2813 |2344 |289 |1922 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |0 |1 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2357 |1989 |253 |1538 |22 |0 |
+| channelPart |channel_part_8478 |130 |126 |3 |123 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1868 |1569 |197 |1154 |0 |0 |
+| adc_addr_gen |adc_addr_gen |219 |190 |27 |127 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |16 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |17 |14 |3 |8 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |948 |678 |170 |643 |0 |0 |
+| ram_switch_state |ram_switch_state |701 |701 |0 |384 |0 |0 |
+| read_ram_i |read_ram |270 |216 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |224 |184 |40 |155 |0 |0 |
+| read_ram_data |read_ram_data |43 |29 |4 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |304 |231 |36 |270 |3 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3301 |2640 |349 |2120 |25 |1 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |114 |17 |161 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |3081 |2499 |332 |1929 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2634 |2185 |290 |1553 |22 |1 |
+| channelPart |channel_part_8478 |147 |131 |3 |137 |0 |0 |
+| fifo_adc |fifo_adc |64 |55 |9 |46 |0 |1 |
+| ram_switch |ram_switch |2045 |1727 |197 |1143 |0 |0 |
+| adc_addr_gen |adc_addr_gen |204 |177 |27 |99 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| insert |insert |952 |661 |170 |647 |0 |0 |
+| ram_switch_state |ram_switch_state |889 |889 |0 |397 |0 |0 |
+| read_ram_i |read_ram_rev |351 |251 |81 |200 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |293 |209 |73 |158 |0 |0 |
+| read_ram_data |read_ram_data_rev |58 |42 |8 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9983
+ #2 2 4223
+ #3 3 1758
+ #4 4 557
+ #5 5-10 776
+ #6 11-50 562
+ #7 51-100 9
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.167784s wall, 3.734375s user + 0.031250s system = 3.765625s CPU (173.7%)
+
+RUN-1004 : used memory is 1158 MB, reserved memory is 1165 MB, peak memory is 1214 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72109, tnet num: 17792, tinst num: 6820, tnode num: 94802, tedge num: 119828.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.722505s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.8%)
+
+RUN-1004 : used memory is 1160 MB, reserved memory is 1167 MB, peak memory is 1214 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17792 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.600003s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.6%)
+
+RUN-1004 : used memory is 1161 MB, reserved memory is 1167 MB, peak memory is 1214 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6820
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17970, pip num: 169972
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 487
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3258 valid insts, and 472921 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 10.114069s wall, 66.406250s user + 0.187500s system = 66.593750s CPU (658.4%)
+
+RUN-1004 : used memory is 1260 MB, reserved memory is 1264 MB, peak memory is 1376 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_103050.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_105319.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_105319.log
new file mode 100644
index 0000000..a55ad0b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_105319.log
@@ -0,0 +1,2004 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 10:53:19 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.328685s wall, 2.250000s user + 0.078125s system = 2.328125s CPU (100.0%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18092 instances
+RUN-0007 : 7700 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20669 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13154 nets have 2 pins
+RUN-1001 : 6477 nets have [3 - 5] pins
+RUN-1001 : 611 nets have [6 - 10] pins
+RUN-1001 : 187 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18090 instances, 7700 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6040 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84467, tnet num: 20491, tinst num: 18090, tnode num: 115022, tedge num: 134702.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.244143s wall, 1.187500s user + 0.062500s system = 1.250000s CPU (100.5%)
+
+RUN-1004 : used memory is 531 MB, reserved memory is 516 MB, peak memory is 531 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20491 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.099397s wall, 2.015625s user + 0.093750s system = 2.109375s CPU (100.5%)
+
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.12734e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18090.
+PHY-3001 : Level 1 #clusters 1995.
+PHY-3001 : End clustering; 0.142833s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (131.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.34986e+06, overlap = 484.812
+PHY-3002 : Step(2): len = 1.23914e+06, overlap = 534.938
+PHY-3002 : Step(3): len = 872466, overlap = 620.625
+PHY-3002 : Step(4): len = 778429, overlap = 652.344
+PHY-3002 : Step(5): len = 610025, overlap = 756.312
+PHY-3002 : Step(6): len = 555282, overlap = 821.938
+PHY-3002 : Step(7): len = 467396, overlap = 909.25
+PHY-3002 : Step(8): len = 425276, overlap = 943
+PHY-3002 : Step(9): len = 376942, overlap = 1018.25
+PHY-3002 : Step(10): len = 351567, overlap = 1107.41
+PHY-3002 : Step(11): len = 315936, overlap = 1115
+PHY-3002 : Step(12): len = 295692, overlap = 1134.5
+PHY-3002 : Step(13): len = 268338, overlap = 1201.06
+PHY-3002 : Step(14): len = 245407, overlap = 1238.66
+PHY-3002 : Step(15): len = 220482, overlap = 1281.47
+PHY-3002 : Step(16): len = 203531, overlap = 1331.88
+PHY-3002 : Step(17): len = 183209, overlap = 1362
+PHY-3002 : Step(18): len = 172397, overlap = 1399.41
+PHY-3002 : Step(19): len = 155023, overlap = 1419.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.23287e-06
+PHY-3002 : Step(20): len = 160483, overlap = 1359.25
+PHY-3002 : Step(21): len = 200623, overlap = 1273.81
+PHY-3002 : Step(22): len = 204505, overlap = 1179.06
+PHY-3002 : Step(23): len = 206807, overlap = 1138
+PHY-3002 : Step(24): len = 203840, overlap = 1145.09
+PHY-3002 : Step(25): len = 203827, overlap = 1134.38
+PHY-3002 : Step(26): len = 201078, overlap = 1108.84
+PHY-3002 : Step(27): len = 199260, overlap = 1100.53
+PHY-3002 : Step(28): len = 195152, overlap = 1097.31
+PHY-3002 : Step(29): len = 193343, overlap = 1078.78
+PHY-3002 : Step(30): len = 190486, overlap = 1076.28
+PHY-3002 : Step(31): len = 188806, overlap = 1061.34
+PHY-3002 : Step(32): len = 187648, overlap = 1057.5
+PHY-3002 : Step(33): len = 186026, overlap = 1075.41
+PHY-3002 : Step(34): len = 184595, overlap = 1070.22
+PHY-3002 : Step(35): len = 182765, overlap = 1070.59
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.46574e-06
+PHY-3002 : Step(36): len = 187687, overlap = 1054.25
+PHY-3002 : Step(37): len = 199200, overlap = 998.219
+PHY-3002 : Step(38): len = 203107, overlap = 987.312
+PHY-3002 : Step(39): len = 207267, overlap = 977.781
+PHY-3002 : Step(40): len = 208869, overlap = 986.469
+PHY-3002 : Step(41): len = 209415, overlap = 987.156
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.93148e-06
+PHY-3002 : Step(42): len = 218909, overlap = 980.344
+PHY-3002 : Step(43): len = 240771, overlap = 879.406
+PHY-3002 : Step(44): len = 253202, overlap = 844.688
+PHY-3002 : Step(45): len = 262742, overlap = 754.562
+PHY-3002 : Step(46): len = 266512, overlap = 717.469
+PHY-3002 : Step(47): len = 265780, overlap = 685.219
+PHY-3002 : Step(48): len = 264912, overlap = 662.906
+PHY-3002 : Step(49): len = 264136, overlap = 676.125
+PHY-3002 : Step(50): len = 263204, overlap = 680.219
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.86296e-06
+PHY-3002 : Step(51): len = 278039, overlap = 641.312
+PHY-3002 : Step(52): len = 297774, overlap = 583.5
+PHY-3002 : Step(53): len = 306066, overlap = 525.25
+PHY-3002 : Step(54): len = 310021, overlap = 502.688
+PHY-3002 : Step(55): len = 308914, overlap = 489.062
+PHY-3002 : Step(56): len = 308506, overlap = 475.312
+PHY-3002 : Step(57): len = 306347, overlap = 474.781
+PHY-3002 : Step(58): len = 305758, overlap = 467.375
+PHY-3002 : Step(59): len = 305969, overlap = 453
+PHY-3002 : Step(60): len = 306466, overlap = 448.344
+PHY-3002 : Step(61): len = 305149, overlap = 457.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.97259e-05
+PHY-3002 : Step(62): len = 321634, overlap = 418.719
+PHY-3002 : Step(63): len = 336167, overlap = 400.688
+PHY-3002 : Step(64): len = 341718, overlap = 352.344
+PHY-3002 : Step(65): len = 342959, overlap = 358.5
+PHY-3002 : Step(66): len = 341254, overlap = 372.156
+PHY-3002 : Step(67): len = 341940, overlap = 361.906
+PHY-3002 : Step(68): len = 342897, overlap = 375.438
+PHY-3002 : Step(69): len = 345121, overlap = 376.156
+PHY-3002 : Step(70): len = 344618, overlap = 382.469
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.94518e-05
+PHY-3002 : Step(71): len = 361201, overlap = 373.312
+PHY-3002 : Step(72): len = 375370, overlap = 337.781
+PHY-3002 : Step(73): len = 376102, overlap = 342.406
+PHY-3002 : Step(74): len = 377687, overlap = 310.469
+PHY-3002 : Step(75): len = 380430, overlap = 295.938
+PHY-3002 : Step(76): len = 383941, overlap = 293.25
+PHY-3002 : Step(77): len = 381231, overlap = 304.312
+PHY-3002 : Step(78): len = 380116, overlap = 297.344
+PHY-3002 : Step(79): len = 383337, overlap = 278.844
+PHY-3002 : Step(80): len = 385342, overlap = 289.719
+PHY-3002 : Step(81): len = 384998, overlap = 284.438
+PHY-3002 : Step(82): len = 385517, overlap = 282.969
+PHY-3002 : Step(83): len = 386009, overlap = 280.656
+PHY-3002 : Step(84): len = 387091, overlap = 260.719
+PHY-3002 : Step(85): len = 387115, overlap = 258.844
+PHY-3002 : Step(86): len = 387081, overlap = 267.531
+PHY-3002 : Step(87): len = 387001, overlap = 261.125
+PHY-3002 : Step(88): len = 387182, overlap = 267.125
+PHY-3002 : Step(89): len = 385207, overlap = 268.312
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.89036e-05
+PHY-3002 : Step(90): len = 402059, overlap = 257.438
+PHY-3002 : Step(91): len = 411683, overlap = 245.562
+PHY-3002 : Step(92): len = 410466, overlap = 250.625
+PHY-3002 : Step(93): len = 411621, overlap = 242
+PHY-3002 : Step(94): len = 413424, overlap = 238.406
+PHY-3002 : Step(95): len = 416129, overlap = 240.531
+PHY-3002 : Step(96): len = 416122, overlap = 230.438
+PHY-3002 : Step(97): len = 417838, overlap = 211.031
+PHY-3002 : Step(98): len = 420338, overlap = 202.688
+PHY-3002 : Step(99): len = 421814, overlap = 203.531
+PHY-3002 : Step(100): len = 419258, overlap = 210.156
+PHY-3002 : Step(101): len = 419048, overlap = 223.812
+PHY-3002 : Step(102): len = 420193, overlap = 222.812
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000157807
+PHY-3002 : Step(103): len = 432352, overlap = 218.875
+PHY-3002 : Step(104): len = 441102, overlap = 212.406
+PHY-3002 : Step(105): len = 439902, overlap = 205.469
+PHY-3002 : Step(106): len = 440694, overlap = 201
+PHY-3002 : Step(107): len = 443984, overlap = 193
+PHY-3002 : Step(108): len = 447512, overlap = 190.656
+PHY-3002 : Step(109): len = 445051, overlap = 189.438
+PHY-3002 : Step(110): len = 445406, overlap = 175.312
+PHY-3002 : Step(111): len = 447069, overlap = 175.469
+PHY-3002 : Step(112): len = 448131, overlap = 178.875
+PHY-3002 : Step(113): len = 446531, overlap = 173.812
+PHY-3002 : Step(114): len = 447706, overlap = 173.531
+PHY-3002 : Step(115): len = 450254, overlap = 174.281
+PHY-3002 : Step(116): len = 452312, overlap = 180.625
+PHY-3002 : Step(117): len = 450924, overlap = 179.438
+PHY-3002 : Step(118): len = 451455, overlap = 180.594
+PHY-3002 : Step(119): len = 452877, overlap = 185
+PHY-3002 : Step(120): len = 454151, overlap = 186.438
+PHY-3002 : Step(121): len = 452414, overlap = 183.5
+PHY-3002 : Step(122): len = 452412, overlap = 182.188
+PHY-3002 : Step(123): len = 453700, overlap = 184.312
+PHY-3002 : Step(124): len = 454604, overlap = 181.75
+PHY-3002 : Step(125): len = 453250, overlap = 179.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000308315
+PHY-3002 : Step(126): len = 461338, overlap = 181.281
+PHY-3002 : Step(127): len = 468946, overlap = 177.031
+PHY-3002 : Step(128): len = 470538, overlap = 173.875
+PHY-3002 : Step(129): len = 472342, overlap = 167.031
+PHY-3002 : Step(130): len = 475608, overlap = 170.625
+PHY-3002 : Step(131): len = 477333, overlap = 165.844
+PHY-3002 : Step(132): len = 475828, overlap = 163.25
+PHY-3002 : Step(133): len = 475597, overlap = 165.344
+PHY-3002 : Step(134): len = 477044, overlap = 171.906
+PHY-3002 : Step(135): len = 478002, overlap = 173.094
+PHY-3002 : Step(136): len = 477103, overlap = 169.812
+PHY-3002 : Step(137): len = 477034, overlap = 169.188
+PHY-3002 : Step(138): len = 478030, overlap = 176.5
+PHY-3002 : Step(139): len = 478447, overlap = 176.438
+PHY-3002 : Step(140): len = 477965, overlap = 171.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00056394
+PHY-3002 : Step(141): len = 483060, overlap = 173.188
+PHY-3002 : Step(142): len = 490603, overlap = 171.094
+PHY-3002 : Step(143): len = 492148, overlap = 168.062
+PHY-3002 : Step(144): len = 493316, overlap = 166.781
+PHY-3002 : Step(145): len = 494803, overlap = 166.031
+PHY-3002 : Step(146): len = 496036, overlap = 167.594
+PHY-3002 : Step(147): len = 495909, overlap = 162.5
+PHY-3002 : Step(148): len = 496981, overlap = 159.688
+PHY-3002 : Step(149): len = 498451, overlap = 163.594
+PHY-3002 : Step(150): len = 499273, overlap = 156.531
+PHY-3002 : Step(151): len = 498819, overlap = 163.344
+PHY-3002 : Step(152): len = 498741, overlap = 162.75
+PHY-3002 : Step(153): len = 499520, overlap = 159.094
+PHY-3002 : Step(154): len = 499914, overlap = 159.969
+PHY-3002 : Step(155): len = 499269, overlap = 161.031
+PHY-3002 : Step(156): len = 499102, overlap = 161.906
+PHY-3002 : Step(157): len = 499668, overlap = 160.781
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00106859
+PHY-3002 : Step(158): len = 502898, overlap = 160.594
+PHY-3002 : Step(159): len = 508487, overlap = 159.5
+PHY-3002 : Step(160): len = 509819, overlap = 155.562
+PHY-3002 : Step(161): len = 511621, overlap = 153.562
+PHY-3002 : Step(162): len = 513909, overlap = 146.5
+PHY-3002 : Step(163): len = 515691, overlap = 150.406
+PHY-3002 : Step(164): len = 515457, overlap = 151.5
+PHY-3002 : Step(165): len = 515341, overlap = 151.188
+PHY-3002 : Step(166): len = 515538, overlap = 153.312
+PHY-3002 : Step(167): len = 515877, overlap = 151.531
+PHY-3002 : Step(168): len = 515761, overlap = 153.969
+PHY-3002 : Step(169): len = 515731, overlap = 149.5
+PHY-3002 : Step(170): len = 516171, overlap = 150.969
+PHY-3002 : Step(171): len = 516319, overlap = 150.281
+PHY-3002 : Step(172): len = 516289, overlap = 152.969
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00188421
+PHY-3002 : Step(173): len = 519688, overlap = 150.094
+PHY-3002 : Step(174): len = 526050, overlap = 153.188
+PHY-3002 : Step(175): len = 528170, overlap = 156.531
+PHY-3002 : Step(176): len = 530651, overlap = 155.062
+PHY-3002 : Step(177): len = 533635, overlap = 144.531
+PHY-3002 : Step(178): len = 535393, overlap = 146.031
+PHY-3002 : Step(179): len = 536244, overlap = 145.938
+PHY-3002 : Step(180): len = 537293, overlap = 150.531
+PHY-3002 : Step(181): len = 537970, overlap = 144.031
+PHY-3002 : Step(182): len = 538538, overlap = 143.75
+PHY-3002 : Step(183): len = 539018, overlap = 141.562
+PHY-3002 : Step(184): len = 539394, overlap = 140.031
+PHY-3002 : Step(185): len = 539415, overlap = 140.344
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014584s wall, 0.015625s user + 0.046875s system = 0.062500s CPU (428.5%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20669.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725272, over cnt = 1589(4%), over = 7549, worst = 37
+PHY-1001 : End global iterations; 0.774652s wall, 0.953125s user + 0.062500s system = 1.015625s CPU (131.1%)
+
+PHY-1001 : Congestion index: top1 = 82.09, top5 = 62.87, top10 = 53.46, top15 = 47.62.
+PHY-3001 : End congestion estimation; 1.028267s wall, 1.187500s user + 0.062500s system = 1.250000s CPU (121.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20491 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.932983s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000145893
+PHY-3002 : Step(186): len = 664191, overlap = 85.0938
+PHY-3002 : Step(187): len = 669247, overlap = 80.1562
+PHY-3002 : Step(188): len = 664267, overlap = 80.5312
+PHY-3002 : Step(189): len = 662530, overlap = 85.3125
+PHY-3002 : Step(190): len = 661338, overlap = 87.4375
+PHY-3002 : Step(191): len = 658223, overlap = 84.0625
+PHY-3002 : Step(192): len = 655529, overlap = 82.3125
+PHY-3002 : Step(193): len = 654658, overlap = 76.9375
+PHY-3002 : Step(194): len = 653558, overlap = 65.8125
+PHY-3002 : Step(195): len = 651550, overlap = 65.25
+PHY-3002 : Step(196): len = 650617, overlap = 56.5938
+PHY-3002 : Step(197): len = 649568, overlap = 50.5625
+PHY-3002 : Step(198): len = 648733, overlap = 50
+PHY-3002 : Step(199): len = 649242, overlap = 47.625
+PHY-3002 : Step(200): len = 650629, overlap = 43.0312
+PHY-3002 : Step(201): len = 650091, overlap = 42.5938
+PHY-3002 : Step(202): len = 648831, overlap = 41.625
+PHY-3002 : Step(203): len = 647019, overlap = 43.9688
+PHY-3002 : Step(204): len = 645765, overlap = 44.0312
+PHY-3002 : Step(205): len = 643988, overlap = 42.7188
+PHY-3002 : Step(206): len = 642841, overlap = 43.5938
+PHY-3002 : Step(207): len = 640822, overlap = 44.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000291786
+PHY-3002 : Step(208): len = 643028, overlap = 46
+PHY-3002 : Step(209): len = 645652, overlap = 47.0312
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000477036
+PHY-3002 : Step(210): len = 648160, overlap = 44.6875
+PHY-3002 : Step(211): len = 655044, overlap = 41.6875
+PHY-3002 : Step(212): len = 671392, overlap = 41.6875
+PHY-3002 : Step(213): len = 668413, overlap = 41.2188
+PHY-3002 : Step(214): len = 666696, overlap = 39.9062
+PHY-3002 : Step(215): len = 663552, overlap = 38.9062
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 56/20669.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743688, over cnt = 2612(7%), over = 11863, worst = 44
+PHY-1001 : End global iterations; 1.776635s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (132.8%)
+
+PHY-1001 : Congestion index: top1 = 83.43, top5 = 66.42, top10 = 57.89, top15 = 52.60.
+PHY-3001 : End congestion estimation; 2.065537s wall, 2.609375s user + 0.031250s system = 2.640625s CPU (127.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20491 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.402816s wall, 1.375000s user + 0.031250s system = 1.406250s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001095
+PHY-3002 : Step(216): len = 659367, overlap = 250.031
+PHY-3002 : Step(217): len = 660268, overlap = 207.625
+PHY-3002 : Step(218): len = 652456, overlap = 198.5
+PHY-3002 : Step(219): len = 647816, overlap = 171.844
+PHY-3002 : Step(220): len = 643973, overlap = 162.594
+PHY-3002 : Step(221): len = 639500, overlap = 151.844
+PHY-3002 : Step(222): len = 637172, overlap = 149.656
+PHY-3002 : Step(223): len = 634478, overlap = 151.75
+PHY-3002 : Step(224): len = 632242, overlap = 141.844
+PHY-3002 : Step(225): len = 629869, overlap = 139.125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000219
+PHY-3002 : Step(226): len = 630438, overlap = 137.469
+PHY-3002 : Step(227): len = 631438, overlap = 136.438
+PHY-3002 : Step(228): len = 633478, overlap = 135.781
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000438
+PHY-3002 : Step(229): len = 639653, overlap = 125.531
+PHY-3002 : Step(230): len = 646673, overlap = 116.094
+PHY-3002 : Step(231): len = 652762, overlap = 108.812
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000876001
+PHY-3002 : Step(232): len = 655041, overlap = 104.656
+PHY-3002 : Step(233): len = 659988, overlap = 94.4062
+PHY-3002 : Step(234): len = 667764, overlap = 85.0312
+PHY-3002 : Step(235): len = 671413, overlap = 80.125
+PHY-3002 : Step(236): len = 671074, overlap = 74.7812
+PHY-3002 : Step(237): len = 670576, overlap = 70.8125
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84467, tnet num: 20491, tinst num: 18090, tnode num: 115022, tedge num: 134702.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.566342s wall, 1.468750s user + 0.093750s system = 1.562500s CPU (99.8%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 565 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 366.69 peak overflow 2.28
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1099/20669.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 767528, over cnt = 3149(8%), over = 11300, worst = 31
+PHY-1001 : End global iterations; 1.402536s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (142.6%)
+
+PHY-1001 : Congestion index: top1 = 71.16, top5 = 58.57, top10 = 52.33, top15 = 48.49.
+PHY-1001 : End incremental global routing; 1.770473s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (133.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20491 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.204734s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (99.9%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17959 has valid locations, 296 needs to be replaced
+PHY-3001 : design contains 18340 instances, 7800 luts, 9319 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6152 pins
+PHY-3001 : Found 1271 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 693240
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17195/20919.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 781400, over cnt = 3181(9%), over = 11337, worst = 31
+PHY-1001 : End global iterations; 0.262616s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (124.9%)
+
+PHY-1001 : Congestion index: top1 = 70.93, top5 = 58.52, top10 = 52.51, top15 = 48.80.
+PHY-3001 : End congestion estimation; 0.555274s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (112.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85461, tnet num: 20741, tinst num: 18340, tnode num: 116483, tedge num: 136190.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.582118s wall, 1.515625s user + 0.062500s system = 1.578125s CPU (99.7%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 627 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20741 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.084841s wall, 3.015625s user + 0.062500s system = 3.078125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(238): len = 692162, overlap = 0
+PHY-3002 : Step(239): len = 691699, overlap = 0
+PHY-3002 : Step(240): len = 691443, overlap = 0
+PHY-3002 : Step(241): len = 691237, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17278/20919.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 778752, over cnt = 3164(8%), over = 11375, worst = 31
+PHY-1001 : End global iterations; 0.212992s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (154.1%)
+
+PHY-1001 : Congestion index: top1 = 71.59, top5 = 58.91, top10 = 52.76, top15 = 48.96.
+PHY-3001 : End congestion estimation; 0.504170s wall, 0.593750s user + 0.015625s system = 0.609375s CPU (120.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20741 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.293606s wall, 1.250000s user + 0.046875s system = 1.296875s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000455051
+PHY-3002 : Step(242): len = 691119, overlap = 73.125
+PHY-3002 : Step(243): len = 691261, overlap = 73.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000910103
+PHY-3002 : Step(244): len = 691231, overlap = 72.7188
+PHY-3002 : Step(245): len = 691700, overlap = 73.3438
+PHY-3001 : Final: Len = 691700, Over = 73.3438
+PHY-3001 : End incremental placement; 6.188592s wall, 6.296875s user + 0.265625s system = 6.562500s CPU (106.0%)
+
+OPT-1001 : Total overflow 373.03 peak overflow 2.28
+OPT-1001 : End high-fanout net optimization; 9.748097s wall, 10.515625s user + 0.328125s system = 10.843750s CPU (111.2%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 711, peak = 734.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17225/20919.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 781528, over cnt = 3132(8%), over = 10408, worst = 31
+PHY-1002 : len = 834864, over cnt = 2087(5%), over = 5180, worst = 17
+PHY-1002 : len = 870592, over cnt = 1043(2%), over = 2322, worst = 15
+PHY-1002 : len = 895696, over cnt = 274(0%), over = 533, worst = 10
+PHY-1002 : len = 904520, over cnt = 21(0%), over = 45, worst = 7
+PHY-1001 : End global iterations; 2.080517s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 58.75, top5 = 51.56, top10 = 47.87, top15 = 45.47.
+OPT-1001 : End congestion update; 2.390780s wall, 3.140625s user + 0.015625s system = 3.156250s CPU (132.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20741 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.872500s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (98.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 113 cells processed and 20300 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 52 cells processed and 8282 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 750 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 150 slack improved
+OPT-1001 : End bottleneck based optimization; 3.740305s wall, 4.468750s user + 0.031250s system = 4.500000s CPU (120.3%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 695, peak = 734.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17260/20921.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905680, over cnt = 105(0%), over = 156, worst = 7
+PHY-1002 : len = 905720, over cnt = 80(0%), over = 100, worst = 6
+PHY-1002 : len = 906296, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 906504, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 906840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.837073s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 57.05, top5 = 51.05, top10 = 47.65, top15 = 45.31.
+OPT-1001 : End congestion update; 1.139542s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20743 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.867179s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.1%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 23 cells processed and 3550 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.154654s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (100.8%)
+
+OPT-1001 : Current memory(MB): used = 706, reserve = 701, peak = 734.
+OPT-1001 : End physical optimization; 17.554909s wall, 19.062500s user + 0.453125s system = 19.515625s CPU (111.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7800 LUT to BLE ...
+SYN-4008 : Packed 7800 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6174 remaining SEQ's ...
+SYN-4005 : Packed 4087 SEQ with LUT/SLICE
+SYN-4006 : 863 single LUT's are left
+SYN-4006 : 2087 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9887/13674 primitive instances ...
+PHY-3001 : End packing; 1.869164s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6681 instances
+RUN-1001 : 3267 mslices, 3266 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17907 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10029 nets have 2 pins
+RUN-1001 : 6530 nets have [3 - 5] pins
+RUN-1001 : 717 nets have [6 - 10] pins
+RUN-1001 : 300 nets have [11 - 20] pins
+RUN-1001 : 299 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6679 instances, 6533 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3545 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 702246, Over = 211.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7616/17907.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853320, over cnt = 2024(5%), over = 3257, worst = 8
+PHY-1002 : len = 860520, over cnt = 1364(3%), over = 1931, worst = 6
+PHY-1002 : len = 874824, over cnt = 505(1%), over = 681, worst = 6
+PHY-1002 : len = 883312, over cnt = 120(0%), over = 164, worst = 6
+PHY-1002 : len = 886832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.804336s wall, 2.421875s user + 0.031250s system = 2.453125s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 57.95, top5 = 51.21, top10 = 47.48, top15 = 45.01.
+PHY-3001 : End congestion estimation; 2.254887s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (128.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71591, tnet num: 17729, tinst num: 6679, tnode num: 93974, tedge num: 119002.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.746698s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.2%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 615 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17729 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.678746s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.0646e-05
+PHY-3002 : Step(246): len = 689450, overlap = 216.75
+PHY-3002 : Step(247): len = 682419, overlap = 222.5
+PHY-3002 : Step(248): len = 676686, overlap = 217.5
+PHY-3002 : Step(249): len = 672475, overlap = 220.5
+PHY-3002 : Step(250): len = 668566, overlap = 219.25
+PHY-3002 : Step(251): len = 665189, overlap = 224
+PHY-3002 : Step(252): len = 662337, overlap = 222.75
+PHY-3002 : Step(253): len = 660000, overlap = 223.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000121292
+PHY-3002 : Step(254): len = 663423, overlap = 218.25
+PHY-3002 : Step(255): len = 667737, overlap = 207
+PHY-3002 : Step(256): len = 668298, overlap = 208
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000242584
+PHY-3002 : Step(257): len = 674985, overlap = 203.5
+PHY-3002 : Step(258): len = 681485, overlap = 197.25
+PHY-3002 : Step(259): len = 680791, overlap = 198.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.425825s wall, 0.421875s user + 0.656250s system = 1.078125s CPU (253.2%)
+
+PHY-3001 : Trial Legalized: Len = 764254
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 833/17907.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 875496, over cnt = 2758(7%), over = 4641, worst = 9
+PHY-1002 : len = 895536, over cnt = 1604(4%), over = 2266, worst = 6
+PHY-1002 : len = 913464, over cnt = 646(1%), over = 901, worst = 5
+PHY-1002 : len = 921664, over cnt = 266(0%), over = 360, worst = 5
+PHY-1002 : len = 928480, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.826833s wall, 4.031250s user + 0.015625s system = 4.046875s CPU (143.2%)
+
+PHY-1001 : Congestion index: top1 = 57.72, top5 = 51.63, top10 = 48.17, top15 = 45.91.
+PHY-3001 : End congestion estimation; 3.354961s wall, 4.562500s user + 0.015625s system = 4.578125s CPU (136.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17729 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.935439s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165542
+PHY-3002 : Step(260): len = 736861, overlap = 41
+PHY-3002 : Step(261): len = 720343, overlap = 67.5
+PHY-3002 : Step(262): len = 706102, overlap = 90.25
+PHY-3002 : Step(263): len = 697763, overlap = 105.25
+PHY-3002 : Step(264): len = 691893, overlap = 123
+PHY-3002 : Step(265): len = 688386, overlap = 138.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000331084
+PHY-3002 : Step(266): len = 692374, overlap = 137.25
+PHY-3002 : Step(267): len = 696210, overlap = 136
+PHY-3002 : Step(268): len = 696487, overlap = 135.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000662169
+PHY-3002 : Step(269): len = 699588, overlap = 133.5
+PHY-3002 : Step(270): len = 706993, overlap = 124.5
+PHY-3002 : Step(271): len = 710954, overlap = 123.75
+PHY-3002 : Step(272): len = 712623, overlap = 129.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.036923s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (127.0%)
+
+PHY-3001 : Legalized: Len = 738802, Over = 0
+PHY-3001 : Spreading special nets. 448 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.106261s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (102.9%)
+
+PHY-3001 : 654 instances has been re-located, deltaX = 198, deltaY = 391, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 748895, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71591, tnet num: 17729, tinst num: 6682, tnode num: 93974, tedge num: 119002.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.983651s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (100.0%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 647 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4084/17907.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 875328, over cnt = 2574(7%), over = 4114, worst = 6
+PHY-1002 : len = 888712, over cnt = 1570(4%), over = 2238, worst = 6
+PHY-1002 : len = 905888, over cnt = 651(1%), over = 908, worst = 6
+PHY-1002 : len = 916144, over cnt = 226(0%), over = 305, worst = 5
+PHY-1002 : len = 921424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.117418s wall, 3.281250s user + 0.015625s system = 3.296875s CPU (155.7%)
+
+PHY-1001 : Congestion index: top1 = 57.05, top5 = 50.49, top10 = 47.23, top15 = 45.03.
+PHY-1001 : End incremental global routing; 2.536275s wall, 3.703125s user + 0.015625s system = 3.718750s CPU (146.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17729 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.941987s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.5%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6589 has valid locations, 34 needs to be replaced
+PHY-3001 : design contains 6711 instances, 6562 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3609 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 754079
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16342/17935.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928488, over cnt = 126(0%), over = 153, worst = 4
+PHY-1002 : len = 928232, over cnt = 85(0%), over = 94, worst = 3
+PHY-1002 : len = 929152, over cnt = 25(0%), over = 27, worst = 2
+PHY-1002 : len = 929416, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 929656, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.943103s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 57.03, top5 = 50.65, top10 = 47.44, top15 = 45.25.
+PHY-3001 : End congestion estimation; 1.301344s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (104.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71818, tnet num: 17757, tinst num: 6711, tnode num: 94246, tedge num: 119282.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.020852s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (99.7%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 666 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17757 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.977259s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(273): len = 752956, overlap = 0.5
+PHY-3002 : Step(274): len = 752532, overlap = 0.75
+PHY-3002 : Step(275): len = 752012, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16332/17935.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 925256, over cnt = 72(0%), over = 97, worst = 4
+PHY-1002 : len = 925312, over cnt = 46(0%), over = 53, worst = 3
+PHY-1002 : len = 925704, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 925976, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 926040, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.875149s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (107.1%)
+
+PHY-1001 : Congestion index: top1 = 57.13, top5 = 50.54, top10 = 47.35, top15 = 45.15.
+PHY-3001 : End congestion estimation; 1.224585s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (105.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17757 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.976181s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000178448
+PHY-3002 : Step(276): len = 752071, overlap = 2.75
+PHY-3002 : Step(277): len = 752171, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.008512s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 752248, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065597s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.3%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 2, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 752436, Over = 0
+PHY-3001 : End incremental placement; 7.019532s wall, 7.125000s user + 0.156250s system = 7.281250s CPU (103.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.033381s wall, 12.421875s user + 0.171875s system = 12.593750s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16299/17935.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926536, over cnt = 76(0%), over = 93, worst = 5
+PHY-1002 : len = 926712, over cnt = 39(0%), over = 43, worst = 2
+PHY-1002 : len = 926976, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 927120, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 927232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.843048s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 57.11, top5 = 50.48, top10 = 47.31, top15 = 45.17.
+OPT-1001 : End congestion update; 1.190719s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (102.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17757 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.764830s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.1%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6623 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6711 instances, 6562 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3609 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 758521, Over = 0
+PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065644s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.2%)
+
+PHY-3001 : 31 instances has been re-located, deltaX = 14, deltaY = 24, maxDist = 2.
+PHY-3001 : Final: Len = 759225, Over = 0
+PHY-3001 : End incremental legalization; 0.428564s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 61 cells processed and 19303 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6623 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6711 instances, 6562 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3609 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 760345, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064516s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.9%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 13, deltaY = 6, maxDist = 3.
+PHY-3001 : Final: Len = 760569, Over = 0
+PHY-3001 : End incremental legalization; 0.411957s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (121.4%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 4233 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6623 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6711 instances, 6562 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3609 pins
+PHY-3001 : Found 498 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 760417, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065440s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.5%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 760447, Over = 0
+PHY-3001 : End incremental legalization; 0.420939s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (100.2%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 6 cells processed and 350 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6626 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6714 instances, 6565 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3610 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 760605, Over = 0
+PHY-3001 : End spreading; 0.063682s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (122.7%)
+
+PHY-3001 : Final: Len = 760605, Over = 0
+PHY-3001 : End incremental legalization; 0.416043s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.6%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 3 cells processed and 404 slack improved
+OPT-1001 : End bottleneck based optimization; 4.228870s wall, 4.453125s user + 0.046875s system = 4.500000s CPU (106.4%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16002/17938.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934504, over cnt = 206(0%), over = 250, worst = 5
+PHY-1002 : len = 934576, over cnt = 111(0%), over = 119, worst = 3
+PHY-1002 : len = 935112, over cnt = 69(0%), over = 73, worst = 2
+PHY-1002 : len = 935712, over cnt = 27(0%), over = 29, worst = 2
+PHY-1002 : len = 936272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.970272s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (103.1%)
+
+PHY-1001 : Congestion index: top1 = 56.75, top5 = 50.59, top10 = 47.29, top15 = 45.16.
+OPT-1001 : End congestion update; 1.338834s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (102.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17760 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.778997s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.3%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6626 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6714 instances, 6565 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3610 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 761111, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065137s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.0%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 12, deltaY = 8, maxDist = 4.
+PHY-3001 : Final: Len = 761347, Over = 0
+PHY-3001 : End incremental legalization; 0.418523s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.8%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 2446 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.738015s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (101.6%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17760 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.783932s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16283/17938.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 936560, over cnt = 65(0%), over = 72, worst = 5
+PHY-1002 : len = 936632, over cnt = 32(0%), over = 34, worst = 2
+PHY-1002 : len = 936848, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 936920, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 936936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.883984s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 56.92, top5 = 50.68, top10 = 47.31, top15 = 45.16.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17760 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.775923s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 56.551724
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 23.060699s wall, 24.750000s user + 0.265625s system = 25.015625s CPU (108.5%)
+
+RUN-1003 : finish command "place" in 71.827423s wall, 100.406250s user + 6.046875s system = 106.453125s CPU (148.2%)
+
+RUN-1004 : used memory is 605 MB, reserved memory is 597 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.824647s wall, 3.078125s user + 0.031250s system = 3.109375s CPU (170.4%)
+
+RUN-1004 : used memory is 606 MB, reserved memory is 599 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6716 instances
+RUN-1001 : 3287 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17938 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10026 nets have 2 pins
+RUN-1001 : 6535 nets have [3 - 5] pins
+RUN-1001 : 725 nets have [6 - 10] pins
+RUN-1001 : 312 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71852, tnet num: 17760, tinst num: 6714, tnode num: 94292, tedge num: 119333.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.709272s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.6%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 626 MB, peak memory is 740 MB
+PHY-1001 : 3287 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17760 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863440, over cnt = 2756(7%), over = 4531, worst = 7
+PHY-1002 : len = 884400, over cnt = 1507(4%), over = 2098, worst = 7
+PHY-1002 : len = 900416, over cnt = 610(1%), over = 866, worst = 6
+PHY-1002 : len = 914384, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 914672, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.541747s wall, 4.562500s user + 0.000000s system = 4.562500s CPU (128.8%)
+
+PHY-1001 : Congestion index: top1 = 56.44, top5 = 50.31, top10 = 46.86, top15 = 44.54.
+PHY-1001 : End global routing; 3.934689s wall, 4.968750s user + 0.000000s system = 4.968750s CPU (126.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 711, reserve = 712, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 983, peak = 982.
+PHY-1001 : End build detailed router design. 4.349318s wall, 4.281250s user + 0.078125s system = 4.359375s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266000, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.120923s wall, 6.109375s user + 0.000000s system = 6.109375s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266056, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.508937s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.3%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1020, peak = 1018.
+PHY-1001 : End phase 1; 6.642828s wall, 6.640625s user + 0.000000s system = 6.640625s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.2737e+06, over cnt = 1736(0%), over = 1753, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1037, peak = 1036.
+PHY-1001 : End initial routed; 34.078210s wall, 70.187500s user + 0.296875s system = 70.484375s CPU (206.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 34/16861(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.222 | -1.883 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.517799s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1049, reserve = 1050, peak = 1049.
+PHY-1001 : End phase 2; 37.596076s wall, 73.703125s user + 0.296875s system = 74.000000s CPU (196.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 15 pins with SWNS -0.762ns STNS -1.423ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.182511s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.7%)
+
+PHY-1022 : len = 2.27378e+06, over cnt = 1751(0%), over = 1768, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.481252s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2445e+06, over cnt = 654(0%), over = 655, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.570106s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (162.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.24134e+06, over cnt = 120(0%), over = 120, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.846925s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (134.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2416e+06, over cnt = 15(0%), over = 15, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.533797s wall, 0.609375s user + 0.046875s system = 0.656250s CPU (122.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.24197e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.265365s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (106.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.24202e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.221018s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.24202e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.285625s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (98.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.24202e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.455971s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.24202e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.187439s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (116.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.24198e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.192246s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 33/16861(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.762 | -1.423 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.552470s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (99.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 537 feed throughs used by 419 nets
+PHY-1001 : End commit to database; 2.382887s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (99.0%)
+
+PHY-1001 : Current memory(MB): used = 1148, reserve = 1154, peak = 1148.
+PHY-1001 : End phase 3; 11.429637s wall, 12.765625s user + 0.062500s system = 12.828125s CPU (112.2%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.750ns STNS -1.411ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.176991s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.1%)
+
+PHY-1022 : len = 2.24195e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.448499s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.750ns, -1.411ns, 2}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.24195e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.175301s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.24195e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.173545s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 33/16861(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.750 | -1.411 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.487801s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 538 feed throughs used by 420 nets
+PHY-1001 : End commit to database; 2.473767s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1164, peak = 1158.
+PHY-1001 : End phase 4; 6.813279s wall, 6.812500s user + 0.000000s system = 6.812500s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.24195e+06
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1168, peak = 1162.
+PHY-1001 : End export database. 0.064467s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.9%)
+
+PHY-1001 : End detail routing; 67.314792s wall, 104.687500s user + 0.437500s system = 105.125000s CPU (156.2%)
+
+RUN-1003 : finish command "route" in 74.139735s wall, 112.531250s user + 0.453125s system = 112.984375s CPU (152.4%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1093 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10238 out of 19600 52.23%
+#reg 9508 out of 19600 48.51%
+#le 12293
+ #lut only 2785 out of 12293 22.66%
+ #reg only 2055 out of 12293 16.72%
+ #lut® 7453 out of 12293 60.63%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1783
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1407
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1300
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 935
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice a_frame_pad_d0_reg_syn_17.q0 136
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg4_syn_186.f1 3
+#11 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg_sdi_n_syn_124.f0 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P19 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P136 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P16 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P147 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P140 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P17 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P11 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P148 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12293 |9211 |1027 |9540 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |522 |420 |23 |444 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |96 |83 |4 |87 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |18 |0 |0 |
+| U_ecc_gen |ecc_gen |12 |12 |0 |9 |0 |0 |
+| exdev_ctl_a |exdev_ctl |755 |426 |96 |565 |0 |0 |
+| u_ADconfig |AD_config |186 |144 |25 |136 |0 |0 |
+| u_gen_sp |gen_sp |264 |146 |71 |124 |0 |0 |
+| exdev_ctl_b |exdev_ctl |745 |399 |96 |559 |0 |0 |
+| u_ADconfig |AD_config |170 |124 |25 |129 |0 |0 |
+| u_gen_sp |gen_sp |270 |184 |71 |125 |0 |0 |
+| sampling_fe_a |sampling_fe |2921 |2398 |306 |2063 |25 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |197 |140 |17 |164 |0 |0 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_sort |sort |2688 |2240 |289 |1863 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2257 |1877 |253 |1505 |22 |0 |
+| channelPart |channel_part_8478 |142 |137 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |64 |55 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1741 |1439 |197 |1106 |0 |0 |
+| adc_addr_gen |adc_addr_gen |238 |207 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |15 |8 |3 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |40 |37 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |15 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| insert |insert |939 |668 |170 |642 |0 |0 |
+| ram_switch_state |ram_switch_state |564 |564 |0 |341 |0 |0 |
+| read_ram_i |read_ram |279 |220 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |231 |191 |40 |154 |0 |0 |
+| read_ram_data |read_ram_data |45 |26 |4 |33 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |298 |240 |36 |266 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3192 |2475 |349 |2099 |25 |1 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |182 |94 |17 |152 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u_sort |sort_rev |2979 |2360 |332 |1916 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2557 |2044 |290 |1552 |22 |1 |
+| channelPart |channel_part_8478 |152 |145 |3 |135 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1964 |1576 |197 |1140 |0 |0 |
+| adc_addr_gen |adc_addr_gen |198 |171 |27 |100 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| insert |insert |972 |615 |170 |689 |0 |0 |
+| ram_switch_state |ram_switch_state |794 |790 |0 |351 |0 |0 |
+| read_ram_i |read_ram_rev |356 |257 |81 |206 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |300 |217 |73 |166 |0 |0 |
+| read_ram_data |read_ram_data_rev |56 |40 |8 |40 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9964
+ #2 2 4286
+ #3 3 1688
+ #4 4 558
+ #5 5-10 769
+ #6 11-50 566
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.172611s wall, 3.750000s user + 0.031250s system = 3.781250s CPU (174.0%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1094 MB, peak memory is 1162 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71852, tnet num: 17760, tinst num: 6714, tnode num: 94292, tedge num: 119333.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.707738s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.7%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1098 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17760 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.577607s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.0%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1101 MB, peak memory is 1162 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6714
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17938, pip num: 167961
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 538
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 468879 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit" in 9.612462s wall, 62.359375s user + 0.312500s system = 62.671875s CPU (652.0%)
+
+RUN-1004 : used memory is 1252 MB, reserved memory is 1255 MB, peak memory is 1368 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_105319.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_110956.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_110956.log
new file mode 100644
index 0000000..994b428
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_110956.log
@@ -0,0 +1,258 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 11:09:56 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 538 feed throughs used by 420 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db hg_anlogic_pr.db" in 12.576825s wall, 12.328125s user + 0.203125s system = 12.531250s CPU (99.6%)
+
+RUN-1004 : used memory is 793 MB, reserved memory is 787 MB, peak memory is 819 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6714
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17938, pip num: 167961
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 538
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 468879 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.847542s wall, 62.078125s user + 0.312500s system = 62.390625s CPU (633.6%)
+
+RUN-1004 : used memory is 817 MB, reserved memory is 821 MB, peak memory is 1085 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_110956.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_112242.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_112242.log
new file mode 100644
index 0000000..803faab
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_112242.log
@@ -0,0 +1,3506 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 11:22:42 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.321210s wall, 2.171875s user + 0.156250s system = 2.328125s CPU (100.3%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18150 instances
+RUN-0007 : 7700 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20727 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13212 nets have 2 pins
+RUN-1001 : 6477 nets have [3 - 5] pins
+RUN-1001 : 611 nets have [6 - 10] pins
+RUN-1001 : 187 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18148 instances, 7700 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6098 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84699, tnet num: 20549, tinst num: 18148, tnode num: 115428, tedge num: 135050.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.296757s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (96.4%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 517 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.186926s wall, 2.109375s user + 0.031250s system = 2.140625s CPU (97.9%)
+
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.16241e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18148.
+PHY-3001 : Level 1 #clusters 2003.
+PHY-3001 : End clustering; 0.295504s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (126.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.3511e+06, overlap = 464.875
+PHY-3002 : Step(2): len = 1.25006e+06, overlap = 530.781
+PHY-3002 : Step(3): len = 848517, overlap = 605.781
+PHY-3002 : Step(4): len = 777857, overlap = 648.562
+PHY-3002 : Step(5): len = 587916, overlap = 785.75
+PHY-3002 : Step(6): len = 536956, overlap = 844.281
+PHY-3002 : Step(7): len = 449404, overlap = 960.438
+PHY-3002 : Step(8): len = 418305, overlap = 988.656
+PHY-3002 : Step(9): len = 374886, overlap = 1045
+PHY-3002 : Step(10): len = 354128, overlap = 1069.75
+PHY-3002 : Step(11): len = 310619, overlap = 1129.81
+PHY-3002 : Step(12): len = 297446, overlap = 1158.94
+PHY-3002 : Step(13): len = 260986, overlap = 1190.25
+PHY-3002 : Step(14): len = 252064, overlap = 1214.78
+PHY-3002 : Step(15): len = 221940, overlap = 1244.75
+PHY-3002 : Step(16): len = 212662, overlap = 1271.28
+PHY-3002 : Step(17): len = 192114, overlap = 1303.31
+PHY-3002 : Step(18): len = 181579, overlap = 1356.41
+PHY-3002 : Step(19): len = 164486, overlap = 1398.38
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2753e-06
+PHY-3002 : Step(20): len = 167990, overlap = 1343.91
+PHY-3002 : Step(21): len = 204975, overlap = 1290.25
+PHY-3002 : Step(22): len = 207507, overlap = 1177.31
+PHY-3002 : Step(23): len = 208921, overlap = 1134.16
+PHY-3002 : Step(24): len = 206785, overlap = 1118.72
+PHY-3002 : Step(25): len = 205828, overlap = 1065.78
+PHY-3002 : Step(26): len = 200483, overlap = 1045.09
+PHY-3002 : Step(27): len = 198999, overlap = 1027.53
+PHY-3002 : Step(28): len = 196750, overlap = 1030.44
+PHY-3002 : Step(29): len = 195020, overlap = 1047.5
+PHY-3002 : Step(30): len = 191761, overlap = 1041.75
+PHY-3002 : Step(31): len = 189435, overlap = 1028.03
+PHY-3002 : Step(32): len = 187135, overlap = 1018.44
+PHY-3002 : Step(33): len = 186702, overlap = 1008.25
+PHY-3002 : Step(34): len = 184245, overlap = 1010.69
+PHY-3002 : Step(35): len = 182416, overlap = 1005.22
+PHY-3002 : Step(36): len = 180580, overlap = 1004.38
+PHY-3002 : Step(37): len = 180449, overlap = 1003.47
+PHY-3002 : Step(38): len = 178981, overlap = 1006.78
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.55061e-06
+PHY-3002 : Step(39): len = 185543, overlap = 1002.41
+PHY-3002 : Step(40): len = 198977, overlap = 946.594
+PHY-3002 : Step(41): len = 205206, overlap = 901.469
+PHY-3002 : Step(42): len = 210994, overlap = 916.719
+PHY-3002 : Step(43): len = 212459, overlap = 924.406
+PHY-3002 : Step(44): len = 212810, overlap = 891.969
+PHY-3002 : Step(45): len = 211065, overlap = 881.875
+PHY-3002 : Step(46): len = 210368, overlap = 887.625
+PHY-3002 : Step(47): len = 208642, overlap = 903.375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.10122e-06
+PHY-3002 : Step(48): len = 217835, overlap = 884.312
+PHY-3002 : Step(49): len = 234646, overlap = 831.781
+PHY-3002 : Step(50): len = 243506, overlap = 797.031
+PHY-3002 : Step(51): len = 249838, overlap = 809.562
+PHY-3002 : Step(52): len = 250862, overlap = 782.375
+PHY-3002 : Step(53): len = 253331, overlap = 754.656
+PHY-3002 : Step(54): len = 251714, overlap = 746.5
+PHY-3002 : Step(55): len = 251409, overlap = 740.844
+PHY-3002 : Step(56): len = 250429, overlap = 732.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.02024e-05
+PHY-3002 : Step(57): len = 263249, overlap = 668.906
+PHY-3002 : Step(58): len = 278700, overlap = 605.906
+PHY-3002 : Step(59): len = 288290, overlap = 560.625
+PHY-3002 : Step(60): len = 294352, overlap = 536.469
+PHY-3002 : Step(61): len = 295508, overlap = 520
+PHY-3002 : Step(62): len = 296901, overlap = 514.875
+PHY-3002 : Step(63): len = 295249, overlap = 512.562
+PHY-3002 : Step(64): len = 294902, overlap = 516.656
+PHY-3002 : Step(65): len = 295773, overlap = 529.156
+PHY-3002 : Step(66): len = 295278, overlap = 529.156
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.04049e-05
+PHY-3002 : Step(67): len = 311707, overlap = 517.25
+PHY-3002 : Step(68): len = 323678, overlap = 497.844
+PHY-3002 : Step(69): len = 329488, overlap = 458.719
+PHY-3002 : Step(70): len = 334006, overlap = 426.594
+PHY-3002 : Step(71): len = 334851, overlap = 420.406
+PHY-3002 : Step(72): len = 337118, overlap = 398.469
+PHY-3002 : Step(73): len = 334336, overlap = 388
+PHY-3002 : Step(74): len = 334844, overlap = 378.656
+PHY-3002 : Step(75): len = 335317, overlap = 379.75
+PHY-3002 : Step(76): len = 336764, overlap = 376.656
+PHY-3002 : Step(77): len = 335776, overlap = 373.156
+PHY-3002 : Step(78): len = 336890, overlap = 376.594
+PHY-3002 : Step(79): len = 337382, overlap = 376.781
+PHY-3002 : Step(80): len = 335994, overlap = 373.031
+PHY-3002 : Step(81): len = 335500, overlap = 394.062
+PHY-3002 : Step(82): len = 335423, overlap = 401.031
+PHY-3002 : Step(83): len = 336745, overlap = 389.062
+PHY-3002 : Step(84): len = 335001, overlap = 391.094
+PHY-3002 : Step(85): len = 334838, overlap = 379.406
+PHY-3002 : Step(86): len = 334196, overlap = 369.656
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.08097e-05
+PHY-3002 : Step(87): len = 349676, overlap = 332.5
+PHY-3002 : Step(88): len = 364330, overlap = 312.438
+PHY-3002 : Step(89): len = 368076, overlap = 302.875
+PHY-3002 : Step(90): len = 369744, overlap = 299.344
+PHY-3002 : Step(91): len = 369271, overlap = 282.812
+PHY-3002 : Step(92): len = 370142, overlap = 279.25
+PHY-3002 : Step(93): len = 369398, overlap = 294.125
+PHY-3002 : Step(94): len = 370814, overlap = 313.625
+PHY-3002 : Step(95): len = 372868, overlap = 299.562
+PHY-3002 : Step(96): len = 374799, overlap = 303.438
+PHY-3002 : Step(97): len = 374978, overlap = 297.062
+PHY-3002 : Step(98): len = 376656, overlap = 293.75
+PHY-3002 : Step(99): len = 377345, overlap = 308.469
+PHY-3002 : Step(100): len = 378840, overlap = 314.25
+PHY-3002 : Step(101): len = 379028, overlap = 317.875
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.16195e-05
+PHY-3002 : Step(102): len = 395131, overlap = 287.344
+PHY-3002 : Step(103): len = 407152, overlap = 266.031
+PHY-3002 : Step(104): len = 404549, overlap = 261.75
+PHY-3002 : Step(105): len = 405161, overlap = 264.5
+PHY-3002 : Step(106): len = 407533, overlap = 253.219
+PHY-3002 : Step(107): len = 410567, overlap = 249
+PHY-3002 : Step(108): len = 407301, overlap = 252.594
+PHY-3002 : Step(109): len = 408018, overlap = 265.125
+PHY-3002 : Step(110): len = 410351, overlap = 257.375
+PHY-3002 : Step(111): len = 413005, overlap = 256.031
+PHY-3002 : Step(112): len = 409675, overlap = 246.938
+PHY-3002 : Step(113): len = 409996, overlap = 245.156
+PHY-3002 : Step(114): len = 410993, overlap = 229.188
+PHY-3002 : Step(115): len = 411724, overlap = 234
+PHY-3002 : Step(116): len = 409764, overlap = 235.938
+PHY-3002 : Step(117): len = 410187, overlap = 239.906
+PHY-3002 : Step(118): len = 411073, overlap = 236.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000163239
+PHY-3002 : Step(119): len = 425009, overlap = 234.781
+PHY-3002 : Step(120): len = 433907, overlap = 218.031
+PHY-3002 : Step(121): len = 435218, overlap = 208.938
+PHY-3002 : Step(122): len = 436803, overlap = 203.906
+PHY-3002 : Step(123): len = 438020, overlap = 205
+PHY-3002 : Step(124): len = 440283, overlap = 196.875
+PHY-3002 : Step(125): len = 439783, overlap = 192.844
+PHY-3002 : Step(126): len = 441558, overlap = 189
+PHY-3002 : Step(127): len = 444515, overlap = 186.375
+PHY-3002 : Step(128): len = 446315, overlap = 187
+PHY-3002 : Step(129): len = 444953, overlap = 188.75
+PHY-3002 : Step(130): len = 445300, overlap = 189.25
+PHY-3002 : Step(131): len = 446662, overlap = 193.75
+PHY-3002 : Step(132): len = 448402, overlap = 191.188
+PHY-3002 : Step(133): len = 446644, overlap = 196.281
+PHY-3002 : Step(134): len = 446065, overlap = 201.75
+PHY-3002 : Step(135): len = 447087, overlap = 199.281
+PHY-3002 : Step(136): len = 448380, overlap = 200.75
+PHY-3002 : Step(137): len = 447604, overlap = 209.812
+PHY-3002 : Step(138): len = 448028, overlap = 217.281
+PHY-3002 : Step(139): len = 448426, overlap = 222.438
+PHY-3002 : Step(140): len = 448612, overlap = 223.781
+PHY-3002 : Step(141): len = 447348, overlap = 233.562
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000310482
+PHY-3002 : Step(142): len = 456065, overlap = 218.875
+PHY-3002 : Step(143): len = 462882, overlap = 210.031
+PHY-3002 : Step(144): len = 462446, overlap = 202.25
+PHY-3002 : Step(145): len = 462921, overlap = 204.5
+PHY-3002 : Step(146): len = 465571, overlap = 199.875
+PHY-3002 : Step(147): len = 466958, overlap = 201.531
+PHY-3002 : Step(148): len = 467019, overlap = 199.031
+PHY-3002 : Step(149): len = 467383, overlap = 197.281
+PHY-3002 : Step(150): len = 468286, overlap = 196.219
+PHY-3002 : Step(151): len = 468688, overlap = 194.781
+PHY-3002 : Step(152): len = 468341, overlap = 202.312
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000560161
+PHY-3002 : Step(153): len = 475086, overlap = 190.594
+PHY-3002 : Step(154): len = 480933, overlap = 184.781
+PHY-3002 : Step(155): len = 480948, overlap = 183.312
+PHY-3002 : Step(156): len = 481228, overlap = 182.906
+PHY-3002 : Step(157): len = 484234, overlap = 176.344
+PHY-3002 : Step(158): len = 488078, overlap = 171.438
+PHY-3002 : Step(159): len = 488683, overlap = 163.656
+PHY-3002 : Step(160): len = 489485, overlap = 162.406
+PHY-3002 : Step(161): len = 490658, overlap = 163.906
+PHY-3002 : Step(162): len = 491403, overlap = 161.812
+PHY-3002 : Step(163): len = 490664, overlap = 161.625
+PHY-3002 : Step(164): len = 490542, overlap = 162.031
+PHY-3002 : Step(165): len = 491569, overlap = 163.562
+PHY-3002 : Step(166): len = 492065, overlap = 166.594
+PHY-3002 : Step(167): len = 491508, overlap = 161.969
+PHY-3002 : Step(168): len = 491709, overlap = 162.812
+PHY-3002 : Step(169): len = 493291, overlap = 161.688
+PHY-3002 : Step(170): len = 494344, overlap = 163.875
+PHY-3002 : Step(171): len = 493309, overlap = 163.688
+PHY-3002 : Step(172): len = 493166, overlap = 164.531
+PHY-3002 : Step(173): len = 493646, overlap = 164.938
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00103178
+PHY-3002 : Step(174): len = 497282, overlap = 158.844
+PHY-3002 : Step(175): len = 502969, overlap = 158.344
+PHY-3002 : Step(176): len = 504605, overlap = 158.031
+PHY-3002 : Step(177): len = 505837, overlap = 157.031
+PHY-3002 : Step(178): len = 506931, overlap = 153.406
+PHY-3002 : Step(179): len = 507707, overlap = 147.562
+PHY-3002 : Step(180): len = 508336, overlap = 144.375
+PHY-3002 : Step(181): len = 508927, overlap = 139.875
+PHY-3002 : Step(182): len = 509823, overlap = 138.094
+PHY-3002 : Step(183): len = 510950, overlap = 140.562
+PHY-3002 : Step(184): len = 511601, overlap = 141.125
+PHY-3002 : Step(185): len = 511810, overlap = 144.281
+PHY-3002 : Step(186): len = 511792, overlap = 143.625
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00174525
+PHY-3002 : Step(187): len = 514558, overlap = 143.75
+PHY-3002 : Step(188): len = 519195, overlap = 142.406
+PHY-3002 : Step(189): len = 520240, overlap = 136.312
+PHY-3002 : Step(190): len = 521580, overlap = 138.031
+PHY-3002 : Step(191): len = 523778, overlap = 133.719
+PHY-3002 : Step(192): len = 525042, overlap = 135.156
+PHY-3002 : Step(193): len = 524839, overlap = 136.844
+PHY-3002 : Step(194): len = 524971, overlap = 136.125
+PHY-3002 : Step(195): len = 526073, overlap = 140.188
+PHY-3002 : Step(196): len = 526340, overlap = 138.219
+PHY-3002 : Step(197): len = 525972, overlap = 137.938
+PHY-3002 : Step(198): len = 525860, overlap = 137.094
+PHY-3002 : Step(199): len = 526581, overlap = 134.594
+PHY-3002 : Step(200): len = 527470, overlap = 134.312
+PHY-3002 : Step(201): len = 527063, overlap = 136.906
+PHY-3002 : Step(202): len = 527057, overlap = 136.281
+PHY-3002 : Step(203): len = 528063, overlap = 135.531
+PHY-3002 : Step(204): len = 529629, overlap = 136.281
+PHY-3002 : Step(205): len = 529618, overlap = 135.656
+PHY-3002 : Step(206): len = 529799, overlap = 135.188
+PHY-3002 : Step(207): len = 530688, overlap = 135.969
+PHY-3002 : Step(208): len = 531348, overlap = 135.969
+PHY-3002 : Step(209): len = 531608, overlap = 137.188
+PHY-3002 : Step(210): len = 531714, overlap = 136.906
+PHY-3002 : Step(211): len = 531868, overlap = 138.094
+PHY-3002 : Step(212): len = 531905, overlap = 138.531
+PHY-3002 : Step(213): len = 531632, overlap = 138.25
+PHY-3002 : Step(214): len = 531568, overlap = 138.75
+PHY-3002 : Step(215): len = 531812, overlap = 139.281
+PHY-3002 : Step(216): len = 532048, overlap = 140.781
+PHY-3002 : Step(217): len = 533038, overlap = 141.656
+PHY-3002 : Step(218): len = 534327, overlap = 140.438
+PHY-3002 : Step(219): len = 535206, overlap = 144.531
+PHY-3002 : Step(220): len = 535684, overlap = 143.906
+PHY-3002 : Step(221): len = 535508, overlap = 143.219
+PHY-3002 : Step(222): len = 535403, overlap = 143.219
+PHY-3002 : Step(223): len = 535288, overlap = 143.094
+PHY-3002 : Step(224): len = 535280, overlap = 141.094
+PHY-3002 : Step(225): len = 535116, overlap = 141.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.018332s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (170.5%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 711424, over cnt = 1618(4%), over = 7446, worst = 44
+PHY-1001 : End global iterations; 0.759229s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (142.0%)
+
+PHY-1001 : Congestion index: top1 = 85.62, top5 = 62.84, top10 = 53.02, top15 = 47.22.
+PHY-3001 : End congestion estimation; 1.006416s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (130.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.929102s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000133971
+PHY-3002 : Step(226): len = 650972, overlap = 81.625
+PHY-3002 : Step(227): len = 651769, overlap = 80.8438
+PHY-3002 : Step(228): len = 643464, overlap = 77.8438
+PHY-3002 : Step(229): len = 639612, overlap = 80.9062
+PHY-3002 : Step(230): len = 639032, overlap = 72.6875
+PHY-3002 : Step(231): len = 638929, overlap = 65.625
+PHY-3002 : Step(232): len = 636214, overlap = 58.6875
+PHY-3002 : Step(233): len = 633868, overlap = 54.5625
+PHY-3002 : Step(234): len = 629369, overlap = 52.8438
+PHY-3002 : Step(235): len = 627661, overlap = 52
+PHY-3002 : Step(236): len = 624390, overlap = 53.875
+PHY-3002 : Step(237): len = 623563, overlap = 54.0625
+PHY-3002 : Step(238): len = 624199, overlap = 56.1875
+PHY-3002 : Step(239): len = 623080, overlap = 54.25
+PHY-3002 : Step(240): len = 622922, overlap = 56.3125
+PHY-3002 : Step(241): len = 622468, overlap = 54.0312
+PHY-3002 : Step(242): len = 621257, overlap = 51.5625
+PHY-3002 : Step(243): len = 622059, overlap = 54.625
+PHY-3002 : Step(244): len = 621364, overlap = 54.0312
+PHY-3002 : Step(245): len = 620882, overlap = 55
+PHY-3002 : Step(246): len = 621375, overlap = 55.4062
+PHY-3002 : Step(247): len = 619613, overlap = 58.7812
+PHY-3002 : Step(248): len = 618992, overlap = 59.125
+PHY-3002 : Step(249): len = 618159, overlap = 60.9062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000267943
+PHY-3002 : Step(250): len = 620022, overlap = 58.9375
+PHY-3002 : Step(251): len = 623021, overlap = 57.7812
+PHY-3002 : Step(252): len = 628185, overlap = 58.1875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000528027
+PHY-3002 : Step(253): len = 637206, overlap = 58.7188
+PHY-3002 : Step(254): len = 651740, overlap = 58.3125
+PHY-3002 : Step(255): len = 659127, overlap = 56.2188
+PHY-3002 : Step(256): len = 667205, overlap = 54.375
+PHY-3002 : Step(257): len = 668086, overlap = 55.75
+PHY-3002 : Step(258): len = 670025, overlap = 55.3125
+PHY-3002 : Step(259): len = 669835, overlap = 55.4688
+PHY-3002 : Step(260): len = 670573, overlap = 52.5625
+PHY-3002 : Step(261): len = 669858, overlap = 54.25
+PHY-3002 : Step(262): len = 670806, overlap = 54.5312
+PHY-3002 : Step(263): len = 670927, overlap = 56.6875
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00105605
+PHY-3002 : Step(264): len = 679011, overlap = 56.1562
+PHY-3002 : Step(265): len = 691236, overlap = 55.2812
+PHY-3002 : Step(266): len = 697705, overlap = 54.9062
+PHY-3002 : Step(267): len = 702209, overlap = 49.4062
+PHY-3002 : Step(268): len = 707851, overlap = 46.4688
+PHY-3002 : Step(269): len = 710099, overlap = 42.625
+PHY-3002 : Step(270): len = 709475, overlap = 46.4688
+PHY-3002 : Step(271): len = 708036, overlap = 47.9688
+PHY-3002 : Step(272): len = 705048, overlap = 45.1875
+PHY-3002 : Step(273): len = 703296, overlap = 42.2812
+PHY-3002 : Step(274): len = 701859, overlap = 41.4375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00175699
+PHY-3002 : Step(275): len = 705264, overlap = 42.3125
+PHY-3002 : Step(276): len = 711710, overlap = 43.625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 798776, over cnt = 2730(7%), over = 13939, worst = 58
+PHY-1001 : End global iterations; 1.780497s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 103.60, top5 = 78.12, top10 = 67.14, top15 = 60.35.
+PHY-3001 : End congestion estimation; 2.215853s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (121.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.966237s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000115894
+PHY-3002 : Step(277): len = 701679, overlap = 259.219
+PHY-3002 : Step(278): len = 695845, overlap = 206.469
+PHY-3002 : Step(279): len = 681270, overlap = 177
+PHY-3002 : Step(280): len = 670786, overlap = 160.875
+PHY-3002 : Step(281): len = 659604, overlap = 147.156
+PHY-3002 : Step(282): len = 652029, overlap = 147.875
+PHY-3002 : Step(283): len = 645190, overlap = 141.75
+PHY-3002 : Step(284): len = 639775, overlap = 131.875
+PHY-3002 : Step(285): len = 634252, overlap = 129.125
+PHY-3002 : Step(286): len = 629214, overlap = 121.438
+PHY-3002 : Step(287): len = 625408, overlap = 123.938
+PHY-3002 : Step(288): len = 619843, overlap = 126.938
+PHY-3002 : Step(289): len = 617986, overlap = 126.875
+PHY-3002 : Step(290): len = 613654, overlap = 125.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000231787
+PHY-3002 : Step(291): len = 614963, overlap = 119.094
+PHY-3002 : Step(292): len = 616318, overlap = 116.844
+PHY-3002 : Step(293): len = 620037, overlap = 111.219
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000463575
+PHY-3002 : Step(294): len = 626855, overlap = 102.375
+PHY-3002 : Step(295): len = 636556, overlap = 89.25
+PHY-3002 : Step(296): len = 640666, overlap = 81.25
+PHY-3002 : Step(297): len = 640152, overlap = 82.5312
+PHY-3002 : Step(298): len = 640224, overlap = 80.0312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00092715
+PHY-3002 : Step(299): len = 643635, overlap = 77.875
+PHY-3002 : Step(300): len = 647844, overlap = 75.4688
+PHY-3002 : Step(301): len = 652762, overlap = 69.5
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84699, tnet num: 20549, tinst num: 18148, tnode num: 115428, tedge num: 135050.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.626514s wall, 1.578125s user + 0.046875s system = 1.625000s CPU (99.9%)
+
+RUN-1004 : used memory is 577 MB, reserved memory is 567 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 385.00 peak overflow 3.56
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 588/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 754560, over cnt = 3175(9%), over = 11366, worst = 24
+PHY-1001 : End global iterations; 1.822779s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (140.6%)
+
+PHY-1001 : Congestion index: top1 = 70.71, top5 = 57.70, top10 = 51.60, top15 = 47.99.
+PHY-1001 : End incremental global routing; 2.237843s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (133.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.072110s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (99.1%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18017 has valid locations, 310 needs to be replaced
+PHY-3001 : design contains 18412 instances, 7801 luts, 9390 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6214 pins
+PHY-3001 : Found 1271 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 677223
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17432/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 770632, over cnt = 3255(9%), over = 11383, worst = 23
+PHY-1001 : End global iterations; 0.250072s wall, 0.312500s user + 0.031250s system = 0.343750s CPU (137.5%)
+
+PHY-1001 : Congestion index: top1 = 70.78, top5 = 57.95, top10 = 51.94, top15 = 48.37.
+PHY-3001 : End congestion estimation; 0.560270s wall, 0.625000s user + 0.031250s system = 0.656250s CPU (117.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85753, tnet num: 20813, tinst num: 18412, tnode num: 116993, tedge num: 136630.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.568604s wall, 1.531250s user + 0.031250s system = 1.562500s CPU (99.6%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 640 MB, peak memory is 719 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.628004s wall, 2.562500s user + 0.062500s system = 2.625000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(302): len = 676111, overlap = 0
+PHY-3002 : Step(303): len = 675586, overlap = 0
+PHY-3002 : Step(304): len = 675113, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17521/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 767840, over cnt = 3247(9%), over = 11447, worst = 24
+PHY-1001 : End global iterations; 0.211781s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (118.0%)
+
+PHY-1001 : Congestion index: top1 = 72.16, top5 = 58.56, top10 = 52.29, top15 = 48.59.
+PHY-3001 : End congestion estimation; 0.489126s wall, 0.515625s user + 0.015625s system = 0.531250s CPU (108.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.137574s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0004948
+PHY-3002 : Step(305): len = 674805, overlap = 71.375
+PHY-3002 : Step(306): len = 674912, overlap = 71.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000989599
+PHY-3002 : Step(307): len = 675367, overlap = 71.9062
+PHY-3002 : Step(308): len = 675884, overlap = 72.5
+PHY-3001 : Final: Len = 675884, Over = 72.5
+PHY-3001 : End incremental placement; 5.586603s wall, 6.046875s user + 0.187500s system = 6.234375s CPU (111.6%)
+
+OPT-1001 : Total overflow 392.34 peak overflow 3.56
+OPT-1001 : End high-fanout net optimization; 9.525222s wall, 10.781250s user + 0.203125s system = 10.984375s CPU (115.3%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 714, peak = 736.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17466/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 771016, over cnt = 3176(9%), over = 10301, worst = 23
+PHY-1002 : len = 828160, over cnt = 2086(5%), over = 4811, worst = 20
+PHY-1002 : len = 867240, over cnt = 877(2%), over = 1743, worst = 15
+PHY-1002 : len = 883328, over cnt = 355(1%), over = 708, worst = 14
+PHY-1002 : len = 895024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.086840s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (137.8%)
+
+PHY-1001 : Congestion index: top1 = 58.51, top5 = 50.43, top10 = 47.17, top15 = 44.97.
+OPT-1001 : End congestion update; 2.382316s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (133.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.900247s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (98.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 105 cells processed and 9502 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 55 cells processed and 8250 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 250 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.762782s wall, 4.546875s user + 0.015625s system = 4.562500s CPU (121.3%)
+
+OPT-1001 : Current memory(MB): used = 696, reserve = 693, peak = 736.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17516/20992.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 895344, over cnt = 90(0%), over = 117, worst = 4
+PHY-1002 : len = 895312, over cnt = 55(0%), over = 63, worst = 3
+PHY-1002 : len = 895816, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 895872, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 895872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.813142s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.9%)
+
+PHY-1001 : Congestion index: top1 = 57.84, top5 = 50.22, top10 = 46.98, top15 = 44.83.
+OPT-1001 : End congestion update; 1.108094s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20814 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.936594s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.1%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 24 cells processed and 5400 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.175605s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (99.8%)
+
+OPT-1001 : Current memory(MB): used = 709, reserve = 703, peak = 736.
+OPT-1001 : End physical optimization; 17.425955s wall, 19.359375s user + 0.312500s system = 19.671875s CPU (112.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7801 LUT to BLE ...
+SYN-4008 : Packed 7801 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6244 remaining SEQ's ...
+SYN-4005 : Packed 4136 SEQ with LUT/SLICE
+SYN-4006 : 822 single LUT's are left
+SYN-4006 : 2108 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9909/13696 primitive instances ...
+PHY-3001 : End packing; 1.875834s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6712 instances
+RUN-1001 : 3282 mslices, 3282 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17978 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10093 nets have 2 pins
+RUN-1001 : 6518 nets have [3 - 5] pins
+RUN-1001 : 720 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 304 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6710 instances, 6564 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3609 pins
+PHY-3001 : Found 502 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 687808, Over = 215
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7546/17978.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843800, over cnt = 2052(5%), over = 3273, worst = 7
+PHY-1002 : len = 851904, over cnt = 1307(3%), over = 1857, worst = 7
+PHY-1002 : len = 866568, over cnt = 392(1%), over = 559, worst = 6
+PHY-1002 : len = 874264, over cnt = 79(0%), over = 96, worst = 5
+PHY-1002 : len = 876176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.964729s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (142.4%)
+
+PHY-1001 : Congestion index: top1 = 57.59, top5 = 50.45, top10 = 46.92, top15 = 44.49.
+PHY-3001 : End congestion estimation; 2.424701s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (134.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71872, tnet num: 17800, tinst num: 6710, tnode num: 94483, tedge num: 119436.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.821208s wall, 1.750000s user + 0.078125s system = 1.828125s CPU (100.4%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 619 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.807045s wall, 2.734375s user + 0.078125s system = 2.812500s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.04479e-05
+PHY-3002 : Step(309): len = 674138, overlap = 216.75
+PHY-3002 : Step(310): len = 666231, overlap = 213.75
+PHY-3002 : Step(311): len = 661568, overlap = 219.25
+PHY-3002 : Step(312): len = 657793, overlap = 222
+PHY-3002 : Step(313): len = 654077, overlap = 229.5
+PHY-3002 : Step(314): len = 651494, overlap = 234.75
+PHY-3002 : Step(315): len = 649577, overlap = 234.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000120896
+PHY-3002 : Step(316): len = 652344, overlap = 228.5
+PHY-3002 : Step(317): len = 657500, overlap = 223.5
+PHY-3002 : Step(318): len = 659867, overlap = 215
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000241792
+PHY-3002 : Step(319): len = 664373, overlap = 207.5
+PHY-3002 : Step(320): len = 669354, overlap = 197.5
+PHY-3002 : Step(321): len = 670611, overlap = 197.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.439681s wall, 0.437500s user + 0.687500s system = 1.125000s CPU (255.9%)
+
+PHY-3001 : Trial Legalized: Len = 753187
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 885/17978.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 868160, over cnt = 2687(7%), over = 4428, worst = 8
+PHY-1002 : len = 885416, over cnt = 1596(4%), over = 2280, worst = 6
+PHY-1002 : len = 906000, over cnt = 556(1%), over = 744, worst = 6
+PHY-1002 : len = 912960, over cnt = 230(0%), over = 303, worst = 6
+PHY-1002 : len = 919528, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.781458s wall, 4.015625s user + 0.062500s system = 4.078125s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 56.59, top5 = 50.64, top10 = 47.42, top15 = 45.37.
+PHY-3001 : End congestion estimation; 3.314432s wall, 4.546875s user + 0.062500s system = 4.609375s CPU (139.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.962306s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171398
+PHY-3002 : Step(322): len = 724795, overlap = 33.75
+PHY-3002 : Step(323): len = 707753, overlap = 59
+PHY-3002 : Step(324): len = 693567, overlap = 85
+PHY-3002 : Step(325): len = 685814, overlap = 106.5
+PHY-3002 : Step(326): len = 681204, overlap = 125.5
+PHY-3002 : Step(327): len = 678607, overlap = 136.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000342797
+PHY-3002 : Step(328): len = 683051, overlap = 131
+PHY-3002 : Step(329): len = 687214, overlap = 124.75
+PHY-3002 : Step(330): len = 687151, overlap = 124
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000685593
+PHY-3002 : Step(331): len = 690270, overlap = 125.5
+PHY-3002 : Step(332): len = 696719, overlap = 117
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.038809s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (120.8%)
+
+PHY-3001 : Legalized: Len = 724209, Over = 0
+PHY-3001 : Spreading special nets. 447 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.109374s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.0%)
+
+PHY-3001 : 636 instances has been re-located, deltaX = 190, deltaY = 381, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 735687, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71872, tnet num: 17800, tinst num: 6713, tnode num: 94483, tedge num: 119436.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.009533s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (100.3%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 645 MB, peak memory is 736 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4732/17978.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 866832, over cnt = 2427(6%), over = 3772, worst = 7
+PHY-1002 : len = 879824, over cnt = 1348(3%), over = 1811, worst = 7
+PHY-1002 : len = 890272, over cnt = 747(2%), over = 972, worst = 5
+PHY-1002 : len = 896448, over cnt = 456(1%), over = 599, worst = 5
+PHY-1002 : len = 904256, over cnt = 69(0%), over = 76, worst = 2
+PHY-1001 : End global iterations; 2.209488s wall, 3.328125s user + 0.046875s system = 3.375000s CPU (152.8%)
+
+PHY-1001 : Congestion index: top1 = 55.09, top5 = 49.39, top10 = 46.31, top15 = 44.39.
+PHY-1001 : End incremental global routing; 2.647619s wall, 3.765625s user + 0.046875s system = 3.812500s CPU (144.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.933055s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.5%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6620 has valid locations, 28 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3682 pins
+PHY-3001 : Found 502 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 741757
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16353/18003.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910880, over cnt = 160(0%), over = 210, worst = 7
+PHY-1002 : len = 911336, over cnt = 95(0%), over = 102, worst = 3
+PHY-1002 : len = 912272, over cnt = 28(0%), over = 29, worst = 2
+PHY-1002 : len = 912680, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 912776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.915601s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 55.22, top5 = 49.50, top10 = 46.42, top15 = 44.52.
+PHY-3001 : End congestion estimation; 1.255602s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (105.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72128, tnet num: 17825, tinst num: 6736, tnode num: 94802, tedge num: 119763.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.024154s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (98.8%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 666 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17825 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.987102s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(333): len = 740959, overlap = 0
+PHY-3002 : Step(334): len = 740334, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16334/18003.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910896, over cnt = 97(0%), over = 129, worst = 5
+PHY-1002 : len = 910944, over cnt = 49(0%), over = 55, worst = 4
+PHY-1002 : len = 911344, over cnt = 9(0%), over = 10, worst = 2
+PHY-1002 : len = 911520, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 911528, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.927370s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (107.8%)
+
+PHY-1001 : Congestion index: top1 = 55.15, top5 = 49.41, top10 = 46.35, top15 = 44.44.
+PHY-3001 : End congestion estimation; 1.320033s wall, 1.375000s user + 0.015625s system = 1.390625s CPU (105.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17825 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.097502s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00101639
+PHY-3002 : Step(335): len = 740055, overlap = 1
+PHY-3002 : Step(336): len = 740051, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005558s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 740041, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064285s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 740163, Over = 0
+PHY-3001 : End incremental placement; 7.185447s wall, 7.562500s user + 0.140625s system = 7.703125s CPU (107.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 11.287635s wall, 12.750000s user + 0.218750s system = 12.968750s CPU (114.9%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16305/18003.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911472, over cnt = 88(0%), over = 122, worst = 8
+PHY-1002 : len = 911648, over cnt = 46(0%), over = 51, worst = 3
+PHY-1002 : len = 911904, over cnt = 24(0%), over = 27, worst = 2
+PHY-1002 : len = 912120, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 912248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.889688s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (110.6%)
+
+PHY-1001 : Congestion index: top1 = 55.02, top5 = 49.54, top10 = 46.47, top15 = 44.55.
+OPT-1001 : End congestion update; 1.238649s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (108.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17825 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.829163s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (98.0%)
+
+OPT-0007 : Start: WNS -179 TNS -179 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3682 pins
+PHY-3001 : Found 502 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744779, Over = 0
+PHY-3001 : Spreading special nets. 24 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.070766s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (88.3%)
+
+PHY-3001 : 34 instances has been re-located, deltaX = 12, deltaY = 23, maxDist = 3.
+PHY-3001 : Final: Len = 745595, Over = 0
+PHY-3001 : End incremental legalization; 0.478280s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (143.7%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 57 cells processed and 13602 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3682 pins
+PHY-3001 : Found 502 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 749817, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066572s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.9%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 13, deltaY = 16, maxDist = 3.
+PHY-3001 : Final: Len = 750485, Over = 0
+PHY-3001 : End incremental legalization; 0.441835s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.6%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 27 cells processed and 9057 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6736 instances, 6587 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3682 pins
+PHY-3001 : Found 502 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 750409, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.066635s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.8%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 9, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 750775, Over = 0
+PHY-3001 : End incremental legalization; 0.416395s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (127.6%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 14 cells processed and 626 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 751034, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065790s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (118.7%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 1, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 750986, Over = 0
+PHY-3001 : End incremental legalization; 0.427056s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.8%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 4 cells processed and 550 slack improved
+OPT-1001 : End bottleneck based optimization; 4.473320s wall, 4.906250s user + 0.000000s system = 4.906250s CPU (109.7%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15900/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922608, over cnt = 222(0%), over = 303, worst = 5
+PHY-1002 : len = 923024, over cnt = 117(0%), over = 126, worst = 2
+PHY-1002 : len = 923856, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 924400, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 924576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.940385s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (108.0%)
+
+PHY-1001 : Congestion index: top1 = 56.08, top5 = 49.99, top10 = 46.75, top15 = 44.78.
+OPT-1001 : End congestion update; 1.286487s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (104.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.777051s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 751068, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064696s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.6%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 9, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 751300, Over = 0
+PHY-3001 : End incremental legalization; 0.419627s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (100.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 14 cells processed and 1300 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 751462, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064419s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.0%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 751482, Over = 0
+PHY-3001 : End incremental legalization; 0.412974s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (124.9%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 8 cells processed and 150 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 3.174904s wall, 3.296875s user + 0.031250s system = 3.328125s CPU (104.8%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.774701s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16304/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924984, over cnt = 47(0%), over = 54, worst = 4
+PHY-1002 : len = 924936, over cnt = 35(0%), over = 35, worst = 1
+PHY-1002 : len = 925040, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 925432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.721643s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.00, top10 = 46.76, top15 = 44.75.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.814904s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.862069
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 751482, Over = 0
+PHY-3001 : End spreading; 0.065142s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.9%)
+
+PHY-3001 : Final: Len = 751482, Over = 0
+PHY-3001 : End incremental legalization; 0.421257s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.770298s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16374/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 925432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139555s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.8%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.00, top10 = 46.76, top15 = 44.75.
+OPT-1001 : End congestion update; 0.489715s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.779961s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 751434, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064985s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 751482, Over = 0
+PHY-3001 : End incremental legalization; 0.465872s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.6%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.856442s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (99.3%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16374/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 925432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139514s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (89.6%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.00, top10 = 46.76, top15 = 44.75.
+OPT-1001 : End congestion update; 0.491934s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.775669s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 751434, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061706s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 751482, Over = 0
+PHY-3001 : End incremental legalization; 0.419119s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.7%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 751434, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064110s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.5%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 751482, Over = 0
+PHY-3001 : End incremental legalization; 0.429491s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.9%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.418750s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.8%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.768544s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.774214s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.9%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16374/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 925432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.142869s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.4%)
+
+PHY-1001 : Congestion index: top1 = 56.23, top5 = 50.00, top10 = 46.76, top15 = 44.75.
+RUN-1001 : End congestion update; 0.489177s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.0%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.266952s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (101.1%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 737, peak = 740.
+OPT-1001 : End physical optimization; 31.559086s wall, 33.625000s user + 0.296875s system = 33.921875s CPU (107.5%)
+
+RUN-1003 : finish command "place" in 84.276188s wall, 123.156250s user + 7.562500s system = 130.718750s CPU (155.1%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 605 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.810414s wall, 3.171875s user + 0.015625s system = 3.187500s CPU (176.1%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 606 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6743 instances
+RUN-1001 : 3292 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18005 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10088 nets have 2 pins
+RUN-1001 : 6518 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 315 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72172, tnet num: 17827, tinst num: 6741, tnode num: 94865, tedge num: 119825.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.704446s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.9%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 632 MB, peak memory is 740 MB
+PHY-1001 : 3292 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855728, over cnt = 2734(7%), over = 4408, worst = 7
+PHY-1002 : len = 870608, over cnt = 1834(5%), over = 2664, worst = 7
+PHY-1002 : len = 889424, over cnt = 869(2%), over = 1263, worst = 7
+PHY-1002 : len = 910208, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 910464, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.437231s wall, 4.500000s user + 0.046875s system = 4.546875s CPU (132.3%)
+
+PHY-1001 : Congestion index: top1 = 55.78, top5 = 49.73, top10 = 46.42, top15 = 44.40.
+PHY-1001 : End global routing; 3.798308s wall, 4.859375s user + 0.046875s system = 4.906250s CPU (129.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 715, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 986, reserve = 991, peak = 986.
+PHY-1001 : End build detailed router design. 4.350927s wall, 4.296875s user + 0.046875s system = 4.343750s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270952, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 6.480077s wall, 6.453125s user + 0.000000s system = 6.453125s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271008, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.514569s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1026, peak = 1021.
+PHY-1001 : End phase 1; 7.007118s wall, 6.984375s user + 0.000000s system = 6.984375s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.29504e+06, over cnt = 1743(0%), over = 1748, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1038, peak = 1035.
+PHY-1001 : End initial routed; 33.798510s wall, 70.812500s user + 0.171875s system = 70.984375s CPU (210.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 15/16928(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.811 | -1.167 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.529221s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1043, reserve = 1047, peak = 1043.
+PHY-1001 : End phase 2; 37.327795s wall, 74.343750s user + 0.171875s system = 74.515625s CPU (199.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 10 pins with SWNS -0.805ns STNS -0.841ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.163647s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.5%)
+
+PHY-1022 : len = 2.29507e+06, over cnt = 1750(0%), over = 1755, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.460096s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26614e+06, over cnt = 671(0%), over = 671, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.417078s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (190.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.26268e+06, over cnt = 123(0%), over = 123, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.833564s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (155.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.26347e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.402926s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (120.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.26358e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.351678s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (115.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.377195s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.340987s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.465805s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.6%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.174900s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.190580s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.230166s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.278179s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.388557s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.5%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.174888s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.189291s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.215411s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.236894s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.374698s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.481662s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.6%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.181540s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (111.9%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.199831s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.217506s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.336583s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.369787s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.449034s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.236449s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.177272s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.192353s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (105.6%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.217042s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.234799s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.394992s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.452130s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.331177s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.280651s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.172886s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (117.5%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.185608s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (92.6%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.215034s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (109.0%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.233950s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.372223s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.441179s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.181236s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.222898s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.181869s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.186493s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.195608s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.210476s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.228517s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.364864s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.425286s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.181720s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.386297s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.200801s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.174897s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.174535s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.181548s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (111.9%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.208736s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.230645s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (108.4%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.368568s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.415354s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.8%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.172125s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.178039s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.188202s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.201700s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.381212s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.176977s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (105.9%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.182124s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.4%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.246873s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.226353s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.377630s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.436937s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.184654s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.198048s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.313335s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.181911s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.279551s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.203927s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 9/16928(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.841 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.581851s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1056, peak = 1051.
+PHY-1001 : End phase 3; 47.417885s wall, 49.359375s user + 0.015625s system = 49.375000s CPU (104.1%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.805ns STNS -0.841ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.159962s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.7%)
+
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.425513s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.805ns, -0.841ns, 2}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.199184s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.228408s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.300685s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.175924s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.6%)
+
+PHY-1001 : ==== DR Iter 5 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.188002s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.214204s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (94.8%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.234047s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (106.8%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.382271s wall, 0.390625s user + 0.046875s system = 0.437500s CPU (114.4%)
+
+PHY-1001 : ===== DR Iter 9 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.172660s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.185852s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.224355s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.242004s wall, 0.234375s user + 0.031250s system = 0.265625s CPU (109.8%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.362169s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.422320s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 15 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.185449s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (109.5%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.194125s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (112.7%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.217519s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.250764s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.363616s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.440377s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 1.462499s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 22 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.180649s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.1%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.189816s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (90.5%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.213959s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.232631s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.386266s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.425659s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 1.199582s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 1.211087s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (100.6%)
+
+PHY-1001 : ===== DR Iter 30 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.178331s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.191542s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.214232s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.231396s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (94.5%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.416917s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.454740s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 1.154802s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 1.165129s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.179993s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 39 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.181533s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.196949s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (111.1%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.232430s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.230622s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.358771s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.420998s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 1.289386s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.204899s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.177266s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.326678s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 49 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.209382s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.194360s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.210008s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (133.9%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.233694s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.377523s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.433440s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 1.145983s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 1.349562s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.247114s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.127991s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.144367s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 60 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.174687s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.182494s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (111.3%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.207440s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.227952s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (109.7%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.359299s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.438206s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 1.162220s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 1.199510s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.134064s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.307943s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.131251s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.133963s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 9/16928(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.841 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.556131s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1059, peak = 1054.
+PHY-1001 : End phase 4; 42.919565s wall, 42.937500s user + 0.171875s system = 43.109375s CPU (100.4%)
+
+PHY-1003 : Routed, final wirelength = 2.2637e+06
+PHY-1001 : 563 feed throughs used by 434 nets
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1160, peak = 1152.
+PHY-1001 : End export database. 2.548223s wall, 2.531250s user + 0.015625s system = 2.546875s CPU (99.9%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6743 instances
+RUN-1001 : 3292 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18005 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10088 nets have 2 pins
+RUN-1001 : 6518 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 315 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 0
+RUN-1001 : No | No | Yes | 0
+RUN-1001 : No | Yes | No | 0
+RUN-1001 : Yes | No | No | 0
+RUN-1001 : Yes | No | Yes | 0
+RUN-1001 : Yes | Yes | No | 0
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 10 | 1 | 1
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 7 3) is for feedthrough
+PHY-3001 : eco cells: (1 8 3) is for feedthrough
+PHY-3001 : eco cells: (1 15 3) is for feedthrough
+PHY-3001 : eco cells: (2 7 1) is for feedthrough
+PHY-3001 : eco cells: (2 7 2) is for feedthrough
+PHY-3001 : eco cells: (2 10 2) is for feedthrough
+PHY-3001 : eco cells: (2 12 3) is for feedthrough
+PHY-3001 : eco cells: (2 16 0) is for feedthrough
+PHY-3001 : eco cells: (2 21 0) is for feedthrough
+PHY-3001 : eco cells: (2 22 0) is for feedthrough
+PHY-3001 : eco cells: (2 37 3) is for feedthrough
+PHY-3001 : eco cells: (2 41 3) is for feedthrough
+PHY-3001 : eco cells: (2 46 1) is for feedthrough
+PHY-3001 : eco cells: (3 6 3) is for feedthrough
+PHY-3001 : eco cells: (3 9 3) is for feedthrough
+PHY-3001 : eco cells: (3 11 3) is for feedthrough
+PHY-3001 : eco cells: (3 14 3) is for feedthrough
+PHY-3001 : eco cells: (3 20 0) is for feedthrough
+PHY-3001 : eco cells: (3 22 2) is for feedthrough
+PHY-3001 : eco cells: (3 37 0) is for feedthrough
+PHY-3001 : eco cells: (3 37 1) is for feedthrough
+PHY-3001 : eco cells: (3 42 0) is for feedthrough
+PHY-3001 : eco cells: (3 42 1) is for feedthrough
+PHY-3001 : eco cells: (3 44 1) is for feedthrough
+PHY-3001 : eco cells: (3 45 0) is for feedthrough
+PHY-3001 : eco cells: (3 46 0) is for feedthrough
+PHY-3001 : eco cells: (3 46 1) is for feedthrough
+PHY-3001 : eco cells: (3 47 3) is for feedthrough
+PHY-3001 : eco cells: (3 48 2) is for feedthrough
+PHY-3001 : eco cells: (3 49 2) is for feedthrough
+PHY-3001 : eco cells: (3 50 0) is for feedthrough
+PHY-3001 : eco cells: (3 55 0) is for feedthrough
+PHY-3001 : eco cells: (3 60 3) is for feedthrough
+PHY-3001 : eco cells: (3 64 3) is for feedthrough
+PHY-3001 : eco cells: (4 3 1) is for feedthrough
+PHY-3001 : eco cells: (4 4 3) is for feedthrough
+PHY-3001 : eco cells: (4 5 1) is for feedthrough
+PHY-3001 : eco cells: (4 6 2) is for feedthrough
+PHY-3001 : eco cells: (4 7 0) is for feedthrough
+PHY-3001 : eco cells: (4 7 3) is for feedthrough
+PHY-3001 : eco cells: (4 8 3) is for feedthrough
+PHY-3001 : eco cells: (4 11 1) is for feedthrough
+PHY-3001 : eco cells: (4 12 3) is for feedthrough
+PHY-3001 : eco cells: (4 21 1) is for feedthrough
+PHY-3001 : eco cells: (4 35 2) is for feedthrough
+PHY-3001 : eco cells: (4 36 0) is for feedthrough
+PHY-3001 : eco cells: (4 36 1) is for feedthrough
+PHY-3001 : eco cells: (4 37 2) is for feedthrough
+PHY-3001 : eco cells: (4 41 0) is for feedthrough
+PHY-3001 : eco cells: (4 44 3) is for feedthrough
+PHY-3001 : eco cells: (4 45 1) is for feedthrough
+PHY-3001 : eco cells: (4 45 3) is for feedthrough
+PHY-3001 : eco cells: (4 49 3) is for feedthrough
+PHY-3001 : eco cells: (4 51 2) is for feedthrough
+PHY-3001 : eco cells: (4 51 3) is for feedthrough
+PHY-3001 : eco cells: (4 52 0) is for feedthrough
+PHY-3001 : eco cells: (4 56 1) is for feedthrough
+PHY-3001 : eco cells: (4 64 2) is for feedthrough
+PHY-3001 : eco cells: (4 66 0) is for feedthrough
+PHY-3001 : eco cells: (4 66 1) is for feedthrough
+PHY-3001 : eco cells: (5 7 0) is for feedthrough
+PHY-3001 : eco cells: (5 11 2) is for feedthrough
+PHY-3001 : eco cells: (5 12 0) is for feedthrough
+PHY-3001 : eco cells: (5 14 0) is for feedthrough
+PHY-3001 : eco cells: (5 14 1) is for feedthrough
+PHY-3001 : eco cells: (5 17 3) is for feedthrough
+PHY-3001 : eco cells: (5 19 2) is for feedthrough
+PHY-3001 : eco cells: (5 23 3) is for feedthrough
+PHY-3001 : eco cells: (5 28 3) is for feedthrough
+PHY-3001 : eco cells: (5 40 3) is for feedthrough
+PHY-3001 : eco cells: (5 46 3) is for feedthrough
+PHY-3001 : eco cells: (5 47 0) is for feedthrough
+PHY-3001 : eco cells: (5 49 0) is for feedthrough
+PHY-3001 : eco cells: (5 50 2) is for feedthrough
+PHY-3001 : eco cells: (5 51 2) is for feedthrough
+PHY-3001 : eco cells: (5 52 0) is for feedthrough
+PHY-3001 : eco cells: (5 54 2) is for feedthrough
+PHY-3001 : eco cells: (5 55 0) is for feedthrough
+PHY-3001 : eco cells: (5 60 0) is for feedthrough
+PHY-3001 : eco cells: (5 64 3) is for feedthrough
+PHY-3001 : eco cells: (5 66 0) is for feedthrough
+PHY-3001 : eco cells: (6 5 0) is for feedthrough
+PHY-3001 : eco cells: (6 8 2) is for feedthrough
+PHY-3001 : eco cells: (6 13 2) is for feedthrough
+PHY-3001 : eco cells: (6 18 3) is for feedthrough
+PHY-3001 : eco cells: (6 19 3) is for feedthrough
+PHY-3001 : eco cells: (6 20 1) is for feedthrough
+PHY-3001 : eco cells: (6 21 0) is for feedthrough
+PHY-3001 : eco cells: (6 22 3) is for feedthrough
+PHY-3001 : eco cells: (6 25 3) is for feedthrough
+PHY-3001 : eco cells: (6 36 2) is for feedthrough
+PHY-3001 : eco cells: (6 54 3) is for feedthrough
+PHY-3001 : eco cells: (6 55 3) is for feedthrough
+PHY-3001 : eco cells: (6 56 0) is for feedthrough
+PHY-3001 : eco cells: (6 60 0) is for feedthrough
+PHY-3001 : eco cells: (7 13 3) is for feedthrough
+PHY-3001 : eco cells: (7 15 3) is for feedthrough
+PHY-3001 : eco cells: (7 21 2) is for feedthrough
+PHY-3001 : eco cells: (7 22 1) is for feedthrough
+PHY-3001 : eco cells: (7 24 2) is for feedthrough
+PHY-3001 : eco cells: (7 29 0) is for feedthrough
+PHY-3001 : eco cells: (7 29 1) is for feedthrough
+PHY-3001 : eco cells: (7 33 1) is for feedthrough
+PHY-3001 : eco cells: (7 34 2) is for feedthrough
+PHY-3001 : eco cells: (7 35 2) is for feedthrough
+PHY-3001 : eco cells: (7 42 3) is for feedthrough
+PHY-3001 : eco cells: (7 47 1) is for feedthrough
+PHY-3001 : eco cells: (7 53 0) is for feedthrough
+PHY-3001 : eco cells: (7 55 0) is for feedthrough
+PHY-3001 : eco cells: (7 55 2) is for feedthrough
+PHY-3001 : eco cells: (7 57 0) is for feedthrough
+PHY-3001 : eco cells: (7 65 2) is for feedthrough
+PHY-3001 : eco cells: (9 4 3) is for feedthrough
+PHY-3001 : eco cells: (9 7 1) is for feedthrough
+PHY-3001 : eco cells: (9 10 0) is for feedthrough
+PHY-3001 : eco cells: (9 11 0) is for feedthrough
+PHY-3001 : eco cells: (9 14 3) is for feedthrough
+PHY-3001 : eco cells: (9 16 1) is for feedthrough
+PHY-3001 : eco cells: (9 17 3) is for feedthrough
+PHY-3001 : eco cells: (9 20 1) is for feedthrough
+PHY-3001 : eco cells: (9 21 3) is for feedthrough
+PHY-3001 : eco cells: (9 22 1) is for feedthrough
+PHY-3001 : eco cells: (9 24 2) is for feedthrough
+PHY-3001 : eco cells: (9 42 0) is for feedthrough
+PHY-3001 : eco cells: (9 43 3) is for feedthrough
+PHY-3001 : eco cells: (9 49 2) is for feedthrough
+PHY-3001 : eco cells: (9 53 1) is for feedthrough
+PHY-3001 : eco cells: (9 65 2) is for feedthrough
+PHY-3001 : eco cells: (10 2 2) is for feedthrough
+PHY-3001 : eco cells: (10 4 2) is for feedthrough
+PHY-3001 : eco cells: (10 5 0) is for feedthrough
+PHY-3001 : eco cells: (10 8 3) is for feedthrough
+PHY-3001 : eco cells: (10 9 2) is for feedthrough
+PHY-3001 : eco cells: (10 14 3) is for feedthrough
+PHY-3001 : eco cells: (10 15 3) is for feedthrough
+PHY-3001 : eco cells: (10 16 0) is for feedthrough
+PHY-3001 : eco cells: (10 20 3) is for feedthrough
+PHY-3001 : eco cells: (10 25 3) is for feedthrough
+PHY-3001 : eco cells: (10 30 0) is for feedthrough
+PHY-3001 : eco cells: (10 30 1) is for feedthrough
+PHY-3001 : eco cells: (10 31 3) is for feedthrough
+PHY-3001 : eco cells: (10 33 2) is for feedthrough
+PHY-3001 : eco cells: (10 42 3) is for feedthrough
+PHY-3001 : eco cells: (10 55 2) is for feedthrough
+PHY-3001 : eco cells: (10 65 3) is for feedthrough
+PHY-3001 : eco cells: (11 1 0) is for feedthrough
+PHY-3001 : eco cells: (11 4 1) is for feedthrough
+PHY-3001 : eco cells: (11 9 1) is for feedthrough
+PHY-3001 : eco cells: (11 9 2) is for feedthrough
+PHY-3001 : eco cells: (11 11 3) is for feedthrough
+PHY-3001 : eco cells: (11 15 2) is for feedthrough
+PHY-3001 : eco cells: (11 17 0) is for feedthrough
+PHY-3001 : eco cells: (11 21 0) is for feedthrough
+PHY-3001 : eco cells: (11 24 0) is for feedthrough
+PHY-3001 : eco cells: (11 29 2) is for feedthrough
+PHY-3001 : eco cells: (11 34 0) is for feedthrough
+PHY-3001 : eco cells: (11 39 2) is for feedthrough
+PHY-3001 : eco cells: (11 40 0) is for feedthrough
+PHY-3001 : eco cells: (11 42 2) is for feedthrough
+PHY-3001 : eco cells: (11 51 3) is for feedthrough
+PHY-3001 : eco cells: (11 58 0) is for feedthrough
+PHY-3001 : eco cells: (12 2 0) is for feedthrough
+PHY-3001 : eco cells: (12 3 1) is for feedthrough
+PHY-3001 : eco cells: (12 6 0) is for feedthrough
+PHY-3001 : eco cells: (12 7 2) is for feedthrough
+PHY-3001 : eco cells: (12 8 0) is for feedthrough
+PHY-3001 : eco cells: (12 10 1) is for feedthrough
+PHY-3001 : eco cells: (12 29 3) is for feedthrough
+PHY-3001 : eco cells: (12 35 3) is for feedthrough
+PHY-3001 : eco cells: (12 41 2) is for feedthrough
+PHY-3001 : eco cells: (12 55 0) is for feedthrough
+PHY-3001 : eco cells: (12 63 2) is for feedthrough
+PHY-3001 : eco cells: (12 64 1) is for feedthrough
+PHY-3001 : eco cells: (13 3 3) is for feedthrough
+PHY-3001 : eco cells: (13 4 0) is for feedthrough
+PHY-3001 : eco cells: (13 7 3) is for feedthrough
+PHY-3001 : eco cells: (13 9 0) is for feedthrough
+PHY-3001 : eco cells: (13 9 1) is for feedthrough
+PHY-3001 : eco cells: (13 10 1) is for feedthrough
+PHY-3001 : eco cells: (13 23 0) is for feedthrough
+PHY-3001 : eco cells: (13 32 3) is for feedthrough
+PHY-3001 : eco cells: (13 36 0) is for feedthrough
+PHY-3001 : eco cells: (13 39 2) is for feedthrough
+PHY-3001 : eco cells: (13 60 1) is for feedthrough
+PHY-3001 : eco cells: (13 61 2) is for feedthrough
+PHY-3001 : eco cells: (13 68 2) is for feedthrough
+PHY-3001 : eco cells: (14 7 0) is for feedthrough
+PHY-3001 : eco cells: (14 9 0) is for feedthrough
+PHY-3001 : eco cells: (14 9 2) is for feedthrough
+PHY-3001 : eco cells: (14 10 1) is for feedthrough
+PHY-3001 : eco cells: (14 41 2) is for feedthrough
+PHY-3001 : eco cells: (14 42 3) is for feedthrough
+PHY-3001 : eco cells: (14 59 0) is for feedthrough
+PHY-3001 : eco cells: (14 62 0) is for feedthrough
+PHY-3001 : eco cells: (14 66 0) is for feedthrough
+PHY-3001 : eco cells: (15 6 1) is for feedthrough
+PHY-3001 : eco cells: (15 7 2) is for feedthrough
+PHY-3001 : eco cells: (15 8 0) is for feedthrough
+PHY-3001 : eco cells: (15 12 2) is for feedthrough
+PHY-3001 : eco cells: (15 32 0) is for feedthrough
+PHY-3001 : eco cells: (15 39 2) is for feedthrough
+PHY-3001 : eco cells: (15 60 0) is for feedthrough
+PHY-3001 : eco cells: (15 64 3) is for feedthrough
+PHY-3001 : eco cells: (15 69 0) is for feedthrough
+PHY-3001 : eco cells: (17 4 3) is for feedthrough
+PHY-3001 : eco cells: (17 5 0) is for feedthrough
+PHY-3001 : eco cells: (17 5 2) is for feedthrough
+PHY-3001 : eco cells: (17 10 0) is for feedthrough
+PHY-3001 : eco cells: (17 13 0) is for feedthrough
+PHY-3001 : eco cells: (17 31 0) is for feedthrough
+PHY-3001 : eco cells: (17 33 2) is for feedthrough
+PHY-3001 : eco cells: (17 41 0) is for feedthrough
+PHY-3001 : eco cells: (17 51 2) is for feedthrough
+PHY-3001 : eco cells: (17 52 0) is for feedthrough
+PHY-3001 : eco cells: (17 53 2) is for feedthrough
+PHY-3001 : eco cells: (17 59 3) is for feedthrough
+PHY-3001 : eco cells: (17 60 0) is for feedthrough
+PHY-3001 : eco cells: (17 65 2) is for feedthrough
+PHY-3001 : eco cells: (18 5 3) is for feedthrough
+PHY-3001 : eco cells: (18 11 3) is for feedthrough
+PHY-3001 : eco cells: (18 15 1) is for feedthrough
+PHY-3001 : eco cells: (18 15 2) is for feedthrough
+PHY-3001 : eco cells: (18 16 2) is for feedthrough
+PHY-3001 : eco cells: (18 22 1) is for feedthrough
+PHY-3001 : eco cells: (18 23 0) is for feedthrough
+PHY-3001 : eco cells: (18 24 1) is for feedthrough
+PHY-3001 : eco cells: (18 25 1) is for feedthrough
+PHY-3001 : eco cells: (18 25 2) is for feedthrough
+PHY-3001 : eco cells: (18 28 1) is for feedthrough
+PHY-3001 : eco cells: (18 29 0) is for feedthrough
+PHY-3001 : eco cells: (18 31 1) is for feedthrough
+PHY-3001 : eco cells: (18 35 1) is for feedthrough
+PHY-3001 : eco cells: (18 52 1) is for feedthrough
+PHY-3001 : eco cells: (18 53 0) is for feedthrough
+PHY-3001 : eco cells: (18 56 2) is for feedthrough
+PHY-3001 : eco cells: (18 58 2) is for feedthrough
+PHY-3001 : eco cells: (18 62 3) is for feedthrough
+PHY-3001 : eco cells: (18 65 2) is for feedthrough
+PHY-3001 : eco cells: (18 66 1) is for feedthrough
+PHY-3001 : eco cells: (19 3 3) is for feedthrough
+PHY-3001 : eco cells: (19 13 3) is for feedthrough
+PHY-3001 : eco cells: (19 15 1) is for feedthrough
+PHY-3001 : eco cells: (19 15 3) is for feedthrough
+PHY-3001 : eco cells: (19 16 1) is for feedthrough
+PHY-3001 : eco cells: (19 19 0) is for feedthrough
+PHY-3001 : eco cells: (19 22 3) is for feedthrough
+PHY-3001 : eco cells: (19 24 1) is for feedthrough
+PHY-3001 : eco cells: (19 24 2) is for feedthrough
+PHY-3001 : eco cells: (19 25 0) is for feedthrough
+PHY-3001 : eco cells: (19 26 0) is for feedthrough
+PHY-3001 : eco cells: (19 27 2) is for feedthrough
+PHY-3001 : eco cells: (19 30 1) is for feedthrough
+PHY-3001 : eco cells: (19 32 3) is for feedthrough
+PHY-3001 : eco cells: (19 34 1) is for feedthrough
+PHY-3001 : eco cells: (19 60 0) is for feedthrough
+PHY-3001 : eco cells: (19 63 0) is for feedthrough
+PHY-3001 : eco cells: (20 4 0) is for feedthrough
+PHY-3001 : eco cells: (20 5 3) is for feedthrough
+PHY-3001 : eco cells: (20 12 1) is for feedthrough
+PHY-3001 : eco cells: (20 14 1) is for feedthrough
+PHY-3001 : eco cells: (20 14 3) is for feedthrough
+PHY-3001 : eco cells: (20 16 0) is for feedthrough
+PHY-3001 : eco cells: (20 17 3) is for feedthrough
+PHY-3001 : eco cells: (20 26 1) is for feedthrough
+PHY-3001 : eco cells: (20 28 2) is for feedthrough
+PHY-3001 : eco cells: (20 29 2) is for feedthrough
+PHY-3001 : eco cells: (20 31 0) is for feedthrough
+PHY-3001 : eco cells: (20 33 0) is for feedthrough
+PHY-3001 : eco cells: (20 45 0) is for feedthrough
+PHY-3001 : eco cells: (20 53 0) is for feedthrough
+PHY-3001 : eco cells: (20 53 2) is for feedthrough
+PHY-3001 : eco cells: (20 55 0) is for feedthrough
+PHY-3001 : eco cells: (20 56 3) is for feedthrough
+PHY-3001 : eco cells: (20 57 2) is for feedthrough
+PHY-3001 : eco cells: (20 61 0) is for feedthrough
+PHY-3001 : eco cells: (20 61 1) is for feedthrough
+PHY-3001 : eco cells: (20 68 1) is for feedthrough
+PHY-3001 : eco cells: (21 2 0) is for feedthrough
+PHY-3001 : eco cells: (21 6 1) is for feedthrough
+PHY-3001 : eco cells: (21 8 3) is for feedthrough
+PHY-3001 : eco cells: (21 12 0) is for feedthrough
+PHY-3001 : eco cells: (21 21 3) is for feedthrough
+PHY-3001 : eco cells: (21 22 1) is for feedthrough
+PHY-3001 : eco cells: (21 25 0) is for feedthrough
+PHY-3001 : eco cells: (21 26 0) is for feedthrough
+PHY-3001 : eco cells: (21 48 2) is for feedthrough
+PHY-3001 : eco cells: (21 57 1) is for feedthrough
+PHY-3001 : eco cells: (21 59 2) is for feedthrough
+PHY-3001 : eco cells: (21 62 0) is for feedthrough
+PHY-3001 : eco cells: (21 63 2) is for feedthrough
+PHY-3001 : eco cells: (21 66 0) is for feedthrough
+PHY-3001 : eco cells: (22 3 0) is for feedthrough
+PHY-3001 : eco cells: (22 4 0) is for feedthrough
+PHY-3001 : eco cells: (22 7 1) is for feedthrough
+PHY-3001 : eco cells: (22 12 1) is for feedthrough
+PHY-3001 : eco cells: (22 16 0) is for feedthrough
+PHY-3001 : eco cells: (22 21 1) is for feedthrough
+PHY-3001 : eco cells: (22 22 1) is for feedthrough
+PHY-3001 : eco cells: (22 25 0) is for feedthrough
+PHY-3001 : eco cells: (22 26 1) is for feedthrough
+PHY-3001 : eco cells: (22 27 0) is for feedthrough
+PHY-3001 : eco cells: (22 29 3) is for feedthrough
+PHY-3001 : eco cells: (22 30 1) is for feedthrough
+PHY-3001 : eco cells: (22 30 3) is for feedthrough
+PHY-3001 : eco cells: (22 32 0) is for feedthrough
+PHY-3001 : eco cells: (22 36 0) is for feedthrough
+PHY-3001 : eco cells: (22 54 2) is for feedthrough
+PHY-3001 : eco cells: (22 55 3) is for feedthrough
+PHY-3001 : eco cells: (23 4 2) is for feedthrough
+PHY-3001 : eco cells: (23 10 2) is for feedthrough
+PHY-3001 : eco cells: (23 21 0) is for feedthrough
+PHY-3001 : eco cells: (23 23 0) is for feedthrough
+PHY-3001 : eco cells: (23 24 3) is for feedthrough
+PHY-3001 : eco cells: (23 38 0) is for feedthrough
+PHY-3001 : eco cells: (23 39 0) is for feedthrough
+PHY-3001 : eco cells: (25 2 3) is for feedthrough
+PHY-3001 : eco cells: (25 20 0) is for feedthrough
+PHY-3001 : eco cells: (25 25 0) is for feedthrough
+PHY-3001 : eco cells: (25 30 2) is for feedthrough
+PHY-3001 : eco cells: (25 34 3) is for feedthrough
+PHY-3001 : eco cells: (25 57 3) is for feedthrough
+PHY-3001 : eco cells: (26 4 1) is for feedthrough
+PHY-3001 : eco cells: (26 5 1) is for feedthrough
+PHY-3001 : eco cells: (26 13 0) is for feedthrough
+PHY-3001 : eco cells: (26 15 3) is for feedthrough
+PHY-3001 : eco cells: (26 18 0) is for feedthrough
+PHY-3001 : eco cells: (26 24 1) is for feedthrough
+PHY-3001 : eco cells: (26 25 0) is for feedthrough
+PHY-3001 : eco cells: (26 27 1) is for feedthrough
+PHY-3001 : eco cells: (26 28 3) is for feedthrough
+PHY-3001 : eco cells: (26 32 0) is for feedthrough
+PHY-3001 : eco cells: (26 35 2) is for feedthrough
+PHY-3001 : eco cells: (26 35 3) is for feedthrough
+PHY-3001 : eco cells: (26 38 3) is for feedthrough
+PHY-3001 : eco cells: (26 39 2) is for feedthrough
+PHY-3001 : eco cells: (26 45 1) is for feedthrough
+PHY-3001 : eco cells: (26 59 2) is for feedthrough
+PHY-3001 : eco cells: (26 61 1) is for feedthrough
+PHY-3001 : eco cells: (27 19 0) is for feedthrough
+PHY-3001 : eco cells: (27 19 2) is for feedthrough
+PHY-3001 : eco cells: (27 25 0) is for feedthrough
+PHY-3001 : eco cells: (27 26 2) is for feedthrough
+PHY-3001 : eco cells: (27 28 1) is for feedthrough
+PHY-3001 : eco cells: (27 33 2) is for feedthrough
+PHY-3001 : eco cells: (27 40 0) is for feedthrough
+PHY-3001 : eco cells: (27 46 2) is for feedthrough
+PHY-3001 : eco cells: (27 52 2) is for feedthrough
+PHY-3001 : eco cells: (27 62 1) is for feedthrough
+PHY-3001 : eco cells: (28 3 2) is for feedthrough
+PHY-3001 : eco cells: (28 18 1) is for feedthrough
+PHY-3001 : eco cells: (28 23 3) is for feedthrough
+PHY-3001 : eco cells: (28 27 2) is for feedthrough
+PHY-3001 : eco cells: (28 36 0) is for feedthrough
+PHY-3001 : eco cells: (28 36 2) is for feedthrough
+PHY-3001 : eco cells: (28 40 2) is for feedthrough
+PHY-3001 : eco cells: (28 43 0) is for feedthrough
+PHY-3001 : eco cells: (28 44 2) is for feedthrough
+PHY-3001 : eco cells: (28 47 0) is for feedthrough
+PHY-3001 : eco cells: (28 53 2) is for feedthrough
+PHY-3001 : eco cells: (28 61 0) is for feedthrough
+PHY-3001 : eco cells: (28 61 2) is for feedthrough
+PHY-3001 : eco cells: (29 2 2) is for feedthrough
+PHY-3001 : eco cells: (29 9 0) is for feedthrough
+PHY-3001 : eco cells: (29 18 1) is for feedthrough
+PHY-3001 : eco cells: (29 23 3) is for feedthrough
+PHY-3001 : eco cells: (29 26 1) is for feedthrough
+PHY-3001 : eco cells: (29 31 1) is for feedthrough
+PHY-3001 : eco cells: (29 32 2) is for feedthrough
+PHY-3001 : eco cells: (29 33 3) is for feedthrough
+PHY-3001 : eco cells: (29 34 0) is for feedthrough
+PHY-3001 : eco cells: (29 36 0) is for feedthrough
+PHY-3001 : eco cells: (29 40 2) is for feedthrough
+PHY-3001 : eco cells: (29 45 0) is for feedthrough
+PHY-3001 : eco cells: (29 66 0) is for feedthrough
+PHY-3001 : eco cells: (30 2 2) is for feedthrough
+PHY-3001 : eco cells: (30 24 1) is for feedthrough
+PHY-3001 : eco cells: (30 28 1) is for feedthrough
+PHY-3001 : eco cells: (30 34 0) is for feedthrough
+PHY-3001 : eco cells: (30 36 0) is for feedthrough
+PHY-3001 : eco cells: (30 37 2) is for feedthrough
+PHY-3001 : eco cells: (30 37 3) is for feedthrough
+PHY-3001 : eco cells: (30 46 1) is for feedthrough
+PHY-3001 : eco cells: (30 54 3) is for feedthrough
+PHY-3001 : eco cells: (31 2 2) is for feedthrough
+PHY-3001 : eco cells: (31 4 2) is for feedthrough
+PHY-3001 : eco cells: (31 10 2) is for feedthrough
+PHY-3001 : eco cells: (31 34 1) is for feedthrough
+PHY-3001 : eco cells: (31 35 0) is for feedthrough
+PHY-3001 : eco cells: (31 35 3) is for feedthrough
+PHY-3001 : eco cells: (31 36 0) is for feedthrough
+PHY-3001 : eco cells: (31 37 0) is for feedthrough
+PHY-3001 : eco cells: (31 39 3) is for feedthrough
+PHY-3001 : eco cells: (31 53 0) is for feedthrough
+PHY-3001 : eco cells: (33 32 0) is for feedthrough
+PHY-3001 : eco cells: (33 33 2) is for feedthrough
+PHY-3001 : eco cells: (33 34 2) is for feedthrough
+PHY-3001 : eco cells: (33 35 1) is for feedthrough
+PHY-3001 : eco cells: (33 35 2) is for feedthrough
+PHY-3001 : eco cells: (33 38 2) is for feedthrough
+PHY-3001 : eco cells: (33 60 2) is for feedthrough
+PHY-3001 : eco cells: (34 2 0) is for feedthrough
+PHY-3001 : eco cells: (34 3 0) is for feedthrough
+PHY-3001 : eco cells: (34 28 2) is for feedthrough
+PHY-3001 : eco cells: (34 30 1) is for feedthrough
+PHY-3001 : eco cells: (34 31 2) is for feedthrough
+PHY-3001 : eco cells: (34 32 0) is for feedthrough
+PHY-3001 : eco cells: (34 35 2) is for feedthrough
+PHY-3001 : eco cells: (34 36 1) is for feedthrough
+PHY-3001 : eco cells: (34 37 3) is for feedthrough
+PHY-3001 : eco cells: (34 38 3) is for feedthrough
+PHY-3001 : eco cells: (34 47 1) is for feedthrough
+PHY-3001 : eco cells: (35 4 0) is for feedthrough
+PHY-3001 : eco cells: (35 7 0) is for feedthrough
+PHY-3001 : eco cells: (35 13 0) is for feedthrough
+PHY-3001 : eco cells: (35 15 2) is for feedthrough
+PHY-3001 : eco cells: (35 20 2) is for feedthrough
+PHY-3001 : eco cells: (35 23 2) is for feedthrough
+PHY-3001 : eco cells: (35 27 0) is for feedthrough
+PHY-3001 : eco cells: (35 27 2) is for feedthrough
+PHY-3001 : eco cells: (35 28 0) is for feedthrough
+PHY-3001 : eco cells: (35 33 0) is for feedthrough
+PHY-3001 : eco cells: (35 33 2) is for feedthrough
+PHY-3001 : eco cells: (35 34 0) is for feedthrough
+PHY-3001 : eco cells: (35 34 1) is for feedthrough
+PHY-3001 : eco cells: (35 34 2) is for feedthrough
+PHY-3001 : eco cells: (35 35 3) is for feedthrough
+PHY-3001 : eco cells: (35 36 0) is for feedthrough
+PHY-3001 : eco cells: (35 36 2) is for feedthrough
+PHY-3001 : eco cells: (35 38 0) is for feedthrough
+PHY-3001 : eco cells: (35 38 1) is for feedthrough
+PHY-3001 : eco cells: (35 41 3) is for feedthrough
+PHY-3001 : eco cells: (35 48 0) is for feedthrough
+PHY-3001 : eco cells: (36 1 0) is for feedthrough
+PHY-3001 : eco cells: (36 2 3) is for feedthrough
+PHY-3001 : eco cells: (36 4 1) is for feedthrough
+PHY-3001 : eco cells: (36 22 3) is for feedthrough
+PHY-3001 : eco cells: (36 27 2) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 30 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 0) is for feedthrough
+PHY-3001 : eco cells: (36 31 1) is for feedthrough
+PHY-3001 : eco cells: (36 32 1) is for feedthrough
+PHY-3001 : eco cells: (36 33 1) is for feedthrough
+PHY-3001 : eco cells: (36 33 3) is for feedthrough
+PHY-3001 : eco cells: (36 34 0) is for feedthrough
+PHY-3001 : eco cells: (36 34 1) is for feedthrough
+PHY-3001 : eco cells: (36 36 1) is for feedthrough
+PHY-3001 : eco cells: (36 36 2) is for feedthrough
+PHY-3001 : eco cells: (36 36 3) is for feedthrough
+PHY-3001 : eco cells: (36 37 2) is for feedthrough
+PHY-3001 : eco cells: (36 38 0) is for feedthrough
+PHY-3001 : eco cells: (37 2 1) is for feedthrough
+PHY-3001 : eco cells: (37 4 0) is for feedthrough
+PHY-3001 : eco cells: (37 14 3) is for feedthrough
+PHY-3001 : eco cells: (37 16 0) is for feedthrough
+PHY-3001 : eco cells: (37 27 0) is for feedthrough
+PHY-3001 : eco cells: (37 28 0) is for feedthrough
+PHY-3001 : eco cells: (37 30 1) is for feedthrough
+PHY-3001 : eco cells: (37 30 3) is for feedthrough
+PHY-3001 : eco cells: (37 32 1) is for feedthrough
+PHY-3001 : eco cells: (37 32 2) is for feedthrough
+PHY-3001 : eco cells: (37 40 0) is for feedthrough
+PHY-3001 : eco cells: (37 41 2) is for feedthrough
+PHY-3001 : eco cells: (37 47 2) is for feedthrough
+PHY-3001 : eco cells: (37 61 3) is for feedthrough
+PHY-3001 : eco cells: (37 68 0) is for feedthrough
+PHY-3001 : eco cells: (38 7 2) is for feedthrough
+PHY-3001 : eco cells: (38 20 2) is for feedthrough
+PHY-3001 : eco cells: (38 29 1) is for feedthrough
+PHY-3001 : eco cells: (38 30 0) is for feedthrough
+PHY-3001 : eco cells: (38 30 1) is for feedthrough
+PHY-3001 : eco cells: (38 31 1) is for feedthrough
+PHY-3001 : eco cells: (38 33 2) is for feedthrough
+PHY-3001 : eco cells: (38 34 2) is for feedthrough
+PHY-3001 : eco cells: (38 34 3) is for feedthrough
+PHY-3001 : eco cells: (38 37 1) is for feedthrough
+PHY-3001 : eco cells: (38 38 0) is for feedthrough
+PHY-3001 : eco cells: (38 47 2) is for feedthrough
+PHY-3001 : eco cells: (39 11 3) is for feedthrough
+PHY-3001 : eco cells: (39 31 1) is for feedthrough
+PHY-3001 : eco cells: (39 37 1) is for feedthrough
+PHY-3001 : eco cells: (39 37 2) is for feedthrough
+PHY-3001 : eco cells: (39 39 0) is for feedthrough
+PHY-3001 : eco cells: (39 40 2) is for feedthrough
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3684 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.983142s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.1%)
+
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in 1.523783s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (100.5%)
+
+RUN-1004 : used memory is 1149 MB, reserved memory is 1157 MB, peak memory is 1152 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6743 instances
+RUN-1001 : 3292 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18005 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10088 nets have 2 pins
+RUN-1001 : 6518 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 315 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3292 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1159, peak = 1152.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1174, peak = 1167.
+PHY-1001 : End build detailed router design. 1.961388s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (99.6%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.023937s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (65.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.033294s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (140.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.032102s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.032057s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.5%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.031422s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.031925s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.9%)
+
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1174, peak = 1167.
+PHY-1001 : End phase 1; 0.223227s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1174, peak = 1167.
+PHY-1001 : End initial routed; 0.180270s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 9/16928(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.841 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.414870s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End phase 2; 3.595229s wall, 3.593750s user + 0.000000s system = 3.593750s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.805ns STNS -0.841ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.148527s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.7%)
+
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.403266s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.137969s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.141633s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.137917s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.139457s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.141363s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.143353s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.146537s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (85.3%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.139630s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.142018s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.162477s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.142567s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.152765s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.167926s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (121.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.147162s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.2%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.145540s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.173395s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.139221s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.144311s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.162522s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (125.0%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.138748s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.138522s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.162982s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.139288s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.137016s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.6%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.165796s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (94.2%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.137779s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.136754s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.4%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.140663s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (111.1%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.160135s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (117.1%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.141330s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.137000s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.2%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.137861s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.0%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.163266s wall, 0.203125s user + 0.062500s system = 0.265625s CPU (162.7%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.137071s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.161213s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.136132s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.136508s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.150452s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (93.5%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.136537s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.135879s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.138651s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.2%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.141695s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (110.3%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.138681s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.136793s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.137249s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.138024s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.6%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.136937s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.168504s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.137918s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.141047s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.139615s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.141525s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.136632s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.140972s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.138982s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.140928s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.137261s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.138300s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.4%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.137219s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.161445s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.136290s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (137.6%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.140027s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.164563s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (151.9%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.143403s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (109.0%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.140384s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (133.6%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.140899s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (110.9%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.170917s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.142467s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (109.7%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.141554s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.140259s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.145527s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.166092s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.140664s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (111.1%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.2637e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.140572s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (122.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 9/16928(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.805 | -0.841 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.601861s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End phase 3; 14.843157s wall, 15.031250s user + 0.234375s system = 15.265625s CPU (102.8%)
+
+PHY-1001 : 563 feed throughs used by 434 nets
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End export database. 2.478811s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (100.2%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x14y42_w2beg5), nets: sampling_fe_a/u_ad_sampling/dpi_mode_d0[1] u_bus_top/u_local_bus_slve_cis/reg1[6]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in 24.447851s wall, 24.625000s user + 0.234375s system = 24.859375s CPU (101.7%)
+
+RUN-1004 : used memory is 1157 MB, reserved memory is 1163 MB, peak memory is 1169 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x14y42_w2beg5), nets: sampling_fe_a/u_ad_sampling/dpi_mode_d0[1] u_bus_top/u_local_bus_slve_cis/reg1[6]
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in 174.367913s wall, 214.453125s user + 0.734375s system = 215.187500s CPU (123.4%)
+
+RUN-1004 : used memory is 1157 MB, reserved memory is 1163 MB, peak memory is 1169 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_112242.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_112903.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_112903.log
new file mode 100644
index 0000000..f63d25d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_112903.log
@@ -0,0 +1,1968 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 11:29:03 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.337165s wall, 2.218750s user + 0.093750s system = 2.312500s CPU (98.9%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18150 instances
+RUN-0007 : 7700 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20727 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13212 nets have 2 pins
+RUN-1001 : 6477 nets have [3 - 5] pins
+RUN-1001 : 611 nets have [6 - 10] pins
+RUN-1001 : 187 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18148 instances, 7700 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6098 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84699, tnet num: 20549, tinst num: 18148, tnode num: 115428, tedge num: 135050.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.243146s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.6%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 517 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.105801s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (100.2%)
+
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.16241e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18148.
+PHY-3001 : Level 1 #clusters 2003.
+PHY-3001 : End clustering; 0.143818s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (119.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35125e+06, overlap = 462.812
+PHY-3002 : Step(2): len = 1.25009e+06, overlap = 531.219
+PHY-3002 : Step(3): len = 849708, overlap = 604.625
+PHY-3002 : Step(4): len = 780016, overlap = 644.5
+PHY-3002 : Step(5): len = 589263, overlap = 785.781
+PHY-3002 : Step(6): len = 538333, overlap = 849.375
+PHY-3002 : Step(7): len = 450402, overlap = 958.75
+PHY-3002 : Step(8): len = 419486, overlap = 987.656
+PHY-3002 : Step(9): len = 376517, overlap = 1039.44
+PHY-3002 : Step(10): len = 354911, overlap = 1075.34
+PHY-3002 : Step(11): len = 311474, overlap = 1134.22
+PHY-3002 : Step(12): len = 298875, overlap = 1164.62
+PHY-3002 : Step(13): len = 262013, overlap = 1186.19
+PHY-3002 : Step(14): len = 253178, overlap = 1212.16
+PHY-3002 : Step(15): len = 223591, overlap = 1245.28
+PHY-3002 : Step(16): len = 212911, overlap = 1266.97
+PHY-3002 : Step(17): len = 193615, overlap = 1315.88
+PHY-3002 : Step(18): len = 182598, overlap = 1358.81
+PHY-3002 : Step(19): len = 169061, overlap = 1386.56
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.40475e-06
+PHY-3002 : Step(20): len = 171377, overlap = 1342.19
+PHY-3002 : Step(21): len = 213175, overlap = 1275.97
+PHY-3002 : Step(22): len = 214714, overlap = 1163.28
+PHY-3002 : Step(23): len = 215505, overlap = 1122.25
+PHY-3002 : Step(24): len = 211997, overlap = 1102.88
+PHY-3002 : Step(25): len = 211298, overlap = 1053.56
+PHY-3002 : Step(26): len = 206994, overlap = 1018.38
+PHY-3002 : Step(27): len = 203698, overlap = 1033.5
+PHY-3002 : Step(28): len = 199720, overlap = 1057.88
+PHY-3002 : Step(29): len = 196875, overlap = 1043.06
+PHY-3002 : Step(30): len = 193612, overlap = 1045.91
+PHY-3002 : Step(31): len = 191784, overlap = 1041.69
+PHY-3002 : Step(32): len = 189796, overlap = 1049.56
+PHY-3002 : Step(33): len = 188371, overlap = 1043.47
+PHY-3002 : Step(34): len = 186071, overlap = 1053.19
+PHY-3002 : Step(35): len = 184605, overlap = 1051.62
+PHY-3002 : Step(36): len = 183669, overlap = 1038.59
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.80951e-06
+PHY-3002 : Step(37): len = 189176, overlap = 1025.09
+PHY-3002 : Step(38): len = 202558, overlap = 974.312
+PHY-3002 : Step(39): len = 208921, overlap = 946.906
+PHY-3002 : Step(40): len = 216055, overlap = 955.406
+PHY-3002 : Step(41): len = 218337, overlap = 950.656
+PHY-3002 : Step(42): len = 219540, overlap = 926.875
+PHY-3002 : Step(43): len = 218554, overlap = 933.062
+PHY-3002 : Step(44): len = 218510, overlap = 937.625
+PHY-3002 : Step(45): len = 216986, overlap = 918.969
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.61902e-06
+PHY-3002 : Step(46): len = 226399, overlap = 903.031
+PHY-3002 : Step(47): len = 244256, overlap = 849.531
+PHY-3002 : Step(48): len = 253532, overlap = 782.469
+PHY-3002 : Step(49): len = 258937, overlap = 727.094
+PHY-3002 : Step(50): len = 260834, overlap = 716.031
+PHY-3002 : Step(51): len = 262534, overlap = 716.781
+PHY-3002 : Step(52): len = 261137, overlap = 696.969
+PHY-3002 : Step(53): len = 261334, overlap = 665.75
+PHY-3002 : Step(54): len = 260314, overlap = 661.531
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.1238e-05
+PHY-3002 : Step(55): len = 275805, overlap = 625.875
+PHY-3002 : Step(56): len = 289506, overlap = 583.406
+PHY-3002 : Step(57): len = 296858, overlap = 547.75
+PHY-3002 : Step(58): len = 302489, overlap = 547.031
+PHY-3002 : Step(59): len = 301472, overlap = 542.125
+PHY-3002 : Step(60): len = 303485, overlap = 539.156
+PHY-3002 : Step(61): len = 302642, overlap = 555.344
+PHY-3002 : Step(62): len = 303630, overlap = 546.844
+PHY-3002 : Step(63): len = 302773, overlap = 543.812
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.24761e-05
+PHY-3002 : Step(64): len = 319444, overlap = 528.5
+PHY-3002 : Step(65): len = 336158, overlap = 478.781
+PHY-3002 : Step(66): len = 343640, overlap = 438.094
+PHY-3002 : Step(67): len = 348285, overlap = 413.688
+PHY-3002 : Step(68): len = 349093, overlap = 391.906
+PHY-3002 : Step(69): len = 349495, overlap = 388.188
+PHY-3002 : Step(70): len = 347923, overlap = 376.75
+PHY-3002 : Step(71): len = 348147, overlap = 368.812
+PHY-3002 : Step(72): len = 348587, overlap = 368.219
+PHY-3002 : Step(73): len = 347929, overlap = 372.75
+PHY-3002 : Step(74): len = 348027, overlap = 371.406
+PHY-3002 : Step(75): len = 348261, overlap = 366.625
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.49521e-05
+PHY-3002 : Step(76): len = 365960, overlap = 369.781
+PHY-3002 : Step(77): len = 380046, overlap = 342.281
+PHY-3002 : Step(78): len = 380568, overlap = 316.094
+PHY-3002 : Step(79): len = 382712, overlap = 303.156
+PHY-3002 : Step(80): len = 385369, overlap = 299.375
+PHY-3002 : Step(81): len = 389410, overlap = 291.094
+PHY-3002 : Step(82): len = 387216, overlap = 283.781
+PHY-3002 : Step(83): len = 393132, overlap = 301.062
+PHY-3002 : Step(84): len = 396491, overlap = 281.688
+PHY-3002 : Step(85): len = 396381, overlap = 269.031
+PHY-3002 : Step(86): len = 392331, overlap = 262.75
+PHY-3002 : Step(87): len = 395196, overlap = 255.188
+PHY-3002 : Step(88): len = 397112, overlap = 249.344
+PHY-3002 : Step(89): len = 399968, overlap = 271.25
+PHY-3002 : Step(90): len = 396718, overlap = 268.375
+PHY-3002 : Step(91): len = 396791, overlap = 268.094
+PHY-3002 : Step(92): len = 397464, overlap = 255.781
+PHY-3002 : Step(93): len = 397731, overlap = 267.844
+PHY-3002 : Step(94): len = 394594, overlap = 268.562
+PHY-3002 : Step(95): len = 394069, overlap = 250.938
+PHY-3002 : Step(96): len = 393344, overlap = 251.344
+PHY-3002 : Step(97): len = 393969, overlap = 244.781
+PHY-3002 : Step(98): len = 392215, overlap = 238.594
+PHY-3002 : Step(99): len = 392668, overlap = 230.188
+PHY-3002 : Step(100): len = 393225, overlap = 237.875
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.99042e-05
+PHY-3002 : Step(101): len = 409405, overlap = 241.531
+PHY-3002 : Step(102): len = 417893, overlap = 239.219
+PHY-3002 : Step(103): len = 415236, overlap = 230.438
+PHY-3002 : Step(104): len = 416624, overlap = 227.312
+PHY-3002 : Step(105): len = 420251, overlap = 223.438
+PHY-3002 : Step(106): len = 422943, overlap = 227.812
+PHY-3002 : Step(107): len = 422117, overlap = 224.656
+PHY-3002 : Step(108): len = 423174, overlap = 218.406
+PHY-3002 : Step(109): len = 424424, overlap = 227.281
+PHY-3002 : Step(110): len = 425726, overlap = 223.938
+PHY-3002 : Step(111): len = 423676, overlap = 222.469
+PHY-3002 : Step(112): len = 423849, overlap = 229.031
+PHY-3002 : Step(113): len = 425108, overlap = 232.531
+PHY-3002 : Step(114): len = 426161, overlap = 233.281
+PHY-3002 : Step(115): len = 424784, overlap = 230.625
+PHY-3002 : Step(116): len = 425190, overlap = 236.531
+PHY-3002 : Step(117): len = 426545, overlap = 235.844
+PHY-3002 : Step(118): len = 427402, overlap = 239.938
+PHY-3002 : Step(119): len = 425838, overlap = 241.375
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000179808
+PHY-3002 : Step(120): len = 436840, overlap = 249.281
+PHY-3002 : Step(121): len = 445411, overlap = 244.844
+PHY-3002 : Step(122): len = 445646, overlap = 242.562
+PHY-3002 : Step(123): len = 446439, overlap = 234.281
+PHY-3002 : Step(124): len = 449486, overlap = 232.5
+PHY-3002 : Step(125): len = 451276, overlap = 234.375
+PHY-3002 : Step(126): len = 450236, overlap = 227.188
+PHY-3002 : Step(127): len = 451220, overlap = 219.781
+PHY-3002 : Step(128): len = 452714, overlap = 214.312
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000359617
+PHY-3002 : Step(129): len = 461923, overlap = 210.094
+PHY-3002 : Step(130): len = 470617, overlap = 212.094
+PHY-3002 : Step(131): len = 473049, overlap = 203.969
+PHY-3002 : Step(132): len = 475599, overlap = 195.844
+PHY-3002 : Step(133): len = 478380, overlap = 191.938
+PHY-3002 : Step(134): len = 480736, overlap = 188.469
+PHY-3002 : Step(135): len = 480473, overlap = 186.625
+PHY-3002 : Step(136): len = 480708, overlap = 186.312
+PHY-3002 : Step(137): len = 482574, overlap = 188.562
+PHY-3002 : Step(138): len = 484053, overlap = 183.656
+PHY-3002 : Step(139): len = 483656, overlap = 185.688
+PHY-3002 : Step(140): len = 484407, overlap = 177.312
+PHY-3002 : Step(141): len = 485298, overlap = 174.688
+PHY-3002 : Step(142): len = 486103, overlap = 171.562
+PHY-3002 : Step(143): len = 485596, overlap = 174.438
+PHY-3002 : Step(144): len = 485590, overlap = 171.906
+PHY-3002 : Step(145): len = 486331, overlap = 172.188
+PHY-3002 : Step(146): len = 486545, overlap = 168.906
+PHY-3002 : Step(147): len = 485458, overlap = 166.938
+PHY-3002 : Step(148): len = 485154, overlap = 163.844
+PHY-3002 : Step(149): len = 485519, overlap = 162.5
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000698662
+PHY-3002 : Step(150): len = 491135, overlap = 159.562
+PHY-3002 : Step(151): len = 497963, overlap = 153.625
+PHY-3002 : Step(152): len = 499960, overlap = 152.781
+PHY-3002 : Step(153): len = 501441, overlap = 151.781
+PHY-3002 : Step(154): len = 504519, overlap = 159.438
+PHY-3002 : Step(155): len = 506118, overlap = 154.875
+PHY-3002 : Step(156): len = 505071, overlap = 148
+PHY-3002 : Step(157): len = 504804, overlap = 149.031
+PHY-3002 : Step(158): len = 505428, overlap = 154.531
+PHY-3002 : Step(159): len = 505945, overlap = 157.312
+PHY-3002 : Step(160): len = 504999, overlap = 155.344
+PHY-3002 : Step(161): len = 504814, overlap = 152.219
+PHY-3002 : Step(162): len = 505891, overlap = 155.625
+PHY-3002 : Step(163): len = 506612, overlap = 151.562
+PHY-3002 : Step(164): len = 506119, overlap = 151.062
+PHY-3002 : Step(165): len = 506178, overlap = 152.312
+PHY-3002 : Step(166): len = 506830, overlap = 150.219
+PHY-3002 : Step(167): len = 507031, overlap = 148.938
+PHY-3002 : Step(168): len = 506746, overlap = 150.938
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0011687
+PHY-3002 : Step(169): len = 509858, overlap = 149.094
+PHY-3002 : Step(170): len = 514194, overlap = 153.906
+PHY-3002 : Step(171): len = 514559, overlap = 149.656
+PHY-3002 : Step(172): len = 515110, overlap = 143.438
+PHY-3002 : Step(173): len = 517452, overlap = 136.688
+PHY-3002 : Step(174): len = 519363, overlap = 134.656
+PHY-3002 : Step(175): len = 519172, overlap = 133.688
+PHY-3002 : Step(176): len = 519345, overlap = 140.594
+PHY-3002 : Step(177): len = 520642, overlap = 139.344
+PHY-3002 : Step(178): len = 521118, overlap = 141.812
+PHY-3002 : Step(179): len = 520333, overlap = 140.312
+PHY-3002 : Step(180): len = 520184, overlap = 139.875
+PHY-3002 : Step(181): len = 520896, overlap = 141.031
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00189095
+PHY-3002 : Step(182): len = 522416, overlap = 138.781
+PHY-3002 : Step(183): len = 525360, overlap = 137.906
+PHY-3002 : Step(184): len = 527003, overlap = 138.531
+PHY-3002 : Step(185): len = 528024, overlap = 138.406
+PHY-3002 : Step(186): len = 528771, overlap = 138.344
+PHY-3002 : Step(187): len = 529550, overlap = 137.969
+PHY-3002 : Step(188): len = 530709, overlap = 139.844
+PHY-3002 : Step(189): len = 530709, overlap = 139.844
+PHY-3002 : Step(190): len = 530684, overlap = 137.281
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.016331s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (95.7%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 699072, over cnt = 1624(4%), over = 7402, worst = 39
+PHY-1001 : End global iterations; 0.732239s wall, 0.984375s user + 0.062500s system = 1.046875s CPU (143.0%)
+
+PHY-1001 : Congestion index: top1 = 83.58, top5 = 61.05, top10 = 51.80, top15 = 46.38.
+PHY-3001 : End congestion estimation; 0.989739s wall, 1.234375s user + 0.062500s system = 1.296875s CPU (131.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.932227s wall, 0.875000s user + 0.062500s system = 0.937500s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143591
+PHY-3002 : Step(191): len = 637059, overlap = 93
+PHY-3002 : Step(192): len = 638096, overlap = 94
+PHY-3002 : Step(193): len = 634972, overlap = 86.625
+PHY-3002 : Step(194): len = 633359, overlap = 78.625
+PHY-3002 : Step(195): len = 632091, overlap = 69.25
+PHY-3002 : Step(196): len = 631076, overlap = 63.1562
+PHY-3002 : Step(197): len = 629283, overlap = 59.9375
+PHY-3002 : Step(198): len = 629274, overlap = 57.3438
+PHY-3002 : Step(199): len = 627944, overlap = 51.9688
+PHY-3002 : Step(200): len = 627415, overlap = 48.5625
+PHY-3002 : Step(201): len = 626183, overlap = 47.7812
+PHY-3002 : Step(202): len = 626580, overlap = 49.75
+PHY-3002 : Step(203): len = 626520, overlap = 50.5625
+PHY-3002 : Step(204): len = 626582, overlap = 51.5938
+PHY-3002 : Step(205): len = 626872, overlap = 50.5312
+PHY-3002 : Step(206): len = 627414, overlap = 48.625
+PHY-3002 : Step(207): len = 628190, overlap = 45.1562
+PHY-3002 : Step(208): len = 626552, overlap = 43.875
+PHY-3002 : Step(209): len = 625586, overlap = 40.7812
+PHY-3002 : Step(210): len = 624683, overlap = 40.375
+PHY-3002 : Step(211): len = 623459, overlap = 38.5938
+PHY-3002 : Step(212): len = 623516, overlap = 37.9062
+PHY-3002 : Step(213): len = 621399, overlap = 39.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000287183
+PHY-3002 : Step(214): len = 624370, overlap = 39.375
+PHY-3002 : Step(215): len = 625993, overlap = 40.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 133/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708008, over cnt = 2647(7%), over = 11674, worst = 56
+PHY-1001 : End global iterations; 1.830325s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (133.2%)
+
+PHY-1001 : Congestion index: top1 = 79.35, top5 = 64.05, top10 = 56.18, top15 = 51.30.
+PHY-3001 : End congestion estimation; 2.114259s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (128.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.978212s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.22371e-05
+PHY-3002 : Step(216): len = 624826, overlap = 263.094
+PHY-3002 : Step(217): len = 627528, overlap = 235.375
+PHY-3002 : Step(218): len = 624599, overlap = 211
+PHY-3002 : Step(219): len = 622126, overlap = 189.75
+PHY-3002 : Step(220): len = 621960, overlap = 173.656
+PHY-3002 : Step(221): len = 618270, overlap = 162.188
+PHY-3002 : Step(222): len = 615299, overlap = 156.781
+PHY-3002 : Step(223): len = 614948, overlap = 154.438
+PHY-3002 : Step(224): len = 611710, overlap = 151
+PHY-3002 : Step(225): len = 610180, overlap = 152.281
+PHY-3002 : Step(226): len = 608033, overlap = 160
+PHY-3002 : Step(227): len = 605765, overlap = 158.094
+PHY-3002 : Step(228): len = 604714, overlap = 155.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000184474
+PHY-3002 : Step(229): len = 605362, overlap = 155.75
+PHY-3002 : Step(230): len = 609435, overlap = 144.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000347186
+PHY-3002 : Step(231): len = 614538, overlap = 131.219
+PHY-3002 : Step(232): len = 622493, overlap = 120.625
+PHY-3002 : Step(233): len = 629150, overlap = 112.312
+PHY-3002 : Step(234): len = 628651, overlap = 113.906
+PHY-3002 : Step(235): len = 628328, overlap = 112.031
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84699, tnet num: 20549, tinst num: 18148, tnode num: 115428, tedge num: 135050.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.625469s wall, 1.546875s user + 0.078125s system = 1.625000s CPU (100.0%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 566 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 429.44 peak overflow 4.06
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1304/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720040, over cnt = 2912(8%), over = 10922, worst = 26
+PHY-1001 : End global iterations; 1.273716s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (147.2%)
+
+PHY-1001 : Congestion index: top1 = 75.34, top5 = 57.39, top10 = 50.87, top15 = 47.15.
+PHY-1001 : End incremental global routing; 1.642599s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (137.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.986789s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.8%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18017 has valid locations, 313 needs to be replaced
+PHY-3001 : design contains 18415 instances, 7794 luts, 9400 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6213 pins
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 651074
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16753/20994.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733448, over cnt = 2943(8%), over = 10945, worst = 26
+PHY-1001 : End global iterations; 0.233935s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 75.22, top5 = 57.81, top10 = 51.33, top15 = 47.58.
+PHY-3001 : End congestion estimation; 0.505287s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (117.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85776, tnet num: 20816, tinst num: 18415, tnode num: 117052, tedge num: 136670.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.590037s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.3%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 618 MB, peak memory is 715 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20816 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.072175s wall, 3.031250s user + 0.031250s system = 3.062500s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(236): len = 650093, overlap = 2.75
+PHY-3002 : Step(237): len = 649511, overlap = 2.6875
+PHY-3002 : Step(238): len = 649098, overlap = 2.6875
+PHY-3002 : Step(239): len = 648827, overlap = 2.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000130271
+PHY-3002 : Step(240): len = 648870, overlap = 2.65625
+PHY-3002 : Step(241): len = 649130, overlap = 2.65625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000260542
+PHY-3002 : Step(242): len = 649217, overlap = 2.59375
+PHY-3002 : Step(243): len = 651169, overlap = 2.46875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16764/20994.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 732368, over cnt = 2945(8%), over = 10977, worst = 26
+PHY-1001 : End global iterations; 0.229842s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (108.8%)
+
+PHY-1001 : Congestion index: top1 = 75.39, top5 = 57.73, top10 = 51.26, top15 = 47.50.
+PHY-3001 : End congestion estimation; 0.505060s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (102.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20816 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.006586s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00093482
+PHY-3002 : Step(244): len = 650883, overlap = 113.812
+PHY-3002 : Step(245): len = 650870, overlap = 113.375
+PHY-3001 : Final: Len = 650870, Over = 113.375
+PHY-3001 : End incremental placement; 5.850493s wall, 5.937500s user + 0.140625s system = 6.078125s CPU (103.9%)
+
+OPT-1001 : Total overflow 433.84 peak overflow 4.06
+OPT-1001 : End high-fanout net optimization; 9.099953s wall, 9.890625s user + 0.156250s system = 10.046875s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 711, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16856/20994.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733664, over cnt = 2915(8%), over = 10272, worst = 26
+PHY-1002 : len = 793984, over cnt = 1899(5%), over = 4599, worst = 26
+PHY-1002 : len = 824216, over cnt = 939(2%), over = 2137, worst = 26
+PHY-1002 : len = 845168, over cnt = 393(1%), over = 873, worst = 22
+PHY-1002 : len = 860232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.068110s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (141.3%)
+
+PHY-1001 : Congestion index: top1 = 58.58, top5 = 50.54, top10 = 46.62, top15 = 44.16.
+OPT-1001 : End congestion update; 2.357732s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (135.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20816 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.868441s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.8%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 96 cells processed and 14100 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 54 cells processed and 12500 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 46 cells processed and 6700 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 34 cells processed and 4396 slack improved
+OPT-0007 : Iter 5: improved WNS 171 TNS 0 NUM_FEPS 0 with 12 cells processed and 650 slack improved
+OPT-0007 : Iter 6: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 100 slack improved
+OPT-1001 : End bottleneck based optimization; 3.911705s wall, 4.750000s user + 0.000000s system = 4.750000s CPU (121.4%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 696, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16835/20996.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861200, over cnt = 94(0%), over = 141, worst = 5
+PHY-1002 : len = 861368, over cnt = 46(0%), over = 54, worst = 3
+PHY-1002 : len = 861800, over cnt = 15(0%), over = 16, worst = 2
+PHY-1002 : len = 861936, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 862224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.811891s wall, 0.859375s user + 0.062500s system = 0.921875s CPU (113.5%)
+
+PHY-1001 : Congestion index: top1 = 58.94, top5 = 50.60, top10 = 46.61, top15 = 44.16.
+OPT-1001 : End congestion update; 1.106091s wall, 1.156250s user + 0.062500s system = 1.218750s CPU (110.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20818 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.870125s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 28 cells processed and 7200 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.125419s wall, 2.171875s user + 0.062500s system = 2.234375s CPU (105.1%)
+
+OPT-1001 : Current memory(MB): used = 703, reserve = 698, peak = 733.
+OPT-1001 : End physical optimization; 17.099086s wall, 18.640625s user + 0.375000s system = 19.015625s CPU (111.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7794 LUT to BLE ...
+SYN-4008 : Packed 7794 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6255 remaining SEQ's ...
+SYN-4005 : Packed 3854 SEQ with LUT/SLICE
+SYN-4006 : 1084 single LUT's are left
+SYN-4006 : 2401 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10195/13982 primitive instances ...
+PHY-3001 : End packing; 1.926668s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (98.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6855 instances
+RUN-1001 : 3353 mslices, 3354 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17982 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10104 nets have 2 pins
+RUN-1001 : 6522 nets have [3 - 5] pins
+RUN-1001 : 719 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 297 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6853 instances, 6707 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3611 pins
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 664550, Over = 255.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7595/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812920, over cnt = 2027(5%), over = 3333, worst = 8
+PHY-1002 : len = 820232, over cnt = 1375(3%), over = 1979, worst = 7
+PHY-1002 : len = 836128, over cnt = 525(1%), over = 718, worst = 6
+PHY-1002 : len = 844192, over cnt = 179(0%), over = 231, worst = 3
+PHY-1002 : len = 848632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.906416s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 58.90, top5 = 51.24, top10 = 46.90, top15 = 44.16.
+PHY-3001 : End congestion estimation; 2.333739s wall, 3.078125s user + 0.015625s system = 3.093750s CPU (132.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71926, tnet num: 17804, tinst num: 6853, tnode num: 94627, tedge num: 119508.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.783626s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (99.9%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 620 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.704538s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.37586e-05
+PHY-3002 : Step(246): len = 653922, overlap = 248.5
+PHY-3002 : Step(247): len = 647194, overlap = 250.75
+PHY-3002 : Step(248): len = 642375, overlap = 254
+PHY-3002 : Step(249): len = 638719, overlap = 264.75
+PHY-3002 : Step(250): len = 636986, overlap = 264.25
+PHY-3002 : Step(251): len = 634508, overlap = 265.75
+PHY-3002 : Step(252): len = 633779, overlap = 263.5
+PHY-3002 : Step(253): len = 631877, overlap = 262.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000107517
+PHY-3002 : Step(254): len = 635464, overlap = 255.25
+PHY-3002 : Step(255): len = 640261, overlap = 247.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000215034
+PHY-3002 : Step(256): len = 643424, overlap = 242
+PHY-3002 : Step(257): len = 654780, overlap = 233.25
+PHY-3002 : Step(258): len = 655889, overlap = 234.25
+PHY-3002 : Step(259): len = 656677, overlap = 228
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.381595s wall, 0.437500s user + 0.671875s system = 1.109375s CPU (290.7%)
+
+PHY-3001 : Trial Legalized: Len = 739174
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 997/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844896, over cnt = 2673(7%), over = 4585, worst = 8
+PHY-1002 : len = 864720, over cnt = 1466(4%), over = 2107, worst = 8
+PHY-1002 : len = 881728, over cnt = 547(1%), over = 768, worst = 8
+PHY-1002 : len = 891688, over cnt = 182(0%), over = 240, worst = 4
+PHY-1002 : len = 894184, over cnt = 71(0%), over = 84, worst = 4
+PHY-1001 : End global iterations; 2.544869s wall, 3.734375s user + 0.046875s system = 3.781250s CPU (148.6%)
+
+PHY-1001 : Congestion index: top1 = 54.89, top5 = 49.54, top10 = 46.58, top15 = 44.67.
+PHY-3001 : End congestion estimation; 3.050575s wall, 4.234375s user + 0.046875s system = 4.281250s CPU (140.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.238996s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000159422
+PHY-3002 : Step(260): len = 712692, overlap = 43
+PHY-3002 : Step(261): len = 698143, overlap = 67.75
+PHY-3002 : Step(262): len = 686491, overlap = 96.25
+PHY-3002 : Step(263): len = 678360, overlap = 111.75
+PHY-3002 : Step(264): len = 671808, overlap = 139.75
+PHY-3002 : Step(265): len = 669216, overlap = 154.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000318845
+PHY-3002 : Step(266): len = 673167, overlap = 149
+PHY-3002 : Step(267): len = 676955, overlap = 148.5
+PHY-3002 : Step(268): len = 676777, overlap = 147.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000593005
+PHY-3002 : Step(269): len = 680949, overlap = 149.5
+PHY-3002 : Step(270): len = 689144, overlap = 145
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.027671s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (112.9%)
+
+PHY-3001 : Legalized: Len = 721585, Over = 0
+PHY-3001 : Spreading special nets. 424 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.114932s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (95.2%)
+
+PHY-3001 : 623 instances has been re-located, deltaX = 227, deltaY = 334, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 731073, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71926, tnet num: 17804, tinst num: 6856, tnode num: 94627, tedge num: 119508.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 2.027102s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (99.4%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 608 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4539/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 851480, over cnt = 2497(7%), over = 4098, worst = 8
+PHY-1002 : len = 865008, over cnt = 1493(4%), over = 2163, worst = 8
+PHY-1002 : len = 884672, over cnt = 558(1%), over = 729, worst = 5
+PHY-1002 : len = 889624, over cnt = 294(0%), over = 380, worst = 4
+PHY-1002 : len = 896384, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.254665s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (151.8%)
+
+PHY-1001 : Congestion index: top1 = 54.61, top5 = 49.10, top10 = 45.95, top15 = 43.89.
+PHY-1001 : End incremental global routing; 2.664816s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (143.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.993694s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (100.6%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6764 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3690 pins
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 733920
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16343/17999.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899200, over cnt = 81(0%), over = 91, worst = 3
+PHY-1002 : len = 899280, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 899600, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 899680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.684449s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 54.61, top5 = 49.10, top10 = 45.97, top15 = 43.92.
+PHY-3001 : End congestion estimation; 1.033421s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (102.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72090, tnet num: 17821, tinst num: 6873, tnode num: 94842, tedge num: 119729.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.982333s wall, 1.953125s user + 0.031250s system = 1.984375s CPU (100.1%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 634 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17821 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.241425s wall, 3.203125s user + 0.046875s system = 3.250000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(271): len = 733920, overlap = 0.25
+PHY-3002 : Step(272): len = 733920, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16360/17999.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.140873s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.8%)
+
+PHY-1001 : Congestion index: top1 = 54.61, top5 = 49.10, top10 = 45.97, top15 = 43.92.
+PHY-3001 : End congestion estimation; 0.473311s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17821 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.940024s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000400351
+PHY-3002 : Step(273): len = 733488, overlap = 1.5
+PHY-3002 : Step(274): len = 733468, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006055s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (258.1%)
+
+PHY-3001 : Legalized: Len = 733591, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063642s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 0, maxDist = 0.
+PHY-3001 : Final: Len = 733591, Over = 0
+PHY-3001 : End incremental placement; 6.186634s wall, 6.171875s user + 0.046875s system = 6.218750s CPU (100.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.366723s wall, 11.578125s user + 0.078125s system = 11.656250s CPU (112.4%)
+
+OPT-1001 : Current memory(MB): used = 720, reserve = 718, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16330/17999.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899576, over cnt = 61(0%), over = 71, worst = 4
+PHY-1002 : len = 899656, over cnt = 34(0%), over = 38, worst = 3
+PHY-1002 : len = 899992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.468681s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 54.61, top5 = 49.07, top10 = 46.01, top15 = 43.97.
+OPT-1001 : End congestion update; 0.807137s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (104.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17821 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.765565s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3690 pins
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 736265, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065490s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.3%)
+
+PHY-3001 : 31 instances has been re-located, deltaX = 19, deltaY = 28, maxDist = 3.
+PHY-3001 : Final: Len = 737073, Over = 0
+PHY-3001 : End incremental legalization; 0.426047s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.0%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 51 cells processed and 9872 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3690 pins
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 738130, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064665s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.7%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 10, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 738500, Over = 0
+PHY-3001 : End incremental legalization; 0.411929s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (117.6%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 18 cells processed and 3535 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3690 pins
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 738140, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062116s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.6%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 738452, Over = 0
+PHY-3001 : End incremental legalization; 0.417804s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.0%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 694 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6788 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6876 instances, 6727 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3690 pins
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 738537, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065504s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.4%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 4, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 738599, Over = 0
+PHY-3001 : End incremental legalization; 0.434735s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.6%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 600 slack improved
+OPT-1001 : End bottleneck based optimization; 3.854038s wall, 4.140625s user + 0.015625s system = 4.156250s CPU (107.8%)
+
+OPT-1001 : Current memory(MB): used = 721, reserve = 720, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15971/18001.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904536, over cnt = 165(0%), over = 196, worst = 4
+PHY-1002 : len = 904648, over cnt = 103(0%), over = 110, worst = 2
+PHY-1002 : len = 905496, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 905776, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 905992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.934295s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (107.0%)
+
+PHY-1001 : Congestion index: top1 = 54.63, top5 = 49.26, top10 = 46.23, top15 = 44.13.
+OPT-1001 : End congestion update; 1.301634s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (104.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17823 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.830259s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.7%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6788 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6876 instances, 6727 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3690 pins
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 738851, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.069061s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.5%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 14, deltaY = 10, maxDist = 5.
+PHY-3001 : Final: Len = 739645, Over = 0
+PHY-3001 : End incremental legalization; 0.439319s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (124.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 23 cells processed and 1850 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.741998s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (106.0%)
+
+OPT-1001 : Current memory(MB): used = 721, reserve = 720, peak = 733.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17823 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.826460s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16283/18001.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906784, over cnt = 43(0%), over = 51, worst = 3
+PHY-1002 : len = 906928, over cnt = 24(0%), over = 26, worst = 2
+PHY-1002 : len = 907160, over cnt = 11(0%), over = 12, worst = 2
+PHY-1002 : len = 907288, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.663765s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (101.2%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 49.16, top10 = 46.13, top15 = 44.11.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17823 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.762407s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.172414
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 21.900653s wall, 23.593750s user + 0.109375s system = 23.703125s CPU (108.2%)
+
+RUN-1003 : finish command "place" in 68.129782s wall, 94.218750s user + 4.546875s system = 98.765625s CPU (145.0%)
+
+RUN-1004 : used memory is 594 MB, reserved memory is 600 MB, peak memory is 733 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.784557s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (174.2%)
+
+RUN-1004 : used memory is 595 MB, reserved memory is 601 MB, peak memory is 733 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6878 instances
+RUN-1001 : 3365 mslices, 3362 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18001 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10103 nets have 2 pins
+RUN-1001 : 6522 nets have [3 - 5] pins
+RUN-1001 : 723 nets have [6 - 10] pins
+RUN-1001 : 315 nets have [11 - 20] pins
+RUN-1001 : 310 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72105, tnet num: 17823, tinst num: 6876, tnode num: 94866, tedge num: 119750.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.741021s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.6%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 634 MB, peak memory is 733 MB
+PHY-1001 : 3365 mslices, 3362 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17823 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 835160, over cnt = 2713(7%), over = 4566, worst = 9
+PHY-1002 : len = 854208, over cnt = 1663(4%), over = 2440, worst = 8
+PHY-1002 : len = 878184, over cnt = 540(1%), over = 704, worst = 5
+PHY-1002 : len = 887352, over cnt = 99(0%), over = 110, worst = 4
+PHY-1002 : len = 889592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.188546s wall, 4.406250s user + 0.015625s system = 4.421875s CPU (138.7%)
+
+PHY-1001 : Congestion index: top1 = 54.48, top5 = 48.56, top10 = 45.62, top15 = 43.67.
+PHY-1001 : End global routing; 3.543505s wall, 4.765625s user + 0.015625s system = 4.781250s CPU (134.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 708, reserve = 711, peak = 733.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 985, peak = 982.
+PHY-1001 : End build detailed router design. 4.306532s wall, 4.265625s user + 0.046875s system = 4.312500s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 258608, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.920017s wall, 5.906250s user + 0.015625s system = 5.921875s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 258664, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.472623s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1021, peak = 1017.
+PHY-1001 : End phase 1; 6.405522s wall, 6.390625s user + 0.015625s system = 6.406250s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.24153e+06, over cnt = 1919(0%), over = 1923, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1035, peak = 1031.
+PHY-1001 : End initial routed; 30.218337s wall, 66.890625s user + 0.437500s system = 67.328125s CPU (222.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 39/16924(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.143 | -1.927 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.533416s wall, 3.515625s user + 0.000000s system = 3.515625s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1047, peak = 1044.
+PHY-1001 : End phase 2; 33.751818s wall, 70.406250s user + 0.437500s system = 70.843750s CPU (209.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 10 pins with SWNS -0.756ns STNS -1.417ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.173317s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.2%)
+
+PHY-1022 : len = 2.24154e+06, over cnt = 1922(0%), over = 1926, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.461344s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.208e+06, over cnt = 822(0%), over = 823, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.400069s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (181.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.20281e+06, over cnt = 153(0%), over = 153, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.811396s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (134.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.20352e+06, over cnt = 17(0%), over = 17, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.436238s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (125.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.20398e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.228074s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.20397e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.175771s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 33/16924(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.756 | -1.417 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.475318s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 586 feed throughs used by 419 nets
+PHY-1001 : End commit to database; 2.348579s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1153, peak = 1146.
+PHY-1001 : End phase 3; 9.781195s wall, 11.343750s user + 0.000000s system = 11.343750s CPU (116.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.756ns STNS -1.417ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.163284s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (105.3%)
+
+PHY-1022 : len = 2.20397e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.423753s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.756ns, -1.417ns, 2}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.20397e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.169532s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 33/16924(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.756 | -1.417 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.494806s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 586 feed throughs used by 419 nets
+PHY-1001 : End commit to database; 2.428543s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1161, peak = 1154.
+PHY-1001 : End phase 4; 6.571263s wall, 6.578125s user + 0.000000s system = 6.578125s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.20397e+06
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1166, peak = 1158.
+PHY-1001 : End export database. 0.155413s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.5%)
+
+PHY-1001 : End detail routing; 61.401942s wall, 99.546875s user + 0.500000s system = 100.046875s CPU (162.9%)
+
+RUN-1003 : finish command "route" in 67.836402s wall, 107.187500s user + 0.546875s system = 107.734375s CPU (158.8%)
+
+RUN-1004 : used memory is 1078 MB, reserved memory is 1082 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10197 out of 19600 52.03%
+#reg 9584 out of 19600 48.90%
+#le 12564
+ #lut only 2980 out of 12564 23.72%
+ #reg only 2367 out of 12564 18.84%
+ #lut® 7217 out of 12564 57.44%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1785
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1456
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1348
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 938
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice a_frame_pad_d0_reg_syn_17.q0 135
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/u_ADconfig/reg0_syn_173.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P16 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P39 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P148 LVCMOS33 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P173 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P115 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P66 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12564 |9170 |1027 |9616 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |529 |416 |23 |436 |4 |1 |
+| U_crc16_24b |crc16_24b |36 |36 |0 |20 |0 |0 |
+| U_ecc_gen |ecc_gen |14 |14 |0 |8 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |103 |82 |4 |91 |4 |0 |
+| exdev_ctl_a |exdev_ctl |757 |379 |96 |579 |0 |0 |
+| u_ADconfig |AD_config |185 |139 |25 |143 |0 |0 |
+| u_gen_sp |gen_sp |256 |153 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |735 |375 |96 |554 |0 |0 |
+| u_ADconfig |AD_config |165 |113 |25 |120 |0 |0 |
+| u_gen_sp |gen_sp |251 |159 |71 |115 |0 |0 |
+| sampling_fe_a |sampling_fe |3131 |2561 |306 |2100 |25 |0 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |193 |112 |17 |162 |0 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_sort |sort |2903 |2439 |289 |1903 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2428 |2055 |253 |1532 |22 |0 |
+| channelPart |channel_part_8478 |128 |123 |3 |124 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1947 |1640 |197 |1151 |0 |0 |
+| adc_addr_gen |adc_addr_gen |220 |193 |27 |125 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |26 |23 |3 |16 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |13 |0 |0 |
+| insert |insert |948 |668 |170 |631 |0 |0 |
+| ram_switch_state |ram_switch_state |779 |779 |0 |395 |0 |0 |
+| read_ram_i |read_ram |262 |212 |44 |185 |0 |0 |
+| read_ram_addr |read_ram_addr |213 |173 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |47 |37 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |316 |239 |36 |272 |3 |0 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3222 |2517 |349 |2085 |25 |1 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |102 |17 |159 |0 |0 |
+| u_sort |sort_rev |3000 |2389 |332 |1894 |25 |1 |
+| u0_rdsoft_n |cdc_sync |6 |5 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2599 |2100 |290 |1545 |22 |1 |
+| channelPart |channel_part_8478 |154 |151 |3 |123 |0 |0 |
+| fifo_adc |fifo_adc |56 |47 |9 |40 |0 |1 |
+| ram_switch |ram_switch |2010 |1636 |197 |1144 |0 |0 |
+| adc_addr_gen |adc_addr_gen |200 |173 |27 |97 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |5 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |19 |16 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |14 |11 |3 |5 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| insert |insert |969 |622 |170 |674 |0 |0 |
+| ram_switch_state |ram_switch_state |841 |841 |0 |373 |0 |0 |
+| read_ram_i |read_ram_rev |352 |245 |81 |211 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |209 |73 |164 |0 |0 |
+| read_ram_data |read_ram_data_rev |61 |36 |8 |47 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10041
+ #2 2 4263
+ #3 3 1697
+ #4 4 559
+ #5 5-10 759
+ #6 11-50 574
+ #7 51-100 12
+ #8 >500 1
+ Average 2.71
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.153243s wall, 3.718750s user + 0.046875s system = 3.765625s CPU (174.9%)
+
+RUN-1004 : used memory is 1080 MB, reserved memory is 1083 MB, peak memory is 1158 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72105, tnet num: 17823, tinst num: 6876, tnode num: 94866, tedge num: 119750.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.699612s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (99.3%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1087 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17823 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.569237s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.6%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1092 MB, peak memory is 1158 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6876
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18001, pip num: 167654
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 586
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3251 valid insts, and 468413 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.641977s wall, 63.843750s user + 0.343750s system = 64.187500s CPU (665.7%)
+
+RUN-1004 : used memory is 1247 MB, reserved memory is 1249 MB, peak memory is 1362 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_112903.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_133509.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_133509.log
new file mode 100644
index 0000000..2563049
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_133509.log
@@ -0,0 +1,2168 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 13:35:09 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.180638s wall, 2.046875s user + 0.140625s system = 2.187500s CPU (100.3%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 316 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18150 instances
+RUN-0007 : 7700 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20727 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13212 nets have 2 pins
+RUN-1001 : 6477 nets have [3 - 5] pins
+RUN-1001 : 611 nets have [6 - 10] pins
+RUN-1001 : 187 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 50 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18148 instances, 7700 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6098 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84699, tnet num: 20549, tinst num: 18148, tnode num: 115428, tedge num: 135050.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.135502s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (100.5%)
+
+RUN-1004 : used memory is 534 MB, reserved memory is 517 MB, peak memory is 534 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.911091s wall, 1.890625s user + 0.015625s system = 1.906250s CPU (99.7%)
+
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.16241e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18148.
+PHY-3001 : Level 1 #clusters 2003.
+PHY-3001 : End clustering; 0.127753s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (159.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35107e+06, overlap = 464.875
+PHY-3002 : Step(2): len = 1.25006e+06, overlap = 531
+PHY-3002 : Step(3): len = 848508, overlap = 605.406
+PHY-3002 : Step(4): len = 777754, overlap = 649.281
+PHY-3002 : Step(5): len = 588031, overlap = 784.094
+PHY-3002 : Step(6): len = 536503, overlap = 845.375
+PHY-3002 : Step(7): len = 446306, overlap = 956.344
+PHY-3002 : Step(8): len = 417053, overlap = 987.5
+PHY-3002 : Step(9): len = 375158, overlap = 1044.59
+PHY-3002 : Step(10): len = 351914, overlap = 1064.94
+PHY-3002 : Step(11): len = 309867, overlap = 1135.84
+PHY-3002 : Step(12): len = 293293, overlap = 1155.66
+PHY-3002 : Step(13): len = 263317, overlap = 1203.41
+PHY-3002 : Step(14): len = 244722, overlap = 1239.97
+PHY-3002 : Step(15): len = 222689, overlap = 1257.84
+PHY-3002 : Step(16): len = 209796, overlap = 1291.88
+PHY-3002 : Step(17): len = 186954, overlap = 1326.5
+PHY-3002 : Step(18): len = 179377, overlap = 1375.56
+PHY-3002 : Step(19): len = 163803, overlap = 1392.44
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.30428e-06
+PHY-3002 : Step(20): len = 166071, overlap = 1343.59
+PHY-3002 : Step(21): len = 202942, overlap = 1279.75
+PHY-3002 : Step(22): len = 207378, overlap = 1178.34
+PHY-3002 : Step(23): len = 212006, overlap = 1108.41
+PHY-3002 : Step(24): len = 210133, overlap = 1106.53
+PHY-3002 : Step(25): len = 207718, overlap = 1097.31
+PHY-3002 : Step(26): len = 203154, overlap = 1086.62
+PHY-3002 : Step(27): len = 200451, overlap = 1059.25
+PHY-3002 : Step(28): len = 196879, overlap = 1048.84
+PHY-3002 : Step(29): len = 195848, overlap = 1054.09
+PHY-3002 : Step(30): len = 193513, overlap = 1045.5
+PHY-3002 : Step(31): len = 192229, overlap = 1031.03
+PHY-3002 : Step(32): len = 189599, overlap = 1008.09
+PHY-3002 : Step(33): len = 188914, overlap = 988.75
+PHY-3002 : Step(34): len = 186251, overlap = 972.406
+PHY-3002 : Step(35): len = 185427, overlap = 978.719
+PHY-3002 : Step(36): len = 183832, overlap = 1008.16
+PHY-3002 : Step(37): len = 182350, overlap = 1022.91
+PHY-3002 : Step(38): len = 180775, overlap = 1030.31
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.60856e-06
+PHY-3002 : Step(39): len = 186831, overlap = 998.469
+PHY-3002 : Step(40): len = 198784, overlap = 947
+PHY-3002 : Step(41): len = 202285, overlap = 932.344
+PHY-3002 : Step(42): len = 207549, overlap = 939.312
+PHY-3002 : Step(43): len = 209442, overlap = 941.812
+PHY-3002 : Step(44): len = 210371, overlap = 925.219
+PHY-3002 : Step(45): len = 209941, overlap = 930.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.21712e-06
+PHY-3002 : Step(46): len = 217589, overlap = 904.906
+PHY-3002 : Step(47): len = 239269, overlap = 829.594
+PHY-3002 : Step(48): len = 250799, overlap = 744.188
+PHY-3002 : Step(49): len = 257036, overlap = 707.062
+PHY-3002 : Step(50): len = 258631, overlap = 670.594
+PHY-3002 : Step(51): len = 258997, overlap = 640.906
+PHY-3002 : Step(52): len = 257866, overlap = 655.125
+PHY-3002 : Step(53): len = 257867, overlap = 670.062
+PHY-3002 : Step(54): len = 256514, overlap = 669.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.04342e-05
+PHY-3002 : Step(55): len = 270300, overlap = 617.781
+PHY-3002 : Step(56): len = 286639, overlap = 547.625
+PHY-3002 : Step(57): len = 295027, overlap = 518.656
+PHY-3002 : Step(58): len = 298963, overlap = 504.688
+PHY-3002 : Step(59): len = 299531, overlap = 485.812
+PHY-3002 : Step(60): len = 299150, overlap = 467.094
+PHY-3002 : Step(61): len = 296804, overlap = 463.219
+PHY-3002 : Step(62): len = 297909, overlap = 466.25
+PHY-3002 : Step(63): len = 299634, overlap = 469.062
+PHY-3002 : Step(64): len = 301114, overlap = 486.812
+PHY-3002 : Step(65): len = 300539, overlap = 485.656
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.08685e-05
+PHY-3002 : Step(66): len = 316343, overlap = 478.844
+PHY-3002 : Step(67): len = 330587, overlap = 454.688
+PHY-3002 : Step(68): len = 338139, overlap = 423.562
+PHY-3002 : Step(69): len = 342235, overlap = 391.656
+PHY-3002 : Step(70): len = 341999, overlap = 377.094
+PHY-3002 : Step(71): len = 343982, overlap = 366.75
+PHY-3002 : Step(72): len = 343035, overlap = 359.938
+PHY-3002 : Step(73): len = 343396, overlap = 357.031
+PHY-3002 : Step(74): len = 340229, overlap = 355.875
+PHY-3002 : Step(75): len = 340338, overlap = 363.125
+PHY-3002 : Step(76): len = 339937, overlap = 352.156
+PHY-3002 : Step(77): len = 340120, overlap = 354.438
+PHY-3002 : Step(78): len = 338222, overlap = 373.844
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.1737e-05
+PHY-3002 : Step(79): len = 354951, overlap = 332.219
+PHY-3002 : Step(80): len = 368709, overlap = 307.844
+PHY-3002 : Step(81): len = 370839, overlap = 283.5
+PHY-3002 : Step(82): len = 373602, overlap = 271.625
+PHY-3002 : Step(83): len = 374186, overlap = 261.75
+PHY-3002 : Step(84): len = 376514, overlap = 260.688
+PHY-3002 : Step(85): len = 374868, overlap = 257.812
+PHY-3002 : Step(86): len = 375741, overlap = 250.125
+PHY-3002 : Step(87): len = 377796, overlap = 236.844
+PHY-3002 : Step(88): len = 379468, overlap = 231.719
+PHY-3002 : Step(89): len = 377349, overlap = 238.812
+PHY-3002 : Step(90): len = 378014, overlap = 238.094
+PHY-3002 : Step(91): len = 378764, overlap = 252.562
+PHY-3002 : Step(92): len = 379253, overlap = 250.594
+PHY-3002 : Step(93): len = 375829, overlap = 249.75
+PHY-3002 : Step(94): len = 376064, overlap = 258.625
+PHY-3002 : Step(95): len = 376903, overlap = 259.469
+PHY-3002 : Step(96): len = 377567, overlap = 260.688
+PHY-3002 : Step(97): len = 375160, overlap = 268.875
+PHY-3002 : Step(98): len = 375091, overlap = 288.5
+PHY-3002 : Step(99): len = 376953, overlap = 295
+PHY-3002 : Step(100): len = 378690, overlap = 288.25
+PHY-3002 : Step(101): len = 375728, overlap = 300.5
+PHY-3002 : Step(102): len = 376695, overlap = 310.031
+PHY-3002 : Step(103): len = 377588, overlap = 298.25
+PHY-3002 : Step(104): len = 379478, overlap = 285.562
+PHY-3002 : Step(105): len = 377443, overlap = 294.5
+PHY-3002 : Step(106): len = 377983, overlap = 294.875
+PHY-3002 : Step(107): len = 379523, overlap = 286.156
+PHY-3002 : Step(108): len = 381746, overlap = 264
+PHY-3002 : Step(109): len = 378253, overlap = 266.562
+PHY-3002 : Step(110): len = 377789, overlap = 279.938
+PHY-3002 : Step(111): len = 377706, overlap = 270.969
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.34739e-05
+PHY-3002 : Step(112): len = 394943, overlap = 265.625
+PHY-3002 : Step(113): len = 403286, overlap = 249.031
+PHY-3002 : Step(114): len = 402536, overlap = 241.531
+PHY-3002 : Step(115): len = 403865, overlap = 234.562
+PHY-3002 : Step(116): len = 405988, overlap = 221.688
+PHY-3002 : Step(117): len = 409008, overlap = 229.906
+PHY-3002 : Step(118): len = 409883, overlap = 229.875
+PHY-3002 : Step(119): len = 411814, overlap = 228
+PHY-3002 : Step(120): len = 414475, overlap = 216.688
+PHY-3002 : Step(121): len = 416149, overlap = 215.188
+PHY-3002 : Step(122): len = 413173, overlap = 228.719
+PHY-3002 : Step(123): len = 413012, overlap = 224.5
+PHY-3002 : Step(124): len = 414455, overlap = 225.062
+PHY-3002 : Step(125): len = 416026, overlap = 223.594
+PHY-3002 : Step(126): len = 414130, overlap = 235.969
+PHY-3002 : Step(127): len = 414047, overlap = 236.719
+PHY-3002 : Step(128): len = 415345, overlap = 243.156
+PHY-3002 : Step(129): len = 416477, overlap = 239.75
+PHY-3002 : Step(130): len = 414734, overlap = 243.75
+PHY-3002 : Step(131): len = 414470, overlap = 248.719
+PHY-3002 : Step(132): len = 415400, overlap = 242.75
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000166948
+PHY-3002 : Step(133): len = 429252, overlap = 243.594
+PHY-3002 : Step(134): len = 435608, overlap = 240.875
+PHY-3002 : Step(135): len = 434924, overlap = 220.781
+PHY-3002 : Step(136): len = 435971, overlap = 223.5
+PHY-3002 : Step(137): len = 440112, overlap = 203.906
+PHY-3002 : Step(138): len = 442951, overlap = 204.062
+PHY-3002 : Step(139): len = 441474, overlap = 207.625
+PHY-3002 : Step(140): len = 441597, overlap = 200.906
+PHY-3002 : Step(141): len = 442490, overlap = 199.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000333896
+PHY-3002 : Step(142): len = 450103, overlap = 196.594
+PHY-3002 : Step(143): len = 456414, overlap = 196.312
+PHY-3002 : Step(144): len = 457555, overlap = 189.875
+PHY-3002 : Step(145): len = 459549, overlap = 187.281
+PHY-3002 : Step(146): len = 463064, overlap = 182.375
+PHY-3002 : Step(147): len = 466055, overlap = 191.219
+PHY-3002 : Step(148): len = 466007, overlap = 187.219
+PHY-3002 : Step(149): len = 466338, overlap = 193.531
+PHY-3002 : Step(150): len = 467587, overlap = 181.531
+PHY-3002 : Step(151): len = 468406, overlap = 176.281
+PHY-3002 : Step(152): len = 467397, overlap = 183.125
+PHY-3002 : Step(153): len = 467102, overlap = 179.219
+PHY-3002 : Step(154): len = 468914, overlap = 167.469
+PHY-3002 : Step(155): len = 470517, overlap = 165.094
+PHY-3002 : Step(156): len = 469955, overlap = 167.875
+PHY-3002 : Step(157): len = 470118, overlap = 170.25
+PHY-3002 : Step(158): len = 471104, overlap = 173.656
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000637153
+PHY-3002 : Step(159): len = 477555, overlap = 178.094
+PHY-3002 : Step(160): len = 482885, overlap = 178.719
+PHY-3002 : Step(161): len = 482536, overlap = 178.531
+PHY-3002 : Step(162): len = 482987, overlap = 177.094
+PHY-3002 : Step(163): len = 485619, overlap = 179.375
+PHY-3002 : Step(164): len = 487424, overlap = 178.875
+PHY-3002 : Step(165): len = 487031, overlap = 179.438
+PHY-3002 : Step(166): len = 487209, overlap = 179.062
+PHY-3002 : Step(167): len = 488788, overlap = 181.188
+PHY-3002 : Step(168): len = 489855, overlap = 183.281
+PHY-3002 : Step(169): len = 489720, overlap = 182.188
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00107583
+PHY-3002 : Step(170): len = 492746, overlap = 182.281
+PHY-3002 : Step(171): len = 495618, overlap = 182.219
+PHY-3002 : Step(172): len = 496148, overlap = 178.344
+PHY-3002 : Step(173): len = 496815, overlap = 172.594
+PHY-3002 : Step(174): len = 498695, overlap = 173.094
+PHY-3002 : Step(175): len = 499821, overlap = 173.469
+PHY-3002 : Step(176): len = 499928, overlap = 173.375
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014383s wall, 0.015625s user + 0.046875s system = 0.062500s CPU (434.5%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 685960, over cnt = 1518(4%), over = 7613, worst = 40
+PHY-1001 : End global iterations; 0.641152s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (136.5%)
+
+PHY-1001 : Congestion index: top1 = 83.47, top5 = 63.15, top10 = 53.37, top15 = 47.42.
+PHY-3001 : End congestion estimation; 0.859182s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (127.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.843410s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000129493
+PHY-3002 : Step(177): len = 632421, overlap = 107.594
+PHY-3002 : Step(178): len = 636024, overlap = 103.781
+PHY-3002 : Step(179): len = 633312, overlap = 100.188
+PHY-3002 : Step(180): len = 632072, overlap = 89.1875
+PHY-3002 : Step(181): len = 631298, overlap = 75.7188
+PHY-3002 : Step(182): len = 630460, overlap = 66.7812
+PHY-3002 : Step(183): len = 629242, overlap = 66.4062
+PHY-3002 : Step(184): len = 628247, overlap = 65.0312
+PHY-3002 : Step(185): len = 626918, overlap = 63.75
+PHY-3002 : Step(186): len = 625575, overlap = 61.8438
+PHY-3002 : Step(187): len = 625203, overlap = 58.3125
+PHY-3002 : Step(188): len = 625442, overlap = 52.5312
+PHY-3002 : Step(189): len = 624054, overlap = 52.3125
+PHY-3002 : Step(190): len = 624450, overlap = 52.1562
+PHY-3002 : Step(191): len = 622293, overlap = 52.75
+PHY-3002 : Step(192): len = 621858, overlap = 53.7188
+PHY-3002 : Step(193): len = 620005, overlap = 55.5
+PHY-3002 : Step(194): len = 618231, overlap = 57.75
+PHY-3002 : Step(195): len = 618295, overlap = 53.4062
+PHY-3002 : Step(196): len = 616542, overlap = 53.4062
+PHY-3002 : Step(197): len = 616235, overlap = 53.5312
+PHY-3002 : Step(198): len = 615835, overlap = 51.5312
+PHY-3002 : Step(199): len = 614427, overlap = 49.9688
+PHY-3002 : Step(200): len = 613912, overlap = 50.875
+PHY-3002 : Step(201): len = 613534, overlap = 50.2188
+PHY-3002 : Step(202): len = 612970, overlap = 51.25
+PHY-3002 : Step(203): len = 612688, overlap = 50.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000258986
+PHY-3002 : Step(204): len = 616062, overlap = 48
+PHY-3002 : Step(205): len = 617754, overlap = 47.5625
+PHY-3002 : Step(206): len = 622276, overlap = 46.4688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000421331
+PHY-3002 : Step(207): len = 627523, overlap = 44.125
+PHY-3002 : Step(208): len = 634715, overlap = 45.0312
+PHY-3002 : Step(209): len = 648246, overlap = 45.3125
+PHY-3002 : Step(210): len = 664378, overlap = 41.125
+PHY-3002 : Step(211): len = 673265, overlap = 41.1562
+PHY-3002 : Step(212): len = 675418, overlap = 45.1562
+PHY-3002 : Step(213): len = 674377, overlap = 41.25
+PHY-3002 : Step(214): len = 673149, overlap = 43.75
+PHY-3002 : Step(215): len = 671389, overlap = 43.6562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000833392
+PHY-3002 : Step(216): len = 679725, overlap = 40.125
+PHY-3002 : Step(217): len = 688216, overlap = 40.0312
+PHY-3002 : Step(218): len = 690010, overlap = 40.6562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00142371
+PHY-3002 : Step(219): len = 694669, overlap = 39.5625
+PHY-3002 : Step(220): len = 716704, overlap = 46.875
+PHY-3002 : Step(221): len = 728740, overlap = 44.875
+PHY-3002 : Step(222): len = 730922, overlap = 44.2188
+PHY-3002 : Step(223): len = 731184, overlap = 45.0938
+PHY-3002 : Step(224): len = 730880, overlap = 46.625
+PHY-3002 : Step(225): len = 730086, overlap = 46.25
+PHY-3002 : Step(226): len = 729153, overlap = 44.25
+PHY-3002 : Step(227): len = 728937, overlap = 44.25
+PHY-3002 : Step(228): len = 727683, overlap = 46.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00233553
+PHY-3002 : Step(229): len = 729907, overlap = 44.25
+PHY-3002 : Step(230): len = 735129, overlap = 43.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 50/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 816808, over cnt = 2830(8%), over = 14682, worst = 52
+PHY-1001 : End global iterations; 1.569124s wall, 2.031250s user + 0.015625s system = 2.046875s CPU (130.4%)
+
+PHY-1001 : Congestion index: top1 = 96.68, top5 = 76.57, top10 = 66.59, top15 = 60.43.
+PHY-3001 : End congestion estimation; 1.838662s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (126.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.357137s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000131607
+PHY-3002 : Step(231): len = 721048, overlap = 261.438
+PHY-3002 : Step(232): len = 711393, overlap = 196.312
+PHY-3002 : Step(233): len = 696510, overlap = 165.75
+PHY-3002 : Step(234): len = 682228, overlap = 139.688
+PHY-3002 : Step(235): len = 671370, overlap = 128.969
+PHY-3002 : Step(236): len = 659920, overlap = 127.344
+PHY-3002 : Step(237): len = 652010, overlap = 116.531
+PHY-3002 : Step(238): len = 645470, overlap = 116.031
+PHY-3002 : Step(239): len = 639685, overlap = 117.688
+PHY-3002 : Step(240): len = 635104, overlap = 117.469
+PHY-3002 : Step(241): len = 629276, overlap = 111.625
+PHY-3002 : Step(242): len = 626429, overlap = 114.594
+PHY-3002 : Step(243): len = 622489, overlap = 114.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000263213
+PHY-3002 : Step(244): len = 623258, overlap = 112.562
+PHY-3002 : Step(245): len = 626720, overlap = 112.219
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000503997
+PHY-3002 : Step(246): len = 630336, overlap = 101.875
+PHY-3002 : Step(247): len = 640493, overlap = 91.6875
+PHY-3002 : Step(248): len = 645961, overlap = 87.125
+PHY-3002 : Step(249): len = 645759, overlap = 90.5312
+PHY-3002 : Step(250): len = 645390, overlap = 93.2188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84699, tnet num: 20549, tinst num: 18148, tnode num: 115428, tedge num: 135050.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.581992s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.8%)
+
+RUN-1004 : used memory is 578 MB, reserved memory is 567 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 387.00 peak overflow 4.28
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 531/20727.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 734312, over cnt = 3054(8%), over = 11091, worst = 23
+PHY-1001 : End global iterations; 1.403415s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (145.8%)
+
+PHY-1001 : Congestion index: top1 = 67.74, top5 = 57.08, top10 = 51.63, top15 = 47.99.
+PHY-1001 : End incremental global routing; 1.732733s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (136.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20549 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.323120s wall, 1.234375s user + 0.093750s system = 1.328125s CPU (100.4%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18017 has valid locations, 306 needs to be replaced
+PHY-3001 : design contains 18408 instances, 7799 luts, 9388 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6217 pins
+PHY-3001 : Found 1270 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 669046
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17126/20987.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751448, over cnt = 3101(8%), over = 11127, worst = 23
+PHY-1001 : End global iterations; 0.233694s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (120.3%)
+
+PHY-1001 : Congestion index: top1 = 67.89, top5 = 57.32, top10 = 51.89, top15 = 48.29.
+PHY-3001 : End congestion estimation; 0.476676s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (108.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85755, tnet num: 20809, tinst num: 18408, tnode num: 116990, tedge num: 136642.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.476842s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.5%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 634 MB, peak memory is 717 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20809 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.424507s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(251): len = 668188, overlap = 0
+PHY-3002 : Step(252): len = 667754, overlap = 0
+PHY-3002 : Step(253): len = 667586, overlap = 0
+PHY-3002 : Step(254): len = 667155, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17206/20987.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 748208, over cnt = 3090(8%), over = 11198, worst = 23
+PHY-1001 : End global iterations; 0.188759s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (124.2%)
+
+PHY-1001 : Congestion index: top1 = 68.58, top5 = 57.61, top10 = 52.08, top15 = 48.48.
+PHY-3001 : End congestion estimation; 0.437318s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (110.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20809 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.421983s wall, 1.390625s user + 0.031250s system = 1.421875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000303263
+PHY-3002 : Step(255): len = 667149, overlap = 95.4688
+PHY-3002 : Step(256): len = 667132, overlap = 95.1562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000606527
+PHY-3002 : Step(257): len = 667361, overlap = 95.25
+PHY-3002 : Step(258): len = 667902, overlap = 95.3125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00121305
+PHY-3002 : Step(259): len = 668197, overlap = 95.1562
+PHY-3002 : Step(260): len = 668527, overlap = 95.375
+PHY-3001 : Final: Len = 668527, Over = 95.375
+PHY-3001 : End incremental placement; 5.495938s wall, 5.968750s user + 0.265625s system = 6.234375s CPU (113.4%)
+
+OPT-1001 : Total overflow 391.94 peak overflow 4.28
+OPT-1001 : End high-fanout net optimization; 9.085290s wall, 10.187500s user + 0.359375s system = 10.546875s CPU (116.1%)
+
+OPT-1001 : Current memory(MB): used = 720, reserve = 714, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17145/20987.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 751904, over cnt = 3018(8%), over = 10110, worst = 23
+PHY-1002 : len = 802760, over cnt = 2068(5%), over = 5261, worst = 22
+PHY-1002 : len = 851008, over cnt = 803(2%), over = 1689, worst = 17
+PHY-1002 : len = 873712, over cnt = 183(0%), over = 296, worst = 12
+PHY-1002 : len = 879776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.611194s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (153.2%)
+
+PHY-1001 : Congestion index: top1 = 57.44, top5 = 50.83, top10 = 47.10, top15 = 44.82.
+OPT-1001 : End congestion update; 1.863449s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (145.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20809 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.797162s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (100.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 110 cells processed and 16384 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 42 cells processed and 4900 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 11 cells processed and 200 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 300 slack improved
+OPT-1001 : End bottleneck based optimization; 3.119529s wall, 3.968750s user + 0.015625s system = 3.984375s CPU (127.7%)
+
+OPT-1001 : Current memory(MB): used = 696, reserve = 691, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17193/20990.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880192, over cnt = 106(0%), over = 132, worst = 6
+PHY-1002 : len = 879920, over cnt = 71(0%), over = 78, worst = 3
+PHY-1002 : len = 880472, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 880656, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 880736, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.729229s wall, 0.734375s user + 0.015625s system = 0.750000s CPU (102.8%)
+
+PHY-1001 : Congestion index: top1 = 57.24, top5 = 50.59, top10 = 46.83, top15 = 44.60.
+OPT-1001 : End congestion update; 0.989841s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (101.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20812 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.011564s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (78.8%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 20 cells processed and 4200 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.128928s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (90.3%)
+
+OPT-1001 : Current memory(MB): used = 708, reserve = 703, peak = 737.
+OPT-1001 : End physical optimization; 16.223716s wall, 17.890625s user + 0.437500s system = 18.328125s CPU (113.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7799 LUT to BLE ...
+SYN-4008 : Packed 7799 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6244 remaining SEQ's ...
+SYN-4005 : Packed 4109 SEQ with LUT/SLICE
+SYN-4006 : 842 single LUT's are left
+SYN-4006 : 2135 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9934/13721 primitive instances ...
+PHY-3001 : End packing; 1.683652s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (99.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6713 instances
+RUN-1001 : 3282 mslices, 3283 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17977 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10094 nets have 2 pins
+RUN-1001 : 6520 nets have [3 - 5] pins
+RUN-1001 : 728 nets have [6 - 10] pins
+RUN-1001 : 316 nets have [11 - 20] pins
+RUN-1001 : 287 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6711 instances, 6565 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3594 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 682164, Over = 230.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7767/17977.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 834624, over cnt = 1977(5%), over = 3149, worst = 9
+PHY-1002 : len = 843192, over cnt = 1303(3%), over = 1770, worst = 6
+PHY-1002 : len = 856608, over cnt = 451(1%), over = 550, worst = 4
+PHY-1002 : len = 863968, over cnt = 96(0%), over = 110, worst = 2
+PHY-1002 : len = 865952, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.662199s wall, 2.312500s user + 0.062500s system = 2.375000s CPU (142.9%)
+
+PHY-1001 : Congestion index: top1 = 58.79, top5 = 51.08, top10 = 47.14, top15 = 44.58.
+PHY-3001 : End congestion estimation; 2.073986s wall, 2.734375s user + 0.062500s system = 2.796875s CPU (134.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71855, tnet num: 17799, tinst num: 6711, tnode num: 94435, tedge num: 119415.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.584591s wall, 1.562500s user + 0.031250s system = 1.593750s CPU (100.6%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 620 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17799 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.437083s wall, 2.375000s user + 0.062500s system = 2.437500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.81796e-05
+PHY-3002 : Step(261): len = 670482, overlap = 230.75
+PHY-3002 : Step(262): len = 663828, overlap = 227
+PHY-3002 : Step(263): len = 658719, overlap = 233.5
+PHY-3002 : Step(264): len = 654908, overlap = 238.5
+PHY-3002 : Step(265): len = 651442, overlap = 242.5
+PHY-3002 : Step(266): len = 648393, overlap = 251
+PHY-3002 : Step(267): len = 646012, overlap = 248.25
+PHY-3002 : Step(268): len = 643942, overlap = 251.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000116359
+PHY-3002 : Step(269): len = 646814, overlap = 245.25
+PHY-3002 : Step(270): len = 651066, overlap = 235
+PHY-3002 : Step(271): len = 651536, overlap = 234.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000232718
+PHY-3002 : Step(272): len = 661228, overlap = 221.25
+PHY-3002 : Step(273): len = 667374, overlap = 213.75
+PHY-3002 : Step(274): len = 665173, overlap = 217
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.347809s wall, 0.343750s user + 0.671875s system = 1.015625s CPU (292.0%)
+
+PHY-3001 : Trial Legalized: Len = 749713
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 927/17977.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860208, over cnt = 2644(7%), over = 4385, worst = 7
+PHY-1002 : len = 876376, over cnt = 1634(4%), over = 2337, worst = 7
+PHY-1002 : len = 895112, over cnt = 645(1%), over = 904, worst = 7
+PHY-1002 : len = 905968, over cnt = 220(0%), over = 279, worst = 4
+PHY-1002 : len = 910856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.464467s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (137.6%)
+
+PHY-1001 : Congestion index: top1 = 54.87, top5 = 50.20, top10 = 47.34, top15 = 45.26.
+PHY-3001 : End congestion estimation; 2.949172s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (131.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17799 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.884607s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000170135
+PHY-3002 : Step(275): len = 723546, overlap = 39.25
+PHY-3002 : Step(276): len = 706665, overlap = 66
+PHY-3002 : Step(277): len = 691828, overlap = 93.5
+PHY-3002 : Step(278): len = 683017, overlap = 114.25
+PHY-3002 : Step(279): len = 677866, overlap = 125.5
+PHY-3002 : Step(280): len = 674022, overlap = 142.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00034027
+PHY-3002 : Step(281): len = 677396, overlap = 136.5
+PHY-3002 : Step(282): len = 680734, overlap = 137.5
+PHY-3002 : Step(283): len = 682443, overlap = 137.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000680541
+PHY-3002 : Step(284): len = 685332, overlap = 134
+PHY-3002 : Step(285): len = 691718, overlap = 133.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032001s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.7%)
+
+PHY-3001 : Legalized: Len = 719458, Over = 0
+PHY-3001 : Spreading special nets. 436 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.098542s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (95.1%)
+
+PHY-3001 : 629 instances has been re-located, deltaX = 186, deltaY = 363, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 729247, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71855, tnet num: 17799, tinst num: 6714, tnode num: 94435, tedge num: 119415.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.815967s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (99.8%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 645 MB, peak memory is 737 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4426/17977.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 852368, over cnt = 2455(6%), over = 3944, worst = 8
+PHY-1002 : len = 867088, over cnt = 1362(3%), over = 1872, worst = 5
+PHY-1002 : len = 885056, over cnt = 358(1%), over = 469, worst = 4
+PHY-1002 : len = 891904, over cnt = 48(0%), over = 62, worst = 3
+PHY-1002 : len = 892872, over cnt = 11(0%), over = 13, worst = 2
+PHY-1001 : End global iterations; 1.987079s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (144.7%)
+
+PHY-1001 : Congestion index: top1 = 53.51, top5 = 48.61, top10 = 45.66, top15 = 43.76.
+PHY-1001 : End incremental global routing; 2.356308s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (137.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17799 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.851820s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.9%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6621 has valid locations, 33 needs to be replaced
+PHY-3001 : design contains 6742 instances, 6593 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735447
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16369/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901096, over cnt = 119(0%), over = 164, worst = 8
+PHY-1002 : len = 901448, over cnt = 70(0%), over = 78, worst = 3
+PHY-1002 : len = 901760, over cnt = 41(0%), over = 44, worst = 2
+PHY-1002 : len = 902200, over cnt = 14(0%), over = 15, worst = 2
+PHY-1002 : len = 902576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.853511s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (111.7%)
+
+PHY-1001 : Congestion index: top1 = 53.53, top5 = 48.84, top10 = 45.93, top15 = 44.07.
+PHY-3001 : End congestion estimation; 1.160658s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (107.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72153, tnet num: 17827, tinst num: 6742, tnode num: 94799, tedge num: 119789.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.866232s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.5%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 667 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.743826s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(286): len = 734651, overlap = 0
+PHY-3002 : Step(287): len = 733634, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16366/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899968, over cnt = 76(0%), over = 119, worst = 6
+PHY-1002 : len = 900432, over cnt = 42(0%), over = 55, worst = 5
+PHY-1002 : len = 900720, over cnt = 23(0%), over = 29, worst = 3
+PHY-1002 : len = 901320, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 901432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.770579s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.4%)
+
+PHY-1001 : Congestion index: top1 = 53.69, top5 = 48.96, top10 = 45.98, top15 = 44.08.
+PHY-3001 : End congestion estimation; 1.081126s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (102.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.849570s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000566989
+PHY-3002 : Step(288): len = 733575, overlap = 2.75
+PHY-3002 : Step(289): len = 733604, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005329s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 733680, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057799s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.1%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 733680, Over = 0
+PHY-3001 : End incremental placement; 6.304575s wall, 6.390625s user + 0.078125s system = 6.468750s CPU (102.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.988619s wall, 10.937500s user + 0.093750s system = 11.031250s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16352/18005.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901336, over cnt = 86(0%), over = 123, worst = 5
+PHY-1002 : len = 901424, over cnt = 43(0%), over = 45, worst = 2
+PHY-1002 : len = 901824, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 901904, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.617576s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (116.4%)
+
+PHY-1001 : Congestion index: top1 = 53.43, top5 = 48.64, top10 = 45.80, top15 = 43.98.
+OPT-1001 : End congestion update; 0.919629s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (110.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17827 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.704571s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.8%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6654 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6742 instances, 6593 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 737370, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059857s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.4%)
+
+PHY-3001 : 22 instances has been re-located, deltaX = 16, deltaY = 13, maxDist = 2.
+PHY-3001 : Final: Len = 737838, Over = 0
+PHY-3001 : End incremental legalization; 0.384579s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (117.8%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 46 cells processed and 12307 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6654 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6742 instances, 6593 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 741730, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059861s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.4%)
+
+PHY-3001 : 28 instances has been re-located, deltaX = 27, deltaY = 14, maxDist = 5.
+PHY-3001 : Final: Len = 742666, Over = 0
+PHY-3001 : End incremental legalization; 0.371793s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.9%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 34 cells processed and 10636 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6654 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6742 instances, 6593 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 492 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 742880, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062621s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 6, maxDist = 3.
+PHY-3001 : Final: Len = 743270, Over = 0
+PHY-3001 : End incremental legalization; 0.378123s wall, 0.406250s user + 0.031250s system = 0.437500s CPU (115.7%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 14 cells processed and 1216 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744062, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057504s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.7%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 6, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 744276, Over = 0
+PHY-3001 : End incremental legalization; 0.367918s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.9%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 700 slack improved
+OPT-1001 : End bottleneck based optimization; 3.659697s wall, 3.875000s user + 0.031250s system = 3.906250s CPU (106.7%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 736, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15926/18007.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911128, over cnt = 157(0%), over = 212, worst = 8
+PHY-1002 : len = 911552, over cnt = 75(0%), over = 89, worst = 3
+PHY-1002 : len = 911992, over cnt = 31(0%), over = 37, worst = 3
+PHY-1002 : len = 912544, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 912576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.828141s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (103.8%)
+
+PHY-1001 : Congestion index: top1 = 53.15, top5 = 48.64, top10 = 45.90, top15 = 44.09.
+OPT-1001 : End congestion update; 1.134965s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.710737s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.1%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744430, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058950s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.0%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 744534, Over = 0
+PHY-3001 : End incremental legalization; 0.368588s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.5%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 6 cells processed and 350 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.382575s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (105.6%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 736, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.730281s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16364/18007.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912712, over cnt = 28(0%), over = 32, worst = 2
+PHY-1002 : len = 912736, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 912808, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 912888, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 912976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.748369s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (104.4%)
+
+PHY-1001 : Congestion index: top1 = 53.06, top5 = 48.58, top10 = 45.87, top15 = 44.09.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.710752s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.517241
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744534, Over = 0
+PHY-3001 : End spreading; 0.057809s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.1%)
+
+PHY-3001 : Final: Len = 744534, Over = 0
+PHY-3001 : End incremental legalization; 0.371328s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (126.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.701872s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16395/18007.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126121s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.1%)
+
+PHY-1001 : Congestion index: top1 = 53.06, top5 = 48.58, top10 = 45.87, top15 = 44.09.
+OPT-1001 : End congestion update; 0.435949s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (96.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.704699s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (102.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744476, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058311s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 744534, Over = 0
+PHY-3001 : End incremental legalization; 0.416669s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.667293s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.3%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 736, peak = 740.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16395/18007.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126138s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.1%)
+
+PHY-1001 : Congestion index: top1 = 53.06, top5 = 48.58, top10 = 45.87, top15 = 44.09.
+OPT-1001 : End congestion update; 0.435783s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.703628s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744476, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058433s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 744534, Over = 0
+PHY-3001 : End incremental legalization; 0.377360s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.4%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 495 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 744476, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056978s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.7%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 744534, Over = 0
+PHY-3001 : End incremental legalization; 0.374381s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.2%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 2.201343s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (105.0%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 736, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.703323s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 737, reserve = 736, peak = 740.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.709961s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.2%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16395/18007.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.139454s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.8%)
+
+PHY-1001 : Congestion index: top1 = 53.06, top5 = 48.58, top10 = 45.87, top15 = 44.09.
+RUN-1001 : End congestion update; 0.447868s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.7%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.161079s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.6%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 736, peak = 740.
+OPT-1001 : End physical optimization; 27.567707s wall, 29.046875s user + 0.156250s system = 29.203125s CPU (105.9%)
+
+RUN-1003 : finish command "place" in 73.683732s wall, 103.921875s user + 6.406250s system = 110.328125s CPU (149.7%)
+
+RUN-1004 : used memory is 607 MB, reserved memory is 598 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.719394s wall, 2.968750s user + 0.031250s system = 3.000000s CPU (174.5%)
+
+RUN-1004 : used memory is 608 MB, reserved memory is 599 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6747 instances
+RUN-1001 : 3308 mslices, 3288 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18007 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10089 nets have 2 pins
+RUN-1001 : 6523 nets have [3 - 5] pins
+RUN-1001 : 741 nets have [6 - 10] pins
+RUN-1001 : 326 nets have [11 - 20] pins
+RUN-1001 : 300 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72181, tnet num: 17829, tinst num: 6745, tnode num: 94836, tedge num: 119826.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.572816s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.3%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 629 MB, peak memory is 740 MB
+PHY-1001 : 3308 mslices, 3288 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 845048, over cnt = 2665(7%), over = 4394, worst = 9
+PHY-1002 : len = 865656, over cnt = 1529(4%), over = 2116, worst = 6
+PHY-1002 : len = 883456, over cnt = 577(1%), over = 785, worst = 6
+PHY-1002 : len = 896400, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 896592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.954697s wall, 4.093750s user + 0.000000s system = 4.093750s CPU (138.6%)
+
+PHY-1001 : Congestion index: top1 = 52.46, top5 = 48.12, top10 = 45.45, top15 = 43.68.
+PHY-1001 : End global routing; 3.290003s wall, 4.437500s user + 0.000000s system = 4.437500s CPU (134.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 715, reserve = 720, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 986, reserve = 993, peak = 986.
+PHY-1001 : End build detailed router design. 4.023068s wall, 3.953125s user + 0.062500s system = 4.015625s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271848, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.104841s wall, 5.109375s user + 0.000000s system = 5.109375s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271904, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.423680s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1022, reserve = 1030, peak = 1022.
+PHY-1001 : End phase 1; 5.540706s wall, 5.546875s user + 0.000000s system = 5.546875s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.28124e+06, over cnt = 1733(0%), over = 1737, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1041, peak = 1036.
+PHY-1001 : End initial routed; 23.948792s wall, 55.734375s user + 0.453125s system = 56.187500s CPU (234.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 31/16930(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.224 | -2.034 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.172527s wall, 3.156250s user + 0.015625s system = 3.171875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1043, reserve = 1047, peak = 1043.
+PHY-1001 : End phase 2; 27.121379s wall, 58.890625s user + 0.468750s system = 59.359375s CPU (218.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 10 pins with SWNS -0.807ns STNS -1.607ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.156887s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.6%)
+
+PHY-1022 : len = 2.28126e+06, over cnt = 1739(0%), over = 1743, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.433792s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.24753e+06, over cnt = 711(0%), over = 713, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.196484s wall, 2.078125s user + 0.000000s system = 2.078125s CPU (173.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.24682e+06, over cnt = 145(0%), over = 145, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.714249s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (137.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.2477e+06, over cnt = 24(0%), over = 24, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.336942s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (115.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.24797e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.230318s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.24801e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.170849s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 26/16930(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.807 | -1.607 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.255549s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 535 feed throughs used by 403 nets
+PHY-1001 : End commit to database; 2.362511s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1148, reserve = 1155, peak = 1148.
+PHY-1001 : End phase 3; 9.103725s wall, 10.281250s user + 0.031250s system = 10.312500s CPU (113.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.807ns STNS -1.607ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.155875s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.2%)
+
+PHY-1022 : len = 2.24801e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.390819s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.807ns, -1.607ns, 2}
+PHY-1001 : Update timing.....
+PHY-1001 : 26/16930(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.807 | -1.607 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.189399s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 535 feed throughs used by 403 nets
+PHY-1001 : End commit to database; 2.285024s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1164, peak = 1156.
+PHY-1001 : End phase 4; 5.891745s wall, 5.890625s user + 0.000000s system = 5.890625s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.24801e+06
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1167, peak = 1158.
+PHY-1001 : End export database. 0.144185s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.5%)
+
+PHY-1001 : End detail routing; 52.213680s wall, 85.078125s user + 0.562500s system = 85.640625s CPU (164.0%)
+
+RUN-1003 : finish command "route" in 58.160483s wall, 92.171875s user + 0.562500s system = 92.734375s CPU (159.4%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1090 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10239 out of 19600 52.24%
+#reg 9578 out of 19600 48.87%
+#le 12340
+ #lut only 2762 out of 12340 22.38%
+ #reg only 2101 out of 12340 17.03%
+ #lut® 7477 out of 12340 60.59%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1781
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1436
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1325
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 944
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 132
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 67
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/reg1_syn_181.f1 2
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_255.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P16 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P39 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P148 LVCMOS33 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE NONE
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P173 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P115 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P83 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P66 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12340 |9212 |1027 |9610 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |528 |452 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |107 |95 |4 |94 |4 |0 |
+| U_crc16_24b |crc16_24b |48 |48 |0 |25 |0 |0 |
+| U_ecc_gen |ecc_gen |11 |11 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |760 |362 |96 |579 |0 |0 |
+| u_ADconfig |AD_config |188 |126 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |260 |146 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |747 |377 |96 |561 |0 |0 |
+| u_ADconfig |AD_config |170 |117 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |267 |150 |71 |125 |0 |0 |
+| sampling_fe_a |sampling_fe |3014 |2431 |306 |2098 |25 |0 |
+| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |186 |117 |17 |153 |0 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_sort |sort |2793 |2310 |289 |1910 |25 |0 |
+| rddpram_ctl |rddpram_ctl |6 |3 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2366 |1990 |253 |1548 |22 |0 |
+| channelPart |channel_part_8478 |132 |124 |3 |128 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |45 |0 |0 |
+| ram_switch |ram_switch |1885 |1581 |197 |1158 |0 |0 |
+| adc_addr_gen |adc_addr_gen |211 |184 |27 |119 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |26 |23 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| insert |insert |965 |689 |170 |642 |0 |0 |
+| ram_switch_state |ram_switch_state |709 |708 |0 |397 |0 |0 |
+| read_ram_i |read_ram |264 |211 |44 |191 |0 |0 |
+| read_ram_addr |read_ram_addr |214 |174 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |46 |33 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |323 |232 |36 |279 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3116 |2501 |349 |2093 |25 |1 |
+| u0_soft_n |cdc_sync |7 |6 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |125 |17 |155 |0 |0 |
+| u_sort |sort_rev |2895 |2352 |332 |1901 |25 |1 |
+| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2464 |2006 |290 |1557 |22 |1 |
+| channelPart |channel_part_8478 |147 |143 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1867 |1536 |197 |1145 |0 |0 |
+| adc_addr_gen |adc_addr_gen |208 |181 |27 |111 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |20 |17 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| insert |insert |973 |671 |170 |685 |0 |0 |
+| ram_switch_state |ram_switch_state |686 |684 |0 |349 |0 |0 |
+| read_ram_i |read_ram_rev |373 |262 |81 |215 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |303 |218 |73 |168 |0 |0 |
+| read_ram_data |read_ram_data_rev |70 |44 |8 |47 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10027
+ #2 2 4253
+ #3 3 1702
+ #4 4 565
+ #5 5-10 780
+ #6 11-50 574
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.380320s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (163.4%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1091 MB, peak memory is 1158 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72181, tnet num: 17829, tinst num: 6745, tnode num: 94836, tedge num: 119826.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.565874s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.8%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1094 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17829 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.430254s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (99.4%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1099 MB, peak memory is 1158 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6745
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18007, pip num: 168320
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 535
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3245 valid insts, and 469487 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.208685s wall, 60.671875s user + 0.187500s system = 60.859375s CPU (660.9%)
+
+RUN-1004 : used memory is 1250 MB, reserved memory is 1252 MB, peak memory is 1365 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_133509.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_134022.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_134022.log
new file mode 100644
index 0000000..e609ed8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_134022.log
@@ -0,0 +1,1988 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 13:40:22 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(923)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(932)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(956)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(964)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(967)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1138)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1227)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1528)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1539)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1557)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1741)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2137)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.207509s wall, 2.078125s user + 0.125000s system = 2.203125s CPU (99.8%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 316 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2951 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18121 instances
+RUN-0007 : 7671 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20698 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13212 nets have 2 pins
+RUN-1001 : 6450 nets have [3 - 5] pins
+RUN-1001 : 618 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18119 instances, 7671 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6100 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84584, tnet num: 20520, tinst num: 18119, tnode num: 115319, tedge num: 134878.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.164751s wall, 1.125000s user + 0.046875s system = 1.171875s CPU (100.6%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 516 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.938649s wall, 1.875000s user + 0.062500s system = 1.937500s CPU (99.9%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.1519e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18119.
+PHY-3001 : Level 1 #clusters 2053.
+PHY-3001 : End clustering; 0.122717s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (89.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.33061e+06, overlap = 444.156
+PHY-3002 : Step(2): len = 1.2387e+06, overlap = 504.75
+PHY-3002 : Step(3): len = 878186, overlap = 585.656
+PHY-3002 : Step(4): len = 797180, overlap = 654.469
+PHY-3002 : Step(5): len = 620402, overlap = 753.25
+PHY-3002 : Step(6): len = 560744, overlap = 859.562
+PHY-3002 : Step(7): len = 468528, overlap = 939.281
+PHY-3002 : Step(8): len = 431613, overlap = 981.656
+PHY-3002 : Step(9): len = 385462, overlap = 1043.5
+PHY-3002 : Step(10): len = 361059, overlap = 1099.56
+PHY-3002 : Step(11): len = 325034, overlap = 1092.06
+PHY-3002 : Step(12): len = 302412, overlap = 1137.97
+PHY-3002 : Step(13): len = 278500, overlap = 1219.91
+PHY-3002 : Step(14): len = 256730, overlap = 1233.69
+PHY-3002 : Step(15): len = 230885, overlap = 1281.97
+PHY-3002 : Step(16): len = 218935, overlap = 1332.19
+PHY-3002 : Step(17): len = 190835, overlap = 1374.44
+PHY-3002 : Step(18): len = 178151, overlap = 1387.19
+PHY-3002 : Step(19): len = 157692, overlap = 1423.81
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.31965e-06
+PHY-3002 : Step(20): len = 159161, overlap = 1401.78
+PHY-3002 : Step(21): len = 191197, overlap = 1274.22
+PHY-3002 : Step(22): len = 200129, overlap = 1218.25
+PHY-3002 : Step(23): len = 207432, overlap = 1180.22
+PHY-3002 : Step(24): len = 205312, overlap = 1140.41
+PHY-3002 : Step(25): len = 204929, overlap = 1129.5
+PHY-3002 : Step(26): len = 200358, overlap = 1113.34
+PHY-3002 : Step(27): len = 198925, overlap = 1107
+PHY-3002 : Step(28): len = 195559, overlap = 1087.59
+PHY-3002 : Step(29): len = 194041, overlap = 1077.09
+PHY-3002 : Step(30): len = 191474, overlap = 1053.66
+PHY-3002 : Step(31): len = 190377, overlap = 1025.38
+PHY-3002 : Step(32): len = 188650, overlap = 1033.72
+PHY-3002 : Step(33): len = 188691, overlap = 1052.06
+PHY-3002 : Step(34): len = 187203, overlap = 1037.91
+PHY-3002 : Step(35): len = 186563, overlap = 1017.91
+PHY-3002 : Step(36): len = 187564, overlap = 1016.91
+PHY-3002 : Step(37): len = 187687, overlap = 998.562
+PHY-3002 : Step(38): len = 186779, overlap = 987.625
+PHY-3002 : Step(39): len = 186538, overlap = 989.031
+PHY-3002 : Step(40): len = 185472, overlap = 981.062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.63929e-06
+PHY-3002 : Step(41): len = 191937, overlap = 959.094
+PHY-3002 : Step(42): len = 207724, overlap = 923.812
+PHY-3002 : Step(43): len = 213665, overlap = 927.25
+PHY-3002 : Step(44): len = 218433, overlap = 943.562
+PHY-3002 : Step(45): len = 219416, overlap = 939.844
+PHY-3002 : Step(46): len = 220714, overlap = 944.875
+PHY-3002 : Step(47): len = 219700, overlap = 932.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.27859e-06
+PHY-3002 : Step(48): len = 228579, overlap = 916.844
+PHY-3002 : Step(49): len = 245476, overlap = 838.938
+PHY-3002 : Step(50): len = 254080, overlap = 764.656
+PHY-3002 : Step(51): len = 261687, overlap = 723.406
+PHY-3002 : Step(52): len = 267107, overlap = 700.094
+PHY-3002 : Step(53): len = 269676, overlap = 686.719
+PHY-3002 : Step(54): len = 270405, overlap = 661.031
+PHY-3002 : Step(55): len = 270034, overlap = 653.781
+PHY-3002 : Step(56): len = 269032, overlap = 653.406
+PHY-3002 : Step(57): len = 267698, overlap = 662.094
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.05572e-05
+PHY-3002 : Step(58): len = 281062, overlap = 644.031
+PHY-3002 : Step(59): len = 296249, overlap = 598.656
+PHY-3002 : Step(60): len = 302669, overlap = 590.375
+PHY-3002 : Step(61): len = 308240, overlap = 560.094
+PHY-3002 : Step(62): len = 308728, overlap = 540.969
+PHY-3002 : Step(63): len = 307891, overlap = 522.781
+PHY-3002 : Step(64): len = 307663, overlap = 506.781
+PHY-3002 : Step(65): len = 308844, overlap = 485.969
+PHY-3002 : Step(66): len = 308706, overlap = 470.969
+PHY-3002 : Step(67): len = 308897, overlap = 473.844
+PHY-3002 : Step(68): len = 307959, overlap = 468.312
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.11144e-05
+PHY-3002 : Step(69): len = 324001, overlap = 430.281
+PHY-3002 : Step(70): len = 336731, overlap = 394.156
+PHY-3002 : Step(71): len = 341848, overlap = 354.844
+PHY-3002 : Step(72): len = 344850, overlap = 367.062
+PHY-3002 : Step(73): len = 344601, overlap = 370.531
+PHY-3002 : Step(74): len = 347206, overlap = 366.5
+PHY-3002 : Step(75): len = 347779, overlap = 373.625
+PHY-3002 : Step(76): len = 350014, overlap = 382.062
+PHY-3002 : Step(77): len = 348568, overlap = 385.844
+PHY-3002 : Step(78): len = 348210, overlap = 390.094
+PHY-3002 : Step(79): len = 347408, overlap = 379.688
+PHY-3002 : Step(80): len = 348594, overlap = 367.656
+PHY-3002 : Step(81): len = 347192, overlap = 359.906
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.22287e-05
+PHY-3002 : Step(82): len = 362643, overlap = 342.938
+PHY-3002 : Step(83): len = 373823, overlap = 314.688
+PHY-3002 : Step(84): len = 377241, overlap = 296.219
+PHY-3002 : Step(85): len = 380705, overlap = 284.531
+PHY-3002 : Step(86): len = 383212, overlap = 295.406
+PHY-3002 : Step(87): len = 387217, overlap = 291.469
+PHY-3002 : Step(88): len = 383846, overlap = 305.969
+PHY-3002 : Step(89): len = 385520, overlap = 312.188
+PHY-3002 : Step(90): len = 385903, overlap = 299.219
+PHY-3002 : Step(91): len = 388034, overlap = 300.344
+PHY-3002 : Step(92): len = 382901, overlap = 315.75
+PHY-3002 : Step(93): len = 382678, overlap = 310.438
+PHY-3002 : Step(94): len = 384180, overlap = 304.625
+PHY-3002 : Step(95): len = 385684, overlap = 289.25
+PHY-3002 : Step(96): len = 383516, overlap = 290.406
+PHY-3002 : Step(97): len = 383295, overlap = 284.25
+PHY-3002 : Step(98): len = 383658, overlap = 293.625
+PHY-3002 : Step(99): len = 384652, overlap = 288.594
+PHY-3002 : Step(100): len = 382927, overlap = 276.281
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.44574e-05
+PHY-3002 : Step(101): len = 398082, overlap = 281.312
+PHY-3002 : Step(102): len = 408291, overlap = 268.406
+PHY-3002 : Step(103): len = 408849, overlap = 266.938
+PHY-3002 : Step(104): len = 410432, overlap = 250
+PHY-3002 : Step(105): len = 413058, overlap = 250.562
+PHY-3002 : Step(106): len = 415318, overlap = 247.594
+PHY-3002 : Step(107): len = 412417, overlap = 250.188
+PHY-3002 : Step(108): len = 412572, overlap = 263.156
+PHY-3002 : Step(109): len = 414918, overlap = 257.25
+PHY-3002 : Step(110): len = 416740, overlap = 258.094
+PHY-3002 : Step(111): len = 414433, overlap = 236.438
+PHY-3002 : Step(112): len = 414629, overlap = 228.938
+PHY-3002 : Step(113): len = 415420, overlap = 230.281
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168915
+PHY-3002 : Step(114): len = 428930, overlap = 204.406
+PHY-3002 : Step(115): len = 436972, overlap = 192.375
+PHY-3002 : Step(116): len = 436388, overlap = 190.688
+PHY-3002 : Step(117): len = 437531, overlap = 178.719
+PHY-3002 : Step(118): len = 440270, overlap = 171.469
+PHY-3002 : Step(119): len = 443196, overlap = 170.094
+PHY-3002 : Step(120): len = 442103, overlap = 179.844
+PHY-3002 : Step(121): len = 443584, overlap = 177.75
+PHY-3002 : Step(122): len = 446345, overlap = 164.375
+PHY-3002 : Step(123): len = 448616, overlap = 165.969
+PHY-3002 : Step(124): len = 447454, overlap = 173
+PHY-3002 : Step(125): len = 447071, overlap = 175.156
+PHY-3002 : Step(126): len = 447741, overlap = 172.656
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00033783
+PHY-3002 : Step(127): len = 455964, overlap = 165.688
+PHY-3002 : Step(128): len = 464436, overlap = 159.906
+PHY-3002 : Step(129): len = 466291, overlap = 141.188
+PHY-3002 : Step(130): len = 468372, overlap = 134.062
+PHY-3002 : Step(131): len = 472772, overlap = 133.781
+PHY-3002 : Step(132): len = 477809, overlap = 137.938
+PHY-3002 : Step(133): len = 476180, overlap = 141.531
+PHY-3002 : Step(134): len = 476882, overlap = 140.75
+PHY-3002 : Step(135): len = 479475, overlap = 135.094
+PHY-3002 : Step(136): len = 480483, overlap = 133.438
+PHY-3002 : Step(137): len = 477527, overlap = 126.969
+PHY-3002 : Step(138): len = 476462, overlap = 126.75
+PHY-3002 : Step(139): len = 478364, overlap = 127.812
+PHY-3002 : Step(140): len = 479140, overlap = 129.969
+PHY-3002 : Step(141): len = 477142, overlap = 126.438
+PHY-3002 : Step(142): len = 476529, overlap = 127.562
+PHY-3002 : Step(143): len = 478320, overlap = 129.344
+PHY-3002 : Step(144): len = 478836, overlap = 125.094
+PHY-3002 : Step(145): len = 477540, overlap = 125.062
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000612707
+PHY-3002 : Step(146): len = 482687, overlap = 117.688
+PHY-3002 : Step(147): len = 489491, overlap = 119.094
+PHY-3002 : Step(148): len = 491534, overlap = 117.906
+PHY-3002 : Step(149): len = 493489, overlap = 117.719
+PHY-3002 : Step(150): len = 496712, overlap = 120.812
+PHY-3002 : Step(151): len = 498244, overlap = 117.625
+PHY-3002 : Step(152): len = 496738, overlap = 117.781
+PHY-3002 : Step(153): len = 496454, overlap = 121.844
+PHY-3002 : Step(154): len = 498107, overlap = 119.812
+PHY-3002 : Step(155): len = 498636, overlap = 119.625
+PHY-3002 : Step(156): len = 497669, overlap = 118.719
+PHY-3002 : Step(157): len = 497308, overlap = 119.594
+PHY-3002 : Step(158): len = 498337, overlap = 121.906
+PHY-3002 : Step(159): len = 499189, overlap = 124
+PHY-3002 : Step(160): len = 498205, overlap = 122.438
+PHY-3002 : Step(161): len = 497967, overlap = 122.312
+PHY-3002 : Step(162): len = 499080, overlap = 115.125
+PHY-3002 : Step(163): len = 499545, overlap = 115.125
+PHY-3002 : Step(164): len = 498835, overlap = 116
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00104417
+PHY-3002 : Step(165): len = 502168, overlap = 116.312
+PHY-3002 : Step(166): len = 508446, overlap = 112.656
+PHY-3002 : Step(167): len = 510203, overlap = 107.688
+PHY-3002 : Step(168): len = 511290, overlap = 105.625
+PHY-3002 : Step(169): len = 513435, overlap = 109.188
+PHY-3002 : Step(170): len = 515093, overlap = 111.188
+PHY-3002 : Step(171): len = 514859, overlap = 112.656
+PHY-3002 : Step(172): len = 515257, overlap = 117.281
+PHY-3002 : Step(173): len = 517023, overlap = 111.094
+PHY-3002 : Step(174): len = 517599, overlap = 110.344
+PHY-3002 : Step(175): len = 516952, overlap = 116.375
+PHY-3002 : Step(176): len = 516692, overlap = 118.5
+PHY-3002 : Step(177): len = 517369, overlap = 118.812
+PHY-3002 : Step(178): len = 517637, overlap = 121.438
+PHY-3002 : Step(179): len = 517211, overlap = 113.188
+PHY-3002 : Step(180): len = 517062, overlap = 113.188
+PHY-3002 : Step(181): len = 517412, overlap = 113.594
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00172627
+PHY-3002 : Step(182): len = 519143, overlap = 113.094
+PHY-3002 : Step(183): len = 520881, overlap = 115.281
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014445s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (108.2%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20698.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719848, over cnt = 1621(4%), over = 7504, worst = 34
+PHY-1001 : End global iterations; 0.681786s wall, 0.890625s user + 0.046875s system = 0.937500s CPU (137.5%)
+
+PHY-1001 : Congestion index: top1 = 80.09, top5 = 61.04, top10 = 52.25, top15 = 46.89.
+PHY-3001 : End congestion estimation; 0.908777s wall, 1.109375s user + 0.046875s system = 1.156250s CPU (127.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.844896s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000120475
+PHY-3002 : Step(184): len = 657750, overlap = 49.3125
+PHY-3002 : Step(185): len = 657934, overlap = 40.9375
+PHY-3002 : Step(186): len = 652546, overlap = 48.6562
+PHY-3002 : Step(187): len = 651492, overlap = 49.25
+PHY-3002 : Step(188): len = 650078, overlap = 49.0625
+PHY-3002 : Step(189): len = 649587, overlap = 47.0938
+PHY-3002 : Step(190): len = 646317, overlap = 41.5312
+PHY-3002 : Step(191): len = 643796, overlap = 34
+PHY-3002 : Step(192): len = 640381, overlap = 27.8438
+PHY-3002 : Step(193): len = 636790, overlap = 24.6562
+PHY-3002 : Step(194): len = 633030, overlap = 22.0625
+PHY-3002 : Step(195): len = 631100, overlap = 25.4375
+PHY-3002 : Step(196): len = 628734, overlap = 26.0625
+PHY-3002 : Step(197): len = 627377, overlap = 26.5938
+PHY-3002 : Step(198): len = 627856, overlap = 30.875
+PHY-3002 : Step(199): len = 625395, overlap = 32.25
+PHY-3002 : Step(200): len = 622813, overlap = 30.9375
+PHY-3002 : Step(201): len = 620431, overlap = 33.0938
+PHY-3002 : Step(202): len = 618234, overlap = 33.375
+PHY-3002 : Step(203): len = 616020, overlap = 33.6875
+PHY-3002 : Step(204): len = 614536, overlap = 33.875
+PHY-3002 : Step(205): len = 612340, overlap = 35.6875
+PHY-3002 : Step(206): len = 611238, overlap = 36.7812
+PHY-3002 : Step(207): len = 611022, overlap = 37.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00024095
+PHY-3002 : Step(208): len = 615252, overlap = 35.0625
+PHY-3002 : Step(209): len = 618384, overlap = 34.6562
+PHY-3002 : Step(210): len = 620851, overlap = 33.7812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000422275
+PHY-3002 : Step(211): len = 632481, overlap = 33
+PHY-3002 : Step(212): len = 645447, overlap = 32.4062
+PHY-3002 : Step(213): len = 647723, overlap = 33.375
+PHY-3002 : Step(214): len = 648018, overlap = 32.3438
+PHY-3002 : Step(215): len = 649012, overlap = 31.9062
+PHY-3002 : Step(216): len = 650205, overlap = 31.8125
+PHY-3002 : Step(217): len = 652680, overlap = 31.0625
+PHY-3002 : Step(218): len = 656314, overlap = 32.75
+PHY-3002 : Step(219): len = 657603, overlap = 33.125
+PHY-3002 : Step(220): len = 657102, overlap = 32.8438
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000844551
+PHY-3002 : Step(221): len = 661404, overlap = 33.5938
+PHY-3002 : Step(222): len = 669924, overlap = 33.4688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00140359
+PHY-3002 : Step(223): len = 673908, overlap = 33.1875
+PHY-3002 : Step(224): len = 684357, overlap = 33.7812
+PHY-3002 : Step(225): len = 696670, overlap = 33.8125
+PHY-3002 : Step(226): len = 704150, overlap = 34.5938
+PHY-3002 : Step(227): len = 709926, overlap = 33.5938
+PHY-3002 : Step(228): len = 713798, overlap = 34.8125
+PHY-3002 : Step(229): len = 714371, overlap = 32.4062
+PHY-3002 : Step(230): len = 714360, overlap = 35.0625
+PHY-3002 : Step(231): len = 712962, overlap = 37.875
+PHY-3002 : Step(232): len = 710494, overlap = 39.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 58/20698.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 798576, over cnt = 2734(7%), over = 13451, worst = 45
+PHY-1001 : End global iterations; 1.556205s wall, 2.125000s user + 0.015625s system = 2.140625s CPU (137.6%)
+
+PHY-1001 : Congestion index: top1 = 99.38, top5 = 75.17, top10 = 64.66, top15 = 58.46.
+PHY-3001 : End congestion estimation; 1.828739s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (131.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.397065s wall, 1.375000s user + 0.015625s system = 1.390625s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00010921
+PHY-3002 : Step(233): len = 698253, overlap = 265.594
+PHY-3002 : Step(234): len = 691575, overlap = 203.25
+PHY-3002 : Step(235): len = 675519, overlap = 194.469
+PHY-3002 : Step(236): len = 664985, overlap = 174.406
+PHY-3002 : Step(237): len = 654400, overlap = 159.625
+PHY-3002 : Step(238): len = 647226, overlap = 148.375
+PHY-3002 : Step(239): len = 639343, overlap = 145.25
+PHY-3002 : Step(240): len = 633479, overlap = 139.781
+PHY-3002 : Step(241): len = 629648, overlap = 133.312
+PHY-3002 : Step(242): len = 624280, overlap = 135.312
+PHY-3002 : Step(243): len = 619108, overlap = 125.031
+PHY-3002 : Step(244): len = 616629, overlap = 123.469
+PHY-3002 : Step(245): len = 611311, overlap = 126.25
+PHY-3002 : Step(246): len = 607386, overlap = 132.688
+PHY-3002 : Step(247): len = 603370, overlap = 139.594
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00021842
+PHY-3002 : Step(248): len = 604486, overlap = 132.75
+PHY-3002 : Step(249): len = 608200, overlap = 124
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000409205
+PHY-3002 : Step(250): len = 612455, overlap = 116.062
+PHY-3002 : Step(251): len = 619252, overlap = 105.469
+PHY-3002 : Step(252): len = 625488, overlap = 100.406
+PHY-3002 : Step(253): len = 626039, overlap = 97.8125
+PHY-3002 : Step(254): len = 626606, overlap = 95.9375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00081841
+PHY-3002 : Step(255): len = 629393, overlap = 93.125
+PHY-3002 : Step(256): len = 635376, overlap = 90.8438
+PHY-3002 : Step(257): len = 642042, overlap = 80.625
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84584, tnet num: 20520, tinst num: 18119, tnode num: 115319, tedge num: 134878.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.421658s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (100.0%)
+
+RUN-1004 : used memory is 577 MB, reserved memory is 568 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 414.69 peak overflow 2.44
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 517/20698.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737056, over cnt = 3092(8%), over = 11076, worst = 28
+PHY-1001 : End global iterations; 1.422908s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 73.53, top5 = 58.64, top10 = 52.11, top15 = 48.16.
+PHY-1001 : End incremental global routing; 1.766910s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (131.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.929830s wall, 0.890625s user + 0.046875s system = 0.937500s CPU (100.8%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17987 has valid locations, 302 needs to be replaced
+PHY-3001 : design contains 18374 instances, 7772 luts, 9381 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6217 pins
+PHY-3001 : Found 1259 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 665411
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17193/20953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753120, over cnt = 3105(8%), over = 11140, worst = 28
+PHY-1001 : End global iterations; 0.229129s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (129.6%)
+
+PHY-1001 : Congestion index: top1 = 73.25, top5 = 58.71, top10 = 52.60, top15 = 48.66.
+PHY-3001 : End congestion estimation; 0.479371s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (114.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85603, tnet num: 20775, tinst num: 18374, tnode num: 116815, tedge num: 136406.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.441668s wall, 1.390625s user + 0.046875s system = 1.437500s CPU (99.7%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 617 MB, peak memory is 716 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.379185s wall, 2.312500s user + 0.062500s system = 2.375000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(258): len = 664324, overlap = 0
+PHY-3002 : Step(259): len = 663814, overlap = 0
+PHY-3002 : Step(260): len = 663440, overlap = 0
+PHY-3002 : Step(261): len = 663243, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17257/20953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 750160, over cnt = 3115(8%), over = 11242, worst = 28
+PHY-1001 : End global iterations; 0.193740s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (129.0%)
+
+PHY-1001 : Congestion index: top1 = 73.75, top5 = 59.15, top10 = 52.79, top15 = 48.82.
+PHY-3001 : End congestion estimation; 0.444408s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (112.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.019659s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000407508
+PHY-3002 : Step(262): len = 663223, overlap = 83.3438
+PHY-3002 : Step(263): len = 663415, overlap = 82.9688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000815016
+PHY-3002 : Step(264): len = 663551, overlap = 82.5938
+PHY-3002 : Step(265): len = 664172, overlap = 82.5312
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00158658
+PHY-3002 : Step(266): len = 664585, overlap = 82.1875
+PHY-3002 : Step(267): len = 665400, overlap = 81.9688
+PHY-3001 : Final: Len = 665400, Over = 81.9688
+PHY-3001 : End incremental placement; 5.034562s wall, 5.359375s user + 0.265625s system = 5.625000s CPU (111.7%)
+
+OPT-1001 : Total overflow 419.91 peak overflow 2.50
+OPT-1001 : End high-fanout net optimization; 8.250217s wall, 9.187500s user + 0.328125s system = 9.515625s CPU (115.3%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 714, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17202/20953.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 754104, over cnt = 3017(8%), over = 10093, worst = 28
+PHY-1002 : len = 808824, over cnt = 2068(5%), over = 5093, worst = 22
+PHY-1002 : len = 850736, over cnt = 843(2%), over = 1843, worst = 22
+PHY-1002 : len = 873424, over cnt = 184(0%), over = 338, worst = 16
+PHY-1002 : len = 880832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.844393s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 58.94, top5 = 51.45, top10 = 47.56, top15 = 45.04.
+OPT-1001 : End congestion update; 2.095974s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (133.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20775 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.811279s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (100.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 127 cells processed and 17650 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 23 cells processed and 1550 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 250 slack improved
+OPT-1001 : End bottleneck based optimization; 3.208704s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (122.2%)
+
+OPT-1001 : Current memory(MB): used = 697, reserve = 695, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17258/20955.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880640, over cnt = 89(0%), over = 117, worst = 3
+PHY-1002 : len = 880064, over cnt = 57(0%), over = 62, worst = 2
+PHY-1002 : len = 880192, over cnt = 30(0%), over = 33, worst = 2
+PHY-1002 : len = 880448, over cnt = 10(0%), over = 12, worst = 2
+PHY-1002 : len = 880592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.776446s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 59.12, top5 = 51.07, top10 = 47.12, top15 = 44.65.
+OPT-1001 : End congestion update; 1.047981s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (101.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20777 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.787905s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.2%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 4650 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.953632s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (100.8%)
+
+OPT-1001 : Current memory(MB): used = 708, reserve = 703, peak = 735.
+OPT-1001 : End physical optimization; 15.139431s wall, 16.843750s user + 0.375000s system = 17.218750s CPU (113.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7772 LUT to BLE ...
+SYN-4008 : Packed 7772 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6236 remaining SEQ's ...
+SYN-4005 : Packed 4089 SEQ with LUT/SLICE
+SYN-4006 : 841 single LUT's are left
+SYN-4006 : 2147 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9919/13706 primitive instances ...
+PHY-3001 : End packing; 1.644348s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6720 instances
+RUN-1001 : 3286 mslices, 3286 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17943 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10111 nets have 2 pins
+RUN-1001 : 6472 nets have [3 - 5] pins
+RUN-1001 : 741 nets have [6 - 10] pins
+RUN-1001 : 293 nets have [11 - 20] pins
+RUN-1001 : 294 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6718 instances, 6572 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3591 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 675476, Over = 219.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7625/17943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 827840, over cnt = 1983(5%), over = 3252, worst = 9
+PHY-1002 : len = 836488, over cnt = 1230(3%), over = 1712, worst = 7
+PHY-1002 : len = 850040, over cnt = 449(1%), over = 571, worst = 7
+PHY-1002 : len = 856672, over cnt = 146(0%), over = 185, worst = 5
+PHY-1002 : len = 861408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.706100s wall, 2.437500s user + 0.031250s system = 2.468750s CPU (144.7%)
+
+PHY-1001 : Congestion index: top1 = 58.92, top5 = 50.71, top10 = 46.87, top15 = 44.42.
+PHY-3001 : End congestion estimation; 2.101332s wall, 2.828125s user + 0.046875s system = 2.875000s CPU (136.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71721, tnet num: 17765, tinst num: 6718, tnode num: 94295, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.591327s wall, 1.546875s user + 0.031250s system = 1.578125s CPU (99.2%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 619 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.437631s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.77824e-05
+PHY-3002 : Step(268): len = 664146, overlap = 227
+PHY-3002 : Step(269): len = 658208, overlap = 236.5
+PHY-3002 : Step(270): len = 654064, overlap = 242
+PHY-3002 : Step(271): len = 650183, overlap = 233.75
+PHY-3002 : Step(272): len = 646761, overlap = 237.25
+PHY-3002 : Step(273): len = 644462, overlap = 239.75
+PHY-3002 : Step(274): len = 642754, overlap = 239.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000115565
+PHY-3002 : Step(275): len = 645152, overlap = 232.25
+PHY-3002 : Step(276): len = 649449, overlap = 216
+PHY-3002 : Step(277): len = 652203, overlap = 203
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00023113
+PHY-3002 : Step(278): len = 656577, overlap = 198.5
+PHY-3002 : Step(279): len = 663720, overlap = 184.5
+PHY-3002 : Step(280): len = 665538, overlap = 185
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.379746s wall, 0.406250s user + 0.609375s system = 1.015625s CPU (267.4%)
+
+PHY-3001 : Trial Legalized: Len = 742271
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 917/17943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856112, over cnt = 2692(7%), over = 4552, worst = 7
+PHY-1002 : len = 870928, over cnt = 1728(4%), over = 2690, worst = 7
+PHY-1002 : len = 890040, over cnt = 799(2%), over = 1215, worst = 6
+PHY-1002 : len = 904288, over cnt = 241(0%), over = 352, worst = 6
+PHY-1002 : len = 910168, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 2.457913s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (141.8%)
+
+PHY-1001 : Congestion index: top1 = 55.39, top5 = 50.02, top10 = 47.02, top15 = 45.09.
+PHY-3001 : End congestion estimation; 2.917645s wall, 3.937500s user + 0.000000s system = 3.937500s CPU (135.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.830046s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164156
+PHY-3002 : Step(281): len = 716602, overlap = 30.5
+PHY-3002 : Step(282): len = 700358, overlap = 58.75
+PHY-3002 : Step(283): len = 685711, overlap = 89.75
+PHY-3002 : Step(284): len = 677013, overlap = 116.25
+PHY-3002 : Step(285): len = 672719, overlap = 127.75
+PHY-3002 : Step(286): len = 670321, overlap = 133
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328313
+PHY-3002 : Step(287): len = 673942, overlap = 129.5
+PHY-3002 : Step(288): len = 677455, overlap = 125.25
+PHY-3002 : Step(289): len = 678533, overlap = 120.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000656625
+PHY-3002 : Step(290): len = 681479, overlap = 121.5
+PHY-3002 : Step(291): len = 688142, overlap = 115
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.032158s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.2%)
+
+PHY-3001 : Legalized: Len = 716194, Over = 0
+PHY-3001 : Spreading special nets. 434 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.096871s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (96.8%)
+
+PHY-3001 : 642 instances has been re-located, deltaX = 189, deltaY = 388, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 726468, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71721, tnet num: 17765, tinst num: 6721, tnode num: 94295, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.806874s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (99.4%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 651 MB, peak memory is 735 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4302/17943.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 854584, over cnt = 2408(6%), over = 3898, worst = 7
+PHY-1002 : len = 868336, over cnt = 1406(3%), over = 2003, worst = 7
+PHY-1002 : len = 881048, over cnt = 685(1%), over = 916, worst = 7
+PHY-1002 : len = 886160, over cnt = 412(1%), over = 545, worst = 5
+PHY-1002 : len = 897416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.778641s wall, 2.687500s user + 0.062500s system = 2.750000s CPU (154.6%)
+
+PHY-1001 : Congestion index: top1 = 55.39, top5 = 49.26, top10 = 46.18, top15 = 44.13.
+PHY-1001 : End incremental global routing; 2.155988s wall, 3.062500s user + 0.062500s system = 3.125000s CPU (144.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17765 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.841073s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (98.5%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6629 has valid locations, 24 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3671 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 731045
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16331/17969.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903576, over cnt = 96(0%), over = 130, worst = 6
+PHY-1002 : len = 903672, over cnt = 77(0%), over = 94, worst = 5
+PHY-1002 : len = 904136, over cnt = 27(0%), over = 36, worst = 5
+PHY-1002 : len = 904544, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 904576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.814062s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (101.7%)
+
+PHY-1001 : Congestion index: top1 = 55.45, top5 = 49.34, top10 = 46.29, top15 = 44.28.
+PHY-3001 : End congestion estimation; 1.121347s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (101.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71938, tnet num: 17791, tinst num: 6741, tnode num: 94563, tedge num: 119469.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.811786s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (99.2%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 660 MB, peak memory is 735 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.671883s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(292): len = 729297, overlap = 0
+PHY-3002 : Step(293): len = 728492, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16312/17969.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900048, over cnt = 70(0%), over = 93, worst = 6
+PHY-1002 : len = 900168, over cnt = 29(0%), over = 29, worst = 1
+PHY-1002 : len = 900512, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 900528, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.570750s wall, 0.656250s user + 0.031250s system = 0.687500s CPU (120.5%)
+
+PHY-1001 : Congestion index: top1 = 55.39, top5 = 49.37, top10 = 46.30, top15 = 44.24.
+PHY-3001 : End congestion estimation; 0.874388s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (112.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.832983s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000130719
+PHY-3002 : Step(294): len = 728669, overlap = 1.75
+PHY-3002 : Step(295): len = 728669, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005569s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 728660, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059228s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.5%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 728702, Over = 0
+PHY-3001 : End incremental placement; 5.958276s wall, 6.062500s user + 0.093750s system = 6.156250s CPU (103.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.466908s wall, 10.484375s user + 0.203125s system = 10.687500s CPU (112.9%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 736, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16297/17969.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900712, over cnt = 59(0%), over = 71, worst = 3
+PHY-1002 : len = 900656, over cnt = 28(0%), over = 31, worst = 2
+PHY-1002 : len = 900816, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 900848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.567048s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (110.2%)
+
+PHY-1001 : Congestion index: top1 = 55.30, top5 = 49.22, top10 = 46.21, top15 = 44.19.
+OPT-1001 : End congestion update; 0.869067s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (104.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.696379s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.0%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3671 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 737962, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059138s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.3%)
+
+PHY-3001 : 36 instances has been re-located, deltaX = 15, deltaY = 39, maxDist = 3.
+PHY-3001 : Final: Len = 738970, Over = 0
+PHY-3001 : End incremental legalization; 0.369486s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (131.1%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 60 cells processed and 19636 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6653 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6741 instances, 6592 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3671 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 739210, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059823s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+
+PHY-3001 : 20 instances has been re-located, deltaX = 13, deltaY = 20, maxDist = 4.
+PHY-3001 : Final: Len = 739828, Over = 0
+PHY-3001 : End incremental legalization; 0.368441s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (123.0%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 22 cells processed and 2785 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6658 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6746 instances, 6597 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 739888, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.056504s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.6%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 3, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 739872, Over = 0
+PHY-3001 : End incremental legalization; 0.364974s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.5%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 5 cells processed and 779 slack improved
+OPT-1001 : End bottleneck based optimization; 3.123858s wall, 3.453125s user + 0.000000s system = 3.453125s CPU (110.5%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 736, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15938/17969.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911680, over cnt = 164(0%), over = 203, worst = 5
+PHY-1002 : len = 911944, over cnt = 88(0%), over = 96, worst = 3
+PHY-1002 : len = 912464, over cnt = 44(0%), over = 47, worst = 3
+PHY-1002 : len = 913088, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 913104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.792960s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (108.4%)
+
+PHY-1001 : Congestion index: top1 = 55.60, top5 = 49.26, top10 = 46.14, top15 = 44.06.
+OPT-1001 : End congestion update; 1.093452s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.712395s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.9%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6658 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6746 instances, 6597 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3672 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 739924, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064390s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.1%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 11, deltaY = 7, maxDist = 4.
+PHY-3001 : Final: Len = 740276, Over = 0
+PHY-3001 : End incremental legalization; 0.441319s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1750 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.378766s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (107.1%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 736, peak = 737.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.706562s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16301/17969.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913304, over cnt = 27(0%), over = 30, worst = 2
+PHY-1002 : len = 913304, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 913392, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 913392, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 913520, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.727389s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.8%)
+
+PHY-1001 : Congestion index: top1 = 55.60, top5 = 49.26, top10 = 46.14, top15 = 44.07.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.697891s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.241379
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 19.453339s wall, 21.062500s user + 0.218750s system = 21.281250s CPU (109.4%)
+
+RUN-1003 : finish command "place" in 64.296792s wall, 98.453125s user + 5.531250s system = 103.984375s CPU (161.7%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 639 MB, peak memory is 737 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.645933s wall, 2.859375s user + 0.015625s system = 2.875000s CPU (174.7%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 641 MB, peak memory is 737 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6748 instances
+RUN-1001 : 3306 mslices, 3291 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17969 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10104 nets have 2 pins
+RUN-1001 : 6480 nets have [3 - 5] pins
+RUN-1001 : 752 nets have [6 - 10] pins
+RUN-1001 : 298 nets have [11 - 20] pins
+RUN-1001 : 307 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71982, tnet num: 17791, tinst num: 6746, tnode num: 94625, tedge num: 119529.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.557849s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.3%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 663 MB, peak memory is 737 MB
+PHY-1001 : 3306 mslices, 3291 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[1] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842256, over cnt = 2624(7%), over = 4347, worst = 8
+PHY-1002 : len = 861312, over cnt = 1502(4%), over = 2126, worst = 7
+PHY-1002 : len = 883048, over cnt = 398(1%), over = 527, worst = 6
+PHY-1002 : len = 890176, over cnt = 40(0%), over = 49, worst = 6
+PHY-1002 : len = 891408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.948156s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (138.9%)
+
+PHY-1001 : Congestion index: top1 = 54.59, top5 = 48.61, top10 = 45.49, top15 = 43.45.
+PHY-1001 : End global routing; 3.274874s wall, 4.390625s user + 0.031250s system = 4.421875s CPU (135.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 713, peak = 737.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 980, reserve = 982, peak = 980.
+PHY-1001 : End build detailed router design. 3.971625s wall, 3.921875s user + 0.062500s system = 3.984375s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266544, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.180759s wall, 5.156250s user + 0.015625s system = 5.171875s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266600, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.533346s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1016, reserve = 1018, peak = 1016.
+PHY-1001 : End phase 1; 5.727378s wall, 5.703125s user + 0.015625s system = 5.718750s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.26814e+06, over cnt = 1698(0%), over = 1701, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1033, peak = 1032.
+PHY-1001 : End initial routed; 25.290880s wall, 57.750000s user + 0.421875s system = 58.171875s CPU (230.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16891(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.808 | -0.808 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.174824s wall, 3.156250s user + 0.015625s system = 3.171875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1043, peak = 1042.
+PHY-1001 : End phase 2; 28.465767s wall, 60.906250s user + 0.437500s system = 61.343750s CPU (215.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.802ns STNS -0.802ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135544s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.2%)
+
+PHY-1022 : len = 2.26815e+06, over cnt = 1699(0%), over = 1702, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.398838s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.23714e+06, over cnt = 578(0%), over = 579, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.633540s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (158.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.23583e+06, over cnt = 132(0%), over = 132, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.642832s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (136.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.23684e+06, over cnt = 14(0%), over = 14, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.369658s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (114.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.23722e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 4; 0.199818s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16891(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.802 | -0.802 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.173250s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 528 feed throughs used by 393 nets
+PHY-1001 : End commit to database; 2.192673s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1143, reserve = 1148, peak = 1143.
+PHY-1001 : End phase 3; 9.000838s wall, 10.234375s user + 0.000000s system = 10.234375s CPU (113.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.802ns STNS -0.802ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.138716s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1022 : len = 2.23722e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.379758s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.802ns, -0.802ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16891(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.802 | -0.802 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.232749s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 528 feed throughs used by 393 nets
+PHY-1001 : End commit to database; 2.269432s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1156, peak = 1151.
+PHY-1001 : End phase 4; 5.908319s wall, 5.921875s user + 0.000000s system = 5.921875s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.23722e+06
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1159, peak = 1153.
+PHY-1001 : End export database. 0.058374s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.1%)
+
+PHY-1001 : End detail routing; 53.524681s wall, 87.109375s user + 0.515625s system = 87.625000s CPU (163.7%)
+
+RUN-1003 : finish command "route" in 59.375924s wall, 94.078125s user + 0.562500s system = 94.640625s CPU (159.4%)
+
+RUN-1004 : used memory is 1148 MB, reserved memory is 1155 MB, peak memory is 1154 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10200 out of 19600 52.04%
+#reg 9569 out of 19600 48.82%
+#le 12312
+ #lut only 2743 out of 12312 22.28%
+ #reg only 2112 out of 12312 17.15%
+ #lut® 7457 out of 12312 60.57%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1779
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1455
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1323
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 933
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice a_frame_pad_d0_reg_syn_17.q0 130
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 27
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/reg1_syn_136.f1 2
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_236.f0 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P107 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P19 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 N/A OREG
+ a_sp_sampling OUTPUT P148 LVCMOS33 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P173 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P163 LVCMOS33 8 N/A OREG
+ onoff_out OUTPUT P68 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P141 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P146 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P147 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12312 |9173 |1027 |9603 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |554 |498 |23 |448 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |113 |105 |4 |99 |4 |0 |
+| U_crc16_24b |crc16_24b |47 |47 |0 |24 |0 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |750 |378 |96 |572 |0 |0 |
+| u_ADconfig |AD_config |183 |128 |25 |140 |0 |0 |
+| u_gen_sp |gen_sp |255 |135 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |719 |375 |96 |545 |0 |0 |
+| u_ADconfig |AD_config |166 |118 |25 |123 |0 |0 |
+| u_gen_sp |gen_sp |248 |153 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |2971 |2416 |306 |2100 |25 |0 |
+| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |174 |119 |17 |144 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2762 |2292 |289 |1921 |25 |0 |
+| rddpram_ctl |rddpram_ctl |3 |3 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |6 |0 |7 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2323 |1931 |253 |1559 |22 |0 |
+| channelPart |channel_part_8478 |136 |132 |3 |127 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |44 |0 |0 |
+| ram_switch |ram_switch |1822 |1504 |197 |1171 |0 |0 |
+| adc_addr_gen |adc_addr_gen |247 |220 |27 |138 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |17 |14 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |17 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |30 |27 |3 |16 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| insert |insert |965 |674 |170 |671 |0 |0 |
+| ram_switch_state |ram_switch_state |610 |610 |0 |362 |0 |0 |
+| read_ram_i |read_ram |260 |204 |44 |184 |0 |0 |
+| read_ram_addr |read_ram_addr |211 |171 |40 |145 |0 |0 |
+| read_ram_data |read_ram_data |48 |32 |4 |38 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |310 |242 |36 |271 |3 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3120 |2408 |349 |2096 |25 |1 |
+| u0_soft_n |cdc_sync |8 |2 |0 |8 |0 |0 |
+| u_ad_sampling |ad_sampling |185 |100 |17 |155 |0 |0 |
+| u0_soft_n |cdc_sync |3 |0 |0 |3 |0 |0 |
+| u_sort |sort_rev |2897 |2304 |332 |1903 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2446 |1973 |290 |1536 |22 |1 |
+| channelPart |channel_part_8478 |141 |126 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1861 |1534 |197 |1117 |0 |0 |
+| adc_addr_gen |adc_addr_gen |199 |172 |27 |101 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |7 |4 |3 |3 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |15 |12 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |28 |25 |3 |18 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| insert |insert |948 |648 |170 |666 |0 |0 |
+| ram_switch_state |ram_switch_state |714 |714 |0 |350 |0 |0 |
+| read_ram_i |read_ram_rev |354 |240 |81 |210 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |291 |207 |73 |162 |0 |0 |
+| read_ram_data |read_ram_data_rev |63 |33 |8 |48 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10042
+ #2 2 4239
+ #3 3 1687
+ #4 4 551
+ #5 5-10 790
+ #6 11-50 554
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.025619s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (172.0%)
+
+RUN-1004 : used memory is 1149 MB, reserved memory is 1155 MB, peak memory is 1204 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71982, tnet num: 17791, tinst num: 6746, tnode num: 94625, tedge num: 119529.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.562596s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.0%)
+
+RUN-1004 : used memory is 1150 MB, reserved memory is 1156 MB, peak memory is 1204 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17791 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.416335s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (100.4%)
+
+RUN-1004 : used memory is 1151 MB, reserved memory is 1156 MB, peak memory is 1204 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6746
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17969, pip num: 167904
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 528
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3222 valid insts, and 468885 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.266823s wall, 62.609375s user + 0.312500s system = 62.921875s CPU (679.0%)
+
+RUN-1004 : used memory is 1248 MB, reserved memory is 1250 MB, peak memory is 1363 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_134022.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_140657.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_140657.log
new file mode 100644
index 0000000..28868f5
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_140657.log
@@ -0,0 +1,2021 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 14:06:57 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1743)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2139)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.253997s wall, 2.156250s user + 0.093750s system = 2.250000s CPU (99.8%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 317 MB, peak memory is 346 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2951 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18121 instances
+RUN-0007 : 7671 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20698 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13212 nets have 2 pins
+RUN-1001 : 6450 nets have [3 - 5] pins
+RUN-1001 : 618 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 167 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18119 instances, 7671 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6100 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84584, tnet num: 20520, tinst num: 18119, tnode num: 115319, tedge num: 134878.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.172879s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (99.9%)
+
+RUN-1004 : used memory is 535 MB, reserved memory is 517 MB, peak memory is 535 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.964134s wall, 1.921875s user + 0.046875s system = 1.968750s CPU (100.2%)
+
+PHY-3001 : Found 1249 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.15067e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18119.
+PHY-3001 : Level 1 #clusters 2053.
+PHY-3001 : End clustering; 0.126962s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (172.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.33074e+06, overlap = 444.781
+PHY-3002 : Step(2): len = 1.2387e+06, overlap = 505.969
+PHY-3002 : Step(3): len = 878337, overlap = 586.906
+PHY-3002 : Step(4): len = 797193, overlap = 657.906
+PHY-3002 : Step(5): len = 620112, overlap = 756.062
+PHY-3002 : Step(6): len = 560897, overlap = 863.781
+PHY-3002 : Step(7): len = 468576, overlap = 928.312
+PHY-3002 : Step(8): len = 434842, overlap = 969.438
+PHY-3002 : Step(9): len = 385510, overlap = 1042.28
+PHY-3002 : Step(10): len = 360146, overlap = 1090.19
+PHY-3002 : Step(11): len = 323503, overlap = 1095.38
+PHY-3002 : Step(12): len = 301081, overlap = 1132.97
+PHY-3002 : Step(13): len = 278841, overlap = 1215
+PHY-3002 : Step(14): len = 255122, overlap = 1226.47
+PHY-3002 : Step(15): len = 230056, overlap = 1288.91
+PHY-3002 : Step(16): len = 214605, overlap = 1337.72
+PHY-3002 : Step(17): len = 191862, overlap = 1382.84
+PHY-3002 : Step(18): len = 181034, overlap = 1407.19
+PHY-3002 : Step(19): len = 160910, overlap = 1430.28
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.41662e-06
+PHY-3002 : Step(20): len = 164713, overlap = 1386.62
+PHY-3002 : Step(21): len = 201591, overlap = 1247.53
+PHY-3002 : Step(22): len = 208489, overlap = 1212.56
+PHY-3002 : Step(23): len = 212946, overlap = 1164.03
+PHY-3002 : Step(24): len = 212301, overlap = 1123.72
+PHY-3002 : Step(25): len = 209394, overlap = 1125.22
+PHY-3002 : Step(26): len = 205565, overlap = 1092.5
+PHY-3002 : Step(27): len = 204201, overlap = 1066.56
+PHY-3002 : Step(28): len = 200340, overlap = 1066.91
+PHY-3002 : Step(29): len = 200613, overlap = 1073.62
+PHY-3002 : Step(30): len = 197428, overlap = 1055.41
+PHY-3002 : Step(31): len = 197177, overlap = 1051.28
+PHY-3002 : Step(32): len = 193800, overlap = 1068
+PHY-3002 : Step(33): len = 193574, overlap = 1066.41
+PHY-3002 : Step(34): len = 192658, overlap = 1071.06
+PHY-3002 : Step(35): len = 194636, overlap = 1065.56
+PHY-3002 : Step(36): len = 193695, overlap = 1056.03
+PHY-3002 : Step(37): len = 193317, overlap = 1056.53
+PHY-3002 : Step(38): len = 192121, overlap = 1057.41
+PHY-3002 : Step(39): len = 191176, overlap = 1081.06
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.83325e-06
+PHY-3002 : Step(40): len = 197773, overlap = 1072.25
+PHY-3002 : Step(41): len = 210190, overlap = 1033.69
+PHY-3002 : Step(42): len = 213977, overlap = 951.031
+PHY-3002 : Step(43): len = 219466, overlap = 927.688
+PHY-3002 : Step(44): len = 221276, overlap = 910.875
+PHY-3002 : Step(45): len = 222851, overlap = 901.594
+PHY-3002 : Step(46): len = 222095, overlap = 901.062
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.6665e-06
+PHY-3002 : Step(47): len = 232730, overlap = 891.656
+PHY-3002 : Step(48): len = 252398, overlap = 849.75
+PHY-3002 : Step(49): len = 263563, overlap = 774.344
+PHY-3002 : Step(50): len = 270862, overlap = 728.188
+PHY-3002 : Step(51): len = 275597, overlap = 705.938
+PHY-3002 : Step(52): len = 278882, overlap = 691.344
+PHY-3002 : Step(53): len = 274806, overlap = 686.781
+PHY-3002 : Step(54): len = 275040, overlap = 674.625
+PHY-3002 : Step(55): len = 274734, overlap = 660.188
+PHY-3002 : Step(56): len = 274452, overlap = 647.969
+PHY-3002 : Step(57): len = 270796, overlap = 647.594
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.1333e-05
+PHY-3002 : Step(58): len = 286604, overlap = 599.312
+PHY-3002 : Step(59): len = 301899, overlap = 538.062
+PHY-3002 : Step(60): len = 308713, overlap = 483.188
+PHY-3002 : Step(61): len = 314512, overlap = 456.219
+PHY-3002 : Step(62): len = 316375, overlap = 449.031
+PHY-3002 : Step(63): len = 317524, overlap = 440.5
+PHY-3002 : Step(64): len = 314692, overlap = 415.656
+PHY-3002 : Step(65): len = 314943, overlap = 423.812
+PHY-3002 : Step(66): len = 315136, overlap = 425.75
+PHY-3002 : Step(67): len = 315875, overlap = 425.469
+PHY-3002 : Step(68): len = 314779, overlap = 413.688
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.2666e-05
+PHY-3002 : Step(69): len = 331844, overlap = 380.062
+PHY-3002 : Step(70): len = 346666, overlap = 360.062
+PHY-3002 : Step(71): len = 350472, overlap = 355.719
+PHY-3002 : Step(72): len = 352577, overlap = 343.531
+PHY-3002 : Step(73): len = 351951, overlap = 343.938
+PHY-3002 : Step(74): len = 351416, overlap = 350.406
+PHY-3002 : Step(75): len = 350323, overlap = 320.938
+PHY-3002 : Step(76): len = 351528, overlap = 326.25
+PHY-3002 : Step(77): len = 351607, overlap = 316.031
+PHY-3002 : Step(78): len = 351675, overlap = 320.531
+PHY-3002 : Step(79): len = 350919, overlap = 325.5
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.5332e-05
+PHY-3002 : Step(80): len = 365343, overlap = 323.531
+PHY-3002 : Step(81): len = 378962, overlap = 304.812
+PHY-3002 : Step(82): len = 386190, overlap = 286.656
+PHY-3002 : Step(83): len = 390792, overlap = 280.688
+PHY-3002 : Step(84): len = 394242, overlap = 289.25
+PHY-3002 : Step(85): len = 398623, overlap = 281.406
+PHY-3002 : Step(86): len = 395993, overlap = 264.406
+PHY-3002 : Step(87): len = 396161, overlap = 259.75
+PHY-3002 : Step(88): len = 396712, overlap = 264.156
+PHY-3002 : Step(89): len = 398122, overlap = 252.875
+PHY-3002 : Step(90): len = 393596, overlap = 261.344
+PHY-3002 : Step(91): len = 393592, overlap = 247.625
+PHY-3002 : Step(92): len = 394314, overlap = 239.688
+PHY-3002 : Step(93): len = 396823, overlap = 233.781
+PHY-3002 : Step(94): len = 392813, overlap = 229.875
+PHY-3002 : Step(95): len = 392824, overlap = 234
+PHY-3002 : Step(96): len = 392844, overlap = 226.719
+PHY-3002 : Step(97): len = 394420, overlap = 222.719
+PHY-3002 : Step(98): len = 391006, overlap = 233.375
+PHY-3002 : Step(99): len = 391505, overlap = 237.844
+PHY-3002 : Step(100): len = 391731, overlap = 224.219
+PHY-3002 : Step(101): len = 393188, overlap = 231.219
+PHY-3002 : Step(102): len = 392094, overlap = 251.25
+PHY-3002 : Step(103): len = 393805, overlap = 260.906
+PHY-3002 : Step(104): len = 393512, overlap = 243.094
+PHY-3002 : Step(105): len = 394281, overlap = 248.156
+PHY-3002 : Step(106): len = 391718, overlap = 251.156
+PHY-3002 : Step(107): len = 391622, overlap = 254.312
+PHY-3002 : Step(108): len = 391794, overlap = 250.719
+PHY-3002 : Step(109): len = 393053, overlap = 254.844
+PHY-3002 : Step(110): len = 390612, overlap = 257.906
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 9.0664e-05
+PHY-3002 : Step(111): len = 404727, overlap = 240.719
+PHY-3002 : Step(112): len = 413188, overlap = 225.25
+PHY-3002 : Step(113): len = 413213, overlap = 210.219
+PHY-3002 : Step(114): len = 415087, overlap = 203.406
+PHY-3002 : Step(115): len = 419482, overlap = 197.938
+PHY-3002 : Step(116): len = 423526, overlap = 211.375
+PHY-3002 : Step(117): len = 422174, overlap = 201.656
+PHY-3002 : Step(118): len = 422737, overlap = 195.688
+PHY-3002 : Step(119): len = 423532, overlap = 187.75
+PHY-3002 : Step(120): len = 424014, overlap = 195.5
+PHY-3002 : Step(121): len = 421772, overlap = 193.469
+PHY-3002 : Step(122): len = 421400, overlap = 196.156
+PHY-3002 : Step(123): len = 422022, overlap = 200.188
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000181328
+PHY-3002 : Step(124): len = 434715, overlap = 188.75
+PHY-3002 : Step(125): len = 442352, overlap = 179.594
+PHY-3002 : Step(126): len = 441632, overlap = 176.062
+PHY-3002 : Step(127): len = 441552, overlap = 179.688
+PHY-3002 : Step(128): len = 444131, overlap = 167.906
+PHY-3002 : Step(129): len = 446636, overlap = 164.688
+PHY-3002 : Step(130): len = 445774, overlap = 167.688
+PHY-3002 : Step(131): len = 446786, overlap = 168.938
+PHY-3002 : Step(132): len = 449037, overlap = 167.188
+PHY-3002 : Step(133): len = 450855, overlap = 169.156
+PHY-3002 : Step(134): len = 448782, overlap = 169.5
+PHY-3002 : Step(135): len = 448603, overlap = 174.469
+PHY-3002 : Step(136): len = 450671, overlap = 170.562
+PHY-3002 : Step(137): len = 452725, overlap = 168.438
+PHY-3002 : Step(138): len = 451001, overlap = 161.125
+PHY-3002 : Step(139): len = 450603, overlap = 164.125
+PHY-3002 : Step(140): len = 451345, overlap = 167
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000362514
+PHY-3002 : Step(141): len = 459052, overlap = 175.5
+PHY-3002 : Step(142): len = 467498, overlap = 172.562
+PHY-3002 : Step(143): len = 468213, overlap = 162.438
+PHY-3002 : Step(144): len = 468747, overlap = 152.656
+PHY-3002 : Step(145): len = 470805, overlap = 147.094
+PHY-3002 : Step(146): len = 472040, overlap = 144.406
+PHY-3002 : Step(147): len = 471183, overlap = 146.375
+PHY-3002 : Step(148): len = 471798, overlap = 148.312
+PHY-3002 : Step(149): len = 473744, overlap = 146.875
+PHY-3002 : Step(150): len = 475304, overlap = 144.844
+PHY-3002 : Step(151): len = 474957, overlap = 143.562
+PHY-3002 : Step(152): len = 475310, overlap = 142.5
+PHY-3002 : Step(153): len = 476462, overlap = 144.625
+PHY-3002 : Step(154): len = 476726, overlap = 143.781
+PHY-3002 : Step(155): len = 476150, overlap = 142.875
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000620666
+PHY-3002 : Step(156): len = 480770, overlap = 135.125
+PHY-3002 : Step(157): len = 488158, overlap = 134.562
+PHY-3002 : Step(158): len = 489482, overlap = 132.938
+PHY-3002 : Step(159): len = 490807, overlap = 130.5
+PHY-3002 : Step(160): len = 493774, overlap = 133.844
+PHY-3002 : Step(161): len = 495455, overlap = 133.188
+PHY-3002 : Step(162): len = 494426, overlap = 138.844
+PHY-3002 : Step(163): len = 494319, overlap = 136.844
+PHY-3002 : Step(164): len = 495751, overlap = 139.938
+PHY-3002 : Step(165): len = 496175, overlap = 140.656
+PHY-3002 : Step(166): len = 495549, overlap = 139.469
+PHY-3002 : Step(167): len = 495502, overlap = 138.969
+PHY-3002 : Step(168): len = 496855, overlap = 138.031
+PHY-3002 : Step(169): len = 497360, overlap = 139.781
+PHY-3002 : Step(170): len = 496752, overlap = 135.906
+PHY-3002 : Step(171): len = 496721, overlap = 135.219
+PHY-3002 : Step(172): len = 497736, overlap = 136.875
+PHY-3002 : Step(173): len = 497931, overlap = 137.188
+PHY-3002 : Step(174): len = 497753, overlap = 135.781
+PHY-3002 : Step(175): len = 498277, overlap = 135.625
+PHY-3002 : Step(176): len = 499511, overlap = 134.281
+PHY-3002 : Step(177): len = 499511, overlap = 134.281
+PHY-3002 : Step(178): len = 499170, overlap = 134.594
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00102308
+PHY-3002 : Step(179): len = 502256, overlap = 134
+PHY-3002 : Step(180): len = 510382, overlap = 133.375
+PHY-3002 : Step(181): len = 512005, overlap = 128.156
+PHY-3002 : Step(182): len = 512888, overlap = 125.531
+PHY-3002 : Step(183): len = 514046, overlap = 128.469
+PHY-3002 : Step(184): len = 514573, overlap = 131.156
+PHY-3002 : Step(185): len = 513555, overlap = 131.188
+PHY-3002 : Step(186): len = 513226, overlap = 129.156
+PHY-3002 : Step(187): len = 514198, overlap = 127.656
+PHY-3002 : Step(188): len = 515152, overlap = 130.062
+PHY-3002 : Step(189): len = 514575, overlap = 126.531
+PHY-3002 : Step(190): len = 514518, overlap = 126.656
+PHY-3002 : Step(191): len = 515208, overlap = 127.781
+PHY-3002 : Step(192): len = 515413, overlap = 128.094
+PHY-3002 : Step(193): len = 515315, overlap = 129.781
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012890s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20698.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712048, over cnt = 1660(4%), over = 7827, worst = 50
+PHY-1001 : End global iterations; 0.688007s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (138.5%)
+
+PHY-1001 : Congestion index: top1 = 85.47, top5 = 61.55, top10 = 52.48, top15 = 46.83.
+PHY-3001 : End congestion estimation; 0.933939s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (127.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.181258s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000145882
+PHY-3002 : Step(194): len = 650587, overlap = 70.0938
+PHY-3002 : Step(195): len = 653189, overlap = 63.9375
+PHY-3002 : Step(196): len = 650640, overlap = 69.2812
+PHY-3002 : Step(197): len = 650060, overlap = 75.8438
+PHY-3002 : Step(198): len = 650053, overlap = 74.3438
+PHY-3002 : Step(199): len = 649211, overlap = 72.9375
+PHY-3002 : Step(200): len = 646088, overlap = 74.375
+PHY-3002 : Step(201): len = 641279, overlap = 70.9688
+PHY-3002 : Step(202): len = 637620, overlap = 66.5
+PHY-3002 : Step(203): len = 635065, overlap = 59.4375
+PHY-3002 : Step(204): len = 633488, overlap = 53.5312
+PHY-3002 : Step(205): len = 631241, overlap = 48.5312
+PHY-3002 : Step(206): len = 630857, overlap = 43.1562
+PHY-3002 : Step(207): len = 630817, overlap = 40.8125
+PHY-3002 : Step(208): len = 632065, overlap = 35.7188
+PHY-3002 : Step(209): len = 630474, overlap = 38.6562
+PHY-3002 : Step(210): len = 628775, overlap = 41.5625
+PHY-3002 : Step(211): len = 626737, overlap = 42.0938
+PHY-3002 : Step(212): len = 624932, overlap = 41.2188
+PHY-3002 : Step(213): len = 624447, overlap = 39.625
+PHY-3002 : Step(214): len = 624071, overlap = 41.2188
+PHY-3002 : Step(215): len = 622609, overlap = 46.125
+PHY-3002 : Step(216): len = 621718, overlap = 42.3125
+PHY-3002 : Step(217): len = 620724, overlap = 43.9375
+PHY-3002 : Step(218): len = 620133, overlap = 48.8125
+PHY-3002 : Step(219): len = 618193, overlap = 50.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000291764
+PHY-3002 : Step(220): len = 620992, overlap = 47.6875
+PHY-3002 : Step(221): len = 624314, overlap = 43.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000480959
+PHY-3002 : Step(222): len = 627451, overlap = 40.875
+PHY-3002 : Step(223): len = 634551, overlap = 38.1562
+PHY-3002 : Step(224): len = 650750, overlap = 38.9375
+PHY-3002 : Step(225): len = 650859, overlap = 40.7188
+PHY-3002 : Step(226): len = 650840, overlap = 47.5938
+PHY-3002 : Step(227): len = 650614, overlap = 45.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 87/20698.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731256, over cnt = 2734(7%), over = 12371, worst = 34
+PHY-1001 : End global iterations; 1.625866s wall, 2.281250s user + 0.046875s system = 2.328125s CPU (143.2%)
+
+PHY-1001 : Congestion index: top1 = 87.95, top5 = 66.92, top10 = 57.83, top15 = 52.51.
+PHY-3001 : End congestion estimation; 1.916896s wall, 2.578125s user + 0.046875s system = 2.625000s CPU (136.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.248073s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000119942
+PHY-3002 : Step(228): len = 646731, overlap = 220.312
+PHY-3002 : Step(229): len = 647145, overlap = 177.656
+PHY-3002 : Step(230): len = 636696, overlap = 160.594
+PHY-3002 : Step(231): len = 632143, overlap = 146.312
+PHY-3002 : Step(232): len = 627521, overlap = 131.969
+PHY-3002 : Step(233): len = 621872, overlap = 127.312
+PHY-3002 : Step(234): len = 619063, overlap = 121.531
+PHY-3002 : Step(235): len = 616293, overlap = 123.344
+PHY-3002 : Step(236): len = 613639, overlap = 124.812
+PHY-3002 : Step(237): len = 609900, overlap = 125.344
+PHY-3002 : Step(238): len = 608039, overlap = 123.625
+PHY-3002 : Step(239): len = 605070, overlap = 125.406
+PHY-3002 : Step(240): len = 601241, overlap = 122.719
+PHY-3002 : Step(241): len = 599875, overlap = 125.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000239884
+PHY-3002 : Step(242): len = 600740, overlap = 122.812
+PHY-3002 : Step(243): len = 602077, overlap = 122.344
+PHY-3002 : Step(244): len = 604656, overlap = 119.688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000479767
+PHY-3002 : Step(245): len = 610997, overlap = 116.062
+PHY-3002 : Step(246): len = 620737, overlap = 110.312
+PHY-3002 : Step(247): len = 624435, overlap = 108.188
+PHY-3002 : Step(248): len = 621083, overlap = 104.188
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84584, tnet num: 20520, tinst num: 18119, tnode num: 115319, tedge num: 134878.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.485028s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (98.9%)
+
+RUN-1004 : used memory is 578 MB, reserved memory is 565 MB, peak memory is 714 MB
+OPT-1001 : Total overflow 422.16 peak overflow 4.28
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 812/20698.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 716088, over cnt = 2947(8%), over = 11001, worst = 33
+PHY-1001 : End global iterations; 1.229501s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (146.1%)
+
+PHY-1001 : Congestion index: top1 = 67.05, top5 = 57.03, top10 = 51.45, top15 = 47.67.
+PHY-1001 : End incremental global routing; 1.555578s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (136.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.919636s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.2%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17987 has valid locations, 316 needs to be replaced
+PHY-3001 : design contains 18388 instances, 7781 luts, 9386 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6220 pins
+PHY-3001 : Found 1260 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 643793
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16907/20967.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730800, over cnt = 3007(8%), over = 11052, worst = 33
+PHY-1001 : End global iterations; 0.237563s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 66.85, top5 = 57.13, top10 = 51.62, top15 = 48.02.
+PHY-3001 : End congestion estimation; 0.492921s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (114.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85660, tnet num: 20789, tinst num: 18388, tnode num: 116894, tedge num: 136492.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.468103s wall, 1.421875s user + 0.046875s system = 1.468750s CPU (100.0%)
+
+RUN-1004 : used memory is 634 MB, reserved memory is 638 MB, peak memory is 719 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20789 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.777783s wall, 2.718750s user + 0.062500s system = 2.781250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(249): len = 642698, overlap = 0
+PHY-3002 : Step(250): len = 642390, overlap = 0
+PHY-3002 : Step(251): len = 641996, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17015/20967.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 728440, over cnt = 2989(8%), over = 11074, worst = 33
+PHY-1001 : End global iterations; 0.175715s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (115.6%)
+
+PHY-1001 : Congestion index: top1 = 67.26, top5 = 57.17, top10 = 51.63, top15 = 47.99.
+PHY-3001 : End congestion estimation; 0.432565s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (108.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20789 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.937951s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000377718
+PHY-3002 : Step(252): len = 641675, overlap = 107.188
+PHY-3002 : Step(253): len = 641608, overlap = 107.094
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000755436
+PHY-3002 : Step(254): len = 642161, overlap = 107.312
+PHY-3002 : Step(255): len = 642540, overlap = 107
+PHY-3001 : Final: Len = 642540, Over = 107
+PHY-3001 : End incremental placement; 5.304531s wall, 5.375000s user + 0.265625s system = 5.640625s CPU (106.3%)
+
+OPT-1001 : Total overflow 427.50 peak overflow 4.28
+OPT-1001 : End high-fanout net optimization; 8.510633s wall, 9.171875s user + 0.312500s system = 9.484375s CPU (111.4%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 711, peak = 737.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16969/20967.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731248, over cnt = 2907(8%), over = 10027, worst = 33
+PHY-1002 : len = 783872, over cnt = 2029(5%), over = 5116, worst = 19
+PHY-1002 : len = 822896, over cnt = 949(2%), over = 2094, worst = 16
+PHY-1002 : len = 841176, over cnt = 400(1%), over = 920, worst = 15
+PHY-1002 : len = 859632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.689020s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (150.8%)
+
+PHY-1001 : Congestion index: top1 = 57.00, top5 = 50.61, top10 = 47.23, top15 = 45.02.
+OPT-1001 : End congestion update; 1.981053s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (143.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20789 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.815063s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (99.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 114 cells processed and 18050 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 29 cells processed and 3000 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 12 cells processed and 1050 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 700 slack improved
+OPT-1001 : End bottleneck based optimization; 3.202660s wall, 4.046875s user + 0.015625s system = 4.062500s CPU (126.8%)
+
+OPT-1001 : Current memory(MB): used = 697, reserve = 692, peak = 737.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16997/20972.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860320, over cnt = 77(0%), over = 91, worst = 4
+PHY-1002 : len = 859912, over cnt = 36(0%), over = 39, worst = 3
+PHY-1002 : len = 860144, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 860224, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 860256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.703901s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (111.0%)
+
+PHY-1001 : Congestion index: top1 = 57.28, top5 = 50.73, top10 = 47.27, top15 = 45.03.
+OPT-1001 : End congestion update; 0.971524s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (107.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20794 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.808158s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.5%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 21 cells processed and 3900 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.902370s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (104.3%)
+
+OPT-1001 : Current memory(MB): used = 709, reserve = 701, peak = 737.
+OPT-1001 : End physical optimization; 15.409168s wall, 16.937500s user + 0.359375s system = 17.296875s CPU (112.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7781 LUT to BLE ...
+SYN-4008 : Packed 7781 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6244 remaining SEQ's ...
+SYN-4005 : Packed 3977 SEQ with LUT/SLICE
+SYN-4006 : 961 single LUT's are left
+SYN-4006 : 2267 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10048/13835 primitive instances ...
+PHY-3001 : End packing; 1.723816s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6777 instances
+RUN-1001 : 3314 mslices, 3315 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17960 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10111 nets have 2 pins
+RUN-1001 : 6485 nets have [3 - 5] pins
+RUN-1001 : 740 nets have [6 - 10] pins
+RUN-1001 : 291 nets have [11 - 20] pins
+RUN-1001 : 301 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6775 instances, 6629 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3574 pins
+PHY-3001 : Found 478 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 654557, Over = 248.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7522/17960.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 804352, over cnt = 1936(5%), over = 3217, worst = 7
+PHY-1002 : len = 813088, over cnt = 1189(3%), over = 1723, worst = 6
+PHY-1002 : len = 824576, over cnt = 491(1%), over = 699, worst = 6
+PHY-1002 : len = 831768, over cnt = 206(0%), over = 286, worst = 5
+PHY-1002 : len = 836240, over cnt = 7(0%), over = 7, worst = 1
+PHY-1001 : End global iterations; 1.492320s wall, 2.187500s user + 0.046875s system = 2.234375s CPU (149.7%)
+
+PHY-1001 : Congestion index: top1 = 56.49, top5 = 50.17, top10 = 46.61, top15 = 44.14.
+PHY-3001 : End congestion estimation; 1.877863s wall, 2.593750s user + 0.046875s system = 2.640625s CPU (140.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71725, tnet num: 17782, tinst num: 6775, tnode num: 94280, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.629457s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (99.7%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 614 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17782 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.485865s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.35334e-05
+PHY-3002 : Step(256): len = 644420, overlap = 247.75
+PHY-3002 : Step(257): len = 638758, overlap = 247.5
+PHY-3002 : Step(258): len = 635405, overlap = 239.5
+PHY-3002 : Step(259): len = 632829, overlap = 236
+PHY-3002 : Step(260): len = 630588, overlap = 240.25
+PHY-3002 : Step(261): len = 627573, overlap = 241
+PHY-3002 : Step(262): len = 624209, overlap = 237.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000107067
+PHY-3002 : Step(263): len = 627329, overlap = 228.25
+PHY-3002 : Step(264): len = 631510, overlap = 219.25
+PHY-3002 : Step(265): len = 632697, overlap = 214.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000214134
+PHY-3002 : Step(266): len = 637860, overlap = 204
+PHY-3002 : Step(267): len = 643512, overlap = 196.25
+PHY-3002 : Step(268): len = 644067, overlap = 193.25
+PHY-3002 : Step(269): len = 643340, overlap = 189
+PHY-3002 : Step(270): len = 643230, overlap = 189
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.355657s wall, 0.343750s user + 0.593750s system = 0.937500s CPU (263.6%)
+
+PHY-3001 : Trial Legalized: Len = 727241
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 1017/17960.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840800, over cnt = 2703(7%), over = 4669, worst = 9
+PHY-1002 : len = 861872, over cnt = 1524(4%), over = 2156, worst = 7
+PHY-1002 : len = 884896, over cnt = 395(1%), over = 482, worst = 5
+PHY-1002 : len = 890632, over cnt = 117(0%), over = 147, worst = 4
+PHY-1002 : len = 894000, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.689424s wall, 3.765625s user + 0.000000s system = 3.765625s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 56.47, top5 = 50.50, top10 = 47.37, top15 = 45.26.
+PHY-3001 : End congestion estimation; 3.161709s wall, 4.218750s user + 0.000000s system = 4.218750s CPU (133.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17782 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.126777s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000167103
+PHY-3002 : Step(271): len = 700725, overlap = 31.25
+PHY-3002 : Step(272): len = 686098, overlap = 59.25
+PHY-3002 : Step(273): len = 672846, overlap = 85.25
+PHY-3002 : Step(274): len = 664998, overlap = 101.75
+PHY-3002 : Step(275): len = 660244, overlap = 116.5
+PHY-3002 : Step(276): len = 656346, overlap = 130.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000334207
+PHY-3002 : Step(277): len = 660559, overlap = 129
+PHY-3002 : Step(278): len = 664297, overlap = 126
+PHY-3002 : Step(279): len = 665210, overlap = 129.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000668413
+PHY-3002 : Step(280): len = 667306, overlap = 127.5
+PHY-3002 : Step(281): len = 672440, overlap = 125.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033238s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (141.0%)
+
+PHY-3001 : Legalized: Len = 700341, Over = 0
+PHY-3001 : Spreading special nets. 426 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.100426s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (108.9%)
+
+PHY-3001 : 625 instances has been re-located, deltaX = 208, deltaY = 323, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 709277, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71725, tnet num: 17782, tinst num: 6778, tnode num: 94280, tedge num: 119193.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.853511s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (99.5%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 648 MB, peak memory is 737 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 4344/17960.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 834408, over cnt = 2430(6%), over = 3969, worst = 8
+PHY-1002 : len = 848432, over cnt = 1487(4%), over = 2136, worst = 7
+PHY-1002 : len = 863952, over cnt = 674(1%), over = 925, worst = 6
+PHY-1002 : len = 876280, over cnt = 88(0%), over = 123, worst = 4
+PHY-1002 : len = 878184, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.905325s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (146.0%)
+
+PHY-1001 : Congestion index: top1 = 53.71, top5 = 48.62, top10 = 45.78, top15 = 43.84.
+PHY-1001 : End incremental global routing; 2.293384s wall, 3.140625s user + 0.015625s system = 3.156250s CPU (137.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17782 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.853950s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.6%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6797 instances, 6648 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3643 pins
+PHY-3001 : Found 478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 713129
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16266/17977.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 882736, over cnt = 94(0%), over = 119, worst = 7
+PHY-1002 : len = 882848, over cnt = 52(0%), over = 61, worst = 3
+PHY-1002 : len = 883328, over cnt = 8(0%), over = 10, worst = 2
+PHY-1002 : len = 883536, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 883568, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.735866s wall, 0.781250s user + 0.046875s system = 0.828125s CPU (112.5%)
+
+PHY-1001 : Congestion index: top1 = 53.97, top5 = 48.78, top10 = 45.96, top15 = 44.03.
+PHY-3001 : End congestion estimation; 1.037729s wall, 1.078125s user + 0.046875s system = 1.125000s CPU (108.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71909, tnet num: 17799, tinst num: 6797, tnode num: 94502, tedge num: 119418.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.861449s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (99.9%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 660 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17799 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.769389s wall, 2.750000s user + 0.015625s system = 2.765625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(282): len = 711777, overlap = 0
+PHY-3002 : Step(283): len = 711124, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16256/17977.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880088, over cnt = 60(0%), over = 77, worst = 5
+PHY-1002 : len = 880368, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 880456, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 880560, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 880576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.747856s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (104.5%)
+
+PHY-1001 : Congestion index: top1 = 53.69, top5 = 48.66, top10 = 45.86, top15 = 43.95.
+PHY-3001 : End congestion estimation; 1.066255s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (102.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17799 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.853355s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000179838
+PHY-3002 : Step(284): len = 711147, overlap = 2
+PHY-3002 : Step(285): len = 711185, overlap = 2.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.006122s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 711334, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065557s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.3%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 711422, Over = 0
+PHY-3001 : End incremental placement; 6.214255s wall, 6.375000s user + 0.078125s system = 6.453125s CPU (103.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.981023s wall, 10.984375s user + 0.093750s system = 11.078125s CPU (111.0%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 736, peak = 741.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16237/17977.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 881056, over cnt = 54(0%), over = 69, worst = 4
+PHY-1002 : len = 881176, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 881304, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.458136s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.9%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.60, top10 = 45.82, top15 = 43.92.
+OPT-1001 : End congestion update; 0.792578s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17799 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.733945s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6709 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6797 instances, 6648 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3643 pins
+PHY-3001 : Found 478 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 717846, Over = 0
+PHY-3001 : Spreading special nets. 27 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.071862s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (108.7%)
+
+PHY-3001 : 42 instances has been re-located, deltaX = 33, deltaY = 33, maxDist = 4.
+PHY-3001 : Final: Len = 719054, Over = 0
+PHY-3001 : End incremental legalization; 0.472219s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (119.1%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 51 cells processed and 18650 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6709 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6797 instances, 6648 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3643 pins
+PHY-3001 : Found 478 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 718580, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061782s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 6, deltaY = 17, maxDist = 3.
+PHY-3001 : Final: Len = 718660, Over = 0
+PHY-3001 : End incremental legalization; 0.424478s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 27 cells processed and 3813 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6709 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6797 instances, 6648 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3643 pins
+PHY-3001 : Found 478 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 719124, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065023s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.1%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 15, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 719628, Over = 0
+PHY-3001 : End incremental legalization; 0.435931s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.4%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 19 cells processed and 1931 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3647 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 719959, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.068596s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (113.9%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 3, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 720149, Over = 0
+PHY-3001 : End incremental legalization; 0.400481s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (117.0%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 5 cells processed and 616 slack improved
+OPT-1001 : End bottleneck based optimization; 3.899200s wall, 4.140625s user + 0.031250s system = 4.171875s CPU (107.0%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 736, peak = 741.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15821/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 889840, over cnt = 172(0%), over = 209, worst = 4
+PHY-1002 : len = 890208, over cnt = 88(0%), over = 93, worst = 2
+PHY-1002 : len = 890896, over cnt = 33(0%), over = 34, worst = 2
+PHY-1002 : len = 891248, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 891432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.901603s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 53.66, top5 = 48.75, top10 = 45.85, top15 = 43.98.
+OPT-1001 : End congestion update; 1.230079s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (106.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.735869s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.8%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6803 instances, 6654 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3647 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 720065, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061584s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.5%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 6, deltaY = 4, maxDist = 3.
+PHY-3001 : Final: Len = 720271, Over = 0
+PHY-3001 : End incremental legalization; 0.429668s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (123.6%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 9 cells processed and 1050 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.521560s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (106.6%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 736, peak = 741.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.760337s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16264/17983.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891504, over cnt = 21(0%), over = 24, worst = 2
+PHY-1002 : len = 891464, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 891512, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 891536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.574056s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (103.4%)
+
+PHY-1001 : Congestion index: top1 = 53.62, top5 = 48.76, top10 = 45.85, top15 = 43.98.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.707931s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.206897
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 20.869117s wall, 22.375000s user + 0.140625s system = 22.515625s CPU (107.9%)
+
+RUN-1003 : finish command "place" in 66.341380s wall, 95.656250s user + 5.484375s system = 101.140625s CPU (152.5%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 643 MB, peak memory is 741 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.739921s wall, 3.031250s user + 0.000000s system = 3.031250s CPU (174.2%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 643 MB, peak memory is 741 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6805 instances
+RUN-1001 : 3321 mslices, 3333 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17983 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10107 nets have 2 pins
+RUN-1001 : 6487 nets have [3 - 5] pins
+RUN-1001 : 749 nets have [6 - 10] pins
+RUN-1001 : 300 nets have [11 - 20] pins
+RUN-1001 : 312 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71957, tnet num: 17805, tinst num: 6803, tnode num: 94569, tedge num: 119489.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.695742s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (99.5%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 661 MB, peak memory is 741 MB
+PHY-1001 : 3321 mslices, 3333 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[25] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 822808, over cnt = 2705(7%), over = 4483, worst = 8
+PHY-1002 : len = 844120, over cnt = 1427(4%), over = 1982, worst = 6
+PHY-1002 : len = 857344, over cnt = 725(2%), over = 976, worst = 6
+PHY-1002 : len = 872920, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 873112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.969999s wall, 4.015625s user + 0.000000s system = 4.015625s CPU (135.2%)
+
+PHY-1001 : Congestion index: top1 = 53.34, top5 = 48.40, top10 = 45.46, top15 = 43.50.
+PHY-1001 : End global routing; 3.317493s wall, 4.359375s user + 0.000000s system = 4.359375s CPU (131.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 714, reserve = 714, peak = 741.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 987, reserve = 988, peak = 987.
+PHY-1001 : End build detailed router design. 4.144445s wall, 4.000000s user + 0.062500s system = 4.062500s CPU (98.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267608, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.446110s wall, 5.406250s user + 0.015625s system = 5.421875s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267664, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.517848s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (96.6%)
+
+PHY-1001 : Current memory(MB): used = 1022, reserve = 1024, peak = 1022.
+PHY-1001 : End phase 1; 5.976319s wall, 5.921875s user + 0.015625s system = 5.937500s CPU (99.4%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.22317e+06, over cnt = 2060(0%), over = 2075, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1035, peak = 1036.
+PHY-1001 : End initial routed; 24.474372s wall, 58.406250s user + 0.250000s system = 58.656250s CPU (239.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16904(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.664 | -0.664 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.237112s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1044, peak = 1045.
+PHY-1001 : End phase 2; 27.711544s wall, 61.640625s user + 0.250000s system = 61.890625s CPU (223.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 2 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135368s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.9%)
+
+PHY-1022 : len = 2.22317e+06, over cnt = 2060(0%), over = 2075, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.398316s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.19106e+06, over cnt = 750(0%), over = 752, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.650327s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (161.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.18826e+06, over cnt = 142(0%), over = 142, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.774334s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (171.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.18912e+06, over cnt = 25(0%), over = 25, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.441165s wall, 0.562500s user + 0.015625s system = 0.578125s CPU (131.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.18942e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.236000s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (112.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.1895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.178210s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (105.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.1895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.196487s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.1895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.256466s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (97.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.1895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.163977s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.18951e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.161892s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16904(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.210794s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 621 feed throughs used by 444 nets
+PHY-1001 : End commit to database; 2.185270s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1148, reserve = 1150, peak = 1148.
+PHY-1001 : End phase 3; 10.273370s wall, 11.968750s user + 0.031250s system = 12.000000s CPU (116.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.131523s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (95.0%)
+
+PHY-1022 : len = 2.18951e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.367584s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16904(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.195923s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 621 feed throughs used by 444 nets
+PHY-1001 : End commit to database; 2.280158s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1159, peak = 1156.
+PHY-1001 : End phase 4; 5.870683s wall, 5.875000s user + 0.000000s system = 5.875000s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.18951e+06
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1161, peak = 1158.
+PHY-1001 : End export database. 0.061425s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.8%)
+
+PHY-1001 : End detail routing; 54.429318s wall, 89.859375s user + 0.359375s system = 90.218750s CPU (165.8%)
+
+RUN-1003 : finish command "route" in 60.588290s wall, 97.062500s user + 0.375000s system = 97.437500s CPU (160.8%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1086 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10204 out of 19600 52.06%
+#reg 9572 out of 19600 48.84%
+#le 12439
+ #lut only 2867 out of 12439 23.05%
+ #reg only 2235 out of 12439 17.97%
+ #lut® 7337 out of 12439 58.98%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1772
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1440
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1313
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 932
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice color_mode_reg_syn_14.q0 139
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg45_syn_193.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u1_test_en/reg0_syn_28.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P173 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P70 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE OREG
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P72 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P107 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P163 LVCMOS33 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12439 |9177 |1027 |9606 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |530 |444 |23 |431 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |99 |92 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |36 |36 |0 |18 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |10 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |748 |367 |96 |570 |0 |0 |
+| u_ADconfig |AD_config |183 |110 |25 |139 |0 |0 |
+| u_gen_sp |gen_sp |248 |161 |71 |114 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |382 |96 |561 |0 |0 |
+| u_ADconfig |AD_config |172 |101 |25 |127 |0 |0 |
+| u_gen_sp |gen_sp |256 |161 |71 |119 |0 |0 |
+| sampling_fe_a |sampling_fe |3012 |2454 |306 |2089 |25 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |183 |143 |17 |152 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2798 |2297 |289 |1906 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2386 |1971 |253 |1557 |22 |0 |
+| channelPart |channel_part_8478 |139 |134 |3 |130 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1878 |1539 |197 |1157 |0 |0 |
+| adc_addr_gen |adc_addr_gen |226 |199 |27 |118 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |27 |24 |3 |17 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |10 |0 |0 |
+| insert |insert |954 |642 |170 |657 |0 |0 |
+| ram_switch_state |ram_switch_state |698 |698 |0 |382 |0 |0 |
+| read_ram_i |read_ram |283 |225 |44 |198 |0 |0 |
+| read_ram_addr |read_ram_addr |231 |191 |40 |156 |0 |0 |
+| read_ram_data |read_ram_data |52 |34 |4 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |312 |232 |36 |273 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3186 |2469 |349 |2069 |25 |1 |
+| u0_soft_n |cdc_sync |8 |2 |0 |8 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |103 |17 |160 |0 |0 |
+| u0_soft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u_sort |sort_rev |2961 |2336 |332 |1873 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2537 |2041 |290 |1520 |22 |1 |
+| channelPart |channel_part_8478 |151 |135 |3 |145 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1951 |1592 |197 |1099 |0 |0 |
+| adc_addr_gen |adc_addr_gen |206 |179 |27 |100 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |13 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |6 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |16 |13 |3 |9 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |8 |0 |0 |
+| insert |insert |959 |628 |170 |680 |0 |0 |
+| ram_switch_state |ram_switch_state |786 |785 |0 |319 |0 |0 |
+| read_ram_i |read_ram_rev |350 |246 |81 |206 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |289 |211 |73 |160 |0 |0 |
+| read_ram_data |read_ram_data_rev |61 |35 |8 |46 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10045
+ #2 2 4252
+ #3 3 1675
+ #4 4 557
+ #5 5-10 792
+ #6 11-50 552
+ #7 51-100 14
+ #8 >500 1
+ Average 2.71
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.027633s wall, 3.468750s user + 0.015625s system = 3.484375s CPU (171.8%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1088 MB, peak memory is 1158 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71957, tnet num: 17805, tinst num: 6803, tnode num: 94569, tedge num: 119489.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.570447s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.5%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1093 MB, peak memory is 1158 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17805 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.424115s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (99.8%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1095 MB, peak memory is 1158 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6803
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17983, pip num: 167077
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 621
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3239 valid insts, and 467795 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.319346s wall, 60.015625s user + 0.171875s system = 60.187500s CPU (645.8%)
+
+RUN-1004 : used memory is 1252 MB, reserved memory is 1251 MB, peak memory is 1368 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_140657.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_141628.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_141628.log
new file mode 100644
index 0000000..c40f592
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_141628.log
@@ -0,0 +1,2144 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 14:16:28 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.285875s wall, 2.218750s user + 0.062500s system = 2.281250s CPU (99.8%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 316 MB, peak memory is 347 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2950 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18108 instances
+RUN-0007 : 7658 luts, 9227 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20685 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13201 nets have 2 pins
+RUN-1001 : 6446 nets have [3 - 5] pins
+RUN-1001 : 622 nets have [6 - 10] pins
+RUN-1001 : 179 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1993
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18106 instances, 7658 luts, 9227 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6099 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84555, tnet num: 20507, tinst num: 18106, tnode num: 115287, tedge num: 134846.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.986114s wall, 1.312500s user + 0.031250s system = 1.343750s CPU (67.7%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 517 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20507 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.802493s wall, 2.093750s user + 0.062500s system = 2.156250s CPU (76.9%)
+
+PHY-3001 : Found 1247 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.12963e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18106.
+PHY-3001 : Level 1 #clusters 2075.
+PHY-3001 : End clustering; 0.130490s wall, 0.140625s user + 0.031250s system = 0.171875s CPU (131.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.363e+06, overlap = 449.375
+PHY-3002 : Step(2): len = 1.26204e+06, overlap = 491.281
+PHY-3002 : Step(3): len = 876550, overlap = 592.188
+PHY-3002 : Step(4): len = 803166, overlap = 656.781
+PHY-3002 : Step(5): len = 613701, overlap = 767.75
+PHY-3002 : Step(6): len = 552443, overlap = 862.156
+PHY-3002 : Step(7): len = 464813, overlap = 945.156
+PHY-3002 : Step(8): len = 426720, overlap = 987.656
+PHY-3002 : Step(9): len = 381925, overlap = 1049.66
+PHY-3002 : Step(10): len = 353406, overlap = 1115.34
+PHY-3002 : Step(11): len = 320667, overlap = 1164.28
+PHY-3002 : Step(12): len = 291213, overlap = 1201.19
+PHY-3002 : Step(13): len = 266861, overlap = 1226.47
+PHY-3002 : Step(14): len = 243771, overlap = 1238.75
+PHY-3002 : Step(15): len = 222667, overlap = 1277.78
+PHY-3002 : Step(16): len = 209196, overlap = 1306
+PHY-3002 : Step(17): len = 191164, overlap = 1344.34
+PHY-3002 : Step(18): len = 173611, overlap = 1368.25
+PHY-3002 : Step(19): len = 161567, overlap = 1417.09
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.41782e-06
+PHY-3002 : Step(20): len = 163927, overlap = 1352.19
+PHY-3002 : Step(21): len = 205049, overlap = 1233.38
+PHY-3002 : Step(22): len = 211950, overlap = 1163.56
+PHY-3002 : Step(23): len = 214115, overlap = 1125.5
+PHY-3002 : Step(24): len = 210924, overlap = 1102.03
+PHY-3002 : Step(25): len = 208466, overlap = 1047.66
+PHY-3002 : Step(26): len = 209880, overlap = 1010.31
+PHY-3002 : Step(27): len = 209025, overlap = 1006.75
+PHY-3002 : Step(28): len = 206932, overlap = 984.906
+PHY-3002 : Step(29): len = 202880, overlap = 975.344
+PHY-3002 : Step(30): len = 200287, overlap = 980.25
+PHY-3002 : Step(31): len = 198176, overlap = 1001.56
+PHY-3002 : Step(32): len = 195387, overlap = 993.719
+PHY-3002 : Step(33): len = 192668, overlap = 988.219
+PHY-3002 : Step(34): len = 190811, overlap = 996.844
+PHY-3002 : Step(35): len = 189243, overlap = 1015.91
+PHY-3002 : Step(36): len = 186913, overlap = 1020.53
+PHY-3002 : Step(37): len = 186008, overlap = 1031.56
+PHY-3002 : Step(38): len = 184433, overlap = 1024.28
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.83564e-06
+PHY-3002 : Step(39): len = 190018, overlap = 1013.31
+PHY-3002 : Step(40): len = 201815, overlap = 972.531
+PHY-3002 : Step(41): len = 205219, overlap = 951.469
+PHY-3002 : Step(42): len = 210222, overlap = 924.906
+PHY-3002 : Step(43): len = 213971, overlap = 907.844
+PHY-3002 : Step(44): len = 214887, overlap = 892.406
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.67128e-06
+PHY-3002 : Step(45): len = 225508, overlap = 839.062
+PHY-3002 : Step(46): len = 247898, overlap = 776.594
+PHY-3002 : Step(47): len = 262707, overlap = 726.875
+PHY-3002 : Step(48): len = 269261, overlap = 711.25
+PHY-3002 : Step(49): len = 267504, overlap = 683.719
+PHY-3002 : Step(50): len = 267697, overlap = 676.312
+PHY-3002 : Step(51): len = 265205, overlap = 676.812
+PHY-3002 : Step(52): len = 264481, overlap = 666.25
+PHY-3002 : Step(53): len = 263603, overlap = 646
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.13426e-05
+PHY-3002 : Step(54): len = 279191, overlap = 617.938
+PHY-3002 : Step(55): len = 297450, overlap = 565.562
+PHY-3002 : Step(56): len = 305755, overlap = 541.625
+PHY-3002 : Step(57): len = 308663, overlap = 529.719
+PHY-3002 : Step(58): len = 305884, overlap = 524.969
+PHY-3002 : Step(59): len = 304798, overlap = 519.281
+PHY-3002 : Step(60): len = 304801, overlap = 501.531
+PHY-3002 : Step(61): len = 306151, overlap = 485.562
+PHY-3002 : Step(62): len = 306709, overlap = 471.438
+PHY-3002 : Step(63): len = 306833, overlap = 466.438
+PHY-3002 : Step(64): len = 307136, overlap = 456.75
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.26851e-05
+PHY-3002 : Step(65): len = 325472, overlap = 425.594
+PHY-3002 : Step(66): len = 340862, overlap = 382.25
+PHY-3002 : Step(67): len = 347384, overlap = 367.344
+PHY-3002 : Step(68): len = 351506, overlap = 363.094
+PHY-3002 : Step(69): len = 349756, overlap = 349.812
+PHY-3002 : Step(70): len = 350648, overlap = 328.406
+PHY-3002 : Step(71): len = 349628, overlap = 296.469
+PHY-3002 : Step(72): len = 350966, overlap = 302.531
+PHY-3002 : Step(73): len = 350257, overlap = 294.312
+PHY-3002 : Step(74): len = 351289, overlap = 291.438
+PHY-3002 : Step(75): len = 350072, overlap = 281.312
+PHY-3002 : Step(76): len = 350095, overlap = 302.438
+PHY-3002 : Step(77): len = 349904, overlap = 273.031
+PHY-3002 : Step(78): len = 349917, overlap = 288.906
+PHY-3002 : Step(79): len = 349687, overlap = 305.344
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.53702e-05
+PHY-3002 : Step(80): len = 367242, overlap = 295.781
+PHY-3002 : Step(81): len = 380213, overlap = 285.531
+PHY-3002 : Step(82): len = 381008, overlap = 269.906
+PHY-3002 : Step(83): len = 382014, overlap = 276.406
+PHY-3002 : Step(84): len = 382805, overlap = 277
+PHY-3002 : Step(85): len = 383993, overlap = 274.844
+PHY-3002 : Step(86): len = 381266, overlap = 264.25
+PHY-3002 : Step(87): len = 382458, overlap = 252.812
+PHY-3002 : Step(88): len = 385085, overlap = 241.938
+PHY-3002 : Step(89): len = 386904, overlap = 249.719
+PHY-3002 : Step(90): len = 385140, overlap = 239.031
+PHY-3002 : Step(91): len = 386078, overlap = 236.375
+PHY-3002 : Step(92): len = 387737, overlap = 243.562
+PHY-3002 : Step(93): len = 388987, overlap = 249.75
+PHY-3002 : Step(94): len = 385141, overlap = 250.906
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.92447e-05
+PHY-3002 : Step(95): len = 402450, overlap = 244.125
+PHY-3002 : Step(96): len = 414961, overlap = 238.188
+PHY-3002 : Step(97): len = 413836, overlap = 231.906
+PHY-3002 : Step(98): len = 413897, overlap = 234.562
+PHY-3002 : Step(99): len = 416130, overlap = 230.938
+PHY-3002 : Step(100): len = 418970, overlap = 225.344
+PHY-3002 : Step(101): len = 417603, overlap = 222.656
+PHY-3002 : Step(102): len = 419577, overlap = 204.156
+PHY-3002 : Step(103): len = 422571, overlap = 217.531
+PHY-3002 : Step(104): len = 424690, overlap = 220.125
+PHY-3002 : Step(105): len = 423417, overlap = 218.812
+PHY-3002 : Step(106): len = 424540, overlap = 213.312
+PHY-3002 : Step(107): len = 426681, overlap = 228.75
+PHY-3002 : Step(108): len = 429597, overlap = 223.344
+PHY-3002 : Step(109): len = 425099, overlap = 225.656
+PHY-3002 : Step(110): len = 424044, overlap = 231.094
+PHY-3002 : Step(111): len = 425453, overlap = 237.031
+PHY-3002 : Step(112): len = 427666, overlap = 237.125
+PHY-3002 : Step(113): len = 423660, overlap = 233.812
+PHY-3002 : Step(114): len = 423311, overlap = 235.281
+PHY-3002 : Step(115): len = 425384, overlap = 250.812
+PHY-3002 : Step(116): len = 427531, overlap = 244.719
+PHY-3002 : Step(117): len = 425179, overlap = 237.312
+PHY-3002 : Step(118): len = 425110, overlap = 233.469
+PHY-3002 : Step(119): len = 426474, overlap = 230.344
+PHY-3002 : Step(120): len = 428153, overlap = 222.688
+PHY-3002 : Step(121): len = 425946, overlap = 208.219
+PHY-3002 : Step(122): len = 425657, overlap = 205.594
+PHY-3002 : Step(123): len = 426910, overlap = 202.562
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000178489
+PHY-3002 : Step(124): len = 439178, overlap = 197.969
+PHY-3002 : Step(125): len = 446888, overlap = 185.5
+PHY-3002 : Step(126): len = 447732, overlap = 186.156
+PHY-3002 : Step(127): len = 449441, overlap = 183.938
+PHY-3002 : Step(128): len = 452191, overlap = 179.812
+PHY-3002 : Step(129): len = 454696, overlap = 170.188
+PHY-3002 : Step(130): len = 453475, overlap = 168.719
+PHY-3002 : Step(131): len = 454302, overlap = 170.844
+PHY-3002 : Step(132): len = 456842, overlap = 167.75
+PHY-3002 : Step(133): len = 458474, overlap = 163.844
+PHY-3002 : Step(134): len = 456954, overlap = 161.906
+PHY-3002 : Step(135): len = 456662, overlap = 161.094
+PHY-3002 : Step(136): len = 457730, overlap = 162.75
+PHY-3002 : Step(137): len = 458346, overlap = 161.281
+PHY-3002 : Step(138): len = 457067, overlap = 161.469
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000331637
+PHY-3002 : Step(139): len = 465108, overlap = 150.656
+PHY-3002 : Step(140): len = 471717, overlap = 152.594
+PHY-3002 : Step(141): len = 472608, overlap = 147.562
+PHY-3002 : Step(142): len = 473381, overlap = 145.156
+PHY-3002 : Step(143): len = 475753, overlap = 150
+PHY-3002 : Step(144): len = 477458, overlap = 151.906
+PHY-3002 : Step(145): len = 476952, overlap = 149
+PHY-3002 : Step(146): len = 477378, overlap = 149.188
+PHY-3002 : Step(147): len = 478397, overlap = 148.344
+PHY-3002 : Step(148): len = 479233, overlap = 148.844
+PHY-3002 : Step(149): len = 479020, overlap = 154.438
+PHY-3002 : Step(150): len = 479904, overlap = 160.75
+PHY-3002 : Step(151): len = 481157, overlap = 160.25
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000663273
+PHY-3002 : Step(152): len = 486713, overlap = 156.188
+PHY-3002 : Step(153): len = 494354, overlap = 159
+PHY-3002 : Step(154): len = 497501, overlap = 157.562
+PHY-3002 : Step(155): len = 500667, overlap = 156.344
+PHY-3002 : Step(156): len = 501986, overlap = 148.812
+PHY-3002 : Step(157): len = 502894, overlap = 149.5
+PHY-3002 : Step(158): len = 502771, overlap = 137.969
+PHY-3002 : Step(159): len = 503066, overlap = 131.375
+PHY-3002 : Step(160): len = 503864, overlap = 128.625
+PHY-3002 : Step(161): len = 504163, overlap = 135.594
+PHY-3002 : Step(162): len = 503881, overlap = 130.219
+PHY-3002 : Step(163): len = 504034, overlap = 127.375
+PHY-3002 : Step(164): len = 504939, overlap = 124.344
+PHY-3002 : Step(165): len = 505390, overlap = 119.188
+PHY-3002 : Step(166): len = 505325, overlap = 129.656
+PHY-3002 : Step(167): len = 505565, overlap = 133
+PHY-3002 : Step(168): len = 505908, overlap = 121.562
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00123484
+PHY-3002 : Step(169): len = 509300, overlap = 127.594
+PHY-3002 : Step(170): len = 513888, overlap = 118.375
+PHY-3002 : Step(171): len = 515695, overlap = 112.281
+PHY-3002 : Step(172): len = 517287, overlap = 115.688
+PHY-3002 : Step(173): len = 519206, overlap = 113.844
+PHY-3002 : Step(174): len = 520724, overlap = 118.156
+PHY-3002 : Step(175): len = 521011, overlap = 115
+PHY-3002 : Step(176): len = 521483, overlap = 116.125
+PHY-3002 : Step(177): len = 523196, overlap = 112.062
+PHY-3002 : Step(178): len = 524294, overlap = 112.531
+PHY-3002 : Step(179): len = 523967, overlap = 111.531
+PHY-3002 : Step(180): len = 524000, overlap = 110.438
+PHY-3002 : Step(181): len = 524646, overlap = 112.469
+PHY-3002 : Step(182): len = 525059, overlap = 117.5
+PHY-3002 : Step(183): len = 524798, overlap = 117.125
+PHY-3002 : Step(184): len = 525083, overlap = 118.156
+PHY-3002 : Step(185): len = 526111, overlap = 120.406
+PHY-3002 : Step(186): len = 526538, overlap = 122.156
+PHY-3002 : Step(187): len = 526109, overlap = 128
+PHY-3002 : Step(188): len = 526077, overlap = 129.469
+PHY-3002 : Step(189): len = 526605, overlap = 127.281
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00220567
+PHY-3002 : Step(190): len = 529645, overlap = 123.844
+PHY-3002 : Step(191): len = 534877, overlap = 125.281
+PHY-3002 : Step(192): len = 536053, overlap = 125.156
+PHY-3002 : Step(193): len = 537015, overlap = 123.062
+PHY-3002 : Step(194): len = 538046, overlap = 119.188
+PHY-3002 : Step(195): len = 538863, overlap = 118.531
+PHY-3002 : Step(196): len = 539629, overlap = 124.062
+PHY-3002 : Step(197): len = 541009, overlap = 120
+PHY-3002 : Step(198): len = 541906, overlap = 117.531
+PHY-3002 : Step(199): len = 542550, overlap = 116.781
+PHY-3002 : Step(200): len = 542970, overlap = 120.125
+PHY-3002 : Step(201): len = 543431, overlap = 121.562
+PHY-3002 : Step(202): len = 543921, overlap = 120.594
+PHY-3002 : Step(203): len = 544207, overlap = 118.906
+PHY-3002 : Step(204): len = 544289, overlap = 119.312
+PHY-3002 : Step(205): len = 544390, overlap = 118.938
+PHY-3002 : Step(206): len = 544377, overlap = 119.531
+PHY-3002 : Step(207): len = 544324, overlap = 119.531
+PHY-3002 : Step(208): len = 544180, overlap = 119.062
+PHY-3002 : Step(209): len = 544186, overlap = 116.812
+PHY-3002 : Step(210): len = 544421, overlap = 117.25
+PHY-3002 : Step(211): len = 544577, overlap = 118.25
+PHY-3002 : Step(212): len = 544416, overlap = 114.281
+PHY-3002 : Step(213): len = 544358, overlap = 112.406
+PHY-3002 : Step(214): len = 544519, overlap = 112.844
+PHY-3002 : Step(215): len = 544589, overlap = 112.844
+PHY-3002 : Step(216): len = 544495, overlap = 111.594
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015117s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (103.4%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20685.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 717576, over cnt = 1635(4%), over = 7737, worst = 36
+PHY-1001 : End global iterations; 0.666881s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (138.2%)
+
+PHY-1001 : Congestion index: top1 = 85.19, top5 = 64.66, top10 = 54.40, top15 = 48.06.
+PHY-3001 : End congestion estimation; 0.903753s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (127.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20507 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.861082s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000168474
+PHY-3002 : Step(217): len = 653099, overlap = 80.4688
+PHY-3002 : Step(218): len = 656542, overlap = 75.5
+PHY-3002 : Step(219): len = 651711, overlap = 72.5625
+PHY-3002 : Step(220): len = 648396, overlap = 73.6875
+PHY-3002 : Step(221): len = 646503, overlap = 72.0312
+PHY-3002 : Step(222): len = 646255, overlap = 74.5625
+PHY-3002 : Step(223): len = 644958, overlap = 70.3125
+PHY-3002 : Step(224): len = 644249, overlap = 66.4688
+PHY-3002 : Step(225): len = 642342, overlap = 62.8125
+PHY-3002 : Step(226): len = 639600, overlap = 60.625
+PHY-3002 : Step(227): len = 636403, overlap = 53.3438
+PHY-3002 : Step(228): len = 634075, overlap = 45.7188
+PHY-3002 : Step(229): len = 631843, overlap = 42.875
+PHY-3002 : Step(230): len = 629438, overlap = 41.2812
+PHY-3002 : Step(231): len = 628010, overlap = 37.5
+PHY-3002 : Step(232): len = 626203, overlap = 36.25
+PHY-3002 : Step(233): len = 624764, overlap = 35.5
+PHY-3002 : Step(234): len = 623646, overlap = 33.4375
+PHY-3002 : Step(235): len = 622388, overlap = 32
+PHY-3002 : Step(236): len = 621707, overlap = 31.4375
+PHY-3002 : Step(237): len = 620071, overlap = 31.5938
+PHY-3002 : Step(238): len = 618392, overlap = 30.0625
+PHY-3002 : Step(239): len = 617109, overlap = 31
+PHY-3002 : Step(240): len = 615757, overlap = 32.375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000336947
+PHY-3002 : Step(241): len = 616907, overlap = 30.5625
+PHY-3002 : Step(242): len = 620698, overlap = 31.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 86/20685.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 703608, over cnt = 2685(7%), over = 11570, worst = 50
+PHY-1001 : End global iterations; 1.705299s wall, 2.171875s user + 0.031250s system = 2.203125s CPU (129.2%)
+
+PHY-1001 : Congestion index: top1 = 84.18, top5 = 65.75, top10 = 56.89, top15 = 51.52.
+PHY-3001 : End congestion estimation; 1.988743s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (124.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20507 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.931156s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.36026e-05
+PHY-3002 : Step(243): len = 618005, overlap = 264.281
+PHY-3002 : Step(244): len = 621497, overlap = 209.875
+PHY-3002 : Step(245): len = 621687, overlap = 197
+PHY-3002 : Step(246): len = 619338, overlap = 182.688
+PHY-3002 : Step(247): len = 619820, overlap = 161.625
+PHY-3002 : Step(248): len = 617953, overlap = 150.438
+PHY-3002 : Step(249): len = 615416, overlap = 144.844
+PHY-3002 : Step(250): len = 612705, overlap = 143.812
+PHY-3002 : Step(251): len = 611609, overlap = 138.594
+PHY-3002 : Step(252): len = 608080, overlap = 132.469
+PHY-3002 : Step(253): len = 606189, overlap = 125.938
+PHY-3002 : Step(254): len = 603672, overlap = 125.281
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000187205
+PHY-3002 : Step(255): len = 603693, overlap = 117.469
+PHY-3002 : Step(256): len = 604626, overlap = 116.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000314307
+PHY-3002 : Step(257): len = 607388, overlap = 110.156
+PHY-3002 : Step(258): len = 612665, overlap = 104.094
+PHY-3002 : Step(259): len = 617147, overlap = 97.25
+PHY-3002 : Step(260): len = 620552, overlap = 91.9688
+PHY-3002 : Step(261): len = 622327, overlap = 87.875
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84555, tnet num: 20507, tinst num: 18106, tnode num: 115287, tedge num: 134846.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.452292s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (100.1%)
+
+RUN-1004 : used memory is 579 MB, reserved memory is 564 MB, peak memory is 717 MB
+OPT-1001 : Total overflow 421.12 peak overflow 2.84
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1156/20685.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 718984, over cnt = 3063(8%), over = 11444, worst = 24
+PHY-1001 : End global iterations; 1.168306s wall, 1.843750s user + 0.062500s system = 1.906250s CPU (163.2%)
+
+PHY-1001 : Congestion index: top1 = 72.50, top5 = 57.52, top10 = 51.42, top15 = 47.77.
+PHY-1001 : End incremental global routing; 1.493183s wall, 2.171875s user + 0.062500s system = 2.234375s CPU (149.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20507 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.916196s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.6%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17974 has valid locations, 292 needs to be replaced
+PHY-3001 : design contains 18351 instances, 7748 luts, 9382 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6204 pins
+PHY-3001 : Found 1259 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 645648
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16820/20930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 732312, over cnt = 3145(8%), over = 11475, worst = 24
+PHY-1001 : End global iterations; 0.216830s wall, 0.312500s user + 0.031250s system = 0.343750s CPU (158.5%)
+
+PHY-1001 : Congestion index: top1 = 71.98, top5 = 57.58, top10 = 51.56, top15 = 48.00.
+PHY-3001 : End congestion estimation; 0.467286s wall, 0.562500s user + 0.031250s system = 0.593750s CPU (127.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85533, tnet num: 20752, tinst num: 18351, tnode num: 116746, tedge num: 136312.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.473472s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.7%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 627 MB, peak memory is 718 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.425939s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(262): len = 644594, overlap = 0
+PHY-3002 : Step(263): len = 644152, overlap = 0.125
+PHY-3002 : Step(264): len = 643963, overlap = 0
+PHY-3002 : Step(265): len = 643673, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16880/20930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 729984, over cnt = 3149(8%), over = 11486, worst = 24
+PHY-1001 : End global iterations; 0.193480s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (145.4%)
+
+PHY-1001 : Congestion index: top1 = 72.84, top5 = 57.92, top10 = 51.84, top15 = 48.22.
+PHY-3001 : End congestion estimation; 0.445829s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (119.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.931336s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000345877
+PHY-3002 : Step(266): len = 643616, overlap = 90.1562
+PHY-3002 : Step(267): len = 643669, overlap = 90.375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000691753
+PHY-3002 : Step(268): len = 643594, overlap = 90.5
+PHY-3002 : Step(269): len = 643963, overlap = 89.7812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00136793
+PHY-3002 : Step(270): len = 644141, overlap = 90.125
+PHY-3002 : Step(271): len = 644703, overlap = 90.0938
+PHY-3001 : Final: Len = 644703, Over = 90.0938
+PHY-3001 : End incremental placement; 5.061969s wall, 5.687500s user + 0.250000s system = 5.937500s CPU (117.3%)
+
+OPT-1001 : Total overflow 427.56 peak overflow 2.84
+OPT-1001 : End high-fanout net optimization; 8.006975s wall, 9.421875s user + 0.312500s system = 9.734375s CPU (121.6%)
+
+OPT-1001 : Current memory(MB): used = 721, reserve = 711, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16841/20930.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 732776, over cnt = 3065(8%), over = 10472, worst = 24
+PHY-1002 : len = 790072, over cnt = 2081(5%), over = 5177, worst = 19
+PHY-1002 : len = 831344, over cnt = 912(2%), over = 2070, worst = 17
+PHY-1002 : len = 851888, over cnt = 335(0%), over = 655, worst = 12
+PHY-1002 : len = 866360, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations; 1.755516s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (151.3%)
+
+PHY-1001 : Congestion index: top1 = 57.56, top5 = 50.16, top10 = 46.74, top15 = 44.61.
+OPT-1001 : End congestion update; 2.021517s wall, 2.890625s user + 0.031250s system = 2.921875s CPU (144.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20752 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804923s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (100.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 135 cells processed and 18650 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 51 cells processed and 8550 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 4 cells processed and 200 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.268126s wall, 4.125000s user + 0.046875s system = 4.171875s CPU (127.7%)
+
+OPT-1001 : Current memory(MB): used = 698, reserve = 693, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16842/20931.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 866848, over cnt = 92(0%), over = 138, worst = 5
+PHY-1002 : len = 866584, over cnt = 48(0%), over = 57, worst = 3
+PHY-1002 : len = 866888, over cnt = 13(0%), over = 16, worst = 3
+PHY-1002 : len = 867024, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 867232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.724312s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 56.77, top5 = 50.04, top10 = 46.62, top15 = 44.49.
+OPT-1001 : End congestion update; 0.995486s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20753 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.001582s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.8%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 28 cells processed and 5300 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.124632s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (101.5%)
+
+OPT-1001 : Current memory(MB): used = 710, reserve = 700, peak = 738.
+OPT-1001 : End physical optimization; 15.161083s wall, 17.515625s user + 0.421875s system = 17.937500s CPU (118.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7748 LUT to BLE ...
+SYN-4008 : Packed 7748 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6236 remaining SEQ's ...
+SYN-4005 : Packed 3975 SEQ with LUT/SLICE
+SYN-4006 : 922 single LUT's are left
+SYN-4006 : 2261 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10009/13796 primitive instances ...
+PHY-3001 : End packing; 1.656236s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6769 instances
+RUN-1001 : 3311 mslices, 3310 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17918 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10091 nets have 2 pins
+RUN-1001 : 6481 nets have [3 - 5] pins
+RUN-1001 : 731 nets have [6 - 10] pins
+RUN-1001 : 285 nets have [11 - 20] pins
+RUN-1001 : 298 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6767 instances, 6621 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3589 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 659992, Over = 238.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7731/17918.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 817016, over cnt = 1976(5%), over = 3333, worst = 9
+PHY-1002 : len = 825480, over cnt = 1262(3%), over = 1828, worst = 6
+PHY-1002 : len = 838672, over cnt = 519(1%), over = 710, worst = 5
+PHY-1002 : len = 846648, over cnt = 208(0%), over = 287, worst = 5
+PHY-1002 : len = 851440, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations; 1.629938s wall, 2.218750s user + 0.031250s system = 2.250000s CPU (138.0%)
+
+PHY-1001 : Congestion index: top1 = 58.30, top5 = 50.55, top10 = 46.71, top15 = 44.22.
+PHY-3001 : End congestion estimation; 2.031511s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (130.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71642, tnet num: 17740, tinst num: 6767, tnode num: 94210, tedge num: 119097.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.645234s wall, 1.609375s user + 0.031250s system = 1.640625s CPU (99.7%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 610 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17740 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.509245s wall, 2.468750s user + 0.046875s system = 2.515625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.03737e-05
+PHY-3002 : Step(272): len = 648605, overlap = 235.5
+PHY-3002 : Step(273): len = 642229, overlap = 235.25
+PHY-3002 : Step(274): len = 638005, overlap = 243.75
+PHY-3002 : Step(275): len = 634422, overlap = 260.25
+PHY-3002 : Step(276): len = 631777, overlap = 261.5
+PHY-3002 : Step(277): len = 629890, overlap = 262.75
+PHY-3002 : Step(278): len = 627671, overlap = 256
+PHY-3002 : Step(279): len = 625759, overlap = 258.25
+PHY-3002 : Step(280): len = 623935, overlap = 260.5
+PHY-3002 : Step(281): len = 622159, overlap = 263.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000100747
+PHY-3002 : Step(282): len = 625265, overlap = 252.25
+PHY-3002 : Step(283): len = 629973, overlap = 239.75
+PHY-3002 : Step(284): len = 632759, overlap = 231
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000201495
+PHY-3002 : Step(285): len = 639344, overlap = 216
+PHY-3002 : Step(286): len = 646342, overlap = 203
+PHY-3002 : Step(287): len = 646694, overlap = 197.75
+PHY-3002 : Step(288): len = 647312, overlap = 197
+PHY-3002 : Step(289): len = 648038, overlap = 194.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.361445s wall, 0.281250s user + 0.750000s system = 1.031250s CPU (285.3%)
+
+PHY-3001 : Trial Legalized: Len = 735338
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 656/17918.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 845960, over cnt = 2641(7%), over = 4464, worst = 7
+PHY-1002 : len = 863208, over cnt = 1622(4%), over = 2368, worst = 6
+PHY-1002 : len = 881056, over cnt = 731(2%), over = 1028, worst = 6
+PHY-1002 : len = 894160, over cnt = 238(0%), over = 306, worst = 5
+PHY-1002 : len = 899360, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.391627s wall, 3.453125s user + 0.031250s system = 3.484375s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 56.14, top5 = 50.83, top10 = 47.62, top15 = 45.47.
+PHY-3001 : End congestion estimation; 2.848537s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (138.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17740 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.855948s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00018075
+PHY-3002 : Step(290): len = 706119, overlap = 35.75
+PHY-3002 : Step(291): len = 690206, overlap = 57
+PHY-3002 : Step(292): len = 677127, overlap = 86.5
+PHY-3002 : Step(293): len = 668922, overlap = 118.5
+PHY-3002 : Step(294): len = 665220, overlap = 132.25
+PHY-3002 : Step(295): len = 662176, overlap = 145.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.0003615
+PHY-3002 : Step(296): len = 667101, overlap = 138.5
+PHY-3002 : Step(297): len = 671618, overlap = 139.75
+PHY-3002 : Step(298): len = 672424, overlap = 143.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000720105
+PHY-3002 : Step(299): len = 675558, overlap = 137.5
+PHY-3002 : Step(300): len = 685657, overlap = 141.75
+PHY-3002 : Step(301): len = 692342, overlap = 136.75
+PHY-3002 : Step(302): len = 689705, overlap = 143.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033775s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (92.5%)
+
+PHY-3001 : Legalized: Len = 718669, Over = 0
+PHY-3001 : Spreading special nets. 375 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.094615s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (99.1%)
+
+PHY-3001 : 530 instances has been re-located, deltaX = 155, deltaY = 327, maxDist = 2.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 726486, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71642, tnet num: 17740, tinst num: 6770, tnode num: 94210, tedge num: 119097.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.847230s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (99.8%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 637 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3748/17918.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 850192, over cnt = 2479(7%), over = 4006, worst = 7
+PHY-1002 : len = 864008, over cnt = 1509(4%), over = 2190, worst = 7
+PHY-1002 : len = 879344, over cnt = 687(1%), over = 947, worst = 7
+PHY-1002 : len = 887808, over cnt = 306(0%), over = 402, worst = 7
+PHY-1002 : len = 894960, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.076722s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (144.5%)
+
+PHY-1001 : Congestion index: top1 = 53.12, top5 = 48.45, top10 = 45.72, top15 = 43.79.
+PHY-1001 : End incremental global routing; 2.463106s wall, 3.375000s user + 0.015625s system = 3.390625s CPU (137.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17740 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.859956s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.9%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6678 has valid locations, 22 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3657 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 731672
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16292/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901040, over cnt = 76(0%), over = 99, worst = 5
+PHY-1002 : len = 901360, over cnt = 25(0%), over = 26, worst = 2
+PHY-1002 : len = 901576, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 901632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.577859s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.56, top10 = 45.84, top15 = 43.95.
+PHY-3001 : End congestion estimation; 0.888004s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (105.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71828, tnet num: 17762, tinst num: 6788, tnode num: 94438, tedge num: 119333.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.861311s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (99.9%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 661 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.741478s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(303): len = 730277, overlap = 0
+PHY-3002 : Step(304): len = 729511, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16277/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898040, over cnt = 80(0%), over = 100, worst = 5
+PHY-1002 : len = 898320, over cnt = 27(0%), over = 31, worst = 5
+PHY-1002 : len = 898504, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 898720, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.617730s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (106.2%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.57, top10 = 45.85, top15 = 43.93.
+PHY-3001 : End congestion estimation; 0.930597s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (104.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.872456s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000154168
+PHY-3002 : Step(305): len = 729446, overlap = 2.5
+PHY-3002 : Step(306): len = 729446, overlap = 2.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005628s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 729771, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062815s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (124.4%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 0, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 729793, Over = 0
+PHY-3001 : End incremental placement; 5.908876s wall, 6.000000s user + 0.078125s system = 6.078125s CPU (102.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.713732s wall, 10.703125s user + 0.109375s system = 10.812500s CPU (111.3%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 731, peak = 742.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16244/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899048, over cnt = 68(0%), over = 87, worst = 3
+PHY-1002 : len = 899056, over cnt = 46(0%), over = 47, worst = 2
+PHY-1002 : len = 899240, over cnt = 23(0%), over = 24, worst = 2
+PHY-1002 : len = 899632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.644633s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (111.5%)
+
+PHY-1001 : Congestion index: top1 = 53.47, top5 = 48.66, top10 = 45.89, top15 = 43.93.
+OPT-1001 : End congestion update; 0.968405s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (108.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.725724s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.0%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3657 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 733191, Over = 0
+PHY-3001 : Spreading special nets. 17 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060562s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.2%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 14, deltaY = 17, maxDist = 3.
+PHY-3001 : Final: Len = 733987, Over = 0
+PHY-3001 : End incremental legalization; 0.393311s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.3%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 56 cells processed and 11936 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6700 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6788 instances, 6639 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3657 pins
+PHY-3001 : Found 476 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738035, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059399s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.2%)
+
+PHY-3001 : 20 instances has been re-located, deltaX = 11, deltaY = 13, maxDist = 3.
+PHY-3001 : Final: Len = 738307, Over = 0
+PHY-3001 : End incremental legalization; 0.385021s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (105.5%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 27 cells processed and 8882 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6702 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6790 instances, 6641 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3658 pins
+PHY-3001 : Found 477 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738353, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058867s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.2%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 738469, Over = 0
+PHY-3001 : End incremental legalization; 0.387608s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.7%)
+
+OPT-0007 : Iter 3: improved WNS 121 TNS 0 NUM_FEPS 0 with 2 cells processed and 400 slack improved
+OPT-1001 : End bottleneck based optimization; 3.298436s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (105.6%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 730, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15886/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 907072, over cnt = 159(0%), over = 206, worst = 4
+PHY-1002 : len = 907128, over cnt = 90(0%), over = 106, worst = 3
+PHY-1002 : len = 907512, over cnt = 60(0%), over = 70, worst = 3
+PHY-1002 : len = 908376, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 908632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.815337s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 53.58, top5 = 48.70, top10 = 45.85, top15 = 43.92.
+OPT-1001 : End congestion update; 1.131535s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.716290s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6702 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6790 instances, 6641 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3658 pins
+PHY-3001 : Found 477 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738323, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060269s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.7%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 7, deltaY = 14, maxDist = 3.
+PHY-3001 : Final: Len = 738695, Over = 0
+PHY-3001 : End incremental legalization; 0.423188s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 20 cells processed and 2050 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.414502s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (106.1%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 742.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.715807s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16243/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908664, over cnt = 34(0%), over = 42, worst = 3
+PHY-1002 : len = 908728, over cnt = 14(0%), over = 15, worst = 2
+PHY-1002 : len = 908848, over cnt = 3(0%), over = 4, worst = 2
+PHY-1002 : len = 908864, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 908888, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.765773s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.0%)
+
+PHY-1001 : Congestion index: top1 = 53.66, top5 = 48.72, top10 = 45.86, top15 = 43.92.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.716634s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 121 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.241379
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 121ps with logic level 1
+RUN-1001 : extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6702 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6790 instances, 6641 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3658 pins
+PHY-3001 : Found 477 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738695, Over = 0
+PHY-3001 : End spreading; 0.059729s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : Final: Len = 738695, Over = 0
+PHY-3001 : End incremental legalization; 0.385083s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (117.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.713777s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.7%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16315/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908888, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127244s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (110.5%)
+
+PHY-1001 : Congestion index: top1 = 53.66, top5 = 48.72, top10 = 45.86, top15 = 43.92.
+OPT-1001 : End congestion update; 0.439452s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.726951s wall, 0.718750s user + 0.015625s system = 0.734375s CPU (101.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.181631s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 742.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16315/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908888, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.135337s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.9%)
+
+PHY-1001 : Congestion index: top1 = 53.66, top5 = 48.72, top10 = 45.86, top15 = 43.92.
+OPT-1001 : End congestion update; 0.475684s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.720976s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.7%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 1.356305s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (100.2%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 742.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.713997s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 742.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.714454s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.6%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16315/17940.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908888, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.127421s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.1%)
+
+PHY-1001 : Congestion index: top1 = 53.66, top5 = 48.72, top10 = 45.86, top15 = 43.92.
+RUN-1001 : End congestion update; 0.441718s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.0%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.159604s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.7%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 731, peak = 742.
+OPT-1001 : End physical optimization; 25.687889s wall, 26.984375s user + 0.203125s system = 27.187500s CPU (105.8%)
+
+RUN-1003 : finish command "place" in 70.433279s wall, 96.953125s user + 6.250000s system = 103.203125s CPU (146.5%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 640 MB, peak memory is 742 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.676366s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (175.2%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 641 MB, peak memory is 742 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6792 instances
+RUN-1001 : 3329 mslices, 3312 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17940 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10088 nets have 2 pins
+RUN-1001 : 6487 nets have [3 - 5] pins
+RUN-1001 : 731 nets have [6 - 10] pins
+RUN-1001 : 297 nets have [11 - 20] pins
+RUN-1001 : 309 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71849, tnet num: 17762, tinst num: 6790, tnode num: 94467, tedge num: 119360.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.599922s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.6%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 618 MB, peak memory is 742 MB
+PHY-1001 : 3329 mslices, 3312 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[18] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838136, over cnt = 2670(7%), over = 4378, worst = 8
+PHY-1002 : len = 855408, over cnt = 1641(4%), over = 2375, worst = 7
+PHY-1002 : len = 873520, over cnt = 735(2%), over = 1035, worst = 6
+PHY-1002 : len = 890400, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 890880, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.277576s wall, 4.296875s user + 0.078125s system = 4.375000s CPU (133.5%)
+
+PHY-1001 : Congestion index: top1 = 53.32, top5 = 48.07, top10 = 45.33, top15 = 43.47.
+PHY-1001 : End global routing; 3.604344s wall, 4.609375s user + 0.093750s system = 4.703125s CPU (130.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 708, reserve = 709, peak = 742.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 984, reserve = 988, peak = 984.
+PHY-1001 : End build detailed router design. 4.014907s wall, 3.968750s user + 0.046875s system = 4.015625s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271400, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.119410s wall, 5.125000s user + 0.000000s system = 5.125000s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271456, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.471967s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1020, reserve = 1024, peak = 1020.
+PHY-1001 : End phase 1; 5.603803s wall, 5.609375s user + 0.000000s system = 5.609375s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.29578e+06, over cnt = 1831(0%), over = 1843, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1036, peak = 1035.
+PHY-1001 : End initial routed; 25.131710s wall, 57.828125s user + 0.187500s system = 58.015625s CPU (230.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 32/16862(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.036 | -1.847 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.254189s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1047, peak = 1047.
+PHY-1001 : End phase 2; 28.385964s wall, 61.078125s user + 0.187500s system = 61.265625s CPU (215.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 11 pins with SWNS -0.805ns STNS -1.586ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.159470s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.0%)
+
+PHY-1022 : len = 2.29581e+06, over cnt = 1838(0%), over = 1850, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.429484s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26343e+06, over cnt = 623(0%), over = 623, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.433157s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (171.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.26331e+06, over cnt = 169(0%), over = 169, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.559428s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (156.4%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.26473e+06, over cnt = 19(0%), over = 19, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.365543s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (119.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.26493e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.252309s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (111.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.26495e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.279773s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (111.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.26495e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.345369s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.26495e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.425257s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.26495e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.175108s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.26496e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.172593s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.26497e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 10; 0.160840s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (97.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 32/16862(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.864 | -1.669 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.261214s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 562 feed throughs used by 415 nets
+PHY-1001 : End commit to database; 2.225007s wall, 2.218750s user + 0.000000s system = 2.218750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1157, peak = 1152.
+PHY-1001 : End phase 3; 10.517833s wall, 11.953125s user + 0.015625s system = 11.968750s CPU (113.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 10 pins with SWNS -0.805ns STNS -1.574ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.177368s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (105.7%)
+
+PHY-1022 : len = 2.26494e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.446321s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.805ns, -1.574ns, 2}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.26494e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.631990s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (27.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 32/16862(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.852 | -1.657 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.243305s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 563 feed throughs used by 416 nets
+PHY-1001 : End commit to database; 2.304327s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1166, peak = 1161.
+PHY-1001 : End phase 4; 6.676191s wall, 6.234375s user + 0.000000s system = 6.234375s CPU (93.4%)
+
+PHY-1003 : Routed, final wirelength = 2.26494e+06
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1170, peak = 1165.
+PHY-1001 : End export database. 0.149480s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.5%)
+
+PHY-1001 : End detail routing; 55.742790s wall, 89.375000s user + 0.250000s system = 89.625000s CPU (160.8%)
+
+RUN-1003 : finish command "route" in 62.017673s wall, 96.625000s user + 0.359375s system = 96.984375s CPU (156.4%)
+
+RUN-1004 : used memory is 1080 MB, reserved memory is 1095 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10167 out of 19600 51.87%
+#reg 9567 out of 19600 48.81%
+#le 12390
+ #lut only 2823 out of 12390 22.78%
+ #reg only 2223 out of 12390 17.94%
+ #lut® 7344 out of 12390 59.27%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 20
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1766
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1432
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1324
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 947
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice color_mode_reg_syn_14.q0 135
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg60_syn_206.f1 3
+#11 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/u_local_bus_slve_cis/reg45_syn_244.f0 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P170 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P82 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE OREG
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P83 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P16 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P64 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12390 |9140 |1027 |9600 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |529 |439 |23 |442 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |96 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |34 |34 |0 |18 |0 |0 |
+| U_ecc_gen |ecc_gen |11 |11 |0 |8 |0 |0 |
+| exdev_ctl_a |exdev_ctl |755 |360 |96 |579 |0 |0 |
+| u_ADconfig |AD_config |186 |135 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |251 |150 |71 |117 |0 |0 |
+| exdev_ctl_b |exdev_ctl |740 |393 |96 |563 |0 |0 |
+| u_ADconfig |AD_config |168 |116 |25 |123 |0 |0 |
+| u_gen_sp |gen_sp |252 |154 |71 |120 |0 |0 |
+| sampling_fe_a |sampling_fe |3006 |2431 |306 |2057 |25 |0 |
+| u0_soft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |117 |17 |155 |0 |0 |
+| u0_soft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_sort |sort |2789 |2307 |289 |1869 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |0 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2371 |1989 |253 |1524 |22 |0 |
+| channelPart |channel_part_8478 |132 |127 |3 |128 |0 |0 |
+| fifo_adc |fifo_adc |59 |50 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1890 |1575 |197 |1146 |0 |0 |
+| adc_addr_gen |adc_addr_gen |222 |195 |27 |123 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |11 |8 |3 |7 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |15 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |15 |0 |0 |
+| insert |insert |951 |664 |170 |653 |0 |0 |
+| ram_switch_state |ram_switch_state |717 |716 |0 |370 |0 |0 |
+| read_ram_i |read_ram |261 |214 |44 |182 |0 |0 |
+| read_ram_addr |read_ram_addr |218 |178 |40 |148 |0 |0 |
+| read_ram_data |read_ram_data |41 |34 |4 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |2 |2 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |303 |216 |36 |262 |3 |0 |
+| u0_soft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3125 |2441 |349 |2077 |25 |1 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |187 |113 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |6 |6 |0 |6 |0 |0 |
+| u_sort |sort_rev |2910 |2309 |332 |1891 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |1 |0 |1 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_rdsoft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2444 |1973 |290 |1531 |22 |1 |
+| channelPart |channel_part_8478 |145 |135 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |64 |55 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1859 |1513 |197 |1114 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |194 |27 |105 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |36 |33 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |7 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |7 |0 |0 |
+| insert |insert |957 |640 |170 |673 |0 |0 |
+| ram_switch_state |ram_switch_state |681 |679 |0 |336 |0 |0 |
+| read_ram_i |read_ram_rev |347 |250 |81 |204 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |286 |204 |73 |157 |0 |0 |
+| read_ram_data |read_ram_data_rev |61 |46 |8 |47 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10026
+ #2 2 4216
+ #3 3 1705
+ #4 4 563
+ #5 5-10 771
+ #6 11-50 552
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.064589s wall, 3.546875s user + 0.031250s system = 3.578125s CPU (173.3%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1096 MB, peak memory is 1165 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71849, tnet num: 17762, tinst num: 6790, tnode num: 94467, tedge num: 119360.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.620961s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.3%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1099 MB, peak memory is 1165 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17762 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.459731s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.6%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1114 MB, peak memory is 1165 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6790
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17940, pip num: 168371
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 563
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3247 valid insts, and 469494 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.376847s wall, 61.703125s user + 0.218750s system = 61.921875s CPU (596.7%)
+
+RUN-1004 : used memory is 1253 MB, reserved memory is 1252 MB, peak memory is 1369 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_141628.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_142553.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_142553.log
new file mode 100644
index 0000000..66fcb9a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_142553.log
@@ -0,0 +1,1982 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 14:25:53 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.218469s wall, 2.062500s user + 0.156250s system = 2.218750s CPU (100.0%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 316 MB, peak memory is 347 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18109 instances
+RUN-0007 : 7660 luts, 9226 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20686 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13190 nets have 2 pins
+RUN-1001 : 6457 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 183 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1992
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18107 instances, 7660 luts, 9226 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6097 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84611, tnet num: 20508, tinst num: 18107, tnode num: 115337, tedge num: 134956.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.193325s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (99.5%)
+
+RUN-1004 : used memory is 536 MB, reserved memory is 516 MB, peak memory is 536 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20508 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.011592s wall, 1.953125s user + 0.046875s system = 2.000000s CPU (99.4%)
+
+PHY-3001 : Found 1251 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.17561e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18107.
+PHY-3001 : Level 1 #clusters 2063.
+PHY-3001 : End clustering; 0.130863s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.3288e+06, overlap = 472.156
+PHY-3002 : Step(2): len = 1.24304e+06, overlap = 522.969
+PHY-3002 : Step(3): len = 864631, overlap = 604.875
+PHY-3002 : Step(4): len = 787004, overlap = 645.25
+PHY-3002 : Step(5): len = 621756, overlap = 797.906
+PHY-3002 : Step(6): len = 550415, overlap = 852.156
+PHY-3002 : Step(7): len = 463336, overlap = 931.844
+PHY-3002 : Step(8): len = 421721, overlap = 992.719
+PHY-3002 : Step(9): len = 378987, overlap = 1012.78
+PHY-3002 : Step(10): len = 351360, overlap = 1082.28
+PHY-3002 : Step(11): len = 312995, overlap = 1132.94
+PHY-3002 : Step(12): len = 293613, overlap = 1179.97
+PHY-3002 : Step(13): len = 264852, overlap = 1197.97
+PHY-3002 : Step(14): len = 246772, overlap = 1264.09
+PHY-3002 : Step(15): len = 220151, overlap = 1306.47
+PHY-3002 : Step(16): len = 203266, overlap = 1330
+PHY-3002 : Step(17): len = 182319, overlap = 1383.25
+PHY-3002 : Step(18): len = 171762, overlap = 1416.78
+PHY-3002 : Step(19): len = 156258, overlap = 1441.22
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.40602e-06
+PHY-3002 : Step(20): len = 159081, overlap = 1375.69
+PHY-3002 : Step(21): len = 195512, overlap = 1275.28
+PHY-3002 : Step(22): len = 207340, overlap = 1216.78
+PHY-3002 : Step(23): len = 218805, overlap = 1142.81
+PHY-3002 : Step(24): len = 219180, overlap = 1096.09
+PHY-3002 : Step(25): len = 218110, overlap = 1080.38
+PHY-3002 : Step(26): len = 214021, overlap = 1100.81
+PHY-3002 : Step(27): len = 210384, overlap = 1089.97
+PHY-3002 : Step(28): len = 206002, overlap = 1077.62
+PHY-3002 : Step(29): len = 203086, overlap = 1087.16
+PHY-3002 : Step(30): len = 199547, overlap = 1080.28
+PHY-3002 : Step(31): len = 198200, overlap = 1090.97
+PHY-3002 : Step(32): len = 196484, overlap = 1076.44
+PHY-3002 : Step(33): len = 195730, overlap = 1057.69
+PHY-3002 : Step(34): len = 194548, overlap = 1049.31
+PHY-3002 : Step(35): len = 194039, overlap = 1055.25
+PHY-3002 : Step(36): len = 192961, overlap = 1053.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.81204e-06
+PHY-3002 : Step(37): len = 200003, overlap = 1022.53
+PHY-3002 : Step(38): len = 218854, overlap = 958.938
+PHY-3002 : Step(39): len = 225902, overlap = 900.562
+PHY-3002 : Step(40): len = 230329, overlap = 875.188
+PHY-3002 : Step(41): len = 233041, overlap = 880.938
+PHY-3002 : Step(42): len = 233451, overlap = 868.281
+PHY-3002 : Step(43): len = 233191, overlap = 863.562
+PHY-3002 : Step(44): len = 232445, overlap = 849.281
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.62407e-06
+PHY-3002 : Step(45): len = 244430, overlap = 822.938
+PHY-3002 : Step(46): len = 264413, overlap = 712.406
+PHY-3002 : Step(47): len = 276186, overlap = 657.875
+PHY-3002 : Step(48): len = 284300, overlap = 644.094
+PHY-3002 : Step(49): len = 285146, overlap = 644.812
+PHY-3002 : Step(50): len = 285401, overlap = 643
+PHY-3002 : Step(51): len = 282587, overlap = 647.125
+PHY-3002 : Step(52): len = 280100, overlap = 644.312
+PHY-3002 : Step(53): len = 278429, overlap = 645.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.12481e-05
+PHY-3002 : Step(54): len = 292973, overlap = 624.188
+PHY-3002 : Step(55): len = 309243, overlap = 586.156
+PHY-3002 : Step(56): len = 314154, overlap = 569.938
+PHY-3002 : Step(57): len = 317444, overlap = 554.312
+PHY-3002 : Step(58): len = 317524, overlap = 528.156
+PHY-3002 : Step(59): len = 317546, overlap = 519.062
+PHY-3002 : Step(60): len = 314357, overlap = 502.625
+PHY-3002 : Step(61): len = 315043, overlap = 470.844
+PHY-3002 : Step(62): len = 314840, overlap = 463.969
+PHY-3002 : Step(63): len = 314141, overlap = 455.812
+PHY-3002 : Step(64): len = 313240, overlap = 449.156
+PHY-3002 : Step(65): len = 312718, overlap = 441.5
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.24963e-05
+PHY-3002 : Step(66): len = 328503, overlap = 437.75
+PHY-3002 : Step(67): len = 341779, overlap = 424.031
+PHY-3002 : Step(68): len = 344748, overlap = 399.062
+PHY-3002 : Step(69): len = 347914, overlap = 394.438
+PHY-3002 : Step(70): len = 349030, overlap = 394.719
+PHY-3002 : Step(71): len = 350239, overlap = 376.406
+PHY-3002 : Step(72): len = 349462, overlap = 368.875
+PHY-3002 : Step(73): len = 350159, overlap = 365.281
+PHY-3002 : Step(74): len = 348846, overlap = 355.031
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.49926e-05
+PHY-3002 : Step(75): len = 366722, overlap = 354.219
+PHY-3002 : Step(76): len = 380334, overlap = 353.469
+PHY-3002 : Step(77): len = 381584, overlap = 330.188
+PHY-3002 : Step(78): len = 382551, overlap = 316
+PHY-3002 : Step(79): len = 386517, overlap = 306.031
+PHY-3002 : Step(80): len = 391334, overlap = 306.719
+PHY-3002 : Step(81): len = 391322, overlap = 302.906
+PHY-3002 : Step(82): len = 390064, overlap = 295.125
+PHY-3002 : Step(83): len = 390063, overlap = 290.125
+PHY-3002 : Step(84): len = 388676, overlap = 293.531
+PHY-3002 : Step(85): len = 388759, overlap = 290.875
+PHY-3002 : Step(86): len = 387193, overlap = 293.219
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.99852e-05
+PHY-3002 : Step(87): len = 403128, overlap = 273.562
+PHY-3002 : Step(88): len = 413989, overlap = 266.156
+PHY-3002 : Step(89): len = 414007, overlap = 253.781
+PHY-3002 : Step(90): len = 414925, overlap = 238.062
+PHY-3002 : Step(91): len = 418217, overlap = 236.406
+PHY-3002 : Step(92): len = 422408, overlap = 237.219
+PHY-3002 : Step(93): len = 420952, overlap = 225.219
+PHY-3002 : Step(94): len = 421472, overlap = 242.219
+PHY-3002 : Step(95): len = 423703, overlap = 251.406
+PHY-3002 : Step(96): len = 426690, overlap = 250.781
+PHY-3002 : Step(97): len = 423547, overlap = 253.438
+PHY-3002 : Step(98): len = 423562, overlap = 243.844
+PHY-3002 : Step(99): len = 425240, overlap = 244.469
+PHY-3002 : Step(100): len = 427425, overlap = 242.625
+PHY-3002 : Step(101): len = 424483, overlap = 249.406
+PHY-3002 : Step(102): len = 426018, overlap = 229.281
+PHY-3002 : Step(103): len = 427964, overlap = 228.156
+PHY-3002 : Step(104): len = 428755, overlap = 232.406
+PHY-3002 : Step(105): len = 426035, overlap = 229.781
+PHY-3002 : Step(106): len = 425988, overlap = 235.719
+PHY-3002 : Step(107): len = 427463, overlap = 230.656
+PHY-3002 : Step(108): len = 429362, overlap = 224.5
+PHY-3002 : Step(109): len = 427260, overlap = 228.594
+PHY-3002 : Step(110): len = 427913, overlap = 229.406
+PHY-3002 : Step(111): len = 428592, overlap = 234.031
+PHY-3002 : Step(112): len = 429282, overlap = 234.812
+PHY-3002 : Step(113): len = 427997, overlap = 239.188
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00017997
+PHY-3002 : Step(114): len = 441459, overlap = 238.719
+PHY-3002 : Step(115): len = 447752, overlap = 241.094
+PHY-3002 : Step(116): len = 445452, overlap = 228.531
+PHY-3002 : Step(117): len = 446383, overlap = 221.062
+PHY-3002 : Step(118): len = 450734, overlap = 220.469
+PHY-3002 : Step(119): len = 454359, overlap = 225.156
+PHY-3002 : Step(120): len = 453255, overlap = 224.219
+PHY-3002 : Step(121): len = 454323, overlap = 225.031
+PHY-3002 : Step(122): len = 456214, overlap = 231.031
+PHY-3002 : Step(123): len = 457864, overlap = 228.438
+PHY-3002 : Step(124): len = 457128, overlap = 222.281
+PHY-3002 : Step(125): len = 457473, overlap = 221.281
+PHY-3002 : Step(126): len = 458492, overlap = 222.562
+PHY-3002 : Step(127): len = 460068, overlap = 219.656
+PHY-3002 : Step(128): len = 459239, overlap = 216.406
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000344378
+PHY-3002 : Step(129): len = 465731, overlap = 214.031
+PHY-3002 : Step(130): len = 471325, overlap = 213.062
+PHY-3002 : Step(131): len = 471736, overlap = 215.312
+PHY-3002 : Step(132): len = 472560, overlap = 210.625
+PHY-3002 : Step(133): len = 475835, overlap = 204.531
+PHY-3002 : Step(134): len = 478664, overlap = 194.688
+PHY-3002 : Step(135): len = 479305, overlap = 206.312
+PHY-3002 : Step(136): len = 480271, overlap = 203.219
+PHY-3002 : Step(137): len = 481362, overlap = 202.406
+PHY-3002 : Step(138): len = 481682, overlap = 198.812
+PHY-3002 : Step(139): len = 480806, overlap = 197.938
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000634135
+PHY-3002 : Step(140): len = 485792, overlap = 190.562
+PHY-3002 : Step(141): len = 491407, overlap = 190.406
+PHY-3002 : Step(142): len = 492838, overlap = 187.062
+PHY-3002 : Step(143): len = 495371, overlap = 182.938
+PHY-3002 : Step(144): len = 498089, overlap = 184.25
+PHY-3002 : Step(145): len = 499525, overlap = 180.688
+PHY-3002 : Step(146): len = 498260, overlap = 176.688
+PHY-3002 : Step(147): len = 497783, overlap = 177.469
+PHY-3002 : Step(148): len = 499396, overlap = 175
+PHY-3002 : Step(149): len = 500617, overlap = 174
+PHY-3002 : Step(150): len = 500300, overlap = 171.812
+PHY-3002 : Step(151): len = 500556, overlap = 170.062
+PHY-3002 : Step(152): len = 501799, overlap = 166.906
+PHY-3002 : Step(153): len = 502340, overlap = 165.844
+PHY-3002 : Step(154): len = 501979, overlap = 168.625
+PHY-3002 : Step(155): len = 502005, overlap = 167.719
+PHY-3002 : Step(156): len = 502374, overlap = 165.406
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00116376
+PHY-3002 : Step(157): len = 506747, overlap = 165.812
+PHY-3002 : Step(158): len = 515431, overlap = 166.625
+PHY-3002 : Step(159): len = 519347, overlap = 163.719
+PHY-3002 : Step(160): len = 522250, overlap = 165.125
+PHY-3002 : Step(161): len = 523309, overlap = 167.75
+PHY-3002 : Step(162): len = 523485, overlap = 164.438
+PHY-3002 : Step(163): len = 523361, overlap = 171
+PHY-3002 : Step(164): len = 523763, overlap = 159.344
+PHY-3002 : Step(165): len = 524516, overlap = 158.031
+PHY-3002 : Step(166): len = 525694, overlap = 164.031
+PHY-3002 : Step(167): len = 526940, overlap = 155.031
+PHY-3002 : Step(168): len = 527716, overlap = 152.781
+PHY-3002 : Step(169): len = 528693, overlap = 151.562
+PHY-3002 : Step(170): len = 529536, overlap = 154.219
+PHY-3002 : Step(171): len = 529602, overlap = 155.281
+PHY-3002 : Step(172): len = 528472, overlap = 151.156
+PHY-3002 : Step(173): len = 528690, overlap = 149.594
+PHY-3002 : Step(174): len = 529484, overlap = 150.625
+PHY-3002 : Step(175): len = 529573, overlap = 144.531
+PHY-3002 : Step(176): len = 528508, overlap = 150.062
+PHY-3002 : Step(177): len = 527869, overlap = 146.281
+PHY-3002 : Step(178): len = 527680, overlap = 150.844
+PHY-3002 : Step(179): len = 527516, overlap = 155.812
+PHY-3002 : Step(180): len = 526679, overlap = 150.438
+PHY-3002 : Step(181): len = 526279, overlap = 150.062
+PHY-3002 : Step(182): len = 526298, overlap = 154.719
+PHY-3002 : Step(183): len = 526206, overlap = 155.125
+PHY-3002 : Step(184): len = 525580, overlap = 152.656
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00221088
+PHY-3002 : Step(185): len = 527368, overlap = 152.25
+PHY-3002 : Step(186): len = 529977, overlap = 151.938
+PHY-3002 : Step(187): len = 530748, overlap = 149.438
+PHY-3002 : Step(188): len = 531344, overlap = 144.656
+PHY-3002 : Step(189): len = 532107, overlap = 145.969
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00359252
+PHY-3002 : Step(190): len = 532750, overlap = 146.531
+PHY-3002 : Step(191): len = 533625, overlap = 147.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014342s wall, 0.000000s user + 0.031250s system = 0.031250s CPU (217.9%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20686.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 676832, over cnt = 1545(4%), over = 7198, worst = 41
+PHY-1001 : End global iterations; 0.696195s wall, 0.984375s user + 0.031250s system = 1.015625s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 88.15, top5 = 63.58, top10 = 53.28, top15 = 47.12.
+PHY-3001 : End congestion estimation; 0.914770s wall, 1.187500s user + 0.031250s system = 1.218750s CPU (133.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20508 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.859623s wall, 0.828125s user + 0.031250s system = 0.859375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000156447
+PHY-3002 : Step(192): len = 615053, overlap = 105.5
+PHY-3002 : Step(193): len = 618285, overlap = 103.906
+PHY-3002 : Step(194): len = 612985, overlap = 105.906
+PHY-3002 : Step(195): len = 609061, overlap = 98.25
+PHY-3002 : Step(196): len = 608269, overlap = 91.25
+PHY-3002 : Step(197): len = 606948, overlap = 89.7812
+PHY-3002 : Step(198): len = 606429, overlap = 78.9375
+PHY-3002 : Step(199): len = 606795, overlap = 70.5938
+PHY-3002 : Step(200): len = 606277, overlap = 60.8438
+PHY-3002 : Step(201): len = 603510, overlap = 62.3438
+PHY-3002 : Step(202): len = 600845, overlap = 56.875
+PHY-3002 : Step(203): len = 599132, overlap = 52.9688
+PHY-3002 : Step(204): len = 597096, overlap = 49.4688
+PHY-3002 : Step(205): len = 595845, overlap = 45.8125
+PHY-3002 : Step(206): len = 594503, overlap = 46.1875
+PHY-3002 : Step(207): len = 592900, overlap = 44.8125
+PHY-3002 : Step(208): len = 591523, overlap = 43.4688
+PHY-3002 : Step(209): len = 590005, overlap = 39.1562
+PHY-3002 : Step(210): len = 588918, overlap = 37.6562
+PHY-3002 : Step(211): len = 588030, overlap = 37.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000312895
+PHY-3002 : Step(212): len = 590153, overlap = 37.1562
+PHY-3002 : Step(213): len = 593188, overlap = 35.9688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000506263
+PHY-3002 : Step(214): len = 595281, overlap = 34.125
+PHY-3002 : Step(215): len = 605704, overlap = 29.625
+PHY-3002 : Step(216): len = 618502, overlap = 23.0938
+PHY-3002 : Step(217): len = 619730, overlap = 23.8125
+PHY-3002 : Step(218): len = 621463, overlap = 23.3438
+PHY-3002 : Step(219): len = 623332, overlap = 21.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 108/20686.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709856, over cnt = 2671(7%), over = 12302, worst = 37
+PHY-1001 : End global iterations; 1.738816s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (128.5%)
+
+PHY-1001 : Congestion index: top1 = 84.59, top5 = 67.62, top10 = 58.83, top15 = 53.27.
+PHY-3001 : End congestion estimation; 2.040553s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (124.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20508 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.888896s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000101588
+PHY-3002 : Step(220): len = 619847, overlap = 249.719
+PHY-3002 : Step(221): len = 621550, overlap = 201.156
+PHY-3002 : Step(222): len = 613303, overlap = 185.094
+PHY-3002 : Step(223): len = 607344, overlap = 170.219
+PHY-3002 : Step(224): len = 603379, overlap = 158.781
+PHY-3002 : Step(225): len = 597691, overlap = 149.656
+PHY-3002 : Step(226): len = 593055, overlap = 146.781
+PHY-3002 : Step(227): len = 590386, overlap = 140.094
+PHY-3002 : Step(228): len = 588466, overlap = 142.969
+PHY-3002 : Step(229): len = 584888, overlap = 142.469
+PHY-3002 : Step(230): len = 582899, overlap = 138.625
+PHY-3002 : Step(231): len = 580306, overlap = 142.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000203176
+PHY-3002 : Step(232): len = 580845, overlap = 136.094
+PHY-3002 : Step(233): len = 582475, overlap = 130.875
+PHY-3002 : Step(234): len = 586281, overlap = 123.281
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000406353
+PHY-3002 : Step(235): len = 592014, overlap = 111.281
+PHY-3002 : Step(236): len = 598252, overlap = 105.031
+PHY-3002 : Step(237): len = 601670, overlap = 97.6875
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000812705
+PHY-3002 : Step(238): len = 605685, overlap = 91.875
+PHY-3002 : Step(239): len = 614177, overlap = 78.625
+PHY-3002 : Step(240): len = 621091, overlap = 69.6562
+PHY-3002 : Step(241): len = 619684, overlap = 68.4062
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84611, tnet num: 20508, tinst num: 18107, tnode num: 115337, tedge num: 134956.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.444220s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (100.6%)
+
+RUN-1004 : used memory is 580 MB, reserved memory is 566 MB, peak memory is 716 MB
+OPT-1001 : Total overflow 386.34 peak overflow 3.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 956/20686.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 718944, over cnt = 3029(8%), over = 10828, worst = 28
+PHY-1001 : End global iterations; 1.350073s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (135.4%)
+
+PHY-1001 : Congestion index: top1 = 73.92, top5 = 58.89, top10 = 52.26, top15 = 48.14.
+PHY-1001 : End incremental global routing; 1.698649s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (128.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20508 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.910067s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.6%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17975 has valid locations, 323 needs to be replaced
+PHY-3001 : design contains 18383 instances, 7758 luts, 9404 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6219 pins
+PHY-3001 : Found 1262 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 644886
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17080/20962.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735328, over cnt = 3098(8%), over = 10892, worst = 28
+PHY-1001 : End global iterations; 0.254505s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 74.05, top5 = 59.02, top10 = 52.47, top15 = 48.44.
+PHY-3001 : End congestion estimation; 0.517978s wall, 0.593750s user + 0.015625s system = 0.609375s CPU (117.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85714, tnet num: 20784, tinst num: 18383, tnode num: 117001, tedge num: 136610.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.481999s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (100.2%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 621 MB, peak memory is 720 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20784 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.441094s wall, 2.359375s user + 0.078125s system = 2.437500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(242): len = 643443, overlap = 0
+PHY-3002 : Step(243): len = 643039, overlap = 0
+PHY-3002 : Step(244): len = 642883, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17182/20962.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 732416, over cnt = 3096(8%), over = 10928, worst = 28
+PHY-1001 : End global iterations; 0.187333s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (125.1%)
+
+PHY-1001 : Congestion index: top1 = 74.55, top5 = 59.50, top10 = 52.83, top15 = 48.76.
+PHY-3001 : End congestion estimation; 0.443244s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (109.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20784 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.935161s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000408234
+PHY-3002 : Step(245): len = 642557, overlap = 70.3438
+PHY-3002 : Step(246): len = 642691, overlap = 70.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000816468
+PHY-3002 : Step(247): len = 643159, overlap = 70.7812
+PHY-3002 : Step(248): len = 643769, overlap = 71.2188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00160505
+PHY-3002 : Step(249): len = 643714, overlap = 71.9375
+PHY-3002 : Step(250): len = 643989, overlap = 71.7812
+PHY-3001 : Final: Len = 643989, Over = 71.7812
+PHY-3001 : End incremental placement; 5.067604s wall, 5.625000s user + 0.437500s system = 6.062500s CPU (119.6%)
+
+OPT-1001 : Total overflow 393.97 peak overflow 3.97
+OPT-1001 : End high-fanout net optimization; 8.207798s wall, 9.312500s user + 0.453125s system = 9.765625s CPU (119.0%)
+
+OPT-1001 : Current memory(MB): used = 722, reserve = 713, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17105/20962.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735864, over cnt = 2996(8%), over = 9815, worst = 28
+PHY-1002 : len = 781424, over cnt = 2135(6%), over = 5438, worst = 20
+PHY-1002 : len = 819984, over cnt = 1013(2%), over = 2497, worst = 20
+PHY-1002 : len = 838144, over cnt = 577(1%), over = 1380, worst = 13
+PHY-1002 : len = 859896, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.819422s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 58.34, top5 = 50.97, top10 = 47.25, top15 = 44.84.
+OPT-1001 : End congestion update; 2.083711s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (132.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20784 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.797610s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 134 cells processed and 16650 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 28 cells processed and 2750 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 43 cells processed and 4550 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 8 cells processed and 1400 slack improved
+OPT-0007 : Iter 5: improved WNS 171 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.428632s wall, 4.109375s user + 0.000000s system = 4.109375s CPU (119.9%)
+
+OPT-1001 : Current memory(MB): used = 721, reserve = 711, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17162/20964.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860616, over cnt = 82(0%), over = 117, worst = 6
+PHY-1002 : len = 860744, over cnt = 55(0%), over = 61, worst = 3
+PHY-1002 : len = 861064, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 861376, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 861424, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.704619s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (104.2%)
+
+PHY-1001 : Congestion index: top1 = 58.36, top5 = 50.91, top10 = 47.07, top15 = 44.70.
+OPT-1001 : End congestion update; 0.979156s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (103.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20786 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.815614s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 17 cells processed and 3900 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.934593s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (101.8%)
+
+OPT-1001 : Current memory(MB): used = 719, reserve = 710, peak = 739.
+OPT-1001 : End physical optimization; 15.346910s wall, 17.156250s user + 0.500000s system = 17.656250s CPU (115.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7758 LUT to BLE ...
+SYN-4008 : Packed 7758 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6259 remaining SEQ's ...
+SYN-4005 : Packed 4201 SEQ with LUT/SLICE
+SYN-4006 : 700 single LUT's are left
+SYN-4006 : 2058 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9816/13603 primitive instances ...
+PHY-3001 : End packing; 1.704338s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6704 instances
+RUN-1001 : 3278 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17951 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10063 nets have 2 pins
+RUN-1001 : 6518 nets have [3 - 5] pins
+RUN-1001 : 731 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 299 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6702 instances, 6556 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3613 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 652937, Over = 216
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7586/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 805672, over cnt = 1890(5%), over = 3066, worst = 8
+PHY-1002 : len = 813336, over cnt = 1183(3%), over = 1732, worst = 7
+PHY-1002 : len = 826600, over cnt = 393(1%), over = 556, worst = 7
+PHY-1002 : len = 832800, over cnt = 111(0%), over = 169, worst = 7
+PHY-1002 : len = 836128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.714544s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (133.1%)
+
+PHY-1001 : Congestion index: top1 = 56.36, top5 = 50.18, top10 = 46.29, top15 = 43.70.
+PHY-3001 : End congestion estimation; 2.119694s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (126.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71835, tnet num: 17773, tinst num: 6702, tnode num: 94489, tedge num: 119432.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.609248s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (100.0%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 615 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.476442s wall, 2.406250s user + 0.062500s system = 2.468750s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.5659e-05
+PHY-3002 : Step(251): len = 640375, overlap = 215.25
+PHY-3002 : Step(252): len = 633580, overlap = 214.75
+PHY-3002 : Step(253): len = 628820, overlap = 217
+PHY-3002 : Step(254): len = 625752, overlap = 222.5
+PHY-3002 : Step(255): len = 623325, overlap = 229
+PHY-3002 : Step(256): len = 620937, overlap = 234.75
+PHY-3002 : Step(257): len = 618910, overlap = 243.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000111318
+PHY-3002 : Step(258): len = 621148, overlap = 236.5
+PHY-3002 : Step(259): len = 622989, overlap = 234.75
+PHY-3002 : Step(260): len = 622929, overlap = 232.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000210205
+PHY-3002 : Step(261): len = 632080, overlap = 214.25
+PHY-3002 : Step(262): len = 637759, overlap = 205.5
+PHY-3002 : Step(263): len = 635839, overlap = 207
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.381632s wall, 0.250000s user + 0.656250s system = 0.906250s CPU (237.5%)
+
+PHY-3001 : Trial Legalized: Len = 723029
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1010/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 836272, over cnt = 2638(7%), over = 4394, worst = 8
+PHY-1002 : len = 850416, over cnt = 1748(4%), over = 2604, worst = 7
+PHY-1002 : len = 869928, over cnt = 828(2%), over = 1216, worst = 6
+PHY-1002 : len = 888424, over cnt = 85(0%), over = 126, worst = 5
+PHY-1002 : len = 890856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.499164s wall, 3.531250s user + 0.015625s system = 3.546875s CPU (141.9%)
+
+PHY-1001 : Congestion index: top1 = 56.55, top5 = 50.39, top10 = 47.19, top15 = 45.12.
+PHY-3001 : End congestion estimation; 2.982261s wall, 4.000000s user + 0.031250s system = 4.031250s CPU (135.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.851153s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000158395
+PHY-3002 : Step(264): len = 696441, overlap = 32.5
+PHY-3002 : Step(265): len = 680193, overlap = 56.5
+PHY-3002 : Step(266): len = 666219, overlap = 83.5
+PHY-3002 : Step(267): len = 659370, overlap = 89
+PHY-3002 : Step(268): len = 653851, overlap = 108
+PHY-3002 : Step(269): len = 650025, overlap = 120.25
+PHY-3002 : Step(270): len = 647423, overlap = 133.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000316789
+PHY-3002 : Step(271): len = 650534, overlap = 127.5
+PHY-3002 : Step(272): len = 654707, overlap = 126.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000633579
+PHY-3002 : Step(273): len = 660616, overlap = 123.75
+PHY-3002 : Step(274): len = 667669, overlap = 125.25
+PHY-3002 : Step(275): len = 667286, overlap = 125.5
+PHY-3002 : Step(276): len = 667209, overlap = 123.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033259s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (94.0%)
+
+PHY-3001 : Legalized: Len = 696223, Over = 0
+PHY-3001 : Spreading special nets. 464 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.101453s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (107.8%)
+
+PHY-3001 : 690 instances has been re-located, deltaX = 196, deltaY = 441, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 707890, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71835, tnet num: 17773, tinst num: 6705, tnode num: 94489, tedge num: 119432.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.852983s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (100.3%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 660 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3717/17951.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 832648, over cnt = 2460(6%), over = 4100, worst = 8
+PHY-1002 : len = 846568, over cnt = 1453(4%), over = 2093, worst = 7
+PHY-1002 : len = 866432, over cnt = 406(1%), over = 554, worst = 5
+PHY-1002 : len = 869384, over cnt = 268(0%), over = 376, worst = 5
+PHY-1002 : len = 876936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.048743s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 54.72, top5 = 48.61, top10 = 45.55, top15 = 43.64.
+PHY-1001 : End incremental global routing; 2.443080s wall, 3.375000s user + 0.015625s system = 3.390625s CPU (138.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17773 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.859795s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.0%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6613 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6726 instances, 6577 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3675 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 711960
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16345/17972.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 881984, over cnt = 89(0%), over = 102, worst = 6
+PHY-1002 : len = 881976, over cnt = 38(0%), over = 41, worst = 2
+PHY-1002 : len = 882328, over cnt = 5(0%), over = 6, worst = 2
+PHY-1002 : len = 882416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.668840s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (102.8%)
+
+PHY-1001 : Congestion index: top1 = 54.87, top5 = 48.75, top10 = 45.72, top15 = 43.82.
+PHY-3001 : End congestion estimation; 0.980243s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (102.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72026, tnet num: 17794, tinst num: 6726, tnode num: 94731, tedge num: 119686.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.864205s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (99.7%)
+
+RUN-1004 : used memory is 687 MB, reserved memory is 692 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17794 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.738631s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(277): len = 711960, overlap = 0
+PHY-3002 : Step(278): len = 711960, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16366/17972.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 882416, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.126904s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.5%)
+
+PHY-1001 : Congestion index: top1 = 54.87, top5 = 48.75, top10 = 45.72, top15 = 43.82.
+PHY-3001 : End congestion estimation; 0.434986s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17794 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.853471s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000536183
+PHY-3002 : Step(279): len = 711251, overlap = 1.5
+PHY-3002 : Step(280): len = 710844, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005410s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (288.8%)
+
+PHY-3001 : Legalized: Len = 710893, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058435s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.0%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 711077, Over = 0
+PHY-3001 : End incremental placement; 5.479458s wall, 5.468750s user + 0.031250s system = 5.500000s CPU (100.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.264256s wall, 10.156250s user + 0.062500s system = 10.218750s CPU (110.3%)
+
+OPT-1001 : Current memory(MB): used = 744, reserve = 739, peak = 747.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16322/17972.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 881384, over cnt = 88(0%), over = 116, worst = 6
+PHY-1002 : len = 881536, over cnt = 43(0%), over = 54, worst = 3
+PHY-1002 : len = 882000, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 882152, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.618880s wall, 0.656250s user + 0.015625s system = 0.671875s CPU (108.6%)
+
+PHY-1001 : Congestion index: top1 = 54.87, top5 = 48.87, top10 = 45.78, top15 = 43.79.
+OPT-1001 : End congestion update; 0.926319s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (108.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17794 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.713379s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.6%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6638 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6726 instances, 6577 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3675 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 716990, Over = 0
+PHY-3001 : Spreading special nets. 21 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061834s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.1%)
+
+PHY-3001 : 34 instances has been re-located, deltaX = 24, deltaY = 34, maxDist = 4.
+PHY-3001 : Final: Len = 718174, Over = 0
+PHY-3001 : End incremental legalization; 0.384443s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.6%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 58 cells processed and 16740 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6638 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6726 instances, 6577 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3675 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 720596, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060136s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.9%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 8, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 720826, Over = 0
+PHY-3001 : End incremental legalization; 0.383101s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.0%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 4611 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6638 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6726 instances, 6577 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3675 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 720984, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058684s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.5%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 6, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 721108, Over = 0
+PHY-3001 : End incremental legalization; 0.381927s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.2%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 1821 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6644 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6732 instances, 6583 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 721489, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059740s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 0, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 721477, Over = 0
+PHY-3001 : End incremental legalization; 0.386031s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.1%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 5 cells processed and 1000 slack improved
+OPT-1001 : End bottleneck based optimization; 3.770586s wall, 3.984375s user + 0.031250s system = 4.015625s CPU (106.5%)
+
+OPT-1001 : Current memory(MB): used = 744, reserve = 739, peak = 747.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15943/17978.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891472, over cnt = 164(0%), over = 236, worst = 5
+PHY-1002 : len = 892040, over cnt = 89(0%), over = 105, worst = 4
+PHY-1002 : len = 892928, over cnt = 22(0%), over = 31, worst = 4
+PHY-1002 : len = 893288, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 893304, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.823557s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (110.0%)
+
+PHY-1001 : Congestion index: top1 = 55.11, top5 = 48.91, top10 = 45.78, top15 = 43.84.
+OPT-1001 : End congestion update; 1.138168s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (105.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.749085s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.1%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6644 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6732 instances, 6583 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3676 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 721633, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058856s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.2%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 4, deltaY = 6, maxDist = 1.
+PHY-3001 : Final: Len = 721691, Over = 0
+PHY-3001 : End incremental legalization; 0.419372s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.6%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 14 cells processed and 1650 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.473043s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (106.8%)
+
+OPT-1001 : Current memory(MB): used = 744, reserve = 739, peak = 747.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.753057s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16321/17978.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 893552, over cnt = 44(0%), over = 49, worst = 2
+PHY-1002 : len = 893496, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 893568, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 893712, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 893744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.757865s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.0%)
+
+PHY-1001 : Congestion index: top1 = 55.02, top5 = 48.85, top10 = 45.77, top15 = 43.85.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717553s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.620690
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 20.154950s wall, 21.421875s user + 0.093750s system = 21.515625s CPU (106.8%)
+
+RUN-1003 : finish command "place" in 64.854304s wall, 91.609375s user + 5.687500s system = 97.296875s CPU (150.0%)
+
+RUN-1004 : used memory is 687 MB, reserved memory is 691 MB, peak memory is 747 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.670209s wall, 2.875000s user + 0.046875s system = 2.921875s CPU (174.9%)
+
+RUN-1004 : used memory is 687 MB, reserved memory is 691 MB, peak memory is 747 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6734 instances
+RUN-1001 : 3297 mslices, 3286 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17978 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10061 nets have 2 pins
+RUN-1001 : 6523 nets have [3 - 5] pins
+RUN-1001 : 742 nets have [6 - 10] pins
+RUN-1001 : 314 nets have [11 - 20] pins
+RUN-1001 : 310 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72082, tnet num: 17800, tinst num: 6732, tnode num: 94807, tedge num: 119776.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.593668s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.0%)
+
+RUN-1004 : used memory is 668 MB, reserved memory is 663 MB, peak memory is 747 MB
+PHY-1001 : 3297 mslices, 3286 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 824896, over cnt = 2677(7%), over = 4465, worst = 8
+PHY-1002 : len = 843056, over cnt = 1568(4%), over = 2264, worst = 8
+PHY-1002 : len = 863424, over cnt = 566(1%), over = 738, worst = 6
+PHY-1002 : len = 875000, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 875496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.071527s wall, 4.093750s user + 0.031250s system = 4.125000s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 52.78, top5 = 47.91, top10 = 45.13, top15 = 43.26.
+PHY-1001 : End global routing; 3.409181s wall, 4.421875s user + 0.031250s system = 4.453125s CPU (130.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 722, reserve = 719, peak = 747.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 989, reserve = 988, peak = 989.
+PHY-1001 : End build detailed router design. 4.055408s wall, 4.046875s user + 0.000000s system = 4.046875s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273784, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.395629s wall, 5.390625s user + 0.000000s system = 5.390625s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273840, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.540678s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (98.3%)
+
+PHY-1001 : Current memory(MB): used = 1024, reserve = 1023, peak = 1024.
+PHY-1001 : End phase 1; 5.950268s wall, 5.937500s user + 0.000000s system = 5.937500s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.30606e+06, over cnt = 1543(0%), over = 1550, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1039, reserve = 1036, peak = 1039.
+PHY-1001 : End initial routed; 23.514420s wall, 54.937500s user + 0.125000s system = 55.062500s CPU (234.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 17/16901(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.784 | -1.020 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.252688s wall, 3.234375s user + 0.015625s system = 3.250000s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1049, reserve = 1047, peak = 1049.
+PHY-1001 : End phase 2; 26.767181s wall, 58.171875s user + 0.140625s system = 58.312500s CPU (217.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 6 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.158936s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.3%)
+
+PHY-1022 : len = 2.30611e+06, over cnt = 1548(0%), over = 1555, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.430470s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.27355e+06, over cnt = 619(0%), over = 621, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.217219s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (165.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.27293e+06, over cnt = 122(0%), over = 122, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.608366s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (159.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.27374e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.411936s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (113.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.27419e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.275361s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2743e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.184827s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16901(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.254333s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 457 feed throughs used by 361 nets
+PHY-1001 : End commit to database; 2.223589s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1150, reserve = 1152, peak = 1150.
+PHY-1001 : End phase 3; 9.000906s wall, 10.203125s user + 0.015625s system = 10.218750s CPU (113.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.135462s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.8%)
+
+PHY-1022 : len = 2.2743e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.380548s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16901(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.246306s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 457 feed throughs used by 361 nets
+PHY-1001 : End commit to database; 2.340540s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1161, peak = 1159.
+PHY-1001 : End phase 4; 5.994572s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.2743e+06
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1163, peak = 1161.
+PHY-1001 : End export database. 0.149066s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.8%)
+
+PHY-1001 : End detail routing; 52.324222s wall, 84.906250s user + 0.156250s system = 85.062500s CPU (162.6%)
+
+RUN-1003 : finish command "route" in 58.378903s wall, 91.953125s user + 0.218750s system = 92.171875s CPU (157.9%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1090 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10184 out of 19600 51.96%
+#reg 9589 out of 19600 48.92%
+#le 12212
+ #lut only 2623 out of 12212 21.48%
+ #reg only 2028 out of 12212 16.61%
+ #lut® 7561 out of 12212 61.91%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1760
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1447
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1334
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 956
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 132
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 68
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 25
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_sot_min/reg1_syn_288.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_eot_min/reg1_syn_253.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P166 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P104 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P83 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P16 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P88 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P82 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P86 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12212 |9157 |1027 |9621 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |507 |389 |23 |440 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |77 |4 |90 |4 |0 |
+| U_crc16_24b |crc16_24b |29 |29 |0 |17 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |10 |0 |7 |0 |0 |
+| exdev_ctl_a |exdev_ctl |766 |430 |96 |588 |0 |0 |
+| u_ADconfig |AD_config |188 |139 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |257 |150 |71 |123 |0 |0 |
+| exdev_ctl_b |exdev_ctl |730 |389 |96 |551 |0 |0 |
+| u_ADconfig |AD_config |165 |124 |25 |123 |0 |0 |
+| u_gen_sp |gen_sp |252 |140 |71 |115 |0 |0 |
+| sampling_fe_a |sampling_fe |2919 |2395 |306 |2074 |25 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |187 |126 |17 |155 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort |2699 |2250 |289 |1886 |25 |0 |
+| rddpram_ctl |rddpram_ctl |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2286 |1908 |253 |1536 |22 |0 |
+| channelPart |channel_part_8478 |135 |129 |3 |122 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1785 |1490 |197 |1142 |0 |0 |
+| adc_addr_gen |adc_addr_gen |229 |200 |27 |128 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |9 |3 |10 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |30 |27 |3 |18 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |19 |16 |3 |9 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |18 |15 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| insert |insert |968 |702 |170 |666 |0 |0 |
+| ram_switch_state |ram_switch_state |588 |588 |0 |348 |0 |0 |
+| read_ram_i |read_ram |273 |216 |44 |193 |0 |0 |
+| read_ram_addr |read_ram_addr |226 |186 |40 |157 |0 |0 |
+| read_ram_data |read_ram_data |45 |28 |4 |34 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |309 |253 |36 |272 |3 |0 |
+| u0_soft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3058 |2417 |349 |2064 |25 |1 |
+| u0_soft_n |cdc_sync |6 |2 |0 |6 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |99 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2837 |2310 |332 |1873 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2455 |1999 |290 |1536 |22 |1 |
+| channelPart |channel_part_8478 |129 |120 |3 |124 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1881 |1557 |197 |1134 |0 |0 |
+| adc_addr_gen |adc_addr_gen |220 |193 |27 |108 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |15 |3 |8 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |34 |31 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |8 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| insert |insert |991 |694 |170 |688 |0 |0 |
+| ram_switch_state |ram_switch_state |670 |670 |0 |338 |0 |0 |
+| read_ram_i |read_ram_rev |363 |252 |81 |210 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |300 |215 |73 |166 |0 |0 |
+| read_ram_data |read_ram_data_rev |63 |37 |8 |44 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9999
+ #2 2 4248
+ #3 3 1712
+ #4 4 560
+ #5 5-10 783
+ #6 11-50 569
+ #7 51-100 11
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.050378s wall, 3.500000s user + 0.031250s system = 3.531250s CPU (172.2%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1090 MB, peak memory is 1161 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72082, tnet num: 17800, tinst num: 6732, tnode num: 94807, tedge num: 119776.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.584250s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.6%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1094 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17800 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.467772s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.1%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1097 MB, peak memory is 1161 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6732
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17978, pip num: 169117
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 457
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 470129 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.778157s wall, 59.031250s user + 0.250000s system = 59.281250s CPU (606.3%)
+
+RUN-1004 : used memory is 1251 MB, reserved memory is 1249 MB, peak memory is 1367 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_142553.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_160201.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_160201.log
new file mode 100644
index 0000000..c5a85f2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_160201.log
@@ -0,0 +1,2040 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 16:02:01 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_12M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.228991s wall, 2.062500s user + 0.171875s system = 2.234375s CPU (100.2%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 318 MB, peak memory is 345 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 2.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 2.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18217 instances
+RUN-0007 : 7761 luts, 9234 seqs, 700 mslices, 374 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20795 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13312 nets have 2 pins
+RUN-1001 : 6388 nets have [3 - 5] pins
+RUN-1001 : 691 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 165 nets have [21 - 99] pins
+RUN-1001 : 57 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2000
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18215 instances, 7761 luts, 9234 seqs, 1074 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6105 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85381, tnet num: 20617, tinst num: 18215, tnode num: 116131, tedge num: 136290.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.156045s wall, 1.093750s user + 0.062500s system = 1.156250s CPU (100.0%)
+
+RUN-1004 : used memory is 536 MB, reserved memory is 520 MB, peak memory is 536 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20617 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.949378s wall, 1.875000s user + 0.078125s system = 1.953125s CPU (100.2%)
+
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.16092e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18215.
+PHY-3001 : Level 1 #clusters 2048.
+PHY-3001 : End clustering; 0.129305s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32595e+06, overlap = 493.594
+PHY-3002 : Step(2): len = 1.24151e+06, overlap = 531.219
+PHY-3002 : Step(3): len = 852952, overlap = 614.719
+PHY-3002 : Step(4): len = 781708, overlap = 690.219
+PHY-3002 : Step(5): len = 617274, overlap = 805.25
+PHY-3002 : Step(6): len = 568401, overlap = 848.594
+PHY-3002 : Step(7): len = 454288, overlap = 936
+PHY-3002 : Step(8): len = 426685, overlap = 959.344
+PHY-3002 : Step(9): len = 376208, overlap = 984.875
+PHY-3002 : Step(10): len = 356007, overlap = 1036.44
+PHY-3002 : Step(11): len = 317432, overlap = 1082.41
+PHY-3002 : Step(12): len = 301966, overlap = 1139.69
+PHY-3002 : Step(13): len = 267323, overlap = 1235
+PHY-3002 : Step(14): len = 251828, overlap = 1289.34
+PHY-3002 : Step(15): len = 224504, overlap = 1347.34
+PHY-3002 : Step(16): len = 213653, overlap = 1381.16
+PHY-3002 : Step(17): len = 187092, overlap = 1408.12
+PHY-3002 : Step(18): len = 172447, overlap = 1410.88
+PHY-3002 : Step(19): len = 160529, overlap = 1428.72
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.22192e-06
+PHY-3002 : Step(20): len = 160693, overlap = 1428.22
+PHY-3002 : Step(21): len = 191735, overlap = 1336.09
+PHY-3002 : Step(22): len = 199234, overlap = 1231.72
+PHY-3002 : Step(23): len = 208368, overlap = 1127.69
+PHY-3002 : Step(24): len = 208188, overlap = 1074.72
+PHY-3002 : Step(25): len = 209725, overlap = 1095.5
+PHY-3002 : Step(26): len = 205388, overlap = 1121.44
+PHY-3002 : Step(27): len = 204474, overlap = 1120.38
+PHY-3002 : Step(28): len = 201143, overlap = 1115.09
+PHY-3002 : Step(29): len = 199148, overlap = 1112.94
+PHY-3002 : Step(30): len = 194383, overlap = 1108.88
+PHY-3002 : Step(31): len = 193560, overlap = 1114.78
+PHY-3002 : Step(32): len = 190623, overlap = 1098.81
+PHY-3002 : Step(33): len = 190657, overlap = 1097.03
+PHY-3002 : Step(34): len = 187480, overlap = 1095.81
+PHY-3002 : Step(35): len = 186759, overlap = 1106.47
+PHY-3002 : Step(36): len = 185801, overlap = 1114.91
+PHY-3002 : Step(37): len = 185253, overlap = 1109.44
+PHY-3002 : Step(38): len = 183566, overlap = 1098.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.44384e-06
+PHY-3002 : Step(39): len = 188936, overlap = 1085.09
+PHY-3002 : Step(40): len = 200753, overlap = 1022.5
+PHY-3002 : Step(41): len = 204973, overlap = 1006.81
+PHY-3002 : Step(42): len = 210710, overlap = 990.5
+PHY-3002 : Step(43): len = 213265, overlap = 991.625
+PHY-3002 : Step(44): len = 214836, overlap = 1001.06
+PHY-3002 : Step(45): len = 213034, overlap = 1009.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.88769e-06
+PHY-3002 : Step(46): len = 222192, overlap = 996.125
+PHY-3002 : Step(47): len = 241187, overlap = 904.531
+PHY-3002 : Step(48): len = 250850, overlap = 848.156
+PHY-3002 : Step(49): len = 258627, overlap = 803.781
+PHY-3002 : Step(50): len = 261196, overlap = 791.688
+PHY-3002 : Step(51): len = 262406, overlap = 766.375
+PHY-3002 : Step(52): len = 261536, overlap = 751.469
+PHY-3002 : Step(53): len = 260204, overlap = 729.562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.77537e-06
+PHY-3002 : Step(54): len = 274435, overlap = 699.75
+PHY-3002 : Step(55): len = 291190, overlap = 636.844
+PHY-3002 : Step(56): len = 301590, overlap = 565.562
+PHY-3002 : Step(57): len = 310086, overlap = 530.531
+PHY-3002 : Step(58): len = 313899, overlap = 488.219
+PHY-3002 : Step(59): len = 316448, overlap = 475.844
+PHY-3002 : Step(60): len = 313373, overlap = 478
+PHY-3002 : Step(61): len = 312489, overlap = 471
+PHY-3002 : Step(62): len = 310054, overlap = 473.75
+PHY-3002 : Step(63): len = 310557, overlap = 479.156
+PHY-3002 : Step(64): len = 309545, overlap = 472.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.95507e-05
+PHY-3002 : Step(65): len = 328334, overlap = 410.281
+PHY-3002 : Step(66): len = 343176, overlap = 356.25
+PHY-3002 : Step(67): len = 348111, overlap = 356.219
+PHY-3002 : Step(68): len = 352195, overlap = 349.531
+PHY-3002 : Step(69): len = 351671, overlap = 346.531
+PHY-3002 : Step(70): len = 352567, overlap = 323.406
+PHY-3002 : Step(71): len = 351788, overlap = 323.375
+PHY-3002 : Step(72): len = 352890, overlap = 312.875
+PHY-3002 : Step(73): len = 353217, overlap = 332.531
+PHY-3002 : Step(74): len = 354572, overlap = 337.094
+PHY-3002 : Step(75): len = 353017, overlap = 335.469
+PHY-3002 : Step(76): len = 352270, overlap = 338.656
+PHY-3002 : Step(77): len = 351547, overlap = 332.438
+PHY-3002 : Step(78): len = 352370, overlap = 336.312
+PHY-3002 : Step(79): len = 350821, overlap = 356.062
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.91015e-05
+PHY-3002 : Step(80): len = 367048, overlap = 310.031
+PHY-3002 : Step(81): len = 375945, overlap = 298.656
+PHY-3002 : Step(82): len = 376545, overlap = 305.406
+PHY-3002 : Step(83): len = 377085, overlap = 298.438
+PHY-3002 : Step(84): len = 378631, overlap = 298.75
+PHY-3002 : Step(85): len = 381779, overlap = 291.094
+PHY-3002 : Step(86): len = 382018, overlap = 272.562
+PHY-3002 : Step(87): len = 382956, overlap = 261.594
+PHY-3002 : Step(88): len = 384790, overlap = 267.906
+PHY-3002 : Step(89): len = 386682, overlap = 277.188
+PHY-3002 : Step(90): len = 384504, overlap = 270.312
+PHY-3002 : Step(91): len = 385549, overlap = 262.438
+PHY-3002 : Step(92): len = 386527, overlap = 264.531
+PHY-3002 : Step(93): len = 387965, overlap = 266.531
+PHY-3002 : Step(94): len = 386768, overlap = 256.375
+PHY-3002 : Step(95): len = 386792, overlap = 264.969
+PHY-3002 : Step(96): len = 387874, overlap = 252.438
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.8203e-05
+PHY-3002 : Step(97): len = 401967, overlap = 270
+PHY-3002 : Step(98): len = 411237, overlap = 266.438
+PHY-3002 : Step(99): len = 411330, overlap = 254.562
+PHY-3002 : Step(100): len = 414252, overlap = 251.844
+PHY-3002 : Step(101): len = 419598, overlap = 232.906
+PHY-3002 : Step(102): len = 424417, overlap = 233.469
+PHY-3002 : Step(103): len = 419426, overlap = 241.156
+PHY-3002 : Step(104): len = 419674, overlap = 241
+PHY-3002 : Step(105): len = 422912, overlap = 232.25
+PHY-3002 : Step(106): len = 426412, overlap = 226.156
+PHY-3002 : Step(107): len = 421148, overlap = 224.312
+PHY-3002 : Step(108): len = 421615, overlap = 217.719
+PHY-3002 : Step(109): len = 424390, overlap = 224.969
+PHY-3002 : Step(110): len = 427038, overlap = 223.438
+PHY-3002 : Step(111): len = 422721, overlap = 222.781
+PHY-3002 : Step(112): len = 422691, overlap = 222.125
+PHY-3002 : Step(113): len = 425097, overlap = 228
+PHY-3002 : Step(114): len = 427113, overlap = 233.969
+PHY-3002 : Step(115): len = 423928, overlap = 235.812
+PHY-3002 : Step(116): len = 424251, overlap = 228.281
+PHY-3002 : Step(117): len = 425532, overlap = 238.469
+PHY-3002 : Step(118): len = 425980, overlap = 238.719
+PHY-3002 : Step(119): len = 423537, overlap = 239.156
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000148628
+PHY-3002 : Step(120): len = 435358, overlap = 234.781
+PHY-3002 : Step(121): len = 443378, overlap = 221.938
+PHY-3002 : Step(122): len = 442970, overlap = 225.969
+PHY-3002 : Step(123): len = 444199, overlap = 218.531
+PHY-3002 : Step(124): len = 447390, overlap = 214.031
+PHY-3002 : Step(125): len = 450050, overlap = 209.688
+PHY-3002 : Step(126): len = 448502, overlap = 209.812
+PHY-3002 : Step(127): len = 449145, overlap = 206.719
+PHY-3002 : Step(128): len = 451623, overlap = 215.781
+PHY-3002 : Step(129): len = 453269, overlap = 210.156
+PHY-3002 : Step(130): len = 451302, overlap = 204.75
+PHY-3002 : Step(131): len = 451082, overlap = 201.5
+PHY-3002 : Step(132): len = 452444, overlap = 200.25
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000297255
+PHY-3002 : Step(133): len = 461501, overlap = 194.812
+PHY-3002 : Step(134): len = 472880, overlap = 174.969
+PHY-3002 : Step(135): len = 475587, overlap = 161.5
+PHY-3002 : Step(136): len = 477763, overlap = 156.75
+PHY-3002 : Step(137): len = 479237, overlap = 157.312
+PHY-3002 : Step(138): len = 480939, overlap = 145.469
+PHY-3002 : Step(139): len = 479325, overlap = 156.281
+PHY-3002 : Step(140): len = 480583, overlap = 167.219
+PHY-3002 : Step(141): len = 483599, overlap = 167.781
+PHY-3002 : Step(142): len = 485164, overlap = 160.125
+PHY-3002 : Step(143): len = 482718, overlap = 151.75
+PHY-3002 : Step(144): len = 482194, overlap = 149.156
+PHY-3002 : Step(145): len = 483420, overlap = 149.219
+PHY-3002 : Step(146): len = 484178, overlap = 144.906
+PHY-3002 : Step(147): len = 482537, overlap = 150.844
+PHY-3002 : Step(148): len = 482531, overlap = 153.469
+PHY-3002 : Step(149): len = 484296, overlap = 149.469
+PHY-3002 : Step(150): len = 485356, overlap = 153.281
+PHY-3002 : Step(151): len = 483411, overlap = 150.312
+PHY-3002 : Step(152): len = 482793, overlap = 148.406
+PHY-3002 : Step(153): len = 483902, overlap = 146.375
+PHY-3002 : Step(154): len = 484219, overlap = 146.312
+PHY-3002 : Step(155): len = 483018, overlap = 148.969
+PHY-3002 : Step(156): len = 482431, overlap = 155.25
+PHY-3002 : Step(157): len = 483786, overlap = 154.625
+PHY-3002 : Step(158): len = 486217, overlap = 148
+PHY-3002 : Step(159): len = 484893, overlap = 155.281
+PHY-3002 : Step(160): len = 484782, overlap = 155.188
+PHY-3002 : Step(161): len = 485256, overlap = 161.688
+PHY-3002 : Step(162): len = 485323, overlap = 157.531
+PHY-3002 : Step(163): len = 484182, overlap = 159.094
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000550709
+PHY-3002 : Step(164): len = 489130, overlap = 157.906
+PHY-3002 : Step(165): len = 494361, overlap = 163.531
+PHY-3002 : Step(166): len = 494988, overlap = 163.406
+PHY-3002 : Step(167): len = 495486, overlap = 162.875
+PHY-3002 : Step(168): len = 496905, overlap = 162.812
+PHY-3002 : Step(169): len = 497838, overlap = 159.875
+PHY-3002 : Step(170): len = 497223, overlap = 156.5
+PHY-3002 : Step(171): len = 497403, overlap = 152.625
+PHY-3002 : Step(172): len = 498444, overlap = 163.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00104323
+PHY-3002 : Step(173): len = 502674, overlap = 160.281
+PHY-3002 : Step(174): len = 508950, overlap = 157.469
+PHY-3002 : Step(175): len = 510616, overlap = 155.969
+PHY-3002 : Step(176): len = 511504, overlap = 154.031
+PHY-3002 : Step(177): len = 512826, overlap = 158.688
+PHY-3002 : Step(178): len = 514052, overlap = 157.781
+PHY-3002 : Step(179): len = 513499, overlap = 149.969
+PHY-3002 : Step(180): len = 513383, overlap = 149.438
+PHY-3002 : Step(181): len = 514801, overlap = 142.375
+PHY-3002 : Step(182): len = 516662, overlap = 146.375
+PHY-3002 : Step(183): len = 516741, overlap = 138.719
+PHY-3002 : Step(184): len = 517805, overlap = 144.844
+PHY-3002 : Step(185): len = 521134, overlap = 143.625
+PHY-3002 : Step(186): len = 523606, overlap = 144.969
+PHY-3002 : Step(187): len = 522563, overlap = 137.781
+PHY-3002 : Step(188): len = 522382, overlap = 137.312
+PHY-3002 : Step(189): len = 523320, overlap = 136.781
+PHY-3002 : Step(190): len = 523670, overlap = 137.625
+PHY-3002 : Step(191): len = 522906, overlap = 138.25
+PHY-3002 : Step(192): len = 522466, overlap = 140.812
+PHY-3002 : Step(193): len = 521799, overlap = 148.938
+PHY-3002 : Step(194): len = 521559, overlap = 150.125
+PHY-3002 : Step(195): len = 521187, overlap = 150.094
+PHY-3002 : Step(196): len = 521057, overlap = 151.125
+PHY-3002 : Step(197): len = 520702, overlap = 149.781
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0019496
+PHY-3002 : Step(198): len = 522368, overlap = 148.562
+PHY-3002 : Step(199): len = 524923, overlap = 142
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012191s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20795.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 713400, over cnt = 1637(4%), over = 7701, worst = 58
+PHY-1001 : End global iterations; 0.732531s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (125.8%)
+
+PHY-1001 : Congestion index: top1 = 80.47, top5 = 62.22, top10 = 53.34, top15 = 47.87.
+PHY-3001 : End congestion estimation; 0.959634s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (118.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20617 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.859158s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000149434
+PHY-3002 : Step(200): len = 637039, overlap = 99.3438
+PHY-3002 : Step(201): len = 637083, overlap = 79.8438
+PHY-3002 : Step(202): len = 632963, overlap = 78.7812
+PHY-3002 : Step(203): len = 632951, overlap = 77.1562
+PHY-3002 : Step(204): len = 635134, overlap = 66.5312
+PHY-3002 : Step(205): len = 632880, overlap = 58.5938
+PHY-3002 : Step(206): len = 629547, overlap = 56.25
+PHY-3002 : Step(207): len = 625659, overlap = 53.8438
+PHY-3002 : Step(208): len = 622828, overlap = 51.25
+PHY-3002 : Step(209): len = 620463, overlap = 47.7812
+PHY-3002 : Step(210): len = 619053, overlap = 44.7812
+PHY-3002 : Step(211): len = 616677, overlap = 43.5938
+PHY-3002 : Step(212): len = 615388, overlap = 41.9688
+PHY-3002 : Step(213): len = 614117, overlap = 40.4688
+PHY-3002 : Step(214): len = 612989, overlap = 39.5938
+PHY-3002 : Step(215): len = 612864, overlap = 37.4062
+PHY-3002 : Step(216): len = 611036, overlap = 35.2188
+PHY-3002 : Step(217): len = 610660, overlap = 34.25
+PHY-3002 : Step(218): len = 608990, overlap = 34.6562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000298867
+PHY-3002 : Step(219): len = 611217, overlap = 34.375
+PHY-3002 : Step(220): len = 612822, overlap = 32.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 176/20795.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 704408, over cnt = 2593(7%), over = 11574, worst = 43
+PHY-1001 : End global iterations; 1.625711s wall, 2.046875s user + 0.093750s system = 2.140625s CPU (131.7%)
+
+PHY-1001 : Congestion index: top1 = 87.03, top5 = 66.05, top10 = 56.72, top15 = 51.25.
+PHY-3001 : End congestion estimation; 1.918802s wall, 2.312500s user + 0.109375s system = 2.421875s CPU (126.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20617 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.928223s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.36516e-05
+PHY-3002 : Step(221): len = 611629, overlap = 303.812
+PHY-3002 : Step(222): len = 616060, overlap = 257.438
+PHY-3002 : Step(223): len = 611442, overlap = 247.188
+PHY-3002 : Step(224): len = 609774, overlap = 221.844
+PHY-3002 : Step(225): len = 610087, overlap = 205.344
+PHY-3002 : Step(226): len = 608041, overlap = 173.719
+PHY-3002 : Step(227): len = 606432, overlap = 163.594
+PHY-3002 : Step(228): len = 604599, overlap = 156.781
+PHY-3002 : Step(229): len = 602161, overlap = 142.625
+PHY-3002 : Step(230): len = 601043, overlap = 139.25
+PHY-3002 : Step(231): len = 597235, overlap = 139.062
+PHY-3002 : Step(232): len = 596076, overlap = 138.625
+PHY-3002 : Step(233): len = 593306, overlap = 146.031
+PHY-3002 : Step(234): len = 590340, overlap = 143.875
+PHY-3002 : Step(235): len = 588191, overlap = 142.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000167303
+PHY-3002 : Step(236): len = 588659, overlap = 138.062
+PHY-3002 : Step(237): len = 589975, overlap = 138.281
+PHY-3002 : Step(238): len = 592687, overlap = 130.938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000334607
+PHY-3002 : Step(239): len = 600110, overlap = 115.75
+PHY-3002 : Step(240): len = 607128, overlap = 108.906
+PHY-3002 : Step(241): len = 615701, overlap = 99.1875
+PHY-3002 : Step(242): len = 618037, overlap = 92.5312
+PHY-3002 : Step(243): len = 618524, overlap = 89.25
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85381, tnet num: 20617, tinst num: 18215, tnode num: 116131, tedge num: 136290.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.463013s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.4%)
+
+RUN-1004 : used memory is 578 MB, reserved memory is 568 MB, peak memory is 715 MB
+OPT-1001 : Total overflow 429.75 peak overflow 3.84
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 814/20795.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719504, over cnt = 3038(8%), over = 11575, worst = 27
+PHY-1001 : End global iterations; 1.356775s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (134.7%)
+
+PHY-1001 : Congestion index: top1 = 76.83, top5 = 61.48, top10 = 53.83, top15 = 49.48.
+PHY-1001 : End incremental global routing; 1.695127s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (128.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20617 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.945270s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.2%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18079 has valid locations, 329 needs to be replaced
+PHY-3001 : design contains 18493 instances, 7848 luts, 9425 seqs, 1074 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6232 pins
+PHY-3001 : Found 1269 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 644049
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16826/21073.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736216, over cnt = 3079(8%), over = 11680, worst = 27
+PHY-1001 : End global iterations; 0.229207s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (129.5%)
+
+PHY-1001 : Congestion index: top1 = 76.34, top5 = 61.54, top10 = 54.18, top15 = 49.77.
+PHY-3001 : End congestion estimation; 0.485852s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (115.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86465, tnet num: 20895, tinst num: 18493, tnode num: 117782, tedge num: 137902.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.482686s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (100.1%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 616 MB, peak memory is 718 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20895 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.439507s wall, 2.406250s user + 0.046875s system = 2.453125s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(244): len = 643036, overlap = 1.0625
+PHY-3002 : Step(245): len = 642485, overlap = 1.0625
+PHY-3002 : Step(246): len = 642235, overlap = 1.125
+PHY-3002 : Step(247): len = 642081, overlap = 1.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16898/21073.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733560, over cnt = 3078(8%), over = 11712, worst = 27
+PHY-1001 : End global iterations; 0.191728s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (146.7%)
+
+PHY-1001 : Congestion index: top1 = 77.20, top5 = 62.22, top10 = 54.61, top15 = 50.10.
+PHY-3001 : End congestion estimation; 0.444453s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (123.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20895 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.943551s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000431261
+PHY-3002 : Step(248): len = 641861, overlap = 91.5938
+PHY-3002 : Step(249): len = 641796, overlap = 91.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000862522
+PHY-3002 : Step(250): len = 642008, overlap = 91.4688
+PHY-3002 : Step(251): len = 642687, overlap = 91.4062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00171909
+PHY-3002 : Step(252): len = 642871, overlap = 91.5312
+PHY-3002 : Step(253): len = 643321, overlap = 91
+PHY-3001 : Final: Len = 643321, Over = 91
+PHY-3001 : End incremental placement; 5.043500s wall, 5.375000s user + 0.265625s system = 5.640625s CPU (111.8%)
+
+OPT-1001 : Total overflow 435.28 peak overflow 3.84
+OPT-1001 : End high-fanout net optimization; 8.259758s wall, 9.156250s user + 0.281250s system = 9.437500s CPU (114.3%)
+
+OPT-1001 : Current memory(MB): used = 720, reserve = 715, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16857/21073.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737376, over cnt = 3028(8%), over = 10607, worst = 25
+PHY-1002 : len = 786344, over cnt = 2364(6%), over = 6318, worst = 25
+PHY-1002 : len = 848888, over cnt = 811(2%), over = 1796, worst = 17
+PHY-1002 : len = 869712, over cnt = 339(0%), over = 595, worst = 10
+PHY-1002 : len = 881592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.132261s wall, 2.765625s user + 0.046875s system = 2.812500s CPU (131.9%)
+
+PHY-1001 : Congestion index: top1 = 62.44, top5 = 54.21, top10 = 49.85, top15 = 46.96.
+OPT-1001 : End congestion update; 2.392848s wall, 3.015625s user + 0.046875s system = 3.062500s CPU (128.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20895 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.800562s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.5%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 127 cells processed and 16400 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 44 cells processed and 6500 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 700 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.666315s wall, 4.281250s user + 0.046875s system = 4.328125s CPU (118.1%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 690, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16914/21075.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 881288, over cnt = 119(0%), over = 172, worst = 5
+PHY-1002 : len = 881008, over cnt = 78(0%), over = 93, worst = 3
+PHY-1002 : len = 881296, over cnt = 27(0%), over = 32, worst = 3
+PHY-1002 : len = 881536, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 881680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.816353s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (101.4%)
+
+PHY-1001 : Congestion index: top1 = 62.11, top5 = 53.98, top10 = 49.60, top15 = 46.75.
+OPT-1001 : End congestion update; 1.100419s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (102.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20897 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.994217s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.0%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 25 cells processed and 4850 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.226240s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (101.1%)
+
+OPT-1001 : Current memory(MB): used = 710, reserve = 704, peak = 738.
+OPT-1001 : End physical optimization; 15.927504s wall, 17.484375s user + 0.390625s system = 17.875000s CPU (112.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7848 LUT to BLE ...
+SYN-4008 : Packed 7848 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6279 remaining SEQ's ...
+SYN-4005 : Packed 4022 SEQ with LUT/SLICE
+SYN-4006 : 979 single LUT's are left
+SYN-4006 : 2257 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10105/13891 primitive instances ...
+PHY-3001 : End packing; 1.746163s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6855 instances
+RUN-1001 : 3353 mslices, 3354 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18068 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10101 nets have 2 pins
+RUN-1001 : 6543 nets have [3 - 5] pins
+RUN-1001 : 786 nets have [6 - 10] pins
+RUN-1001 : 291 nets have [11 - 20] pins
+RUN-1001 : 317 nets have [21 - 99] pins
+RUN-1001 : 10 nets have 100+ pins
+PHY-3001 : design contains 6853 instances, 6707 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3621 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 657487, Over = 246.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7682/18068.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 824464, over cnt = 2108(5%), over = 3501, worst = 7
+PHY-1002 : len = 832928, over cnt = 1345(3%), over = 1893, worst = 7
+PHY-1002 : len = 847656, over cnt = 457(1%), over = 632, worst = 6
+PHY-1002 : len = 857480, over cnt = 84(0%), over = 118, worst = 4
+PHY-1002 : len = 859984, over cnt = 4(0%), over = 4, worst = 1
+PHY-1001 : End global iterations; 1.678704s wall, 2.375000s user + 0.046875s system = 2.421875s CPU (144.3%)
+
+PHY-1001 : Congestion index: top1 = 61.59, top5 = 53.01, top10 = 48.67, top15 = 45.90.
+PHY-3001 : End congestion estimation; 2.072195s wall, 2.750000s user + 0.046875s system = 2.796875s CPU (135.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73082, tnet num: 17890, tinst num: 6853, tnode num: 95753, tedge num: 121802.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.618884s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (100.4%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 615 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17890 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.488636s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.83423e-05
+PHY-3002 : Step(254): len = 648232, overlap = 244.5
+PHY-3002 : Step(255): len = 642969, overlap = 239
+PHY-3002 : Step(256): len = 640125, overlap = 241.5
+PHY-3002 : Step(257): len = 638458, overlap = 249.25
+PHY-3002 : Step(258): len = 636341, overlap = 265.75
+PHY-3002 : Step(259): len = 633987, overlap = 268.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.66846e-05
+PHY-3002 : Step(260): len = 636976, overlap = 252.75
+PHY-3002 : Step(261): len = 640436, overlap = 248.5
+PHY-3002 : Step(262): len = 640218, overlap = 248.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000193369
+PHY-3002 : Step(263): len = 649329, overlap = 230.75
+PHY-3002 : Step(264): len = 657851, overlap = 208.75
+PHY-3002 : Step(265): len = 656151, overlap = 207
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.409100s wall, 0.421875s user + 0.578125s system = 1.000000s CPU (244.4%)
+
+PHY-3001 : Trial Legalized: Len = 738836
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1196/18068.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858040, over cnt = 2790(7%), over = 4764, worst = 9
+PHY-1002 : len = 877592, over cnt = 1622(4%), over = 2374, worst = 9
+PHY-1002 : len = 894992, over cnt = 737(2%), over = 1040, worst = 6
+PHY-1002 : len = 907080, over cnt = 284(0%), over = 393, worst = 5
+PHY-1002 : len = 913544, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations; 2.363187s wall, 3.500000s user + 0.031250s system = 3.531250s CPU (149.4%)
+
+PHY-1001 : Congestion index: top1 = 56.75, top5 = 51.53, top10 = 48.40, top15 = 46.32.
+PHY-3001 : End congestion estimation; 2.837665s wall, 3.953125s user + 0.031250s system = 3.984375s CPU (140.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17890 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.855718s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000158444
+PHY-3002 : Step(266): len = 711059, overlap = 47.5
+PHY-3002 : Step(267): len = 694708, overlap = 77.5
+PHY-3002 : Step(268): len = 683733, overlap = 99.5
+PHY-3002 : Step(269): len = 674654, overlap = 126.5
+PHY-3002 : Step(270): len = 670754, overlap = 138.25
+PHY-3002 : Step(271): len = 668068, overlap = 144.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000316889
+PHY-3002 : Step(272): len = 672733, overlap = 140.5
+PHY-3002 : Step(273): len = 677439, overlap = 137.25
+PHY-3002 : Step(274): len = 677280, overlap = 143.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000610285
+PHY-3002 : Step(275): len = 681736, overlap = 144.5
+PHY-3002 : Step(276): len = 692151, overlap = 142.5
+PHY-3002 : Step(277): len = 697572, overlap = 136.5
+PHY-3002 : Step(278): len = 694956, overlap = 140.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.037651s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (83.0%)
+
+PHY-3001 : Legalized: Len = 723284, Over = 0
+PHY-3001 : Spreading special nets. 506 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.113366s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (96.5%)
+
+PHY-3001 : 752 instances has been re-located, deltaX = 288, deltaY = 427, maxDist = 4.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 736080, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73082, tnet num: 17890, tinst num: 6856, tnode num: 95753, tedge num: 121802.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.849140s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (99.7%)
+
+RUN-1004 : used memory is 634 MB, reserved memory is 652 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3345/18068.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 866360, over cnt = 2538(7%), over = 4146, worst = 8
+PHY-1002 : len = 881984, over cnt = 1467(4%), over = 2060, worst = 7
+PHY-1002 : len = 897520, over cnt = 595(1%), over = 822, worst = 6
+PHY-1002 : len = 906920, over cnt = 159(0%), over = 230, worst = 4
+PHY-1002 : len = 910576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.195582s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (137.3%)
+
+PHY-1001 : Congestion index: top1 = 54.46, top5 = 49.39, top10 = 46.62, top15 = 44.71.
+PHY-1001 : End incremental global routing; 2.571953s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (131.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17890 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.884932s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.6%)
+
+OPT-1001 : 2 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6766 has valid locations, 11 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3687 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 739202
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16409/18080.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913720, over cnt = 37(0%), over = 45, worst = 4
+PHY-1002 : len = 913776, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 913864, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 913960, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 914032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.733852s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 54.46, top5 = 49.43, top10 = 46.66, top15 = 44.75.
+PHY-3001 : End congestion estimation; 1.041854s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (99.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73182, tnet num: 17902, tinst num: 6865, tnode num: 95880, tedge num: 121927.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.850616s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (100.5%)
+
+RUN-1004 : used memory is 656 MB, reserved memory is 652 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17902 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.024667s wall, 3.000000s user + 0.031250s system = 3.031250s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(279): len = 738579, overlap = 0
+PHY-3002 : Step(280): len = 737760, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16401/18080.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913040, over cnt = 28(0%), over = 37, worst = 4
+PHY-1002 : len = 913080, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 913272, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 913312, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 913312, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.788079s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.1%)
+
+PHY-1001 : Congestion index: top1 = 54.42, top5 = 49.40, top10 = 46.63, top15 = 44.73.
+PHY-3001 : End congestion estimation; 1.117788s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17902 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.886812s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000346466
+PHY-3002 : Step(281): len = 737392, overlap = 0.5
+PHY-3002 : Step(282): len = 737500, overlap = 0.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005412s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (288.7%)
+
+PHY-3001 : Legalized: Len = 737521, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060983s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.5%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 737545, Over = 0
+PHY-3001 : End incremental placement; 6.555918s wall, 6.515625s user + 0.078125s system = 6.593750s CPU (100.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.527835s wall, 11.281250s user + 0.078125s system = 11.359375s CPU (107.9%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 736, peak = 738.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16396/18080.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912464, over cnt = 28(0%), over = 46, worst = 4
+PHY-1002 : len = 912608, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 912728, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.418994s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.7%)
+
+PHY-1001 : Congestion index: top1 = 54.42, top5 = 49.38, top10 = 46.61, top15 = 44.70.
+OPT-1001 : End congestion update; 0.754618s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17902 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.739047s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.4%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6777 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3687 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 743193, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065858s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.9%)
+
+PHY-3001 : 27 instances has been re-located, deltaX = 16, deltaY = 17, maxDist = 3.
+PHY-3001 : Final: Len = 743745, Over = 0
+PHY-3001 : End incremental legalization; 0.396026s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.6%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 59 cells processed and 14478 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6777 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3687 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 745635, Over = 0
+PHY-3001 : Spreading special nets. 21 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062902s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.4%)
+
+PHY-3001 : 28 instances has been re-located, deltaX = 23, deltaY = 17, maxDist = 3.
+PHY-3001 : Final: Len = 746135, Over = 0
+PHY-3001 : End incremental legalization; 0.389642s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.2%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 33 cells processed and 8581 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6777 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3687 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 746379, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065386s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.6%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 10, deltaY = 10, maxDist = 3.
+PHY-3001 : Final: Len = 746811, Over = 0
+PHY-3001 : End incremental legalization; 0.414091s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (109.4%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 17 cells processed and 1393 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6787 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3689 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748080, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059768s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 5, deltaY = 13, maxDist = 2.
+PHY-3001 : Final: Len = 748152, Over = 0
+PHY-3001 : End incremental legalization; 0.410660s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (121.8%)
+
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 9 cells processed and 1545 slack improved
+OPT-1001 : End bottleneck based optimization; 3.777884s wall, 3.984375s user + 0.031250s system = 4.015625s CPU (106.3%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 735, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15858/18084.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 923792, over cnt = 209(0%), over = 283, worst = 5
+PHY-1002 : len = 923952, over cnt = 124(0%), over = 143, worst = 3
+PHY-1002 : len = 924992, over cnt = 41(0%), over = 48, worst = 3
+PHY-1002 : len = 925696, over cnt = 3(0%), over = 4, worst = 2
+PHY-1002 : len = 925728, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.902691s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (114.2%)
+
+PHY-1001 : Congestion index: top1 = 54.16, top5 = 49.31, top10 = 46.51, top15 = 44.65.
+OPT-1001 : End congestion update; 1.220351s wall, 1.312500s user + 0.031250s system = 1.343750s CPU (110.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17906 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.729100s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.7%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6787 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3689 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748600, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063015s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (124.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 5, deltaY = 12, maxDist = 2.
+PHY-3001 : Final: Len = 748708, Over = 0
+PHY-3001 : End incremental legalization; 0.386699s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.0%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 18 cells processed and 1500 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6787 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3689 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748708, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059204s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.6%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 1, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 748786, Over = 0
+PHY-3001 : End incremental legalization; 0.381995s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (118.6%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 8 cells processed and 200 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6787 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3689 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748756, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063036s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.1%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 4, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 748948, Over = 0
+PHY-3001 : End incremental legalization; 0.384097s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.7%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 8 cells processed and 200 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6787 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6875 instances, 6726 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3689 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 748896, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059325s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.0%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 1, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 748948, Over = 0
+PHY-3001 : End incremental legalization; 0.381556s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (126.9%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 8 cells processed and 100 slack improved
+OPT-1001 : End path based optimization; 3.981958s wall, 4.375000s user + 0.031250s system = 4.406250s CPU (110.7%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 735, peak = 738.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17906 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.726579s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16334/18084.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926304, over cnt = 55(0%), over = 63, worst = 3
+PHY-1002 : len = 926312, over cnt = 35(0%), over = 36, worst = 2
+PHY-1002 : len = 926568, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 926632, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 926688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.989587s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 54.12, top5 = 49.42, top10 = 46.64, top15 = 44.76.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17906 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.771563s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 53.724138
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 23.211593s wall, 24.703125s user + 0.187500s system = 24.890625s CPU (107.2%)
+
+RUN-1003 : finish command "place" in 66.641700s wall, 91.875000s user + 6.062500s system = 97.937500s CPU (147.0%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 600 MB, peak memory is 738 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.724342s wall, 2.953125s user + 0.046875s system = 3.000000s CPU (174.0%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 601 MB, peak memory is 738 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6877 instances
+RUN-1001 : 3362 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18084 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10089 nets have 2 pins
+RUN-1001 : 6556 nets have [3 - 5] pins
+RUN-1001 : 791 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 330 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73271, tnet num: 17906, tinst num: 6875, tnode num: 96001, tedge num: 122056.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.654974s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.1%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 622 MB, peak memory is 738 MB
+PHY-1001 : 3362 mslices, 3364 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17906 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859280, over cnt = 2755(7%), over = 4550, worst = 9
+PHY-1002 : len = 874144, over cnt = 1899(5%), over = 2833, worst = 8
+PHY-1002 : len = 901640, over cnt = 495(1%), over = 670, worst = 6
+PHY-1002 : len = 911936, over cnt = 6(0%), over = 7, worst = 2
+PHY-1002 : len = 912200, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.015918s wall, 3.968750s user + 0.046875s system = 4.015625s CPU (133.1%)
+
+PHY-1001 : Congestion index: top1 = 54.48, top5 = 49.18, top10 = 46.45, top15 = 44.58.
+PHY-1001 : End global routing; 3.356707s wall, 4.296875s user + 0.046875s system = 4.343750s CPU (129.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 708, reserve = 710, peak = 738.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 984, reserve = 986, peak = 984.
+PHY-1001 : End build detailed router design. 4.118637s wall, 4.046875s user + 0.078125s system = 4.125000s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266440, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.083766s wall, 5.078125s user + 0.000000s system = 5.078125s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266496, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.427838s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.3%)
+
+PHY-1001 : Current memory(MB): used = 1019, reserve = 1022, peak = 1019.
+PHY-1001 : End phase 1; 5.523775s wall, 5.515625s user + 0.000000s system = 5.515625s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.30154e+06, over cnt = 1828(0%), over = 1837, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1034, reserve = 1037, peak = 1034.
+PHY-1001 : End initial routed; 28.693952s wall, 58.453125s user + 0.375000s system = 58.828125s CPU (205.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 15/17008(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.784 | -0.981 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.279762s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1047, peak = 1044.
+PHY-1001 : End phase 2; 31.973879s wall, 61.734375s user + 0.375000s system = 62.109375s CPU (194.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.152763s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.1%)
+
+PHY-1022 : len = 2.30157e+06, over cnt = 1832(0%), over = 1841, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.442409s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2695e+06, over cnt = 617(0%), over = 618, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.271843s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (221.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.26963e+06, over cnt = 144(0%), over = 144, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.612155s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (137.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.27016e+06, over cnt = 19(0%), over = 19, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.510893s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (110.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.27038e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.245581s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (108.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2705e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.177482s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/17008(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.256086s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 547 feed throughs used by 418 nets
+PHY-1001 : End commit to database; 2.240628s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1146, reserve = 1153, peak = 1146.
+PHY-1001 : End phase 3; 9.158345s wall, 10.968750s user + 0.015625s system = 10.984375s CPU (119.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.661ns STNS -0.661ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.136515s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1022 : len = 2.2705e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.382370s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -0.661ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/17008(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -0.661 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.295928s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 547 feed throughs used by 418 nets
+PHY-1001 : End commit to database; 2.358902s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1155, reserve = 1163, peak = 1155.
+PHY-1001 : End phase 4; 6.066026s wall, 6.062500s user + 0.000000s system = 6.062500s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.2705e+06
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1165, peak = 1157.
+PHY-1001 : End export database. 0.060505s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.3%)
+
+PHY-1001 : End detail routing; 57.297923s wall, 88.765625s user + 0.468750s system = 89.234375s CPU (155.7%)
+
+RUN-1003 : finish command "route" in 63.390635s wall, 95.796875s user + 0.515625s system = 96.312500s CPU (151.9%)
+
+RUN-1004 : used memory is 1152 MB, reserved memory is 1160 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10383 out of 19600 52.97%
+#reg 9613 out of 19600 49.05%
+#le 12573
+ #lut only 2960 out of 12573 23.54%
+ #reg only 2190 out of 12573 17.42%
+ #lut® 7423 out of 12573 59.04%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1765
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1454
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1335
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 965
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 134
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 26
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/reg11_syn_132.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_387.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P16 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P140 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P35 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P64 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P150 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P169 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P14 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12573 |9357 |1026 |9645 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |521 |417 |23 |439 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |87 |4 |89 |4 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |7 |0 |0 |
+| U_crc16_24b |crc16_24b |41 |41 |0 |22 |0 |0 |
+| exdev_ctl_a |exdev_ctl |751 |389 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |187 |137 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |259 |160 |71 |123 |0 |0 |
+| exdev_ctl_b |exdev_ctl |743 |384 |96 |563 |0 |0 |
+| u_ADconfig |AD_config |170 |112 |25 |128 |0 |0 |
+| u_gen_sp |gen_sp |253 |148 |71 |115 |0 |0 |
+| sampling_fe_a |sampling_fe |3085 |2437 |306 |2126 |25 |0 |
+| u0_soft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u_ad_sampling |ad_sampling |191 |127 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |7 |5 |0 |7 |0 |0 |
+| u_sort |sort |2864 |2292 |289 |1937 |25 |0 |
+| rddpram_ctl |rddpram_ctl |7 |7 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |7 |7 |0 |7 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |0 |1 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2443 |1979 |253 |1581 |22 |0 |
+| channelPart |channel_part_8478 |136 |131 |3 |122 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |46 |0 |0 |
+| ram_switch |ram_switch |1935 |1544 |197 |1178 |0 |0 |
+| adc_addr_gen |adc_addr_gen |251 |224 |27 |119 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |14 |11 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |27 |24 |3 |16 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |10 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |27 |24 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |25 |22 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |12 |0 |0 |
+| insert |insert |971 |607 |170 |687 |0 |0 |
+| ram_switch_state |ram_switch_state |713 |713 |0 |372 |0 |0 |
+| read_ram_i |read_ram |271 |214 |44 |196 |0 |0 |
+| read_ram_addr |read_ram_addr |218 |178 |40 |153 |0 |0 |
+| read_ram_data |read_ram_data |50 |33 |4 |40 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |323 |231 |36 |276 |3 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3260 |2622 |346 |2089 |25 |1 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |196 |114 |17 |167 |0 |0 |
+| u0_soft_n |cdc_sync |7 |2 |0 |7 |0 |0 |
+| u_sort |sort_rev |3035 |2498 |329 |1893 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |3 |1 |0 |3 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2610 |2165 |287 |1539 |22 |1 |
+| channelPart |channel_part_8478 |161 |157 |3 |128 |0 |0 |
+| fifo_adc |fifo_adc |60 |51 |9 |43 |0 |1 |
+| ram_switch |ram_switch |2002 |1677 |197 |1122 |0 |0 |
+| adc_addr_gen |adc_addr_gen |220 |193 |27 |110 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |13 |3 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |22 |19 |3 |9 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |15 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |6 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |18 |15 |3 |9 |0 |0 |
+| insert |insert |1004 |707 |170 |695 |0 |0 |
+| ram_switch_state |ram_switch_state |778 |777 |0 |317 |0 |0 |
+| read_ram_i |read_ram_rev |355 |253 |78 |214 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |290 |208 |70 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |65 |45 |8 |49 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10027
+ #2 2 4270
+ #3 3 1721
+ #4 4 562
+ #5 5-10 842
+ #6 11-50 545
+ #7 51-100 21
+ #8 >500 1
+ Average 2.76
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.076507s wall, 3.546875s user + 0.015625s system = 3.562500s CPU (171.6%)
+
+RUN-1004 : used memory is 1152 MB, reserved memory is 1159 MB, peak memory is 1207 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73271, tnet num: 17906, tinst num: 6875, tnode num: 96001, tedge num: 122056.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.597459s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (98.8%)
+
+RUN-1004 : used memory is 1153 MB, reserved memory is 1161 MB, peak memory is 1207 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17906 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.469942s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (98.9%)
+
+RUN-1004 : used memory is 1154 MB, reserved memory is 1161 MB, peak memory is 1207 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6875
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18084, pip num: 171058
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 547
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3229 valid insts, and 477570 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.530179s wall, 64.437500s user + 0.171875s system = 64.609375s CPU (677.9%)
+
+RUN-1004 : used memory is 1258 MB, reserved memory is 1260 MB, peak memory is 1373 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_160201.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_160923.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_160923.log
new file mode 100644
index 0000000..97581b2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_160923.log
@@ -0,0 +1,2289 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 16:09:24 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_12M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.243273s wall, 2.140625s user + 0.093750s system = 2.234375s CPU (99.6%)
+
+RUN-1004 : used memory is 342 MB, reserved memory is 320 MB, peak memory is 347 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 1.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18458 instances
+RUN-0007 : 8002 luts, 9234 seqs, 700 mslices, 374 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21036 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13255 nets have 2 pins
+RUN-1001 : 6680 nets have [3 - 5] pins
+RUN-1001 : 688 nets have [6 - 10] pins
+RUN-1001 : 165 nets have [11 - 20] pins
+RUN-1001 : 169 nets have [21 - 99] pins
+RUN-1001 : 59 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 2000
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18456 instances, 8002 luts, 9234 seqs, 1074 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6105 pins
+PHY-0007 : Cell area utilization is 51%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86808, tnet num: 20858, tinst num: 18456, tnode num: 117558, tedge num: 138662.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.177528s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.8%)
+
+RUN-1004 : used memory is 541 MB, reserved memory is 525 MB, peak memory is 541 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20858 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.970244s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (100.7%)
+
+PHY-3001 : Found 1261 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.24675e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18456.
+PHY-3001 : Level 1 #clusters 2062.
+PHY-3001 : End clustering; 0.139080s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (112.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.36441e+06, overlap = 485.312
+PHY-3002 : Step(2): len = 1.27771e+06, overlap = 549.906
+PHY-3002 : Step(3): len = 868590, overlap = 619.656
+PHY-3002 : Step(4): len = 799102, overlap = 663.312
+PHY-3002 : Step(5): len = 614169, overlap = 786.062
+PHY-3002 : Step(6): len = 544874, overlap = 835.375
+PHY-3002 : Step(7): len = 459922, overlap = 964.219
+PHY-3002 : Step(8): len = 429603, overlap = 1003.5
+PHY-3002 : Step(9): len = 368392, overlap = 1089.94
+PHY-3002 : Step(10): len = 346889, overlap = 1117.56
+PHY-3002 : Step(11): len = 302394, overlap = 1164.28
+PHY-3002 : Step(12): len = 282069, overlap = 1237.25
+PHY-3002 : Step(13): len = 249650, overlap = 1296.16
+PHY-3002 : Step(14): len = 232261, overlap = 1323.03
+PHY-3002 : Step(15): len = 211075, overlap = 1374.03
+PHY-3002 : Step(16): len = 198027, overlap = 1416.59
+PHY-3002 : Step(17): len = 181577, overlap = 1458.69
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.37789e-06
+PHY-3002 : Step(18): len = 184805, overlap = 1436.16
+PHY-3002 : Step(19): len = 223246, overlap = 1291.03
+PHY-3002 : Step(20): len = 230892, overlap = 1183.5
+PHY-3002 : Step(21): len = 235573, overlap = 1101.19
+PHY-3002 : Step(22): len = 230559, overlap = 1093.12
+PHY-3002 : Step(23): len = 226295, overlap = 1091.66
+PHY-3002 : Step(24): len = 221127, overlap = 1107.75
+PHY-3002 : Step(25): len = 217669, overlap = 1113.62
+PHY-3002 : Step(26): len = 212964, overlap = 1115.22
+PHY-3002 : Step(27): len = 211659, overlap = 1089.91
+PHY-3002 : Step(28): len = 208233, overlap = 1071.56
+PHY-3002 : Step(29): len = 208023, overlap = 1066.44
+PHY-3002 : Step(30): len = 205195, overlap = 1082.75
+PHY-3002 : Step(31): len = 205547, overlap = 1077.72
+PHY-3002 : Step(32): len = 203763, overlap = 1079.22
+PHY-3002 : Step(33): len = 205331, overlap = 1095.41
+PHY-3002 : Step(34): len = 203738, overlap = 1115.41
+PHY-3002 : Step(35): len = 202967, overlap = 1120.62
+PHY-3002 : Step(36): len = 200652, overlap = 1122.28
+PHY-3002 : Step(37): len = 200039, overlap = 1107.47
+PHY-3002 : Step(38): len = 199559, overlap = 1109.44
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.75577e-06
+PHY-3002 : Step(39): len = 202999, overlap = 1105.22
+PHY-3002 : Step(40): len = 214292, overlap = 1075.19
+PHY-3002 : Step(41): len = 218912, overlap = 1063.62
+PHY-3002 : Step(42): len = 224831, overlap = 1045.38
+PHY-3002 : Step(43): len = 228841, overlap = 1024.66
+PHY-3002 : Step(44): len = 230815, overlap = 1002.59
+PHY-3002 : Step(45): len = 229851, overlap = 981.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.51155e-06
+PHY-3002 : Step(46): len = 240421, overlap = 942.938
+PHY-3002 : Step(47): len = 267374, overlap = 858.938
+PHY-3002 : Step(48): len = 280164, overlap = 824.812
+PHY-3002 : Step(49): len = 288501, overlap = 790.375
+PHY-3002 : Step(50): len = 291480, overlap = 738.406
+PHY-3002 : Step(51): len = 293178, overlap = 725.438
+PHY-3002 : Step(52): len = 292041, overlap = 699.719
+PHY-3002 : Step(53): len = 292536, overlap = 685.75
+PHY-3002 : Step(54): len = 291397, overlap = 666.188
+PHY-3002 : Step(55): len = 290690, overlap = 657.656
+PHY-3002 : Step(56): len = 289557, overlap = 659.031
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.10231e-05
+PHY-3002 : Step(57): len = 308086, overlap = 611.75
+PHY-3002 : Step(58): len = 326356, overlap = 562.562
+PHY-3002 : Step(59): len = 332509, overlap = 525.562
+PHY-3002 : Step(60): len = 335216, overlap = 497.781
+PHY-3002 : Step(61): len = 332055, overlap = 499.406
+PHY-3002 : Step(62): len = 331259, overlap = 492.531
+PHY-3002 : Step(63): len = 331005, overlap = 493.781
+PHY-3002 : Step(64): len = 331922, overlap = 497.906
+PHY-3002 : Step(65): len = 330647, overlap = 504.938
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.20462e-05
+PHY-3002 : Step(66): len = 349617, overlap = 453.281
+PHY-3002 : Step(67): len = 366049, overlap = 416.531
+PHY-3002 : Step(68): len = 373418, overlap = 392.781
+PHY-3002 : Step(69): len = 375889, overlap = 380.438
+PHY-3002 : Step(70): len = 372061, overlap = 370.25
+PHY-3002 : Step(71): len = 373476, overlap = 356.219
+PHY-3002 : Step(72): len = 373030, overlap = 344
+PHY-3002 : Step(73): len = 373480, overlap = 335.844
+PHY-3002 : Step(74): len = 372656, overlap = 319.875
+PHY-3002 : Step(75): len = 374122, overlap = 316.062
+PHY-3002 : Step(76): len = 375955, overlap = 322.344
+PHY-3002 : Step(77): len = 375870, overlap = 335.219
+PHY-3002 : Step(78): len = 376154, overlap = 337.594
+PHY-3002 : Step(79): len = 377362, overlap = 337.719
+PHY-3002 : Step(80): len = 378436, overlap = 319.125
+PHY-3002 : Step(81): len = 378624, overlap = 326.312
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.40924e-05
+PHY-3002 : Step(82): len = 396463, overlap = 291.562
+PHY-3002 : Step(83): len = 407616, overlap = 272.562
+PHY-3002 : Step(84): len = 406622, overlap = 266.875
+PHY-3002 : Step(85): len = 408744, overlap = 251.906
+PHY-3002 : Step(86): len = 410618, overlap = 246.906
+PHY-3002 : Step(87): len = 412387, overlap = 247.781
+PHY-3002 : Step(88): len = 409551, overlap = 261.375
+PHY-3002 : Step(89): len = 409749, overlap = 270.25
+PHY-3002 : Step(90): len = 412128, overlap = 268.688
+PHY-3002 : Step(91): len = 414571, overlap = 268.094
+PHY-3002 : Step(92): len = 411230, overlap = 270.156
+PHY-3002 : Step(93): len = 411916, overlap = 273.562
+PHY-3002 : Step(94): len = 414289, overlap = 255.812
+PHY-3002 : Step(95): len = 416545, overlap = 259.688
+PHY-3002 : Step(96): len = 413414, overlap = 257.625
+PHY-3002 : Step(97): len = 413758, overlap = 267.781
+PHY-3002 : Step(98): len = 417073, overlap = 247.531
+PHY-3002 : Step(99): len = 419420, overlap = 244.562
+PHY-3002 : Step(100): len = 414958, overlap = 244.438
+PHY-3002 : Step(101): len = 414463, overlap = 247.719
+PHY-3002 : Step(102): len = 415687, overlap = 250.094
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.81847e-05
+PHY-3002 : Step(103): len = 432812, overlap = 246.656
+PHY-3002 : Step(104): len = 441874, overlap = 236.031
+PHY-3002 : Step(105): len = 441906, overlap = 228.344
+PHY-3002 : Step(106): len = 443238, overlap = 210.469
+PHY-3002 : Step(107): len = 446831, overlap = 214.625
+PHY-3002 : Step(108): len = 450615, overlap = 211.438
+PHY-3002 : Step(109): len = 448525, overlap = 214.281
+PHY-3002 : Step(110): len = 450054, overlap = 221.094
+PHY-3002 : Step(111): len = 452106, overlap = 207.844
+PHY-3002 : Step(112): len = 453290, overlap = 205.844
+PHY-3002 : Step(113): len = 451329, overlap = 213.438
+PHY-3002 : Step(114): len = 451100, overlap = 211.938
+PHY-3002 : Step(115): len = 451785, overlap = 204.281
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000176369
+PHY-3002 : Step(116): len = 465284, overlap = 199.562
+PHY-3002 : Step(117): len = 475212, overlap = 203.875
+PHY-3002 : Step(118): len = 477345, overlap = 188.469
+PHY-3002 : Step(119): len = 478472, overlap = 175.75
+PHY-3002 : Step(120): len = 479991, overlap = 168.844
+PHY-3002 : Step(121): len = 481587, overlap = 165.938
+PHY-3002 : Step(122): len = 481059, overlap = 163.812
+PHY-3002 : Step(123): len = 482403, overlap = 162.125
+PHY-3002 : Step(124): len = 483631, overlap = 154.344
+PHY-3002 : Step(125): len = 485866, overlap = 146.406
+PHY-3002 : Step(126): len = 487191, overlap = 145.875
+PHY-3002 : Step(127): len = 488883, overlap = 145.75
+PHY-3002 : Step(128): len = 491035, overlap = 151.156
+PHY-3002 : Step(129): len = 490623, overlap = 151.094
+PHY-3002 : Step(130): len = 490928, overlap = 160.812
+PHY-3002 : Step(131): len = 491146, overlap = 157.75
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000352739
+PHY-3002 : Step(132): len = 499258, overlap = 154.75
+PHY-3002 : Step(133): len = 506641, overlap = 147.031
+PHY-3002 : Step(134): len = 509604, overlap = 140.5
+PHY-3002 : Step(135): len = 510607, overlap = 137.562
+PHY-3002 : Step(136): len = 511513, overlap = 146.688
+PHY-3002 : Step(137): len = 512279, overlap = 145.781
+PHY-3002 : Step(138): len = 511872, overlap = 144.531
+PHY-3002 : Step(139): len = 512195, overlap = 138.844
+PHY-3002 : Step(140): len = 512868, overlap = 137.188
+PHY-3002 : Step(141): len = 513441, overlap = 136.375
+PHY-3002 : Step(142): len = 512914, overlap = 133.719
+PHY-3002 : Step(143): len = 512808, overlap = 133.969
+PHY-3002 : Step(144): len = 513131, overlap = 136
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000681278
+PHY-3002 : Step(145): len = 519594, overlap = 131.531
+PHY-3002 : Step(146): len = 526652, overlap = 127.438
+PHY-3002 : Step(147): len = 529228, overlap = 127.75
+PHY-3002 : Step(148): len = 531558, overlap = 128.188
+PHY-3002 : Step(149): len = 534923, overlap = 131.438
+PHY-3002 : Step(150): len = 540284, overlap = 138.688
+PHY-3002 : Step(151): len = 541375, overlap = 135.719
+PHY-3002 : Step(152): len = 545926, overlap = 134.062
+PHY-3002 : Step(153): len = 549024, overlap = 134.219
+PHY-3002 : Step(154): len = 550619, overlap = 124.938
+PHY-3002 : Step(155): len = 549418, overlap = 133.438
+PHY-3002 : Step(156): len = 547994, overlap = 141.5
+PHY-3002 : Step(157): len = 548105, overlap = 141.625
+PHY-3002 : Step(158): len = 549158, overlap = 142.938
+PHY-3002 : Step(159): len = 549045, overlap = 142.406
+PHY-3002 : Step(160): len = 547722, overlap = 143.938
+PHY-3002 : Step(161): len = 546673, overlap = 146.219
+PHY-3002 : Step(162): len = 546275, overlap = 147.875
+PHY-3002 : Step(163): len = 545875, overlap = 151.656
+PHY-3002 : Step(164): len = 544941, overlap = 141.125
+PHY-3002 : Step(165): len = 545160, overlap = 146.438
+PHY-3002 : Step(166): len = 545594, overlap = 141.5
+PHY-3002 : Step(167): len = 545235, overlap = 142.25
+PHY-3002 : Step(168): len = 543732, overlap = 141.719
+PHY-3002 : Step(169): len = 543471, overlap = 143.812
+PHY-3002 : Step(170): len = 543679, overlap = 144.875
+PHY-3002 : Step(171): len = 543498, overlap = 147.125
+PHY-3002 : Step(172): len = 542140, overlap = 148.469
+PHY-3002 : Step(173): len = 541568, overlap = 152.031
+PHY-3002 : Step(174): len = 541941, overlap = 152.281
+PHY-3002 : Step(175): len = 541967, overlap = 151.688
+PHY-3002 : Step(176): len = 541004, overlap = 155.562
+PHY-3002 : Step(177): len = 540521, overlap = 155.312
+PHY-3002 : Step(178): len = 540449, overlap = 154.031
+PHY-3002 : Step(179): len = 540397, overlap = 154.094
+PHY-3002 : Step(180): len = 539975, overlap = 154.875
+PHY-3002 : Step(181): len = 539873, overlap = 156.188
+PHY-3002 : Step(182): len = 539981, overlap = 150.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00127621
+PHY-3002 : Step(183): len = 543127, overlap = 153.438
+PHY-3002 : Step(184): len = 547113, overlap = 155.594
+PHY-3002 : Step(185): len = 548668, overlap = 152.719
+PHY-3002 : Step(186): len = 549502, overlap = 147.125
+PHY-3002 : Step(187): len = 550078, overlap = 150.594
+PHY-3002 : Step(188): len = 550358, overlap = 150.531
+PHY-3002 : Step(189): len = 550284, overlap = 150.312
+PHY-3002 : Step(190): len = 550456, overlap = 152.531
+PHY-3002 : Step(191): len = 551407, overlap = 152.906
+PHY-3002 : Step(192): len = 552484, overlap = 152.5
+PHY-3002 : Step(193): len = 552394, overlap = 153
+PHY-3002 : Step(194): len = 552381, overlap = 153
+PHY-3002 : Step(195): len = 552593, overlap = 149.344
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00233696
+PHY-3002 : Step(196): len = 554612, overlap = 150.969
+PHY-3002 : Step(197): len = 558324, overlap = 142.219
+PHY-3002 : Step(198): len = 559546, overlap = 140.375
+PHY-3002 : Step(199): len = 560332, overlap = 140.25
+PHY-3002 : Step(200): len = 561158, overlap = 140.25
+PHY-3002 : Step(201): len = 561705, overlap = 141.062
+PHY-3002 : Step(202): len = 561704, overlap = 137.844
+PHY-3002 : Step(203): len = 561743, overlap = 134.031
+PHY-3002 : Step(204): len = 561993, overlap = 135.062
+PHY-3002 : Step(205): len = 562148, overlap = 138.625
+PHY-3002 : Step(206): len = 562082, overlap = 133.031
+PHY-3002 : Step(207): len = 562082, overlap = 133.031
+PHY-3002 : Step(208): len = 562056, overlap = 138.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.015901s wall, 0.000000s user + 0.015625s system = 0.015625s CPU (98.3%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21036.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740512, over cnt = 1641(4%), over = 7611, worst = 32
+PHY-1001 : End global iterations; 0.719713s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (132.4%)
+
+PHY-1001 : Congestion index: top1 = 75.93, top5 = 61.28, top10 = 52.56, top15 = 47.14.
+PHY-3001 : End congestion estimation; 0.963751s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (124.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20858 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.877374s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000141641
+PHY-3002 : Step(209): len = 672397, overlap = 107.312
+PHY-3002 : Step(210): len = 675225, overlap = 97.9688
+PHY-3002 : Step(211): len = 671318, overlap = 87.9688
+PHY-3002 : Step(212): len = 670178, overlap = 81.9062
+PHY-3002 : Step(213): len = 670144, overlap = 72.1562
+PHY-3002 : Step(214): len = 666487, overlap = 67
+PHY-3002 : Step(215): len = 664385, overlap = 63.125
+PHY-3002 : Step(216): len = 660771, overlap = 64.25
+PHY-3002 : Step(217): len = 659410, overlap = 61.9062
+PHY-3002 : Step(218): len = 657500, overlap = 60.9062
+PHY-3002 : Step(219): len = 656446, overlap = 57.2812
+PHY-3002 : Step(220): len = 654436, overlap = 54.75
+PHY-3002 : Step(221): len = 654226, overlap = 55.7188
+PHY-3002 : Step(222): len = 651098, overlap = 54.3125
+PHY-3002 : Step(223): len = 650125, overlap = 49.375
+PHY-3002 : Step(224): len = 647258, overlap = 50.625
+PHY-3002 : Step(225): len = 646303, overlap = 50.6875
+PHY-3002 : Step(226): len = 644125, overlap = 47.2812
+PHY-3002 : Step(227): len = 643032, overlap = 46.75
+PHY-3002 : Step(228): len = 641085, overlap = 46.7188
+PHY-3002 : Step(229): len = 639898, overlap = 44.2812
+PHY-3002 : Step(230): len = 638407, overlap = 44.3125
+PHY-3002 : Step(231): len = 637417, overlap = 38.2812
+PHY-3002 : Step(232): len = 636171, overlap = 38.7188
+PHY-3002 : Step(233): len = 635750, overlap = 36.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000283283
+PHY-3002 : Step(234): len = 637486, overlap = 34.9688
+PHY-3002 : Step(235): len = 641051, overlap = 34.6562
+PHY-3002 : Step(236): len = 647678, overlap = 33.7188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00055775
+PHY-3002 : Step(237): len = 651779, overlap = 32.75
+PHY-3002 : Step(238): len = 665771, overlap = 30.8438
+PHY-3002 : Step(239): len = 683583, overlap = 30.75
+PHY-3002 : Step(240): len = 682253, overlap = 30.75
+PHY-3002 : Step(241): len = 681679, overlap = 29.4375
+PHY-3002 : Step(242): len = 679561, overlap = 28.9062
+PHY-3002 : Step(243): len = 680012, overlap = 28.1875
+PHY-3002 : Step(244): len = 681629, overlap = 27.125
+PHY-3002 : Step(245): len = 683030, overlap = 26.8438
+PHY-3002 : Step(246): len = 683159, overlap = 27.8125
+PHY-3002 : Step(247): len = 683382, overlap = 28.9062
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.0011155
+PHY-3002 : Step(248): len = 687181, overlap = 30.6875
+PHY-3002 : Step(249): len = 695921, overlap = 32.2188
+PHY-3002 : Step(250): len = 706710, overlap = 34.25
+PHY-3002 : Step(251): len = 708522, overlap = 34.1875
+PHY-3002 : Step(252): len = 709553, overlap = 38.0625
+PHY-3002 : Step(253): len = 709239, overlap = 39.1875
+PHY-3002 : Step(254): len = 709548, overlap = 40.5312
+PHY-3002 : Step(255): len = 709941, overlap = 45.25
+PHY-3002 : Step(256): len = 708010, overlap = 47.4062
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00185463
+PHY-3002 : Step(257): len = 710835, overlap = 46.8125
+PHY-3002 : Step(258): len = 718379, overlap = 47.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 56/21036.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 804904, over cnt = 2749(7%), over = 13606, worst = 53
+PHY-1001 : End global iterations; 1.535988s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 101.92, top5 = 75.94, top10 = 64.87, top15 = 58.58.
+PHY-3001 : End congestion estimation; 1.821644s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (128.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20858 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.902181s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124904
+PHY-3002 : Step(259): len = 705641, overlap = 279.719
+PHY-3002 : Step(260): len = 700488, overlap = 213.344
+PHY-3002 : Step(261): len = 687018, overlap = 197.219
+PHY-3002 : Step(262): len = 677934, overlap = 177.125
+PHY-3002 : Step(263): len = 668120, overlap = 165.062
+PHY-3002 : Step(264): len = 661069, overlap = 158.562
+PHY-3002 : Step(265): len = 656907, overlap = 158.688
+PHY-3002 : Step(266): len = 650084, overlap = 150.562
+PHY-3002 : Step(267): len = 647646, overlap = 146.969
+PHY-3002 : Step(268): len = 641838, overlap = 145.5
+PHY-3002 : Step(269): len = 638763, overlap = 145.938
+PHY-3002 : Step(270): len = 634373, overlap = 146.375
+PHY-3002 : Step(271): len = 631559, overlap = 145.469
+PHY-3002 : Step(272): len = 627925, overlap = 149.688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000249808
+PHY-3002 : Step(273): len = 628663, overlap = 146.344
+PHY-3002 : Step(274): len = 631270, overlap = 139.469
+PHY-3002 : Step(275): len = 633666, overlap = 131.094
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000499616
+PHY-3002 : Step(276): len = 639506, overlap = 123.969
+PHY-3002 : Step(277): len = 647065, overlap = 115.156
+PHY-3002 : Step(278): len = 653309, overlap = 111.688
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86808, tnet num: 20858, tinst num: 18456, tnode num: 117558, tedge num: 138662.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.449438s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (100.3%)
+
+RUN-1004 : used memory is 585 MB, reserved memory is 574 MB, peak memory is 723 MB
+OPT-1001 : Total overflow 431.25 peak overflow 5.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 589/21036.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753064, over cnt = 3106(8%), over = 11441, worst = 27
+PHY-1001 : End global iterations; 1.443431s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 74.85, top5 = 59.40, top10 = 52.66, top15 = 48.71.
+PHY-1001 : End incremental global routing; 1.786039s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (132.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20858 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.918926s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (100.3%)
+
+OPT-1001 : 52 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18319 has valid locations, 359 needs to be replaced
+PHY-3001 : design contains 18763 instances, 8103 luts, 9440 seqs, 1074 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6232 pins
+PHY-3001 : Found 1271 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 678691
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17195/21343.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 769448, over cnt = 3130(8%), over = 11484, worst = 27
+PHY-1001 : End global iterations; 0.243210s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (147.8%)
+
+PHY-1001 : Congestion index: top1 = 74.44, top5 = 59.45, top10 = 52.83, top15 = 49.01.
+PHY-3001 : End congestion estimation; 0.500523s wall, 0.609375s user + 0.015625s system = 0.625000s CPU (124.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87997, tnet num: 21165, tinst num: 18763, tnode num: 119364, tedge num: 140426.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.469881s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (101.0%)
+
+RUN-1004 : used memory is 630 MB, reserved memory is 626 MB, peak memory is 728 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21165 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 3.495804s wall, 2.671875s user + 0.078125s system = 2.750000s CPU (78.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(279): len = 677718, overlap = 0.125
+PHY-3002 : Step(280): len = 677515, overlap = 0
+PHY-3002 : Step(281): len = 677416, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17288/21343.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 767824, over cnt = 3131(8%), over = 11533, worst = 27
+PHY-1001 : End global iterations; 0.208282s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (157.5%)
+
+PHY-1001 : Congestion index: top1 = 75.34, top5 = 59.93, top10 = 53.09, top15 = 49.25.
+PHY-3001 : End congestion estimation; 0.469411s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (123.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21165 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.936648s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000369756
+PHY-3002 : Step(282): len = 677026, overlap = 114
+PHY-3002 : Step(283): len = 676991, overlap = 113.031
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000739512
+PHY-3002 : Step(284): len = 677132, overlap = 113.469
+PHY-3002 : Step(285): len = 677652, overlap = 113.031
+PHY-3001 : Final: Len = 677652, Over = 113.031
+PHY-3001 : End incremental placement; 6.060297s wall, 5.656250s user + 0.156250s system = 5.812500s CPU (95.9%)
+
+OPT-1001 : Total overflow 437.19 peak overflow 5.00
+OPT-1001 : End high-fanout net optimization; 9.317730s wall, 9.531250s user + 0.203125s system = 9.734375s CPU (104.5%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 725, peak = 746.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17257/21343.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 769704, over cnt = 3084(8%), over = 10481, worst = 27
+PHY-1002 : len = 824016, over cnt = 2282(6%), over = 5652, worst = 26
+PHY-1002 : len = 866176, over cnt = 1059(3%), over = 2378, worst = 26
+PHY-1002 : len = 898856, over cnt = 223(0%), over = 402, worst = 13
+PHY-1002 : len = 908144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.694390s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (144.8%)
+
+PHY-1001 : Congestion index: top1 = 59.68, top5 = 52.92, top10 = 48.93, top15 = 46.38.
+OPT-1001 : End congestion update; 1.958421s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (138.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21165 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.809578s wall, 0.765625s user + 0.046875s system = 0.812500s CPU (100.4%)
+
+OPT-0007 : Start: WNS -1076 TNS -2072 NUM_FEPS 5
+OPT-0007 : Iter 1: improved WNS -576 TNS -1436 NUM_FEPS 5 with 107 cells processed and 16300 slack improved
+OPT-0007 : Iter 2: improved WNS -576 TNS -1436 NUM_FEPS 5 with 21 cells processed and 3550 slack improved
+OPT-0007 : Iter 3: improved WNS -576 TNS -1436 NUM_FEPS 5 with 8 cells processed and 500 slack improved
+OPT-0007 : Iter 4: improved WNS -576 TNS -1436 NUM_FEPS 5 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.246837s wall, 3.953125s user + 0.046875s system = 4.000000s CPU (123.2%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 703, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17355/21344.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910280, over cnt = 123(0%), over = 199, worst = 9
+PHY-1002 : len = 909728, over cnt = 103(0%), over = 131, worst = 5
+PHY-1002 : len = 910360, over cnt = 49(0%), over = 55, worst = 3
+PHY-1002 : len = 911152, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 911872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.772524s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (107.2%)
+
+PHY-1001 : Congestion index: top1 = 59.72, top5 = 53.22, top10 = 49.07, top15 = 46.51.
+OPT-1001 : End congestion update; 1.049200s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (105.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21166 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.820122s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.1%)
+
+OPT-0007 : Start: WNS -576 TNS -1436 NUM_FEPS 5
+OPT-0007 : Iter 1: improved WNS -576 TNS -1436 NUM_FEPS 5 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.899771s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (102.8%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 712, peak = 746.
+OPT-1001 : End physical optimization; 16.230649s wall, 17.234375s user + 0.312500s system = 17.546875s CPU (108.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8103 LUT to BLE ...
+SYN-4008 : Packed 8103 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6293 remaining SEQ's ...
+SYN-4005 : Packed 4225 SEQ with LUT/SLICE
+SYN-4006 : 1024 single LUT's are left
+SYN-4006 : 2068 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10171/13957 primitive instances ...
+PHY-3001 : End packing; 1.735649s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6914 instances
+RUN-1001 : 3383 mslices, 3383 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18302 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9930 nets have 2 pins
+RUN-1001 : 6918 nets have [3 - 5] pins
+RUN-1001 : 764 nets have [6 - 10] pins
+RUN-1001 : 331 nets have [11 - 20] pins
+RUN-1001 : 327 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6912 instances, 6766 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3666 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 693881, Over = 267.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7982/18302.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856368, over cnt = 2078(5%), over = 3431, worst = 8
+PHY-1002 : len = 863808, over cnt = 1336(3%), over = 1961, worst = 8
+PHY-1002 : len = 879344, over cnt = 526(1%), over = 740, worst = 7
+PHY-1002 : len = 887248, over cnt = 200(0%), over = 271, worst = 6
+PHY-1002 : len = 892960, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.690954s wall, 2.484375s user + 0.078125s system = 2.562500s CPU (151.5%)
+
+PHY-1001 : Congestion index: top1 = 60.32, top5 = 52.71, top10 = 48.36, top15 = 45.69.
+PHY-3001 : End congestion estimation; 2.116496s wall, 2.890625s user + 0.078125s system = 2.968750s CPU (140.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75120, tnet num: 18124, tinst num: 6912, tnode num: 98029, tedge num: 125137.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.644010s wall, 1.609375s user + 0.046875s system = 1.656250s CPU (100.7%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 627 MB, peak memory is 746 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18124 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.539556s wall, 2.468750s user + 0.078125s system = 2.546875s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.18424e-05
+PHY-3002 : Step(286): len = 679494, overlap = 266
+PHY-3002 : Step(287): len = 673460, overlap = 263
+PHY-3002 : Step(288): len = 669652, overlap = 263
+PHY-3002 : Step(289): len = 666518, overlap = 259
+PHY-3002 : Step(290): len = 663563, overlap = 259.25
+PHY-3002 : Step(291): len = 662154, overlap = 265.25
+PHY-3002 : Step(292): len = 660528, overlap = 268
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103685
+PHY-3002 : Step(293): len = 662699, overlap = 259
+PHY-3002 : Step(294): len = 666655, overlap = 253.5
+PHY-3002 : Step(295): len = 667983, overlap = 253.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00020737
+PHY-3002 : Step(296): len = 676829, overlap = 243.75
+PHY-3002 : Step(297): len = 687518, overlap = 233
+PHY-3002 : Step(298): len = 686883, overlap = 230.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.363353s wall, 0.328125s user + 0.531250s system = 0.859375s CPU (236.5%)
+
+PHY-3001 : Trial Legalized: Len = 775588
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 1068/18302.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898208, over cnt = 2952(8%), over = 4951, worst = 8
+PHY-1002 : len = 913240, over cnt = 2043(5%), over = 3097, worst = 8
+PHY-1002 : len = 940744, over cnt = 847(2%), over = 1206, worst = 6
+PHY-1002 : len = 952536, over cnt = 315(0%), over = 444, worst = 6
+PHY-1002 : len = 961560, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.354415s wall, 3.421875s user + 0.015625s system = 3.437500s CPU (146.0%)
+
+PHY-1001 : Congestion index: top1 = 57.35, top5 = 51.96, top10 = 49.08, top15 = 47.12.
+PHY-3001 : End congestion estimation; 2.827751s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (138.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18124 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.898260s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000179896
+PHY-3002 : Step(299): len = 745041, overlap = 51.25
+PHY-3002 : Step(300): len = 728900, overlap = 70
+PHY-3002 : Step(301): len = 715207, overlap = 106.25
+PHY-3002 : Step(302): len = 706413, overlap = 135.75
+PHY-3002 : Step(303): len = 701455, overlap = 158.5
+PHY-3002 : Step(304): len = 699217, overlap = 166.25
+PHY-3002 : Step(305): len = 697985, overlap = 171
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000359793
+PHY-3002 : Step(306): len = 703870, overlap = 165.25
+PHY-3002 : Step(307): len = 711160, overlap = 158.5
+PHY-3002 : Step(308): len = 715700, overlap = 159.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000719585
+PHY-3002 : Step(309): len = 719569, overlap = 157.75
+PHY-3002 : Step(310): len = 732279, overlap = 155.5
+PHY-3002 : Step(311): len = 738580, overlap = 156.25
+PHY-3002 : Step(312): len = 736065, overlap = 157.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.036584s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (85.4%)
+
+PHY-3001 : Legalized: Len = 765168, Over = 0
+PHY-3001 : Spreading special nets. 478 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.117888s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (106.0%)
+
+PHY-3001 : 706 instances has been re-located, deltaX = 255, deltaY = 410, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 777134, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75120, tnet num: 18124, tinst num: 6915, tnode num: 98029, tedge num: 125137.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.889430s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (100.1%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 662 MB, peak memory is 746 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3514/18302.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912504, over cnt = 2795(7%), over = 4541, worst = 8
+PHY-1002 : len = 929952, over cnt = 1579(4%), over = 2172, worst = 6
+PHY-1002 : len = 943080, over cnt = 791(2%), over = 1067, worst = 6
+PHY-1002 : len = 952224, over cnt = 364(1%), over = 491, worst = 6
+PHY-1002 : len = 960784, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.242655s wall, 3.375000s user + 0.062500s system = 3.437500s CPU (153.3%)
+
+PHY-1001 : Congestion index: top1 = 55.50, top5 = 50.15, top10 = 47.46, top15 = 45.63.
+PHY-1001 : End incremental global routing; 2.625370s wall, 3.765625s user + 0.062500s system = 3.828125s CPU (145.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18124 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.889436s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6823 has valid locations, 22 needs to be replaced
+PHY-3001 : design contains 6933 instances, 6784 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3736 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 781828
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16766/18316.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 966648, over cnt = 75(0%), over = 105, worst = 5
+PHY-1002 : len = 966824, over cnt = 35(0%), over = 39, worst = 2
+PHY-1002 : len = 967112, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 967256, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 967352, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.844699s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (109.1%)
+
+PHY-1001 : Congestion index: top1 = 55.39, top5 = 50.24, top10 = 47.57, top15 = 45.75.
+PHY-3001 : End congestion estimation; 1.170244s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (106.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75324, tnet num: 18138, tinst num: 6933, tnode num: 98272, tedge num: 125380.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.889651s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.1%)
+
+RUN-1004 : used memory is 671 MB, reserved memory is 673 MB, peak memory is 746 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18138 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.837201s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(313): len = 780838, overlap = 0
+PHY-3002 : Step(314): len = 780229, overlap = 0
+PHY-3002 : Step(315): len = 779739, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16748/18316.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 963648, over cnt = 61(0%), over = 68, worst = 3
+PHY-1002 : len = 963648, over cnt = 33(0%), over = 34, worst = 2
+PHY-1002 : len = 963896, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 964032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.618314s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (108.7%)
+
+PHY-1001 : Congestion index: top1 = 55.11, top5 = 50.08, top10 = 47.44, top15 = 45.64.
+PHY-3001 : End congestion estimation; 0.941439s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (106.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18138 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.880687s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000913284
+PHY-3002 : Step(316): len = 779635, overlap = 1.5
+PHY-3002 : Step(317): len = 779607, overlap = 2.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005558s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 779818, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060638s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.1%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 779860, Over = 0
+PHY-3001 : End incremental placement; 6.332245s wall, 6.453125s user + 0.125000s system = 6.578125s CPU (103.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.389762s wall, 11.656250s user + 0.187500s system = 11.843750s CPU (114.0%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 759, peak = 758.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16734/18316.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 964808, over cnt = 51(0%), over = 67, worst = 4
+PHY-1002 : len = 965128, over cnt = 27(0%), over = 27, worst = 1
+PHY-1002 : len = 965336, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 965408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.635015s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 55.22, top5 = 50.13, top10 = 47.46, top15 = 45.68.
+OPT-1001 : End congestion update; 0.958531s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (104.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18138 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.731693s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.2%)
+
+OPT-0007 : Start: WNS -1024 TNS -2947 NUM_FEPS 10
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6845 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6933 instances, 6784 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3736 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 783039, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064166s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.4%)
+
+PHY-3001 : 22 instances has been re-located, deltaX = 10, deltaY = 21, maxDist = 3.
+PHY-3001 : Final: Len = 783541, Over = 0
+PHY-3001 : End incremental legalization; 0.394896s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (118.7%)
+
+OPT-0007 : Iter 1: improved WNS -624 TNS -1614 NUM_FEPS 6 with 34 cells processed and 8292 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6845 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6933 instances, 6784 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3736 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 784865, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061481s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 8, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 785151, Over = 0
+PHY-3001 : End incremental legalization; 0.396693s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.1%)
+
+OPT-0007 : Iter 2: improved WNS -524 TNS -1514 NUM_FEPS 6 with 18 cells processed and 5300 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6845 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6933 instances, 6784 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3736 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 787265, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064799s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.5%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 14, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 787649, Over = 0
+PHY-3001 : End incremental legalization; 0.395977s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.3%)
+
+OPT-0007 : Iter 3: improved WNS -524 TNS -1514 NUM_FEPS 6 with 13 cells processed and 3100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6845 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6933 instances, 6784 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3736 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 787853, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061293s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.0%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 6, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 788049, Over = 0
+PHY-3001 : End incremental legalization; 0.389935s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.2%)
+
+OPT-0007 : Iter 4: improved WNS -524 TNS -1514 NUM_FEPS 6 with 8 cells processed and 900 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3737 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 789223, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065690s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.1%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 3, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 789435, Over = 0
+PHY-3001 : End incremental legalization; 0.411848s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (110.0%)
+
+OPT-0007 : Iter 5: improved WNS -524 TNS -1514 NUM_FEPS 6 with 2 cells processed and 706 slack improved
+OPT-1001 : End bottleneck based optimization; 4.386063s wall, 4.671875s user + 0.015625s system = 4.687500s CPU (106.9%)
+
+OPT-1001 : Current memory(MB): used = 755, reserve = 759, peak = 758.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16503/18318.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 974896, over cnt = 138(0%), over = 180, worst = 4
+PHY-1002 : len = 974952, over cnt = 66(0%), over = 73, worst = 3
+PHY-1002 : len = 975336, over cnt = 30(0%), over = 32, worst = 2
+PHY-1002 : len = 975608, over cnt = 13(0%), over = 14, worst = 2
+PHY-1002 : len = 976096, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.866536s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (106.4%)
+
+PHY-1001 : Congestion index: top1 = 55.15, top5 = 49.99, top10 = 47.40, top15 = 45.62.
+OPT-1001 : End congestion update; 1.195970s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (104.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18139 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.736562s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.8%)
+
+OPT-0007 : Start: WNS -524 TNS -1514 NUM_FEPS 6
+OPT-0007 : Iter 1: improved WNS -524 TNS -1514 NUM_FEPS 6 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.971350s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (103.0%)
+
+OPT-1001 : Current memory(MB): used = 755, reserve = 759, peak = 758.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18139 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.742664s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16782/18318.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 976096, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.147940s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.1%)
+
+PHY-1001 : Congestion index: top1 = 55.15, top5 = 49.99, top10 = 47.40, top15 = 45.62.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18139 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.740784s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -524 TNS -1514 NUM_FEPS 6
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 54.689655
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -524ps with logic level 5
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 18318 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18318 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3737 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 789435, Over = 0
+PHY-3001 : End spreading; 0.060710s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.9%)
+
+PHY-3001 : Final: Len = 789435, Over = 0
+PHY-3001 : End incremental legalization; 0.386920s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18139 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.730016s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.6%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16782/18318.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 976096, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.140515s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 55.15, top5 = 49.99, top10 = 47.40, top15 = 45.62.
+OPT-1001 : End congestion update; 0.468230s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (100.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18139 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.733457s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%)
+
+OPT-0007 : Start: WNS -524 TNS -1514 NUM_FEPS 6
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3737 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 794829, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063235s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.8%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 11, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 795095, Over = 0
+PHY-3001 : End incremental legalization; 0.390939s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.9%)
+
+OPT-0007 : Iter 1: improved WNS -524 TNS -524 NUM_FEPS 1 with 26 cells processed and 6750 slack improved
+OPT-0007 : Iter 2: improved WNS -524 TNS -524 NUM_FEPS 1 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.785898s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (99.7%)
+
+OPT-1001 : Current memory(MB): used = 755, reserve = 759, peak = 758.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16673/18318.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 980984, over cnt = 126(0%), over = 148, worst = 5
+PHY-1002 : len = 980976, over cnt = 77(0%), over = 83, worst = 2
+PHY-1002 : len = 981856, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 981896, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.683281s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 55.50, top5 = 50.29, top10 = 47.59, top15 = 45.80.
+OPT-1001 : End congestion update; 1.012267s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (101.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18139 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.733829s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%)
+
+OPT-0007 : Start: WNS -624 TNS -642 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3737 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 795081, Over = 0
+PHY-3001 : End spreading; 0.060424s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.4%)
+
+PHY-3001 : Final: Len = 795081, Over = 0
+PHY-3001 : End incremental legalization; 0.428465s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (113.0%)
+
+OPT-0007 : Iter 1: improved WNS -524 TNS -542 NUM_FEPS 2 with 2 cells processed and 150 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3737 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 795169, Over = 0
+PHY-3001 : End spreading; 0.060380s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.5%)
+
+PHY-3001 : Final: Len = 795169, Over = 0
+PHY-3001 : End incremental legalization; 0.426916s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (120.8%)
+
+OPT-0007 : Iter 2: improved WNS -424 TNS -442 NUM_FEPS 2 with 1 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3737 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 795127, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060355s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.6%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 795281, Over = 0
+PHY-3001 : End incremental legalization; 0.421046s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.2%)
+
+OPT-0007 : Iter 3: improved WNS -424 TNS -442 NUM_FEPS 2 with 4 cells processed and 74 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3737 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 795179, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064809s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 795281, Over = 0
+PHY-3001 : End incremental legalization; 0.433924s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (118.8%)
+
+OPT-0007 : Iter 4: improved WNS -424 TNS -442 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6850 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6938 instances, 6789 slices, 222 macros(1074 instances: 700 mslices 374 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3741 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 795506, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061202s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.1%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 795536, Over = 0
+PHY-3001 : End incremental legalization; 0.401512s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (109.0%)
+
+OPT-0007 : Iter 5: improved WNS -424 TNS -424 NUM_FEPS 1 with 2 cells processed and 200 slack improved
+OPT-0007 : Iter 6: improved WNS -424 TNS -424 NUM_FEPS 1 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 4.716726s wall, 4.984375s user + 0.000000s system = 4.984375s CPU (105.7%)
+
+OPT-1001 : Current memory(MB): used = 756, reserve = 761, peak = 759.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18142 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.749088s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 756, reserve = 761, peak = 759.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18142 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.769562s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.5%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16743/18321.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 982336, over cnt = 23(0%), over = 37, worst = 6
+PHY-1002 : len = 982480, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 982584, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 982616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.656198s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (100.0%)
+
+PHY-1001 : Congestion index: top1 = 55.78, top5 = 50.37, top10 = 47.64, top15 = 45.85.
+RUN-1001 : End congestion update; 0.990110s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.4%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.763359s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 756, reserve = 761, peak = 759.
+OPT-1001 : End physical optimization; 31.266248s wall, 33.109375s user + 0.234375s system = 33.343750s CPU (106.6%)
+
+RUN-1003 : finish command "place" in 78.508863s wall, 108.609375s user + 6.437500s system = 115.046875s CPU (146.5%)
+
+RUN-1004 : used memory is 666 MB, reserved memory is 659 MB, peak memory is 759 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.716288s wall, 2.968750s user + 0.031250s system = 3.000000s CPU (174.8%)
+
+RUN-1004 : used memory is 667 MB, reserved memory is 660 MB, peak memory is 759 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6940 instances
+RUN-1001 : 3383 mslices, 3406 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18321 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9922 nets have 2 pins
+RUN-1001 : 6920 nets have [3 - 5] pins
+RUN-1001 : 770 nets have [6 - 10] pins
+RUN-1001 : 337 nets have [11 - 20] pins
+RUN-1001 : 343 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75374, tnet num: 18143, tinst num: 6938, tnode num: 98342, tedge num: 125450.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.625790s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.0%)
+
+RUN-1004 : used memory is 680 MB, reserved memory is 684 MB, peak memory is 759 MB
+PHY-1001 : 3383 mslices, 3406 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18143 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908896, over cnt = 2932(8%), over = 4891, worst = 9
+PHY-1002 : len = 929232, over cnt = 1746(4%), over = 2530, worst = 9
+PHY-1002 : len = 950024, over cnt = 684(1%), over = 961, worst = 6
+PHY-1002 : len = 963296, over cnt = 55(0%), over = 78, worst = 5
+PHY-1002 : len = 964976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.287428s wall, 4.343750s user + 0.000000s system = 4.343750s CPU (132.1%)
+
+PHY-1001 : Congestion index: top1 = 55.80, top5 = 49.86, top10 = 46.91, top15 = 45.04.
+PHY-1001 : End global routing; 3.627367s wall, 4.671875s user + 0.000000s system = 4.671875s CPU (128.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 730, reserve = 733, peak = 759.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1001, reserve = 1004, peak = 1001.
+PHY-1001 : End build detailed router design. 4.019179s wall, 3.984375s user + 0.031250s system = 4.015625s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 269328, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.140717s wall, 5.140625s user + 0.000000s system = 5.140625s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 269384, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.436178s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1040, peak = 1035.
+PHY-1001 : End phase 1; 5.589930s wall, 5.593750s user + 0.000000s system = 5.593750s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.42494e+06, over cnt = 1796(0%), over = 1803, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1055, peak = 1052.
+PHY-1001 : End initial routed; 31.886412s wall, 64.250000s user + 0.359375s system = 64.609375s CPU (202.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 75/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.960 | -23.459 | 23
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.300254s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1062, reserve = 1068, peak = 1062.
+PHY-1001 : End phase 2; 35.186728s wall, 67.562500s user + 0.359375s system = 67.921875s CPU (193.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 26 pins with SWNS -1.630ns STNS -20.428ns FEP 23.
+PHY-1001 : End OPT Iter 1; 0.228022s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.9%)
+
+PHY-1022 : len = 2.42503e+06, over cnt = 1811(0%), over = 1818, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.504491s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (99.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.39486e+06, over cnt = 717(0%), over = 718, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.196350s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (199.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.39202e+06, over cnt = 111(0%), over = 111, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.693610s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (175.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.39244e+06, over cnt = 28(0%), over = 28, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.339981s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (128.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.39263e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.278847s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (112.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.39268e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.206216s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.39268e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.246009s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.39268e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.410476s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.8%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.3927e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.175840s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (115.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.39267e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.170924s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 75/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.776 | -20.799 | 23
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.336957s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 558 feed throughs used by 413 nets
+PHY-1001 : End commit to database; 2.320429s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1176, peak = 1167.
+PHY-1001 : End phase 3; 10.299591s wall, 12.156250s user + 0.000000s system = 12.156250s CPU (118.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 18 pins with SWNS -1.595ns STNS -20.299ns FEP 23.
+PHY-1001 : End OPT Iter 1; 0.199543s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.8%)
+
+PHY-1022 : len = 2.39267e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.449665s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.595ns, -20.299ns, 23}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3925e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.195994s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (111.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.39245e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.171846s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 75/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.595 | -20.299 | 23
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.317258s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 561 feed throughs used by 416 nets
+PHY-1001 : End commit to database; 2.444757s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1176, reserve = 1185, peak = 1176.
+PHY-1001 : End phase 4; 6.634488s wall, 6.640625s user + 0.015625s system = 6.656250s CPU (100.3%)
+
+PHY-1003 : Routed, final wirelength = 2.39245e+06
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1188, peak = 1178.
+PHY-1001 : End export database. 0.064690s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.6%)
+
+PHY-1001 : End detail routing; 62.196906s wall, 96.406250s user + 0.406250s system = 96.812500s CPU (155.7%)
+
+RUN-1003 : finish command "route" in 68.522203s wall, 103.765625s user + 0.406250s system = 104.171875s CPU (152.0%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1100 MB, peak memory is 1179 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10737 out of 19600 54.78%
+#reg 9621 out of 19600 49.09%
+#le 12752
+ #lut only 3131 out of 12752 24.55%
+ #reg only 2015 out of 12752 15.80%
+ #lut® 7606 out of 12752 59.65%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1834
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1478
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1368
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 945
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/reg6_syn_51.q0 140
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 75
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_279.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_b/u_ADconfig/reg0_syn_149.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P16 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P140 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P35 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P64 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P150 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P169 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P14 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12752 |9711 |1026 |9653 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |525 |420 |23 |436 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |101 |81 |4 |90 |4 |0 |
+| U_ecc_gen |ecc_gen |15 |15 |0 |9 |0 |0 |
+| U_crc16_24b |crc16_24b |36 |36 |0 |22 |0 |0 |
+| exdev_ctl_a |exdev_ctl |778 |440 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |188 |126 |25 |140 |0 |0 |
+| u_gen_sp |gen_sp |277 |165 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |752 |448 |96 |560 |0 |0 |
+| u_ADconfig |AD_config |177 |132 |25 |126 |0 |0 |
+| u_gen_sp |gen_sp |258 |162 |71 |117 |0 |0 |
+| sampling_fe_a |sampling_fe |3172 |2606 |306 |2109 |25 |0 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |176 |132 |17 |145 |0 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_sort |sort |2962 |2468 |289 |1930 |25 |0 |
+| rddpram_ctl |rddpram_ctl |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |3 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2495 |2090 |253 |1573 |22 |0 |
+| channelPart |channel_part_8478 |141 |137 |3 |128 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1957 |1630 |197 |1165 |0 |0 |
+| adc_addr_gen |adc_addr_gen |256 |229 |27 |122 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |29 |26 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |28 |25 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |27 |24 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |30 |27 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| insert |insert |925 |625 |170 |633 |0 |0 |
+| ram_switch_state |ram_switch_state |776 |776 |0 |410 |0 |0 |
+| read_ram_i |read_ram |288 |230 |44 |197 |0 |0 |
+| read_ram_addr |read_ram_addr |238 |198 |40 |158 |0 |0 |
+| read_ram_data |read_ram_data |47 |30 |4 |36 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |330 |257 |36 |270 |3 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3286 |2646 |346 |2131 |25 |1 |
+| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |207 |122 |17 |168 |0 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_sort |sort_rev |3045 |2507 |329 |1929 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |1 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2540 |2099 |287 |1542 |22 |1 |
+| channelPart |channel_part_8478 |197 |194 |3 |139 |0 |0 |
+| fifo_adc |fifo_adc |61 |52 |9 |44 |0 |1 |
+| ram_switch |ram_switch |1899 |1578 |197 |1117 |0 |0 |
+| adc_addr_gen |adc_addr_gen |221 |193 |27 |110 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |7 |0 |0 |
+| insert |insert |994 |703 |170 |670 |0 |0 |
+| ram_switch_state |ram_switch_state |684 |682 |0 |337 |0 |0 |
+| read_ram_i |read_ram_rev |350 |254 |78 |209 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |287 |205 |70 |163 |0 |0 |
+| read_ram_data |read_ram_data_rev |63 |49 |8 |46 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9860
+ #2 2 4448
+ #3 3 1910
+ #4 4 559
+ #5 5-10 821
+ #6 11-50 607
+ #7 51-100 19
+ #8 >500 1
+ Average 2.82
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.123325s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (172.9%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1102 MB, peak memory is 1179 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75374, tnet num: 18143, tinst num: 6938, tnode num: 98342, tedge num: 125450.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.618443s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.4%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1109 MB, peak memory is 1179 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18143 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.489890s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (99.6%)
+
+RUN-1004 : used memory is 1109 MB, reserved memory is 1111 MB, peak memory is 1179 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6938
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18321, pip num: 177672
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 561
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3260 valid insts, and 491719 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.046458s wall, 59.859375s user + 0.250000s system = 60.109375s CPU (598.3%)
+
+RUN-1004 : used memory is 1274 MB, reserved memory is 1276 MB, peak memory is 1389 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_160923.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_161709.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_161709.log
new file mode 100644
index 0000000..10f15e7
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_161709.log
@@ -0,0 +1,2259 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 16:17:09 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_24mhz.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.239945s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (99.8%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 321 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 1.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18443 instances
+RUN-0007 : 7981 luts, 9236 seqs, 705 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21016 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13232 nets have 2 pins
+RUN-1001 : 6674 nets have [3 - 5] pins
+RUN-1001 : 693 nets have [6 - 10] pins
+RUN-1001 : 172 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 59 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 803
+RUN-1001 : No | No | Yes | 1941
+RUN-1001 : No | Yes | No | 3675
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2681
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 77 | 60
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 145
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18441 instances, 7981 luts, 9236 seqs, 1078 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 6083 pins
+PHY-0007 : Cell area utilization is 51%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86804, tnet num: 20838, tinst num: 18441, tnode num: 117580, tedge num: 138676.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.191934s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (99.6%)
+
+RUN-1004 : used memory is 541 MB, reserved memory is 525 MB, peak memory is 541 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20838 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.996051s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.2%)
+
+PHY-3001 : Found 1257 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.32141e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18441.
+PHY-3001 : Level 1 #clusters 2003.
+PHY-3001 : End clustering; 0.135362s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.33022e+06, overlap = 514.062
+PHY-3002 : Step(2): len = 1.25147e+06, overlap = 570.688
+PHY-3002 : Step(3): len = 865883, overlap = 667.781
+PHY-3002 : Step(4): len = 800164, overlap = 731.469
+PHY-3002 : Step(5): len = 600073, overlap = 854.375
+PHY-3002 : Step(6): len = 523482, overlap = 947.531
+PHY-3002 : Step(7): len = 454707, overlap = 1011.5
+PHY-3002 : Step(8): len = 415867, overlap = 1064.31
+PHY-3002 : Step(9): len = 366353, overlap = 1113.69
+PHY-3002 : Step(10): len = 330915, overlap = 1146.81
+PHY-3002 : Step(11): len = 302417, overlap = 1204.91
+PHY-3002 : Step(12): len = 274411, overlap = 1261.97
+PHY-3002 : Step(13): len = 245552, overlap = 1322.62
+PHY-3002 : Step(14): len = 223923, overlap = 1363.72
+PHY-3002 : Step(15): len = 202290, overlap = 1401.78
+PHY-3002 : Step(16): len = 189521, overlap = 1441.84
+PHY-3002 : Step(17): len = 174455, overlap = 1469.47
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.144e-06
+PHY-3002 : Step(18): len = 177697, overlap = 1435.84
+PHY-3002 : Step(19): len = 208023, overlap = 1311.47
+PHY-3002 : Step(20): len = 214876, overlap = 1284.81
+PHY-3002 : Step(21): len = 218251, overlap = 1187.5
+PHY-3002 : Step(22): len = 214511, overlap = 1142.56
+PHY-3002 : Step(23): len = 215244, overlap = 1121.56
+PHY-3002 : Step(24): len = 209773, overlap = 1144.28
+PHY-3002 : Step(25): len = 210022, overlap = 1129.53
+PHY-3002 : Step(26): len = 207977, overlap = 1134.97
+PHY-3002 : Step(27): len = 208480, overlap = 1154
+PHY-3002 : Step(28): len = 204055, overlap = 1181.34
+PHY-3002 : Step(29): len = 203271, overlap = 1175.84
+PHY-3002 : Step(30): len = 200160, overlap = 1182.97
+PHY-3002 : Step(31): len = 200239, overlap = 1166.12
+PHY-3002 : Step(32): len = 198073, overlap = 1152.22
+PHY-3002 : Step(33): len = 197119, overlap = 1160.41
+PHY-3002 : Step(34): len = 195369, overlap = 1173.22
+PHY-3002 : Step(35): len = 195874, overlap = 1155.47
+PHY-3002 : Step(36): len = 194272, overlap = 1168.12
+PHY-3002 : Step(37): len = 193279, overlap = 1203.41
+PHY-3002 : Step(38): len = 190377, overlap = 1209.31
+PHY-3002 : Step(39): len = 189534, overlap = 1202.84
+PHY-3002 : Step(40): len = 187237, overlap = 1182.88
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.288e-06
+PHY-3002 : Step(41): len = 190776, overlap = 1185.81
+PHY-3002 : Step(42): len = 202885, overlap = 1113.94
+PHY-3002 : Step(43): len = 209814, overlap = 1081.94
+PHY-3002 : Step(44): len = 215445, overlap = 1056.19
+PHY-3002 : Step(45): len = 218254, overlap = 1048.84
+PHY-3002 : Step(46): len = 219911, overlap = 1030.72
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.576e-06
+PHY-3002 : Step(47): len = 225305, overlap = 1008.19
+PHY-3002 : Step(48): len = 240238, overlap = 990.688
+PHY-3002 : Step(49): len = 251021, overlap = 916.875
+PHY-3002 : Step(50): len = 260921, overlap = 850.594
+PHY-3002 : Step(51): len = 264851, overlap = 832.906
+PHY-3002 : Step(52): len = 267205, overlap = 822.25
+PHY-3002 : Step(53): len = 266530, overlap = 831.312
+PHY-3002 : Step(54): len = 267403, overlap = 805.875
+PHY-3002 : Step(55): len = 266324, overlap = 804.906
+PHY-3002 : Step(56): len = 264863, overlap = 815.938
+PHY-3002 : Step(57): len = 262337, overlap = 828.781
+PHY-3002 : Step(58): len = 261358, overlap = 844.812
+PHY-3002 : Step(59): len = 259737, overlap = 866.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.152e-06
+PHY-3002 : Step(60): len = 272822, overlap = 816.438
+PHY-3002 : Step(61): len = 298542, overlap = 674.094
+PHY-3002 : Step(62): len = 313796, overlap = 596.562
+PHY-3002 : Step(63): len = 323660, overlap = 553.531
+PHY-3002 : Step(64): len = 324883, overlap = 524.562
+PHY-3002 : Step(65): len = 324732, overlap = 525.656
+PHY-3002 : Step(66): len = 322287, overlap = 531.781
+PHY-3002 : Step(67): len = 321616, overlap = 540.75
+PHY-3002 : Step(68): len = 321077, overlap = 556.75
+PHY-3002 : Step(69): len = 319532, overlap = 567.562
+PHY-3002 : Step(70): len = 319072, overlap = 554.125
+PHY-3002 : Step(71): len = 318150, overlap = 549.281
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.8304e-05
+PHY-3002 : Step(72): len = 336556, overlap = 487.781
+PHY-3002 : Step(73): len = 348982, overlap = 460.781
+PHY-3002 : Step(74): len = 354238, overlap = 450.625
+PHY-3002 : Step(75): len = 357843, overlap = 455.812
+PHY-3002 : Step(76): len = 355197, overlap = 440.625
+PHY-3002 : Step(77): len = 356862, overlap = 440
+PHY-3002 : Step(78): len = 358834, overlap = 426.625
+PHY-3002 : Step(79): len = 360231, overlap = 421.594
+PHY-3002 : Step(80): len = 359171, overlap = 411.75
+PHY-3002 : Step(81): len = 359873, overlap = 411.062
+PHY-3002 : Step(82): len = 359945, overlap = 427.938
+PHY-3002 : Step(83): len = 361055, overlap = 406.062
+PHY-3002 : Step(84): len = 359258, overlap = 401.875
+PHY-3002 : Step(85): len = 359942, overlap = 385.969
+PHY-3002 : Step(86): len = 359756, overlap = 380.906
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.6608e-05
+PHY-3002 : Step(87): len = 380330, overlap = 350.688
+PHY-3002 : Step(88): len = 392637, overlap = 333.75
+PHY-3002 : Step(89): len = 395454, overlap = 317.719
+PHY-3002 : Step(90): len = 398744, overlap = 314.375
+PHY-3002 : Step(91): len = 399375, overlap = 307.625
+PHY-3002 : Step(92): len = 402833, overlap = 293.906
+PHY-3002 : Step(93): len = 402632, overlap = 296.875
+PHY-3002 : Step(94): len = 404625, overlap = 282.531
+PHY-3002 : Step(95): len = 405973, overlap = 265.031
+PHY-3002 : Step(96): len = 409178, overlap = 278.375
+PHY-3002 : Step(97): len = 408683, overlap = 290.062
+PHY-3002 : Step(98): len = 410435, overlap = 287.625
+PHY-3002 : Step(99): len = 409393, overlap = 290.875
+PHY-3002 : Step(100): len = 411282, overlap = 297.469
+PHY-3002 : Step(101): len = 409569, overlap = 293.312
+PHY-3002 : Step(102): len = 411198, overlap = 288.312
+PHY-3002 : Step(103): len = 412241, overlap = 302.438
+PHY-3002 : Step(104): len = 412434, overlap = 299.25
+PHY-3002 : Step(105): len = 411861, overlap = 296.906
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.3216e-05
+PHY-3002 : Step(106): len = 429165, overlap = 265.719
+PHY-3002 : Step(107): len = 439262, overlap = 259.938
+PHY-3002 : Step(108): len = 437282, overlap = 265.312
+PHY-3002 : Step(109): len = 438099, overlap = 258.188
+PHY-3002 : Step(110): len = 440284, overlap = 245.656
+PHY-3002 : Step(111): len = 442645, overlap = 245.062
+PHY-3002 : Step(112): len = 440569, overlap = 239.312
+PHY-3002 : Step(113): len = 441760, overlap = 250.688
+PHY-3002 : Step(114): len = 444520, overlap = 241.062
+PHY-3002 : Step(115): len = 446320, overlap = 231.688
+PHY-3002 : Step(116): len = 443649, overlap = 229.625
+PHY-3002 : Step(117): len = 443744, overlap = 227.406
+PHY-3002 : Step(118): len = 445256, overlap = 232
+PHY-3002 : Step(119): len = 447287, overlap = 228.25
+PHY-3002 : Step(120): len = 445735, overlap = 230.844
+PHY-3002 : Step(121): len = 445766, overlap = 238
+PHY-3002 : Step(122): len = 447453, overlap = 230.969
+PHY-3002 : Step(123): len = 448679, overlap = 229.906
+PHY-3002 : Step(124): len = 446021, overlap = 241.406
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000139506
+PHY-3002 : Step(125): len = 459038, overlap = 235.281
+PHY-3002 : Step(126): len = 467726, overlap = 227.75
+PHY-3002 : Step(127): len = 468654, overlap = 220
+PHY-3002 : Step(128): len = 469368, overlap = 219.531
+PHY-3002 : Step(129): len = 472183, overlap = 206.156
+PHY-3002 : Step(130): len = 475009, overlap = 201.75
+PHY-3002 : Step(131): len = 475111, overlap = 194.094
+PHY-3002 : Step(132): len = 476293, overlap = 195.625
+PHY-3002 : Step(133): len = 477369, overlap = 194.312
+PHY-3002 : Step(134): len = 478732, overlap = 195.375
+PHY-3002 : Step(135): len = 478409, overlap = 196.656
+PHY-3002 : Step(136): len = 479354, overlap = 198.469
+PHY-3002 : Step(137): len = 480960, overlap = 208.438
+PHY-3002 : Step(138): len = 483029, overlap = 204.344
+PHY-3002 : Step(139): len = 482204, overlap = 211.344
+PHY-3002 : Step(140): len = 482234, overlap = 209.062
+PHY-3002 : Step(141): len = 482594, overlap = 204.188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000279011
+PHY-3002 : Step(142): len = 494416, overlap = 193.875
+PHY-3002 : Step(143): len = 502891, overlap = 189.031
+PHY-3002 : Step(144): len = 504615, overlap = 176.188
+PHY-3002 : Step(145): len = 505867, overlap = 167.906
+PHY-3002 : Step(146): len = 508902, overlap = 171.656
+PHY-3002 : Step(147): len = 511274, overlap = 171.969
+PHY-3002 : Step(148): len = 509677, overlap = 169.75
+PHY-3002 : Step(149): len = 509267, overlap = 170.719
+PHY-3002 : Step(150): len = 510557, overlap = 172.125
+PHY-3002 : Step(151): len = 512270, overlap = 168.156
+PHY-3002 : Step(152): len = 510727, overlap = 170.781
+PHY-3002 : Step(153): len = 510717, overlap = 175.656
+PHY-3002 : Step(154): len = 512169, overlap = 167.375
+PHY-3002 : Step(155): len = 513241, overlap = 170.75
+PHY-3002 : Step(156): len = 512502, overlap = 165.875
+PHY-3002 : Step(157): len = 512785, overlap = 168.656
+PHY-3002 : Step(158): len = 514322, overlap = 170.031
+PHY-3002 : Step(159): len = 514724, overlap = 171.062
+PHY-3002 : Step(160): len = 513205, overlap = 169.562
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000517593
+PHY-3002 : Step(161): len = 521142, overlap = 170.812
+PHY-3002 : Step(162): len = 530280, overlap = 160.312
+PHY-3002 : Step(163): len = 532348, overlap = 152.219
+PHY-3002 : Step(164): len = 533556, overlap = 141.625
+PHY-3002 : Step(165): len = 536567, overlap = 147.781
+PHY-3002 : Step(166): len = 539416, overlap = 154.156
+PHY-3002 : Step(167): len = 538835, overlap = 145.031
+PHY-3002 : Step(168): len = 539220, overlap = 142.969
+PHY-3002 : Step(169): len = 541131, overlap = 144.812
+PHY-3002 : Step(170): len = 541770, overlap = 146.125
+PHY-3002 : Step(171): len = 540068, overlap = 142.75
+PHY-3002 : Step(172): len = 539231, overlap = 147.5
+PHY-3002 : Step(173): len = 539681, overlap = 151.344
+PHY-3002 : Step(174): len = 540038, overlap = 151.031
+PHY-3002 : Step(175): len = 538783, overlap = 148.906
+PHY-3002 : Step(176): len = 538392, overlap = 148.812
+PHY-3002 : Step(177): len = 539339, overlap = 148.781
+PHY-3002 : Step(178): len = 540020, overlap = 142.156
+PHY-3002 : Step(179): len = 539013, overlap = 141.25
+PHY-3002 : Step(180): len = 538675, overlap = 141.562
+PHY-3002 : Step(181): len = 539279, overlap = 139.938
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00103028
+PHY-3002 : Step(182): len = 545283, overlap = 139.406
+PHY-3002 : Step(183): len = 551259, overlap = 140.375
+PHY-3002 : Step(184): len = 554775, overlap = 130.281
+PHY-3002 : Step(185): len = 557064, overlap = 127.375
+PHY-3002 : Step(186): len = 557872, overlap = 120.25
+PHY-3002 : Step(187): len = 558191, overlap = 122.906
+PHY-3002 : Step(188): len = 557567, overlap = 123.594
+PHY-3002 : Step(189): len = 557483, overlap = 122.719
+PHY-3002 : Step(190): len = 558349, overlap = 125.281
+PHY-3002 : Step(191): len = 558697, overlap = 126.469
+PHY-3002 : Step(192): len = 558611, overlap = 123.844
+PHY-3002 : Step(193): len = 558719, overlap = 120.906
+PHY-3002 : Step(194): len = 558954, overlap = 127.344
+PHY-3002 : Step(195): len = 559061, overlap = 127.906
+PHY-3002 : Step(196): len = 558919, overlap = 124.812
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.001667
+PHY-3002 : Step(197): len = 561017, overlap = 128.094
+PHY-3002 : Step(198): len = 562693, overlap = 124.938
+PHY-3002 : Step(199): len = 563670, overlap = 123.562
+PHY-3002 : Step(200): len = 564093, overlap = 122.688
+PHY-3002 : Step(201): len = 564705, overlap = 126.375
+PHY-3002 : Step(202): len = 565062, overlap = 125.75
+PHY-3002 : Step(203): len = 565740, overlap = 121.25
+PHY-3002 : Step(204): len = 566333, overlap = 121.219
+PHY-3002 : Step(205): len = 566704, overlap = 122.75
+PHY-3002 : Step(206): len = 566704, overlap = 122.75
+PHY-3002 : Step(207): len = 566931, overlap = 121.938
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.014660s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (106.6%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21016.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740984, over cnt = 1622(4%), over = 7766, worst = 58
+PHY-1001 : End global iterations; 0.715206s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (139.8%)
+
+PHY-1001 : Congestion index: top1 = 79.46, top5 = 61.17, top10 = 52.76, top15 = 47.30.
+PHY-3001 : End congestion estimation; 0.949829s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (128.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20838 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.866063s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000140974
+PHY-3002 : Step(208): len = 676573, overlap = 69.7812
+PHY-3002 : Step(209): len = 685387, overlap = 62.6875
+PHY-3002 : Step(210): len = 680311, overlap = 64.2188
+PHY-3002 : Step(211): len = 676683, overlap = 60
+PHY-3002 : Step(212): len = 672542, overlap = 53.1562
+PHY-3002 : Step(213): len = 670354, overlap = 54.9688
+PHY-3002 : Step(214): len = 667191, overlap = 48.375
+PHY-3002 : Step(215): len = 664747, overlap = 41.8125
+PHY-3002 : Step(216): len = 662204, overlap = 42.875
+PHY-3002 : Step(217): len = 659075, overlap = 40.75
+PHY-3002 : Step(218): len = 655758, overlap = 40.75
+PHY-3002 : Step(219): len = 653974, overlap = 38.4688
+PHY-3002 : Step(220): len = 652478, overlap = 41.3438
+PHY-3002 : Step(221): len = 652015, overlap = 41.25
+PHY-3002 : Step(222): len = 650139, overlap = 40.25
+PHY-3002 : Step(223): len = 650139, overlap = 39.6562
+PHY-3002 : Step(224): len = 648244, overlap = 40.3125
+PHY-3002 : Step(225): len = 646873, overlap = 39.2812
+PHY-3002 : Step(226): len = 643714, overlap = 41.75
+PHY-3002 : Step(227): len = 641413, overlap = 42.125
+PHY-3002 : Step(228): len = 640207, overlap = 44.8438
+PHY-3002 : Step(229): len = 638344, overlap = 47.1562
+PHY-3002 : Step(230): len = 637498, overlap = 48.5938
+PHY-3002 : Step(231): len = 635501, overlap = 51.4375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000281947
+PHY-3002 : Step(232): len = 637717, overlap = 50.375
+PHY-3002 : Step(233): len = 640495, overlap = 50.6875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000462262
+PHY-3002 : Step(234): len = 644030, overlap = 47.875
+PHY-3002 : Step(235): len = 647482, overlap = 47.875
+PHY-3002 : Step(236): len = 657611, overlap = 44.7812
+PHY-3002 : Step(237): len = 668026, overlap = 44.6875
+PHY-3002 : Step(238): len = 671288, overlap = 43.9062
+PHY-3002 : Step(239): len = 674417, overlap = 45.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 60/21016.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 764360, over cnt = 2741(7%), over = 13028, worst = 41
+PHY-1001 : End global iterations; 1.639646s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (129.6%)
+
+PHY-1001 : Congestion index: top1 = 88.88, top5 = 70.23, top10 = 61.72, top15 = 56.10.
+PHY-3001 : End congestion estimation; 1.915059s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (124.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20838 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.944813s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000102481
+PHY-3002 : Step(240): len = 667525, overlap = 316.5
+PHY-3002 : Step(241): len = 668350, overlap = 243.156
+PHY-3002 : Step(242): len = 660578, overlap = 230.438
+PHY-3002 : Step(243): len = 654125, overlap = 213.281
+PHY-3002 : Step(244): len = 650498, overlap = 198.188
+PHY-3002 : Step(245): len = 645028, overlap = 184.969
+PHY-3002 : Step(246): len = 642688, overlap = 173.5
+PHY-3002 : Step(247): len = 639828, overlap = 159.656
+PHY-3002 : Step(248): len = 637277, overlap = 151.281
+PHY-3002 : Step(249): len = 633879, overlap = 145.531
+PHY-3002 : Step(250): len = 632128, overlap = 148.125
+PHY-3002 : Step(251): len = 628717, overlap = 149.562
+PHY-3002 : Step(252): len = 625670, overlap = 153.688
+PHY-3002 : Step(253): len = 624123, overlap = 151.719
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000204962
+PHY-3002 : Step(254): len = 624054, overlap = 149.594
+PHY-3002 : Step(255): len = 625707, overlap = 145.125
+PHY-3002 : Step(256): len = 628236, overlap = 143.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000409924
+PHY-3002 : Step(257): len = 634244, overlap = 134.812
+PHY-3002 : Step(258): len = 640726, overlap = 125.156
+PHY-3002 : Step(259): len = 644500, overlap = 112.062
+PHY-3002 : Step(260): len = 645318, overlap = 107.531
+PHY-3002 : Step(261): len = 645895, overlap = 105.531
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86804, tnet num: 20838, tinst num: 18441, tnode num: 117580, tedge num: 138676.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.450115s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (100.2%)
+
+RUN-1004 : used memory is 585 MB, reserved memory is 575 MB, peak memory is 723 MB
+OPT-1001 : Total overflow 444.94 peak overflow 4.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 654/21016.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744448, over cnt = 3137(8%), over = 11813, worst = 22
+PHY-1001 : End global iterations; 1.356906s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (134.7%)
+
+PHY-1001 : Congestion index: top1 = 74.59, top5 = 59.35, top10 = 52.90, top15 = 49.04.
+PHY-1001 : End incremental global routing; 1.693266s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (128.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20838 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.917911s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (98.7%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18305 has valid locations, 349 needs to be replaced
+PHY-3001 : design contains 18739 instances, 8073 luts, 9442 seqs, 1078 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 6210 pins
+PHY-3001 : Found 1272 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 671611
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17136/21314.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 759736, over cnt = 3180(9%), over = 11799, worst = 23
+PHY-1001 : End global iterations; 0.235082s wall, 0.359375s user + 0.031250s system = 0.390625s CPU (166.2%)
+
+PHY-1001 : Congestion index: top1 = 74.70, top5 = 59.66, top10 = 53.36, top15 = 49.49.
+PHY-3001 : End congestion estimation; 0.501126s wall, 0.609375s user + 0.031250s system = 0.640625s CPU (127.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87952, tnet num: 21136, tinst num: 18739, tnode num: 119336, tedge num: 140376.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.458211s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.7%)
+
+RUN-1004 : used memory is 630 MB, reserved memory is 638 MB, peak memory is 728 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21136 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.413086s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(262): len = 670826, overlap = 0.125
+PHY-3002 : Step(263): len = 670538, overlap = 0.125
+PHY-3002 : Step(264): len = 670325, overlap = 0.125
+PHY-3002 : Step(265): len = 670161, overlap = 0.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17237/21314.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 758080, over cnt = 3207(9%), over = 11911, worst = 22
+PHY-1001 : End global iterations; 0.195440s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (135.9%)
+
+PHY-1001 : Congestion index: top1 = 74.74, top5 = 59.81, top10 = 53.45, top15 = 49.60.
+PHY-3001 : End congestion estimation; 0.447651s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (115.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21136 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.938210s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000270336
+PHY-3002 : Step(266): len = 669998, overlap = 107.906
+PHY-3002 : Step(267): len = 669940, overlap = 107.719
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000540672
+PHY-3002 : Step(268): len = 669977, overlap = 108
+PHY-3002 : Step(269): len = 670469, overlap = 107.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00105464
+PHY-3002 : Step(270): len = 670738, overlap = 106.719
+PHY-3002 : Step(271): len = 671445, overlap = 106.719
+PHY-3001 : Final: Len = 671445, Over = 106.719
+PHY-3001 : End incremental placement; 5.112824s wall, 5.296875s user + 0.281250s system = 5.578125s CPU (109.1%)
+
+OPT-1001 : Total overflow 449.34 peak overflow 4.00
+OPT-1001 : End high-fanout net optimization; 8.272398s wall, 8.984375s user + 0.296875s system = 9.281250s CPU (112.2%)
+
+OPT-1001 : Current memory(MB): used = 730, reserve = 725, peak = 747.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17163/21314.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 762360, over cnt = 3113(8%), over = 10679, worst = 22
+PHY-1002 : len = 816344, over cnt = 2229(6%), over = 5637, worst = 21
+PHY-1002 : len = 864992, over cnt = 944(2%), over = 2102, worst = 16
+PHY-1002 : len = 894104, over cnt = 126(0%), over = 180, worst = 8
+PHY-1002 : len = 897280, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations; 1.835793s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (138.7%)
+
+PHY-1001 : Congestion index: top1 = 58.94, top5 = 51.73, top10 = 47.96, top15 = 45.62.
+OPT-1001 : End congestion update; 2.097226s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (133.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21136 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.808067s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (100.5%)
+
+OPT-0007 : Start: WNS -1326 TNS -1631 NUM_FEPS 6
+OPT-0007 : Iter 1: improved WNS -726 TNS -726 NUM_FEPS 1 with 123 cells processed and 18950 slack improved
+OPT-0007 : Iter 2: improved WNS -726 TNS -726 NUM_FEPS 1 with 16 cells processed and 800 slack improved
+OPT-0007 : Iter 3: improved WNS -726 TNS -726 NUM_FEPS 1 with 1 cells processed and 300 slack improved
+OPT-1001 : End bottleneck based optimization; 3.293521s wall, 3.968750s user + 0.015625s system = 3.984375s CPU (121.0%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 704, peak = 747.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17314/21315.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899792, over cnt = 131(0%), over = 196, worst = 6
+PHY-1002 : len = 899520, over cnt = 101(0%), over = 117, worst = 3
+PHY-1002 : len = 900368, over cnt = 40(0%), over = 44, worst = 3
+PHY-1002 : len = 901064, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 901304, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.756402s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.2%)
+
+PHY-1001 : Congestion index: top1 = 59.29, top5 = 52.10, top10 = 48.29, top15 = 45.89.
+OPT-1001 : End congestion update; 1.028085s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (101.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21137 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.826990s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.1%)
+
+OPT-0007 : Start: WNS -726 TNS -726 NUM_FEPS 1
+OPT-0007 : Iter 1: improved WNS -726 TNS -726 NUM_FEPS 1 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.889950s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (100.9%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 711, peak = 747.
+OPT-1001 : End physical optimization; 15.235725s wall, 16.687500s user + 0.359375s system = 17.046875s CPU (111.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 8073 LUT to BLE ...
+SYN-4008 : Packed 8073 LUT and 3135 SEQ to BLE.
+SYN-4003 : Packing 6308 remaining SEQ's ...
+SYN-4005 : Packed 4203 SEQ with LUT/SLICE
+SYN-4006 : 1036 single LUT's are left
+SYN-4006 : 2105 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10178/13968 primitive instances ...
+PHY-3001 : End packing; 1.705944s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (99.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6939 instances
+RUN-1001 : 3396 mslices, 3395 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18287 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 24 nets with only 1 pin.
+RUN-1001 : 9924 nets have 2 pins
+RUN-1001 : 6896 nets have [3 - 5] pins
+RUN-1001 : 780 nets have [6 - 10] pins
+RUN-1001 : 312 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6937 instances, 6791 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3642 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 685934, Over = 290.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7829/18287.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844568, over cnt = 2116(6%), over = 3603, worst = 8
+PHY-1002 : len = 853184, over cnt = 1335(3%), over = 2032, worst = 7
+PHY-1002 : len = 872920, over cnt = 380(1%), over = 499, worst = 6
+PHY-1002 : len = 878624, over cnt = 159(0%), over = 206, worst = 3
+PHY-1002 : len = 882944, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations; 1.608869s wall, 2.265625s user + 0.031250s system = 2.296875s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 61.40, top5 = 52.47, top10 = 48.42, top15 = 45.80.
+PHY-3001 : End congestion estimation; 2.001152s wall, 2.656250s user + 0.031250s system = 2.687500s CPU (134.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75077, tnet num: 18109, tinst num: 6937, tnode num: 97984, tedge num: 125137.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.684939s wall, 1.656250s user + 0.031250s system = 1.687500s CPU (100.2%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 633 MB, peak memory is 747 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.562103s wall, 2.531250s user + 0.031250s system = 2.562500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.03172e-05
+PHY-3002 : Step(272): len = 673151, overlap = 295.5
+PHY-3002 : Step(273): len = 668204, overlap = 299.25
+PHY-3002 : Step(274): len = 664988, overlap = 293
+PHY-3002 : Step(275): len = 662791, overlap = 285.25
+PHY-3002 : Step(276): len = 661133, overlap = 286.5
+PHY-3002 : Step(277): len = 659079, overlap = 285.25
+PHY-3002 : Step(278): len = 656949, overlap = 286
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000100634
+PHY-3002 : Step(279): len = 659032, overlap = 279.75
+PHY-3002 : Step(280): len = 662073, overlap = 261.5
+PHY-3002 : Step(281): len = 662991, overlap = 262.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000201269
+PHY-3002 : Step(282): len = 671074, overlap = 251
+PHY-3002 : Step(283): len = 680318, overlap = 239.75
+PHY-3002 : Step(284): len = 680179, overlap = 240.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.344836s wall, 0.281250s user + 0.562500s system = 0.843750s CPU (244.7%)
+
+PHY-3001 : Trial Legalized: Len = 776941
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 924/18287.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898848, over cnt = 2934(8%), over = 5064, worst = 9
+PHY-1002 : len = 917312, over cnt = 1779(5%), over = 2795, worst = 7
+PHY-1002 : len = 941216, over cnt = 720(2%), over = 1115, worst = 7
+PHY-1002 : len = 958344, over cnt = 71(0%), over = 102, worst = 4
+PHY-1002 : len = 959936, over cnt = 14(0%), over = 23, worst = 3
+PHY-1001 : End global iterations; 2.558259s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (149.6%)
+
+PHY-1001 : Congestion index: top1 = 58.08, top5 = 52.42, top10 = 49.29, top15 = 47.25.
+PHY-3001 : End congestion estimation; 3.021278s wall, 4.281250s user + 0.000000s system = 4.281250s CPU (141.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.858558s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00017601
+PHY-3002 : Step(285): len = 742099, overlap = 55
+PHY-3002 : Step(286): len = 725813, overlap = 77
+PHY-3002 : Step(287): len = 711684, overlap = 112.25
+PHY-3002 : Step(288): len = 704102, overlap = 128.5
+PHY-3002 : Step(289): len = 697772, overlap = 149.75
+PHY-3002 : Step(290): len = 694203, overlap = 164.25
+PHY-3002 : Step(291): len = 692009, overlap = 179
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000352019
+PHY-3002 : Step(292): len = 697599, overlap = 172.75
+PHY-3002 : Step(293): len = 703899, overlap = 169.25
+PHY-3002 : Step(294): len = 705537, overlap = 169.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000683579
+PHY-3002 : Step(295): len = 709090, overlap = 167.25
+PHY-3002 : Step(296): len = 717702, overlap = 155.75
+PHY-3002 : Step(297): len = 722061, overlap = 154.5
+PHY-3002 : Step(298): len = 722736, overlap = 157
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.035121s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.0%)
+
+PHY-3001 : Legalized: Len = 754283, Over = 0
+PHY-3001 : Spreading special nets. 553 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.115027s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (95.1%)
+
+PHY-3001 : 813 instances has been re-located, deltaX = 299, deltaY = 474, maxDist = 4.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 767353, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75077, tnet num: 18109, tinst num: 6940, tnode num: 97984, tedge num: 125137.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.855909s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (100.2%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 664 MB, peak memory is 747 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3528/18287.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901456, over cnt = 2793(7%), over = 4613, worst = 8
+PHY-1002 : len = 916104, over cnt = 1780(5%), over = 2669, worst = 7
+PHY-1002 : len = 932136, over cnt = 944(2%), over = 1403, worst = 7
+PHY-1002 : len = 941224, over cnt = 582(1%), over = 899, worst = 7
+PHY-1002 : len = 951416, over cnt = 144(0%), over = 221, worst = 6
+PHY-1001 : End global iterations; 2.043081s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (145.3%)
+
+PHY-1001 : Congestion index: top1 = 55.80, top5 = 50.34, top10 = 47.51, top15 = 45.65.
+PHY-1001 : End incremental global routing; 2.422517s wall, 3.312500s user + 0.031250s system = 3.343750s CPU (138.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18109 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.872358s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.3%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6848 has valid locations, 20 needs to be replaced
+PHY-3001 : design contains 6956 instances, 6807 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3715 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 770304
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16763/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 954360, over cnt = 222(0%), over = 313, worst = 6
+PHY-1002 : len = 955440, over cnt = 116(0%), over = 137, worst = 3
+PHY-1002 : len = 956680, over cnt = 35(0%), over = 40, worst = 2
+PHY-1002 : len = 957296, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 957376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.822254s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.7%)
+
+PHY-1001 : Congestion index: top1 = 56.08, top5 = 50.47, top10 = 47.59, top15 = 45.71.
+PHY-3001 : End congestion estimation; 1.146613s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75217, tnet num: 18125, tinst num: 6956, tnode num: 98156, tedge num: 125312.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.889960s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (100.0%)
+
+RUN-1004 : used memory is 697 MB, reserved memory is 704 MB, peak memory is 747 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.771761s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(299): len = 769781, overlap = 0
+PHY-3002 : Step(300): len = 769531, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16761/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 956232, over cnt = 35(0%), over = 43, worst = 4
+PHY-1002 : len = 956272, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 956240, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 956312, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 956376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.783050s wall, 0.781250s user + 0.031250s system = 0.812500s CPU (103.8%)
+
+PHY-1001 : Congestion index: top1 = 55.78, top5 = 50.38, top10 = 47.54, top15 = 45.66.
+PHY-3001 : End congestion estimation; 1.096867s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (104.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.867570s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000892176
+PHY-3002 : Step(301): len = 769465, overlap = 0.5
+PHY-3002 : Step(302): len = 769194, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005661s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 769310, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059085s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 769286, Over = 0
+PHY-3001 : End incremental placement; 6.367181s wall, 6.437500s user + 0.140625s system = 6.578125s CPU (103.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.150281s wall, 11.125000s user + 0.171875s system = 11.296875s CPU (111.3%)
+
+OPT-1001 : Current memory(MB): used = 752, reserve = 748, peak = 755.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16757/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 956648, over cnt = 31(0%), over = 41, worst = 6
+PHY-1002 : len = 956672, over cnt = 17(0%), over = 20, worst = 3
+PHY-1002 : len = 956912, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 956928, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.594159s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (99.9%)
+
+PHY-1001 : Congestion index: top1 = 55.78, top5 = 50.39, top10 = 47.53, top15 = 45.63.
+OPT-1001 : End congestion update; 0.909397s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.727332s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.0%)
+
+OPT-0007 : Start: WNS -1105 TNS -1290 NUM_FEPS 4
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6868 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6956 instances, 6807 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3715 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 771072, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062966s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.3%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 13, deltaY = 6, maxDist = 4.
+PHY-3001 : Final: Len = 771154, Over = 0
+PHY-3001 : End incremental legalization; 0.392767s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.5%)
+
+OPT-0007 : Iter 1: improved WNS -638 TNS -772 NUM_FEPS 2 with 29 cells processed and 6914 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6868 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6956 instances, 6807 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3715 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 771376, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061638s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.4%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 12, deltaY = 4, maxDist = 4.
+PHY-3001 : Final: Len = 771764, Over = 0
+PHY-3001 : End incremental legalization; 0.390407s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.1%)
+
+OPT-0007 : Iter 2: improved WNS -638 TNS -772 NUM_FEPS 2 with 11 cells processed and 871 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6868 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6956 instances, 6807 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3715 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 771708, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064057s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.6%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 6, deltaY = 0, maxDist = 4.
+PHY-3001 : Final: Len = 771784, Over = 0
+PHY-3001 : End incremental legalization; 0.395261s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.5%)
+
+OPT-0007 : Iter 3: improved WNS -638 TNS -772 NUM_FEPS 2 with 4 cells processed and 250 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6869 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6957 instances, 6808 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3716 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 771944, Over = 0
+PHY-3001 : End spreading; 0.061283s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.0%)
+
+PHY-3001 : Final: Len = 771944, Over = 0
+PHY-3001 : End incremental legalization; 0.390924s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (139.9%)
+
+OPT-0007 : Iter 4: improved WNS -1005 TNS -1139 NUM_FEPS 2 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization; 3.790047s wall, 4.140625s user + 0.000000s system = 4.140625s CPU (109.2%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 750, peak = 756.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16598/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 958912, over cnt = 114(0%), over = 147, worst = 6
+PHY-1002 : len = 958976, over cnt = 60(0%), over = 61, worst = 2
+PHY-1002 : len = 959400, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 959544, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 959720, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.831316s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (103.4%)
+
+PHY-1001 : Congestion index: top1 = 55.58, top5 = 50.52, top10 = 47.64, top15 = 45.73.
+OPT-1001 : End congestion update; 1.149196s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (102.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.758299s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.0%)
+
+OPT-0007 : Start: WNS -1005 TNS -1139 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6869 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6957 instances, 6808 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3716 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 780030, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065069s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.1%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 17, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 780648, Over = 0
+PHY-3001 : End incremental legalization; 0.400138s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (113.2%)
+
+OPT-0007 : Iter 1: improved WNS -719 TNS -719 NUM_FEPS 1 with 69 cells processed and 17386 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6869 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6957 instances, 6808 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3716 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 781842, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061954s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.9%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 2.
+PHY-3001 : Final: Len = 781842, Over = 0
+PHY-3001 : End incremental legalization; 0.388609s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.5%)
+
+OPT-0007 : Iter 2: improved WNS -719 TNS -719 NUM_FEPS 1 with 9 cells processed and 1200 slack improved
+OPT-1001 : End path based optimization; 3.146247s wall, 3.234375s user + 0.015625s system = 3.250000s CPU (103.3%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 750, peak = 756.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.724977s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16486/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 968736, over cnt = 231(0%), over = 285, worst = 4
+PHY-1002 : len = 968840, over cnt = 155(0%), over = 175, worst = 3
+PHY-1002 : len = 970616, over cnt = 31(0%), over = 31, worst = 1
+PHY-1002 : len = 971216, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 971264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.952564s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 56.19, top5 = 50.70, top10 = 47.89, top15 = 46.01.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.861175s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS -719 TNS -719 NUM_FEPS 1
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 55.827586
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack -719ps with logic level 5
+RUN-1001 : #2 path slack -705ps with logic level 5
+RUN-1001 : extra opt step will be enabled to improve QoR
+RUN-1001 : 0 HFN exist on timing critical paths out of 18303 nets
+RUN-1001 : 0 long nets exist on timing critical paths out of 18303 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6869 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6957 instances, 6808 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3716 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 781842, Over = 0
+PHY-3001 : End spreading; 0.059543s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.7%)
+
+PHY-3001 : Final: Len = 781842, Over = 0
+PHY-3001 : End incremental legalization; 0.387857s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (124.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.724515s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.2%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16777/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 971264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.134919s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.2%)
+
+PHY-1001 : Congestion index: top1 = 56.19, top5 = 50.70, top10 = 47.89, top15 = 46.01.
+OPT-1001 : End congestion update; 0.454215s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.724609s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.3%)
+
+OPT-0007 : Start: WNS -719 TNS -719 NUM_FEPS 1
+OPT-0007 : Iter 1: improved WNS -719 TNS -719 NUM_FEPS 1 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.249813s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 750, peak = 756.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16777/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 971264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.366698s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.3%)
+
+PHY-1001 : Congestion index: top1 = 56.19, top5 = 50.70, top10 = 47.89, top15 = 46.01.
+OPT-1001 : End congestion update; 0.704629s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.731383s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.4%)
+
+OPT-0007 : Start: WNS -719 TNS -719 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6869 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6957 instances, 6808 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3716 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 781678, Over = 0
+PHY-3001 : End spreading; 0.058998s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.9%)
+
+PHY-3001 : Final: Len = 781678, Over = 0
+PHY-3001 : End incremental legalization; 0.387947s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.7%)
+
+OPT-0007 : Iter 1: improved WNS -719 TNS -719 NUM_FEPS 1 with 1 cells processed and 26 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6869 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6957 instances, 6808 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3716 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 781666, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059637s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.6%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 781678, Over = 0
+PHY-3001 : End incremental legalization; 0.428435s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.1%)
+
+OPT-0007 : Iter 2: improved WNS -719 TNS -719 NUM_FEPS 1 with 1 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6869 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6957 instances, 6808 slices, 223 macros(1078 instances: 705 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1229 with 3716 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 781666, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063512s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 781678, Over = 0
+PHY-3001 : End incremental legalization; 0.423316s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (118.1%)
+
+OPT-0007 : Iter 3: improved WNS -719 TNS -719 NUM_FEPS 1 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 4: improved WNS -719 TNS -719 NUM_FEPS 1 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization; 3.128764s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (103.4%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 752, peak = 757.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.738135s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 754, reserve = 752, peak = 757.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.729297s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.7%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16771/18303.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 970984, over cnt = 5(0%), over = 6, worst = 2
+PHY-1002 : len = 970960, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 970992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.421729s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.0%)
+
+PHY-1001 : Congestion index: top1 = 56.19, top5 = 50.68, top10 = 47.88, top15 = 46.00.
+RUN-1001 : End congestion update; 0.747186s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.4%)
+
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery; 1.479905s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (100.3%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 752, peak = 757.
+OPT-1001 : End physical optimization; 30.020096s wall, 31.593750s user + 0.234375s system = 31.828125s CPU (106.0%)
+
+RUN-1003 : finish command "place" in 74.524666s wall, 100.062500s user + 5.812500s system = 105.875000s CPU (142.1%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 655 MB, peak memory is 757 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.716607s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (174.8%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 656 MB, peak memory is 757 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6959 instances
+RUN-1001 : 3404 mslices, 3404 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18303 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 24 nets with only 1 pin.
+RUN-1001 : 9924 nets have 2 pins
+RUN-1001 : 6893 nets have [3 - 5] pins
+RUN-1001 : 781 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 352 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75232, tnet num: 18125, tinst num: 6957, tnode num: 98176, tedge num: 125331.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.625048s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.0%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 632 MB, peak memory is 757 MB
+PHY-1001 : 3404 mslices, 3404 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[7] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892896, over cnt = 2941(8%), over = 4972, worst = 8
+PHY-1002 : len = 912064, over cnt = 1870(5%), over = 2749, worst = 8
+PHY-1002 : len = 937736, over cnt = 607(1%), over = 842, worst = 7
+PHY-1002 : len = 951696, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 951984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.128151s wall, 4.437500s user + 0.031250s system = 4.468750s CPU (142.9%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 50.22, top10 = 47.51, top15 = 45.56.
+PHY-1001 : End global routing; 3.481625s wall, 4.796875s user + 0.031250s system = 4.828125s CPU (138.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 723, reserve = 726, peak = 757.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 997, reserve = 1003, peak = 997.
+PHY-1001 : End build detailed router design. 4.020375s wall, 3.968750s user + 0.046875s system = 4.015625s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 273024, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.167276s wall, 5.171875s user + 0.000000s system = 5.171875s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 273080, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.526823s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (97.9%)
+
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1038, peak = 1031.
+PHY-1001 : End phase 1; 5.707191s wall, 5.703125s user + 0.000000s system = 5.703125s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.39879e+06, over cnt = 2004(0%), over = 2015, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1056, peak = 1051.
+PHY-1001 : End initial routed; 28.469928s wall, 57.625000s user + 0.281250s system = 57.906250s CPU (203.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 81/17220(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.202 | -23.761 | 15
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.335539s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1064, reserve = 1070, peak = 1064.
+PHY-1001 : End phase 2; 31.805530s wall, 60.968750s user + 0.281250s system = 61.250000s CPU (192.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 21 pins with SWNS -1.793ns STNS -21.146ns FEP 15.
+PHY-1001 : End OPT Iter 1; 0.233163s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.5%)
+
+PHY-1022 : len = 2.39892e+06, over cnt = 2023(0%), over = 2036, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.500734s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.36016e+06, over cnt = 743(0%), over = 743, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.761364s wall, 3.156250s user + 0.031250s system = 3.187500s CPU (181.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.35842e+06, over cnt = 157(0%), over = 157, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.826532s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (151.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.35909e+06, over cnt = 21(0%), over = 21, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.418650s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (112.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.35956e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.226481s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (110.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.35974e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.251271s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.3597e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.226201s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.3597e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 7; 0.282320s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (99.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 81/17220(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.213 | -26.454 | 15
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.351184s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 616 feed throughs used by 456 nets
+PHY-1001 : End commit to database; 2.308605s wall, 2.250000s user + 0.046875s system = 2.296875s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1177, peak = 1167.
+PHY-1001 : End phase 3; 10.576751s wall, 12.390625s user + 0.109375s system = 12.500000s CPU (118.2%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -1.793ns STNS -21.414ns FEP 15.
+PHY-1001 : End OPT Iter 1; 0.183797s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.0%)
+
+PHY-1022 : len = 2.35969e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.428922s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.793ns, -21.414ns, 15}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3597e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.168312s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 81/17220(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -2.063 | -24.654 | 15
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.305038s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 617 feed throughs used by 457 nets
+PHY-1001 : End commit to database; 2.394919s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1177, reserve = 1187, peak = 1177.
+PHY-1001 : End phase 4; 6.346226s wall, 6.343750s user + 0.000000s system = 6.343750s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.3597e+06
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1189, peak = 1178.
+PHY-1001 : End export database. 0.148301s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.4%)
+
+PHY-1001 : End detail routing; 59.016475s wall, 89.937500s user + 0.437500s system = 90.375000s CPU (153.1%)
+
+RUN-1003 : finish command "route" in 65.243361s wall, 97.453125s user + 0.484375s system = 97.937500s CPU (150.1%)
+
+RUN-1004 : used memory is 1105 MB, reserved memory is 1113 MB, peak memory is 1178 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10702 out of 19600 54.60%
+#reg 9628 out of 19600 49.12%
+#le 12749
+ #lut only 3121 out of 12749 24.48%
+ #reg only 2047 out of 12749 16.06%
+ #lut® 7581 out of 12749 59.46%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1813
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1478
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1368
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 951
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 137
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 70
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_280.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK mslice u_mipi_sot_min/reg1_syn_303.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P11 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P114 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P66 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P82 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P146 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P119 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P2 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12749 |9672 |1030 |9660 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |538 |446 |23 |448 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |108 |92 |4 |92 |4 |0 |
+| U_crc16_24b |crc16_24b |26 |26 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |7 |7 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |770 |392 |96 |580 |0 |0 |
+| u_ADconfig |AD_config |193 |132 |25 |145 |0 |0 |
+| u_gen_sp |gen_sp |262 |151 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |746 |415 |96 |557 |0 |0 |
+| u_ADconfig |AD_config |175 |127 |25 |129 |0 |0 |
+| u_gen_sp |gen_sp |259 |168 |71 |116 |0 |0 |
+| sampling_fe_a |sampling_fe |3112 |2569 |306 |2106 |25 |0 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |185 |136 |17 |155 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort |2893 |2426 |289 |1917 |25 |0 |
+| rddpram_ctl |rddpram_ctl |8 |8 |0 |8 |0 |0 |
+| u0_rdsoft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2431 |2033 |253 |1553 |22 |0 |
+| channelPart |channel_part_8478 |156 |151 |3 |133 |0 |0 |
+| fifo_adc |fifo_adc |55 |46 |9 |41 |0 |0 |
+| ram_switch |ram_switch |1913 |1595 |197 |1146 |0 |0 |
+| adc_addr_gen |adc_addr_gen |252 |225 |27 |117 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |6 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |28 |25 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |30 |27 |3 |15 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |30 |27 |3 |15 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |25 |22 |3 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |11 |0 |0 |
+| insert |insert |962 |671 |170 |663 |0 |0 |
+| ram_switch_state |ram_switch_state |699 |699 |0 |366 |0 |0 |
+| read_ram_i |read_ram |263 |206 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |211 |171 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |52 |35 |4 |41 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |335 |270 |36 |279 |3 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3350 |2701 |343 |2104 |25 |1 |
+| u0_soft_n |cdc_sync |5 |2 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |186 |107 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u_sort |sort_rev |3130 |2577 |326 |1912 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |5 |4 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |0 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2669 |2224 |284 |1547 |22 |1 |
+| channelPart |channel_part_8478 |236 |233 |3 |143 |0 |0 |
+| fifo_adc |fifo_adc |58 |49 |9 |43 |0 |1 |
+| ram_switch |ram_switch |1983 |1655 |197 |1108 |0 |0 |
+| adc_addr_gen |adc_addr_gen |206 |179 |27 |100 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |19 |16 |3 |10 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |25 |22 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |14 |11 |3 |7 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |8 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |21 |18 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |6 |0 |0 |
+| insert |insert |984 |688 |170 |663 |0 |0 |
+| ram_switch_state |ram_switch_state |793 |788 |0 |345 |0 |0 |
+| read_ram_i |read_ram_rev |357 |264 |75 |218 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |290 |220 |67 |168 |0 |0 |
+| read_ram_data |read_ram_data_rev |67 |44 |8 |50 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9862
+ #2 2 4431
+ #3 3 1884
+ #4 4 575
+ #5 5-10 837
+ #6 11-50 592
+ #7 51-100 22
+ #8 >500 1
+ Average 2.82
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.116346s wall, 3.640625s user + 0.000000s system = 3.640625s CPU (172.0%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1115 MB, peak memory is 1178 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75232, tnet num: 18125, tinst num: 6957, tnode num: 98176, tedge num: 125331.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.613501s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.7%)
+
+RUN-1004 : used memory is 1110 MB, reserved memory is 1118 MB, peak memory is 1178 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18125 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.483988s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (100.0%)
+
+RUN-1004 : used memory is 1113 MB, reserved memory is 1120 MB, peak memory is 1178 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6957
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18303, pip num: 176586
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 617
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3265 valid insts, and 489566 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.286352s wall, 63.484375s user + 0.234375s system = 63.718750s CPU (619.4%)
+
+RUN-1004 : used memory is 1279 MB, reserved memory is 1282 MB, peak memory is 1395 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_161709.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_162610.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_162610.log
new file mode 100644
index 0000000..0974cd6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_162610.log
@@ -0,0 +1,2030 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 16:26:10 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_16mhz.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.222939s wall, 2.125000s user + 0.093750s system = 2.218750s CPU (99.8%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 319 MB, peak memory is 345 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 1.5000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 1.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18203 instances
+RUN-0007 : 7747 luts, 9231 seqs, 704 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20775 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13298 nets have 2 pins
+RUN-1001 : 6390 nets have [3 - 5] pins
+RUN-1001 : 683 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 165 nets have [21 - 99] pins
+RUN-1001 : 57 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1997
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18201 instances, 7747 luts, 9231 seqs, 1077 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6102 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85331, tnet num: 20597, tinst num: 18201, tnode num: 116072, tedge num: 136210.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.181626s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (100.5%)
+
+RUN-1004 : used memory is 536 MB, reserved memory is 520 MB, peak memory is 536 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20597 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.968012s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (100.0%)
+
+PHY-3001 : Found 1258 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.13103e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18201.
+PHY-3001 : Level 1 #clusters 2035.
+PHY-3001 : End clustering; 0.130250s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (120.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31688e+06, overlap = 467.094
+PHY-3002 : Step(2): len = 1.2243e+06, overlap = 559.375
+PHY-3002 : Step(3): len = 852494, overlap = 641.25
+PHY-3002 : Step(4): len = 770572, overlap = 703.375
+PHY-3002 : Step(5): len = 603204, overlap = 868.5
+PHY-3002 : Step(6): len = 557265, overlap = 920.469
+PHY-3002 : Step(7): len = 442915, overlap = 995.562
+PHY-3002 : Step(8): len = 412433, overlap = 1028.47
+PHY-3002 : Step(9): len = 358065, overlap = 1109.59
+PHY-3002 : Step(10): len = 329386, overlap = 1125.56
+PHY-3002 : Step(11): len = 298333, overlap = 1159.91
+PHY-3002 : Step(12): len = 275863, overlap = 1210
+PHY-3002 : Step(13): len = 250135, overlap = 1256.16
+PHY-3002 : Step(14): len = 231438, overlap = 1293.88
+PHY-3002 : Step(15): len = 202701, overlap = 1382.25
+PHY-3002 : Step(16): len = 190977, overlap = 1420
+PHY-3002 : Step(17): len = 172008, overlap = 1436.97
+PHY-3002 : Step(18): len = 166477, overlap = 1443.84
+PHY-3002 : Step(19): len = 150740, overlap = 1431.59
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2466e-06
+PHY-3002 : Step(20): len = 153572, overlap = 1418.66
+PHY-3002 : Step(21): len = 183776, overlap = 1343.47
+PHY-3002 : Step(22): len = 197609, overlap = 1233.06
+PHY-3002 : Step(23): len = 204829, overlap = 1180.09
+PHY-3002 : Step(24): len = 204206, overlap = 1133.81
+PHY-3002 : Step(25): len = 203049, overlap = 1138.91
+PHY-3002 : Step(26): len = 199957, overlap = 1130.84
+PHY-3002 : Step(27): len = 198837, overlap = 1133.19
+PHY-3002 : Step(28): len = 196886, overlap = 1114.59
+PHY-3002 : Step(29): len = 194674, overlap = 1080.31
+PHY-3002 : Step(30): len = 193011, overlap = 1096.16
+PHY-3002 : Step(31): len = 190450, overlap = 1107.91
+PHY-3002 : Step(32): len = 189168, overlap = 1100.34
+PHY-3002 : Step(33): len = 186297, overlap = 1073.94
+PHY-3002 : Step(34): len = 184462, overlap = 1067.12
+PHY-3002 : Step(35): len = 183060, overlap = 1056.09
+PHY-3002 : Step(36): len = 182004, overlap = 1070.81
+PHY-3002 : Step(37): len = 181837, overlap = 1074.94
+PHY-3002 : Step(38): len = 180696, overlap = 1067.31
+PHY-3002 : Step(39): len = 179526, overlap = 1077.69
+PHY-3002 : Step(40): len = 178525, overlap = 1102.53
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.49319e-06
+PHY-3002 : Step(41): len = 183929, overlap = 1067.72
+PHY-3002 : Step(42): len = 192715, overlap = 1036.75
+PHY-3002 : Step(43): len = 198308, overlap = 993.719
+PHY-3002 : Step(44): len = 206077, overlap = 949.219
+PHY-3002 : Step(45): len = 208210, overlap = 953.344
+PHY-3002 : Step(46): len = 209992, overlap = 957.156
+PHY-3002 : Step(47): len = 209966, overlap = 955.25
+PHY-3002 : Step(48): len = 211072, overlap = 942.656
+PHY-3002 : Step(49): len = 210057, overlap = 927.156
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.98638e-06
+PHY-3002 : Step(50): len = 217004, overlap = 913.344
+PHY-3002 : Step(51): len = 229524, overlap = 849.906
+PHY-3002 : Step(52): len = 238530, overlap = 814.344
+PHY-3002 : Step(53): len = 246892, overlap = 770.875
+PHY-3002 : Step(54): len = 250084, overlap = 745.5
+PHY-3002 : Step(55): len = 253595, overlap = 727.5
+PHY-3002 : Step(56): len = 253931, overlap = 711.469
+PHY-3002 : Step(57): len = 254295, overlap = 703.688
+PHY-3002 : Step(58): len = 253028, overlap = 702.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.97277e-06
+PHY-3002 : Step(59): len = 267335, overlap = 679.969
+PHY-3002 : Step(60): len = 283447, overlap = 644.781
+PHY-3002 : Step(61): len = 289820, overlap = 561.281
+PHY-3002 : Step(62): len = 296220, overlap = 546.031
+PHY-3002 : Step(63): len = 297438, overlap = 531.688
+PHY-3002 : Step(64): len = 299026, overlap = 523.125
+PHY-3002 : Step(65): len = 296248, overlap = 510.125
+PHY-3002 : Step(66): len = 295887, overlap = 507.406
+PHY-3002 : Step(67): len = 297021, overlap = 502.938
+PHY-3002 : Step(68): len = 297966, overlap = 500.719
+PHY-3002 : Step(69): len = 297013, overlap = 499.781
+PHY-3002 : Step(70): len = 296042, overlap = 495.25
+PHY-3002 : Step(71): len = 294430, overlap = 511.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.99455e-05
+PHY-3002 : Step(72): len = 307795, overlap = 457.781
+PHY-3002 : Step(73): len = 320211, overlap = 419.281
+PHY-3002 : Step(74): len = 326253, overlap = 408.344
+PHY-3002 : Step(75): len = 331930, overlap = 402.281
+PHY-3002 : Step(76): len = 333536, overlap = 373.031
+PHY-3002 : Step(77): len = 335709, overlap = 344.969
+PHY-3002 : Step(78): len = 333993, overlap = 347.656
+PHY-3002 : Step(79): len = 333934, overlap = 349.75
+PHY-3002 : Step(80): len = 333539, overlap = 362.5
+PHY-3002 : Step(81): len = 332616, overlap = 374.469
+PHY-3002 : Step(82): len = 330989, overlap = 365.938
+PHY-3002 : Step(83): len = 330212, overlap = 370.938
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.98911e-05
+PHY-3002 : Step(84): len = 343532, overlap = 359
+PHY-3002 : Step(85): len = 354098, overlap = 343.219
+PHY-3002 : Step(86): len = 356968, overlap = 326.656
+PHY-3002 : Step(87): len = 361313, overlap = 306.688
+PHY-3002 : Step(88): len = 365840, overlap = 307.719
+PHY-3002 : Step(89): len = 370209, overlap = 301.594
+PHY-3002 : Step(90): len = 367571, overlap = 317.906
+PHY-3002 : Step(91): len = 370631, overlap = 312.094
+PHY-3002 : Step(92): len = 373454, overlap = 305.781
+PHY-3002 : Step(93): len = 376394, overlap = 317.781
+PHY-3002 : Step(94): len = 370957, overlap = 313.312
+PHY-3002 : Step(95): len = 369654, overlap = 311.969
+PHY-3002 : Step(96): len = 368713, overlap = 328.844
+PHY-3002 : Step(97): len = 369541, overlap = 325.281
+PHY-3002 : Step(98): len = 367613, overlap = 334.594
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.88254e-05
+PHY-3002 : Step(99): len = 382669, overlap = 290.75
+PHY-3002 : Step(100): len = 392212, overlap = 288.469
+PHY-3002 : Step(101): len = 393173, overlap = 280.188
+PHY-3002 : Step(102): len = 397536, overlap = 259.781
+PHY-3002 : Step(103): len = 400178, overlap = 260.844
+PHY-3002 : Step(104): len = 402882, overlap = 250.5
+PHY-3002 : Step(105): len = 400466, overlap = 244.5
+PHY-3002 : Step(106): len = 400474, overlap = 252.281
+PHY-3002 : Step(107): len = 402518, overlap = 262.5
+PHY-3002 : Step(108): len = 404782, overlap = 264.656
+PHY-3002 : Step(109): len = 402222, overlap = 257.219
+PHY-3002 : Step(110): len = 402485, overlap = 251.844
+PHY-3002 : Step(111): len = 403205, overlap = 261.812
+PHY-3002 : Step(112): len = 404169, overlap = 271.312
+PHY-3002 : Step(113): len = 403186, overlap = 270.688
+PHY-3002 : Step(114): len = 403705, overlap = 267.938
+PHY-3002 : Step(115): len = 404550, overlap = 266.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000157651
+PHY-3002 : Step(116): len = 416915, overlap = 261.219
+PHY-3002 : Step(117): len = 426330, overlap = 251.344
+PHY-3002 : Step(118): len = 427272, overlap = 251.094
+PHY-3002 : Step(119): len = 428295, overlap = 251.438
+PHY-3002 : Step(120): len = 430797, overlap = 241.625
+PHY-3002 : Step(121): len = 433876, overlap = 237.156
+PHY-3002 : Step(122): len = 433349, overlap = 227.969
+PHY-3002 : Step(123): len = 434348, overlap = 235.062
+PHY-3002 : Step(124): len = 435675, overlap = 228.344
+PHY-3002 : Step(125): len = 436976, overlap = 236.781
+PHY-3002 : Step(126): len = 436387, overlap = 239.812
+PHY-3002 : Step(127): len = 436424, overlap = 231.312
+PHY-3002 : Step(128): len = 437713, overlap = 224.219
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000315301
+PHY-3002 : Step(129): len = 446102, overlap = 226.344
+PHY-3002 : Step(130): len = 454812, overlap = 216.812
+PHY-3002 : Step(131): len = 458381, overlap = 206.625
+PHY-3002 : Step(132): len = 462639, overlap = 189.844
+PHY-3002 : Step(133): len = 466448, overlap = 187.281
+PHY-3002 : Step(134): len = 471656, overlap = 185.75
+PHY-3002 : Step(135): len = 471619, overlap = 176.875
+PHY-3002 : Step(136): len = 472533, overlap = 179.75
+PHY-3002 : Step(137): len = 475937, overlap = 164.531
+PHY-3002 : Step(138): len = 479054, overlap = 160.75
+PHY-3002 : Step(139): len = 476491, overlap = 157.219
+PHY-3002 : Step(140): len = 475715, overlap = 154.531
+PHY-3002 : Step(141): len = 477419, overlap = 155.812
+PHY-3002 : Step(142): len = 477967, overlap = 157.75
+PHY-3002 : Step(143): len = 475685, overlap = 155.844
+PHY-3002 : Step(144): len = 475430, overlap = 167.281
+PHY-3002 : Step(145): len = 476503, overlap = 167
+PHY-3002 : Step(146): len = 477343, overlap = 162.156
+PHY-3002 : Step(147): len = 475856, overlap = 161.812
+PHY-3002 : Step(148): len = 475699, overlap = 160.219
+PHY-3002 : Step(149): len = 476909, overlap = 161.844
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000626165
+PHY-3002 : Step(150): len = 482443, overlap = 148.531
+PHY-3002 : Step(151): len = 489831, overlap = 147.344
+PHY-3002 : Step(152): len = 492168, overlap = 151.812
+PHY-3002 : Step(153): len = 493607, overlap = 148.438
+PHY-3002 : Step(154): len = 494746, overlap = 147.5
+PHY-3002 : Step(155): len = 495587, overlap = 140
+PHY-3002 : Step(156): len = 495855, overlap = 137.688
+PHY-3002 : Step(157): len = 496362, overlap = 139.594
+PHY-3002 : Step(158): len = 497392, overlap = 144.531
+PHY-3002 : Step(159): len = 498478, overlap = 143.031
+PHY-3002 : Step(160): len = 498865, overlap = 138.875
+PHY-3002 : Step(161): len = 499334, overlap = 138.469
+PHY-3002 : Step(162): len = 499750, overlap = 138.469
+PHY-3002 : Step(163): len = 500295, overlap = 134.562
+PHY-3002 : Step(164): len = 500435, overlap = 137.094
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00115363
+PHY-3002 : Step(165): len = 503174, overlap = 135.219
+PHY-3002 : Step(166): len = 506885, overlap = 129.875
+PHY-3002 : Step(167): len = 508640, overlap = 134.25
+PHY-3002 : Step(168): len = 510100, overlap = 132
+PHY-3002 : Step(169): len = 511426, overlap = 130.688
+PHY-3002 : Step(170): len = 512383, overlap = 133.469
+PHY-3002 : Step(171): len = 512942, overlap = 133.906
+PHY-3002 : Step(172): len = 513312, overlap = 138.062
+PHY-3002 : Step(173): len = 513870, overlap = 134.531
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0019783
+PHY-3002 : Step(174): len = 516254, overlap = 138.594
+PHY-3002 : Step(175): len = 522088, overlap = 134.406
+PHY-3002 : Step(176): len = 523599, overlap = 133.719
+PHY-3002 : Step(177): len = 524589, overlap = 134.531
+PHY-3002 : Step(178): len = 526099, overlap = 132.875
+PHY-3002 : Step(179): len = 527218, overlap = 132.25
+PHY-3002 : Step(180): len = 527228, overlap = 130.312
+PHY-3002 : Step(181): len = 527403, overlap = 130.469
+PHY-3002 : Step(182): len = 528189, overlap = 128.688
+PHY-3002 : Step(183): len = 528814, overlap = 131.094
+PHY-3002 : Step(184): len = 529012, overlap = 126.812
+PHY-3002 : Step(185): len = 529314, overlap = 126.25
+PHY-3002 : Step(186): len = 529845, overlap = 128.781
+PHY-3002 : Step(187): len = 530069, overlap = 129.719
+PHY-3002 : Step(188): len = 530585, overlap = 130.281
+PHY-3002 : Step(189): len = 533223, overlap = 124.094
+PHY-3002 : Step(190): len = 535521, overlap = 126.031
+PHY-3002 : Step(191): len = 537092, overlap = 125.125
+PHY-3002 : Step(192): len = 537391, overlap = 125.844
+PHY-3002 : Step(193): len = 537964, overlap = 125.219
+PHY-3002 : Step(194): len = 538594, overlap = 129.406
+PHY-3002 : Step(195): len = 538533, overlap = 123.875
+PHY-3002 : Step(196): len = 537984, overlap = 121.875
+PHY-3002 : Step(197): len = 537770, overlap = 119.844
+PHY-3002 : Step(198): len = 538133, overlap = 113.938
+PHY-3002 : Step(199): len = 538582, overlap = 111.75
+PHY-3002 : Step(200): len = 538791, overlap = 111.781
+PHY-3002 : Step(201): len = 538987, overlap = 107.531
+PHY-3002 : Step(202): len = 539471, overlap = 111.906
+PHY-3002 : Step(203): len = 539978, overlap = 113.344
+PHY-3002 : Step(204): len = 539716, overlap = 110.188
+PHY-3002 : Step(205): len = 539557, overlap = 108.688
+PHY-3002 : Step(206): len = 539755, overlap = 108.094
+PHY-3002 : Step(207): len = 539850, overlap = 109.969
+PHY-3002 : Step(208): len = 539544, overlap = 107.875
+PHY-3002 : Step(209): len = 539463, overlap = 107.719
+PHY-3002 : Step(210): len = 539422, overlap = 107.406
+PHY-3002 : Step(211): len = 539308, overlap = 106.75
+PHY-3002 : Step(212): len = 538824, overlap = 109.594
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013487s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (115.8%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20775.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 721840, over cnt = 1613(4%), over = 7185, worst = 27
+PHY-1001 : End global iterations; 0.689205s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (151.9%)
+
+PHY-1001 : Congestion index: top1 = 79.09, top5 = 59.94, top10 = 51.47, top15 = 46.05.
+PHY-3001 : End congestion estimation; 0.927575s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (139.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20597 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.861365s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000153428
+PHY-3002 : Step(213): len = 654564, overlap = 70.5938
+PHY-3002 : Step(214): len = 650743, overlap = 55.375
+PHY-3002 : Step(215): len = 648619, overlap = 54.125
+PHY-3002 : Step(216): len = 648840, overlap = 55.5
+PHY-3002 : Step(217): len = 647612, overlap = 56.2812
+PHY-3002 : Step(218): len = 643310, overlap = 61.875
+PHY-3002 : Step(219): len = 639379, overlap = 61.5312
+PHY-3002 : Step(220): len = 636794, overlap = 53.75
+PHY-3002 : Step(221): len = 636442, overlap = 45.6562
+PHY-3002 : Step(222): len = 635995, overlap = 40.8125
+PHY-3002 : Step(223): len = 633402, overlap = 40.0312
+PHY-3002 : Step(224): len = 632132, overlap = 37.375
+PHY-3002 : Step(225): len = 630649, overlap = 39.7188
+PHY-3002 : Step(226): len = 629514, overlap = 41.4062
+PHY-3002 : Step(227): len = 629325, overlap = 36.9062
+PHY-3002 : Step(228): len = 627706, overlap = 32.8125
+PHY-3002 : Step(229): len = 627132, overlap = 38.2188
+PHY-3002 : Step(230): len = 624359, overlap = 41
+PHY-3002 : Step(231): len = 622503, overlap = 40.4062
+PHY-3002 : Step(232): len = 621248, overlap = 39.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000306856
+PHY-3002 : Step(233): len = 622432, overlap = 40.4688
+PHY-3002 : Step(234): len = 625040, overlap = 38.6875
+PHY-3002 : Step(235): len = 629030, overlap = 38.5938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000613713
+PHY-3002 : Step(236): len = 639786, overlap = 42.875
+PHY-3002 : Step(237): len = 652844, overlap = 42.0312
+PHY-3002 : Step(238): len = 661075, overlap = 41.9375
+PHY-3002 : Step(239): len = 666287, overlap = 40.1875
+PHY-3002 : Step(240): len = 670095, overlap = 38.625
+PHY-3002 : Step(241): len = 673002, overlap = 37.9062
+PHY-3002 : Step(242): len = 672526, overlap = 38.375
+PHY-3002 : Step(243): len = 672803, overlap = 36.2812
+PHY-3002 : Step(244): len = 670828, overlap = 36.125
+PHY-3002 : Step(245): len = 669400, overlap = 36.3125
+PHY-3002 : Step(246): len = 667423, overlap = 37.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00122743
+PHY-3002 : Step(247): len = 673138, overlap = 37.6562
+PHY-3002 : Step(248): len = 679443, overlap = 36.4062
+PHY-3002 : Step(249): len = 684790, overlap = 35.4688
+PHY-3002 : Step(250): len = 689722, overlap = 33.5625
+PHY-3002 : Step(251): len = 694358, overlap = 33.125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00224124
+PHY-3002 : Step(252): len = 699155, overlap = 34.0312
+PHY-3002 : Step(253): len = 709939, overlap = 32.625
+PHY-3002 : Step(254): len = 720680, overlap = 30.4688
+PHY-3002 : Step(255): len = 723538, overlap = 28.9375
+PHY-3002 : Step(256): len = 725099, overlap = 30.625
+PHY-3002 : Step(257): len = 726133, overlap = 28.9062
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/20775.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 810608, over cnt = 2972(8%), over = 13854, worst = 54
+PHY-1001 : End global iterations; 1.712183s wall, 2.171875s user + 0.015625s system = 2.187500s CPU (127.8%)
+
+PHY-1001 : Congestion index: top1 = 90.95, top5 = 73.94, top10 = 64.62, top15 = 58.88.
+PHY-3001 : End congestion estimation; 1.970195s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (123.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20597 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.880802s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000144912
+PHY-3002 : Step(258): len = 706402, overlap = 215.312
+PHY-3002 : Step(259): len = 692047, overlap = 165.312
+PHY-3002 : Step(260): len = 678675, overlap = 149.344
+PHY-3002 : Step(261): len = 667333, overlap = 136.312
+PHY-3002 : Step(262): len = 658051, overlap = 127.219
+PHY-3002 : Step(263): len = 649908, overlap = 120.438
+PHY-3002 : Step(264): len = 642691, overlap = 119.875
+PHY-3002 : Step(265): len = 637091, overlap = 108.844
+PHY-3002 : Step(266): len = 632382, overlap = 103.344
+PHY-3002 : Step(267): len = 626015, overlap = 106.719
+PHY-3002 : Step(268): len = 621990, overlap = 110.688
+PHY-3002 : Step(269): len = 619087, overlap = 106.719
+PHY-3002 : Step(270): len = 613475, overlap = 105.594
+PHY-3002 : Step(271): len = 611152, overlap = 104.031
+PHY-3002 : Step(272): len = 607757, overlap = 102.781
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000289825
+PHY-3002 : Step(273): len = 608401, overlap = 96.8125
+PHY-3002 : Step(274): len = 610330, overlap = 92.7812
+PHY-3002 : Step(275): len = 611177, overlap = 94.3438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000579649
+PHY-3002 : Step(276): len = 616741, overlap = 88.2812
+PHY-3002 : Step(277): len = 625049, overlap = 82.75
+PHY-3002 : Step(278): len = 625931, overlap = 84.3125
+PHY-3002 : Step(279): len = 624575, overlap = 84.9062
+PHY-3002 : Step(280): len = 624577, overlap = 85.1562
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85331, tnet num: 20597, tinst num: 18201, tnode num: 116072, tedge num: 136210.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.449859s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.2%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 572 MB, peak memory is 717 MB
+OPT-1001 : Total overflow 441.38 peak overflow 3.56
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 718/20775.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719384, over cnt = 2963(8%), over = 10626, worst = 27
+PHY-1001 : End global iterations; 1.486881s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (135.6%)
+
+PHY-1001 : Congestion index: top1 = 72.97, top5 = 58.31, top10 = 51.79, top15 = 47.90.
+PHY-1001 : End incremental global routing; 1.830729s wall, 2.359375s user + 0.015625s system = 2.375000s CPU (129.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20597 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.922756s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.9%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18065 has valid locations, 348 needs to be replaced
+PHY-3001 : design contains 18498 instances, 7837 luts, 9438 seqs, 1077 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6235 pins
+PHY-3001 : Found 1269 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 650259
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16870/21072.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736920, over cnt = 3065(8%), over = 10762, worst = 27
+PHY-1001 : End global iterations; 0.219574s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (128.1%)
+
+PHY-1001 : Congestion index: top1 = 72.54, top5 = 58.45, top10 = 52.05, top15 = 48.21.
+PHY-3001 : End congestion estimation; 0.468439s wall, 0.515625s user + 0.015625s system = 0.531250s CPU (113.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86508, tnet num: 20894, tinst num: 18498, tnode num: 117874, tedge num: 137970.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.480908s wall, 1.421875s user + 0.062500s system = 1.484375s CPU (100.2%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 620 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20894 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.432935s wall, 2.375000s user + 0.062500s system = 2.437500s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(281): len = 649122, overlap = 2.5625
+PHY-3002 : Step(282): len = 648609, overlap = 2.5
+PHY-3002 : Step(283): len = 648337, overlap = 2.4375
+PHY-3002 : Step(284): len = 648192, overlap = 2.4375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000175299
+PHY-3002 : Step(285): len = 648055, overlap = 2.4375
+PHY-3002 : Step(286): len = 648469, overlap = 2.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000350599
+PHY-3002 : Step(287): len = 648972, overlap = 2.25
+PHY-3002 : Step(288): len = 650558, overlap = 2.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16889/21072.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735880, over cnt = 3053(8%), over = 10832, worst = 26
+PHY-1001 : End global iterations; 0.237858s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 72.69, top5 = 58.53, top10 = 52.10, top15 = 48.25.
+PHY-3001 : End congestion estimation; 0.495199s wall, 0.578125s user + 0.015625s system = 0.593750s CPU (119.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20894 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.931713s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000634638
+PHY-3002 : Step(289): len = 650184, overlap = 87.1875
+PHY-3002 : Step(290): len = 650014, overlap = 86.8438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00126928
+PHY-3002 : Step(291): len = 650207, overlap = 86.4375
+PHY-3002 : Step(292): len = 650848, overlap = 86.5625
+PHY-3001 : Final: Len = 650848, Over = 86.5625
+PHY-3001 : End incremental placement; 5.141339s wall, 5.671875s user + 0.234375s system = 5.906250s CPU (114.9%)
+
+OPT-1001 : Total overflow 446.22 peak overflow 3.56
+OPT-1001 : End high-fanout net optimization; 8.464758s wall, 9.593750s user + 0.265625s system = 9.859375s CPU (116.5%)
+
+OPT-1001 : Current memory(MB): used = 723, reserve = 718, peak = 741.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16950/21072.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738560, over cnt = 3005(8%), over = 9816, worst = 26
+PHY-1002 : len = 787960, over cnt = 2047(5%), over = 5097, worst = 20
+PHY-1002 : len = 825328, over cnt = 895(2%), over = 2219, worst = 20
+PHY-1002 : len = 844480, over cnt = 381(1%), over = 976, worst = 18
+PHY-1002 : len = 860696, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.759485s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (135.0%)
+
+PHY-1001 : Congestion index: top1 = 58.94, top5 = 51.23, top10 = 47.31, top15 = 44.81.
+OPT-1001 : End congestion update; 2.018506s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (130.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20894 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.800086s wall, 0.765625s user + 0.046875s system = 0.812500s CPU (101.6%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 139 cells processed and 21784 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 43 cells processed and 5750 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 5 cells processed and 550 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 3 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization; 3.267199s wall, 3.843750s user + 0.046875s system = 3.890625s CPU (119.1%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 700, peak = 741.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16992/21079.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861776, over cnt = 76(0%), over = 116, worst = 4
+PHY-1002 : len = 861832, over cnt = 50(0%), over = 62, worst = 4
+PHY-1002 : len = 862440, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 862544, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 862624, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.722181s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 59.03, top5 = 51.16, top10 = 47.16, top15 = 44.70.
+OPT-1001 : End congestion update; 1.001340s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (106.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20901 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.804428s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.0%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 22 cells processed and 3400 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.932935s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (103.5%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 709, peak = 741.
+OPT-1001 : End physical optimization; 15.426498s wall, 17.281250s user + 0.328125s system = 17.609375s CPU (114.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7837 LUT to BLE ...
+SYN-4008 : Packed 7837 LUT and 3142 SEQ to BLE.
+SYN-4003 : Packing 6303 remaining SEQ's ...
+SYN-4005 : Packed 4106 SEQ with LUT/SLICE
+SYN-4006 : 884 single LUT's are left
+SYN-4006 : 2197 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10034/13823 primitive instances ...
+PHY-3001 : End packing; 1.686225s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6847 instances
+RUN-1001 : 3349 mslices, 3350 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18079 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10082 nets have 2 pins
+RUN-1001 : 6558 nets have [3 - 5] pins
+RUN-1001 : 800 nets have [6 - 10] pins
+RUN-1001 : 286 nets have [11 - 20] pins
+RUN-1001 : 323 nets have [21 - 99] pins
+RUN-1001 : 10 nets have 100+ pins
+PHY-3001 : design contains 6845 instances, 6699 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3649 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 666077, Over = 237
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7679/18079.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 816480, over cnt = 2032(5%), over = 3379, worst = 9
+PHY-1002 : len = 823528, over cnt = 1384(3%), over = 2117, worst = 9
+PHY-1002 : len = 833432, over cnt = 886(2%), over = 1340, worst = 6
+PHY-1002 : len = 847584, over cnt = 349(0%), over = 493, worst = 6
+PHY-1002 : len = 855440, over cnt = 51(0%), over = 67, worst = 5
+PHY-1001 : End global iterations; 1.599608s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (140.7%)
+
+PHY-1001 : Congestion index: top1 = 61.36, top5 = 52.29, top10 = 47.72, top15 = 44.95.
+PHY-3001 : End congestion estimation; 1.999321s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (132.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73235, tnet num: 17901, tinst num: 6845, tnode num: 96087, tedge num: 122015.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.620492s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.3%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 625 MB, peak memory is 741 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17901 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.487187s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.92845e-05
+PHY-3002 : Step(293): len = 654641, overlap = 243.5
+PHY-3002 : Step(294): len = 649023, overlap = 247.25
+PHY-3002 : Step(295): len = 645982, overlap = 244.25
+PHY-3002 : Step(296): len = 643392, overlap = 243.25
+PHY-3002 : Step(297): len = 640634, overlap = 246.25
+PHY-3002 : Step(298): len = 638370, overlap = 248.5
+PHY-3002 : Step(299): len = 635500, overlap = 258.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.85691e-05
+PHY-3002 : Step(300): len = 638544, overlap = 249.25
+PHY-3002 : Step(301): len = 641551, overlap = 247.75
+PHY-3002 : Step(302): len = 641451, overlap = 247.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000197138
+PHY-3002 : Step(303): len = 650532, overlap = 227
+PHY-3002 : Step(304): len = 658358, overlap = 217.5
+PHY-3002 : Step(305): len = 656278, overlap = 219.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.382250s wall, 0.296875s user + 0.687500s system = 0.984375s CPU (257.5%)
+
+PHY-3001 : Trial Legalized: Len = 748753
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 964/18079.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863640, over cnt = 2785(7%), over = 4809, worst = 9
+PHY-1002 : len = 882168, over cnt = 1638(4%), over = 2469, worst = 9
+PHY-1002 : len = 900352, over cnt = 645(1%), over = 939, worst = 6
+PHY-1002 : len = 909448, over cnt = 236(0%), over = 375, worst = 4
+PHY-1002 : len = 916168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.380230s wall, 3.406250s user + 0.062500s system = 3.468750s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 55.06, top5 = 49.92, top10 = 47.07, top15 = 45.12.
+PHY-3001 : End congestion estimation; 2.846845s wall, 3.859375s user + 0.078125s system = 3.937500s CPU (138.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17901 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.849033s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000163947
+PHY-3002 : Step(306): len = 719720, overlap = 38
+PHY-3002 : Step(307): len = 701798, overlap = 70.25
+PHY-3002 : Step(308): len = 686942, overlap = 99.5
+PHY-3002 : Step(309): len = 678676, overlap = 111.75
+PHY-3002 : Step(310): len = 672305, overlap = 137.5
+PHY-3002 : Step(311): len = 669594, overlap = 154.5
+PHY-3002 : Step(312): len = 667642, overlap = 170.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000327894
+PHY-3002 : Step(313): len = 672339, overlap = 162.75
+PHY-3002 : Step(314): len = 676718, overlap = 160
+PHY-3002 : Step(315): len = 676712, overlap = 162.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000655787
+PHY-3002 : Step(316): len = 680952, overlap = 157.75
+PHY-3002 : Step(317): len = 688994, overlap = 156
+PHY-3002 : Step(318): len = 689746, overlap = 152
+PHY-3002 : Step(319): len = 691197, overlap = 150
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.036191s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (129.5%)
+
+PHY-3001 : Legalized: Len = 721832, Over = 0
+PHY-3001 : Spreading special nets. 490 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.104383s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (104.8%)
+
+PHY-3001 : 709 instances has been re-located, deltaX = 228, deltaY = 428, maxDist = 4.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 733686, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73235, tnet num: 17901, tinst num: 6848, tnode num: 96087, tedge num: 122015.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.855137s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (100.2%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 647 MB, peak memory is 741 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3425/18079.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858640, over cnt = 2650(7%), over = 4371, worst = 8
+PHY-1002 : len = 874504, over cnt = 1624(4%), over = 2351, worst = 8
+PHY-1002 : len = 889128, over cnt = 819(2%), over = 1214, worst = 8
+PHY-1002 : len = 902088, over cnt = 206(0%), over = 298, worst = 5
+PHY-1002 : len = 906264, over cnt = 34(0%), over = 43, worst = 3
+PHY-1001 : End global iterations; 1.996617s wall, 2.921875s user + 0.015625s system = 2.937500s CPU (147.1%)
+
+PHY-1001 : Congestion index: top1 = 53.12, top5 = 48.37, top10 = 45.80, top15 = 44.07.
+PHY-1001 : End incremental global routing; 2.385928s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (139.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17901 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.863555s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.5%)
+
+OPT-1001 : 2 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6758 has valid locations, 11 needs to be replaced
+PHY-3001 : design contains 6857 instances, 6708 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3721 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735639
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16494/18086.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908904, over cnt = 76(0%), over = 89, worst = 3
+PHY-1002 : len = 908984, over cnt = 35(0%), over = 39, worst = 3
+PHY-1002 : len = 909344, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 909480, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 909480, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.799475s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.6%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.43, top10 = 45.86, top15 = 44.15.
+PHY-3001 : End congestion estimation; 1.133770s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (102.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73316, tnet num: 17908, tinst num: 6857, tnode num: 96195, tedge num: 122121.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.895897s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.7%)
+
+RUN-1004 : used memory is 663 MB, reserved memory is 673 MB, peak memory is 741 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17908 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.792740s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(320): len = 735144, overlap = 0
+PHY-3002 : Step(321): len = 735144, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16488/18086.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908352, over cnt = 27(0%), over = 40, worst = 5
+PHY-1002 : len = 908176, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 908256, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 908432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.602757s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (101.1%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.45, top10 = 45.86, top15 = 44.10.
+PHY-3001 : End congestion estimation; 0.922655s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (101.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17908 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.151686s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000214685
+PHY-3002 : Step(322): len = 735172, overlap = 1.25
+PHY-3002 : Step(323): len = 735172, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005925s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 735263, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060779s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 735271, Over = 0
+PHY-3001 : End incremental placement; 6.490199s wall, 6.500000s user + 0.078125s system = 6.578125s CPU (101.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.220517s wall, 11.140625s user + 0.140625s system = 11.281250s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 744, peak = 746.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16487/18086.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908616, over cnt = 27(0%), over = 31, worst = 3
+PHY-1002 : len = 908648, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 908728, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 908752, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 908800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.776269s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (108.7%)
+
+PHY-1001 : Congestion index: top1 = 53.06, top5 = 48.39, top10 = 45.82, top15 = 44.10.
+OPT-1001 : End congestion update; 1.095821s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17908 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.719908s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.8%)
+
+OPT-0007 : Start: WNS -29 TNS -29 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6769 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6857 instances, 6708 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3721 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 742729, Over = 0
+PHY-3001 : Spreading special nets. 24 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062976s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.2%)
+
+PHY-3001 : 33 instances has been re-located, deltaX = 7, deltaY = 32, maxDist = 3.
+PHY-3001 : Final: Len = 743307, Over = 0
+PHY-3001 : End incremental legalization; 0.393940s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (126.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 68 cells processed and 21492 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6769 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6857 instances, 6708 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3721 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 743541, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061860s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.0%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 5, deltaY = 18, maxDist = 3.
+PHY-3001 : Final: Len = 743833, Over = 0
+PHY-3001 : End incremental legalization; 0.390562s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.0%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 25 cells processed and 2496 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6769 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6857 instances, 6708 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3721 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 743541, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062207s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 12, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 744235, Over = 0
+PHY-3001 : End incremental legalization; 0.395144s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (106.8%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 18 cells processed and 1452 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6773 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6861 instances, 6712 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3721 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744397, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.065351s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.6%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 0, deltaY = 4, maxDist = 1.
+PHY-3001 : Final: Len = 744459, Over = 0
+PHY-3001 : End incremental legalization; 0.411286s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.8%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 4 cells processed and 400 slack improved
+OPT-1001 : End bottleneck based optimization; 4.001458s wall, 4.281250s user + 0.015625s system = 4.296875s CPU (107.4%)
+
+OPT-1001 : Current memory(MB): used = 744, reserve = 746, peak = 747.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16081/18087.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 917648, over cnt = 213(0%), over = 279, worst = 5
+PHY-1002 : len = 918144, over cnt = 102(0%), over = 118, worst = 4
+PHY-1002 : len = 918696, over cnt = 60(0%), over = 65, worst = 2
+PHY-1002 : len = 919448, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 919496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.938081s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 53.08, top5 = 48.30, top10 = 45.79, top15 = 44.07.
+OPT-1001 : End congestion update; 1.273233s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (105.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17908 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.714074s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.5%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6773 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6861 instances, 6712 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3721 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 744387, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.061444s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 1, deltaY = 14, maxDist = 3.
+PHY-3001 : Final: Len = 744693, Over = 0
+PHY-3001 : End incremental legalization; 0.387947s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.7%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 20 cells processed and 2100 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.508622s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (102.8%)
+
+OPT-1001 : Current memory(MB): used = 744, reserve = 746, peak = 747.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17908 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.731817s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16407/18087.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919408, over cnt = 39(0%), over = 50, worst = 4
+PHY-1002 : len = 919584, over cnt = 19(0%), over = 21, worst = 3
+PHY-1002 : len = 919656, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 919792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.632915s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (111.1%)
+
+PHY-1001 : Congestion index: top1 = 52.87, top5 = 48.13, top10 = 45.66, top15 = 43.99.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17908 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.717654s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.482759
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 21.236946s wall, 22.546875s user + 0.171875s system = 22.718750s CPU (107.0%)
+
+RUN-1003 : finish command "place" in 66.818897s wall, 97.484375s user + 6.343750s system = 103.828125s CPU (155.4%)
+
+RUN-1004 : used memory is 689 MB, reserved memory is 696 MB, peak memory is 747 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.705659s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (173.1%)
+
+RUN-1004 : used memory is 689 MB, reserved memory is 696 MB, peak memory is 747 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6863 instances
+RUN-1001 : 3359 mslices, 3353 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18087 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10070 nets have 2 pins
+RUN-1001 : 6566 nets have [3 - 5] pins
+RUN-1001 : 804 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 329 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73355, tnet num: 17909, tinst num: 6861, tnode num: 96247, tedge num: 122171.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.616343s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.5%)
+
+RUN-1004 : used memory is 667 MB, reserved memory is 671 MB, peak memory is 747 MB
+PHY-1001 : 3359 mslices, 3353 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17909 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 849560, over cnt = 2783(7%), over = 4612, worst = 8
+PHY-1002 : len = 867688, over cnt = 1727(4%), over = 2535, worst = 8
+PHY-1002 : len = 886424, over cnt = 753(2%), over = 1052, worst = 5
+PHY-1002 : len = 902696, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 902984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.835602s wall, 4.062500s user + 0.031250s system = 4.093750s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 53.08, top5 = 47.58, top10 = 45.03, top15 = 43.38.
+PHY-1001 : End global routing; 3.163949s wall, 4.406250s user + 0.031250s system = 4.437500s CPU (140.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 719, reserve = 722, peak = 747.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 990, reserve = 990, peak = 990.
+PHY-1001 : End build detailed router design. 3.958561s wall, 3.890625s user + 0.078125s system = 3.968750s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266936, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.980944s wall, 4.968750s user + 0.000000s system = 4.968750s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266992, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.432541s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.1%)
+
+PHY-1001 : Current memory(MB): used = 1026, reserve = 1027, peak = 1026.
+PHY-1001 : End phase 1; 5.425686s wall, 5.421875s user + 0.000000s system = 5.421875s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.32822e+06, over cnt = 1665(0%), over = 1672, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1043, peak = 1042.
+PHY-1001 : End initial routed; 23.848713s wall, 58.859375s user + 0.265625s system = 59.125000s CPU (247.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 34/17009(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -1.304 | -2.088 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.323301s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1053, peak = 1052.
+PHY-1001 : End phase 2; 27.172090s wall, 62.187500s user + 0.265625s system = 62.453125s CPU (229.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 10 pins with SWNS -0.672ns STNS -1.333ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.158021s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.9%)
+
+PHY-1022 : len = 2.32826e+06, over cnt = 1675(0%), over = 1682, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.416374s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3038e+06, over cnt = 584(0%), over = 584, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.265367s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (186.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.3037e+06, over cnt = 154(0%), over = 154, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.534646s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (146.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.30498e+06, over cnt = 17(0%), over = 17, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.337240s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (139.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.30505e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.203087s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.30494e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.184636s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 28/17009(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.672 | -1.333 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.232484s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 483 feed throughs used by 381 nets
+PHY-1001 : End commit to database; 2.279944s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1157, peak = 1152.
+PHY-1001 : End phase 3; 8.873221s wall, 10.328125s user + 0.000000s system = 10.328125s CPU (116.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.672ns STNS -1.333ns FEP 2.
+PHY-1001 : End OPT Iter 1; 0.157415s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.3%)
+
+PHY-1022 : len = 2.30494e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.394367s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.672ns, -1.333ns, 2}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.30494e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.163040s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (105.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 29/17009(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.692 | -1.353 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.369552s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1166, peak = 1161.
+PHY-1001 : End phase 4; 3.974570s wall, 3.968750s user + 0.000000s system = 3.968750s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.30494e+06
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1166, peak = 1161.
+PHY-1001 : End export database. 0.062425s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-1001 : End detail routing; 49.866583s wall, 86.234375s user + 0.343750s system = 86.578125s CPU (173.6%)
+
+RUN-1003 : finish command "route" in 55.710050s wall, 93.281250s user + 0.406250s system = 93.687500s CPU (168.2%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1092 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10356 out of 19600 52.84%
+#reg 9622 out of 19600 49.09%
+#le 12497
+ #lut only 2875 out of 12497 23.01%
+ #reg only 2141 out of 12497 17.13%
+ #lut® 7481 out of 12497 59.86%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1798
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1463
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1369
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 946
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 137
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 72
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 28
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice u_bus_top/reg2_syn_226.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_531.f0 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P16 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P140 LVCMOS33 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P35 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P70 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P146 LVCMOS33 8 N/A NONE
+ scan_out OUTPUT P166 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P11 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12497 |9327 |1029 |9654 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |556 |459 |23 |456 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |104 |90 |4 |94 |4 |0 |
+| U_crc16_24b |crc16_24b |52 |52 |0 |28 |0 |0 |
+| U_ecc_gen |ecc_gen |7 |7 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |757 |385 |96 |568 |0 |0 |
+| u_ADconfig |AD_config |180 |116 |25 |135 |0 |0 |
+| u_gen_sp |gen_sp |266 |157 |71 |122 |0 |0 |
+| exdev_ctl_b |exdev_ctl |751 |413 |96 |568 |0 |0 |
+| u_ADconfig |AD_config |172 |131 |25 |127 |0 |0 |
+| u_gen_sp |gen_sp |259 |148 |71 |121 |0 |0 |
+| sampling_fe_a |sampling_fe |2994 |2410 |306 |2104 |25 |0 |
+| u0_soft_n |cdc_sync |5 |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |184 |132 |17 |155 |0 |0 |
+| u0_soft_n |cdc_sync |3 |3 |0 |3 |0 |0 |
+| u_sort |sort |2775 |2269 |289 |1914 |25 |0 |
+| rddpram_ctl |rddpram_ctl |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |5 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2352 |1946 |253 |1564 |22 |0 |
+| channelPart |channel_part_8478 |132 |127 |3 |120 |0 |0 |
+| fifo_adc |fifo_adc |57 |48 |9 |43 |0 |0 |
+| ram_switch |ram_switch |1859 |1537 |197 |1176 |0 |0 |
+| adc_addr_gen |adc_addr_gen |244 |214 |27 |126 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |6 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |29 |26 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |21 |18 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |30 |27 |3 |13 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |28 |25 |3 |12 |0 |0 |
+| insert |insert |968 |677 |170 |667 |0 |0 |
+| ram_switch_state |ram_switch_state |647 |646 |0 |383 |0 |0 |
+| read_ram_i |read_ram |270 |210 |44 |193 |0 |0 |
+| read_ram_addr |read_ram_addr |218 |178 |40 |151 |0 |0 |
+| read_ram_data |read_ram_data |49 |30 |4 |39 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |342 |246 |36 |279 |3 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3197 |2574 |343 |2104 |25 |1 |
+| u0_soft_n |cdc_sync |7 |4 |0 |7 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |117 |17 |160 |0 |0 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_sort |sort_rev |2971 |2429 |326 |1907 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |1 |0 |1 |0 |0 |
+| u0_wrsoft_n |cdc_sync |5 |4 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2570 |2121 |284 |1563 |22 |1 |
+| channelPart |channel_part_8478 |159 |155 |3 |140 |0 |0 |
+| fifo_adc |fifo_adc |55 |46 |9 |40 |0 |1 |
+| ram_switch |ram_switch |1976 |1654 |197 |1141 |0 |0 |
+| adc_addr_gen |adc_addr_gen |214 |187 |27 |108 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |10 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |26 |23 |3 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |18 |15 |3 |10 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |22 |19 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 |
+| insert |insert |999 |705 |170 |679 |0 |0 |
+| ram_switch_state |ram_switch_state |763 |762 |0 |354 |0 |0 |
+| read_ram_i |read_ram_rev |344 |241 |75 |206 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |277 |199 |67 |160 |0 |0 |
+| read_ram_data |read_ram_data_rev |67 |42 |8 |46 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10008
+ #2 2 4251
+ #3 3 1749
+ #4 4 563
+ #5 5-10 843
+ #6 11-50 562
+ #7 51-100 15
+ #8 >500 1
+ Average 2.76
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.115746s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (171.3%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1093 MB, peak memory is 1161 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73355, tnet num: 17909, tinst num: 6861, tnode num: 96247, tedge num: 122171.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.613127s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.7%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1098 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17909 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.470920s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1100 MB, peak memory is 1161 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6861
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18087, pip num: 171259
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 483
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3265 valid insts, and 477019 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.734673s wall, 57.718750s user + 0.109375s system = 57.828125s CPU (594.0%)
+
+RUN-1004 : used memory is 1254 MB, reserved memory is 1255 MB, peak memory is 1369 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_162610.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_163236.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_163236.log
new file mode 100644
index 0000000..c2bd42a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240318_163236.log
@@ -0,0 +1,2001 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Mon Mar 18 16:32:36 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_16M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.207180s wall, 2.078125s user + 0.125000s system = 2.203125s CPU (99.8%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 1.5000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 1.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2303 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2144 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18121 instances
+RUN-0007 : 7665 luts, 9231 seqs, 704 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20693 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13200 nets have 2 pins
+RUN-1001 : 6451 nets have [3 - 5] pins
+RUN-1001 : 633 nets have [6 - 10] pins
+RUN-1001 : 172 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1997
+RUN-1001 : No | Yes | No | 3628
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18119 instances, 7665 luts, 9231 seqs, 1077 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6102 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84563, tnet num: 20515, tinst num: 18119, tnode num: 115304, tedge num: 134838.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.153906s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.2%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 517 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.938837s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (99.9%)
+
+PHY-3001 : Found 1250 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.1874e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18119.
+PHY-3001 : Level 1 #clusters 2066.
+PHY-3001 : End clustering; 0.241404s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (129.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.38739e+06, overlap = 467.531
+PHY-3002 : Step(2): len = 1.28121e+06, overlap = 513.375
+PHY-3002 : Step(3): len = 871879, overlap = 605.312
+PHY-3002 : Step(4): len = 791308, overlap = 661.375
+PHY-3002 : Step(5): len = 611595, overlap = 792.938
+PHY-3002 : Step(6): len = 553721, overlap = 845.625
+PHY-3002 : Step(7): len = 460104, overlap = 937.281
+PHY-3002 : Step(8): len = 426633, overlap = 953.688
+PHY-3002 : Step(9): len = 382230, overlap = 1016.75
+PHY-3002 : Step(10): len = 351881, overlap = 1072.41
+PHY-3002 : Step(11): len = 317612, overlap = 1111.03
+PHY-3002 : Step(12): len = 293863, overlap = 1136.66
+PHY-3002 : Step(13): len = 262725, overlap = 1191.03
+PHY-3002 : Step(14): len = 243495, overlap = 1232.91
+PHY-3002 : Step(15): len = 219892, overlap = 1285.88
+PHY-3002 : Step(16): len = 205499, overlap = 1345.69
+PHY-3002 : Step(17): len = 184048, overlap = 1383.59
+PHY-3002 : Step(18): len = 174161, overlap = 1410.47
+PHY-3002 : Step(19): len = 160336, overlap = 1454.66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.24058e-06
+PHY-3002 : Step(20): len = 161435, overlap = 1411.94
+PHY-3002 : Step(21): len = 197844, overlap = 1246
+PHY-3002 : Step(22): len = 199941, overlap = 1219.56
+PHY-3002 : Step(23): len = 203419, overlap = 1177.16
+PHY-3002 : Step(24): len = 201296, overlap = 1116.03
+PHY-3002 : Step(25): len = 198879, overlap = 1077.16
+PHY-3002 : Step(26): len = 198482, overlap = 1054.91
+PHY-3002 : Step(27): len = 197708, overlap = 1068.81
+PHY-3002 : Step(28): len = 194826, overlap = 1054.62
+PHY-3002 : Step(29): len = 192081, overlap = 1047.47
+PHY-3002 : Step(30): len = 190540, overlap = 1053.81
+PHY-3002 : Step(31): len = 187646, overlap = 1047.25
+PHY-3002 : Step(32): len = 185600, overlap = 1044.38
+PHY-3002 : Step(33): len = 182594, overlap = 1037.31
+PHY-3002 : Step(34): len = 181217, overlap = 1055.91
+PHY-3002 : Step(35): len = 180472, overlap = 1061.81
+PHY-3002 : Step(36): len = 179755, overlap = 1063.03
+PHY-3002 : Step(37): len = 179275, overlap = 1082.97
+PHY-3002 : Step(38): len = 178974, overlap = 1084.59
+PHY-3002 : Step(39): len = 177198, overlap = 1086.03
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.48116e-06
+PHY-3002 : Step(40): len = 182632, overlap = 1063.06
+PHY-3002 : Step(41): len = 194346, overlap = 1009.75
+PHY-3002 : Step(42): len = 198965, overlap = 975.969
+PHY-3002 : Step(43): len = 203532, overlap = 997.875
+PHY-3002 : Step(44): len = 205727, overlap = 985.875
+PHY-3002 : Step(45): len = 206083, overlap = 961.375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.96233e-06
+PHY-3002 : Step(46): len = 212601, overlap = 950.406
+PHY-3002 : Step(47): len = 229933, overlap = 881.594
+PHY-3002 : Step(48): len = 242648, overlap = 791.812
+PHY-3002 : Step(49): len = 249281, overlap = 724.656
+PHY-3002 : Step(50): len = 252306, overlap = 688.812
+PHY-3002 : Step(51): len = 253815, overlap = 679.094
+PHY-3002 : Step(52): len = 253506, overlap = 683.906
+PHY-3002 : Step(53): len = 252917, overlap = 683.438
+PHY-3002 : Step(54): len = 252053, overlap = 687.094
+PHY-3002 : Step(55): len = 251691, overlap = 691.188
+PHY-3002 : Step(56): len = 250586, overlap = 682.188
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.92466e-06
+PHY-3002 : Step(57): len = 267201, overlap = 647.344
+PHY-3002 : Step(58): len = 283398, overlap = 610.844
+PHY-3002 : Step(59): len = 289498, overlap = 553.469
+PHY-3002 : Step(60): len = 293477, overlap = 551.594
+PHY-3002 : Step(61): len = 293215, overlap = 535.219
+PHY-3002 : Step(62): len = 295142, overlap = 538.594
+PHY-3002 : Step(63): len = 294246, overlap = 535.875
+PHY-3002 : Step(64): len = 295621, overlap = 533.406
+PHY-3002 : Step(65): len = 295441, overlap = 520.219
+PHY-3002 : Step(66): len = 296102, overlap = 542.562
+PHY-3002 : Step(67): len = 295988, overlap = 530.719
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.98493e-05
+PHY-3002 : Step(68): len = 311401, overlap = 502.594
+PHY-3002 : Step(69): len = 328322, overlap = 465.812
+PHY-3002 : Step(70): len = 334336, overlap = 451.5
+PHY-3002 : Step(71): len = 336541, overlap = 436.062
+PHY-3002 : Step(72): len = 336314, overlap = 404.938
+PHY-3002 : Step(73): len = 336300, overlap = 392.094
+PHY-3002 : Step(74): len = 335751, overlap = 386.562
+PHY-3002 : Step(75): len = 336826, overlap = 370.344
+PHY-3002 : Step(76): len = 336519, overlap = 373.469
+PHY-3002 : Step(77): len = 337325, overlap = 375.875
+PHY-3002 : Step(78): len = 336666, overlap = 392.062
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.96986e-05
+PHY-3002 : Step(79): len = 354443, overlap = 353.25
+PHY-3002 : Step(80): len = 368239, overlap = 309.281
+PHY-3002 : Step(81): len = 372249, overlap = 306.688
+PHY-3002 : Step(82): len = 374549, overlap = 312.094
+PHY-3002 : Step(83): len = 377120, overlap = 288.781
+PHY-3002 : Step(84): len = 381311, overlap = 263.656
+PHY-3002 : Step(85): len = 379093, overlap = 258.531
+PHY-3002 : Step(86): len = 383024, overlap = 256.031
+PHY-3002 : Step(87): len = 384691, overlap = 282.156
+PHY-3002 : Step(88): len = 386257, overlap = 278.938
+PHY-3002 : Step(89): len = 384124, overlap = 280.938
+PHY-3002 : Step(90): len = 385815, overlap = 282.781
+PHY-3002 : Step(91): len = 385770, overlap = 267.906
+PHY-3002 : Step(92): len = 386054, overlap = 258.375
+PHY-3002 : Step(93): len = 384317, overlap = 248.875
+PHY-3002 : Step(94): len = 384154, overlap = 236.875
+PHY-3002 : Step(95): len = 383772, overlap = 244.156
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.93973e-05
+PHY-3002 : Step(96): len = 399629, overlap = 239.938
+PHY-3002 : Step(97): len = 409911, overlap = 237.844
+PHY-3002 : Step(98): len = 408324, overlap = 220.219
+PHY-3002 : Step(99): len = 410395, overlap = 221.469
+PHY-3002 : Step(100): len = 412485, overlap = 220.344
+PHY-3002 : Step(101): len = 415341, overlap = 231.625
+PHY-3002 : Step(102): len = 413329, overlap = 238.938
+PHY-3002 : Step(103): len = 417489, overlap = 237.75
+PHY-3002 : Step(104): len = 421259, overlap = 247.188
+PHY-3002 : Step(105): len = 424273, overlap = 246.156
+PHY-3002 : Step(106): len = 421354, overlap = 250.312
+PHY-3002 : Step(107): len = 420918, overlap = 250.25
+PHY-3002 : Step(108): len = 421674, overlap = 249.938
+PHY-3002 : Step(109): len = 423079, overlap = 250.469
+PHY-3002 : Step(110): len = 420183, overlap = 246
+PHY-3002 : Step(111): len = 420419, overlap = 238
+PHY-3002 : Step(112): len = 422361, overlap = 234.406
+PHY-3002 : Step(113): len = 424512, overlap = 225.062
+PHY-3002 : Step(114): len = 421949, overlap = 213.969
+PHY-3002 : Step(115): len = 422095, overlap = 207.781
+PHY-3002 : Step(116): len = 423150, overlap = 206.25
+PHY-3002 : Step(117): len = 423680, overlap = 204.719
+PHY-3002 : Step(118): len = 420991, overlap = 210.125
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000157979
+PHY-3002 : Step(119): len = 435320, overlap = 195.969
+PHY-3002 : Step(120): len = 443001, overlap = 187.188
+PHY-3002 : Step(121): len = 441656, overlap = 189.469
+PHY-3002 : Step(122): len = 442056, overlap = 193
+PHY-3002 : Step(123): len = 444825, overlap = 195.375
+PHY-3002 : Step(124): len = 447408, overlap = 196.375
+PHY-3002 : Step(125): len = 446438, overlap = 191.375
+PHY-3002 : Step(126): len = 446663, overlap = 187.75
+PHY-3002 : Step(127): len = 448565, overlap = 185.656
+PHY-3002 : Step(128): len = 450480, overlap = 181.344
+PHY-3002 : Step(129): len = 448416, overlap = 181.906
+PHY-3002 : Step(130): len = 447958, overlap = 180.969
+PHY-3002 : Step(131): len = 448847, overlap = 176.438
+PHY-3002 : Step(132): len = 449514, overlap = 165.938
+PHY-3002 : Step(133): len = 448415, overlap = 167.719
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000307215
+PHY-3002 : Step(134): len = 456445, overlap = 162.688
+PHY-3002 : Step(135): len = 463442, overlap = 158.062
+PHY-3002 : Step(136): len = 464829, overlap = 147.188
+PHY-3002 : Step(137): len = 466546, overlap = 146.5
+PHY-3002 : Step(138): len = 469177, overlap = 147.156
+PHY-3002 : Step(139): len = 470752, overlap = 147.094
+PHY-3002 : Step(140): len = 469107, overlap = 147.625
+PHY-3002 : Step(141): len = 469386, overlap = 148.844
+PHY-3002 : Step(142): len = 471673, overlap = 147.406
+PHY-3002 : Step(143): len = 473315, overlap = 146.125
+PHY-3002 : Step(144): len = 472193, overlap = 142.656
+PHY-3002 : Step(145): len = 472327, overlap = 144.188
+PHY-3002 : Step(146): len = 473278, overlap = 153.531
+PHY-3002 : Step(147): len = 473764, overlap = 153.375
+PHY-3002 : Step(148): len = 473995, overlap = 145.312
+PHY-3002 : Step(149): len = 475619, overlap = 144.281
+PHY-3002 : Step(150): len = 476646, overlap = 147.062
+PHY-3002 : Step(151): len = 477447, overlap = 144.344
+PHY-3002 : Step(152): len = 475766, overlap = 146.781
+PHY-3002 : Step(153): len = 475164, overlap = 146.875
+PHY-3002 : Step(154): len = 475848, overlap = 146.969
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000598141
+PHY-3002 : Step(155): len = 482219, overlap = 149.094
+PHY-3002 : Step(156): len = 487680, overlap = 149.406
+PHY-3002 : Step(157): len = 487831, overlap = 147.938
+PHY-3002 : Step(158): len = 488388, overlap = 144.625
+PHY-3002 : Step(159): len = 491218, overlap = 148.688
+PHY-3002 : Step(160): len = 493679, overlap = 143.062
+PHY-3002 : Step(161): len = 493734, overlap = 143.688
+PHY-3002 : Step(162): len = 494303, overlap = 142.875
+PHY-3002 : Step(163): len = 495758, overlap = 146.938
+PHY-3002 : Step(164): len = 496401, overlap = 144.875
+PHY-3002 : Step(165): len = 495852, overlap = 141.844
+PHY-3002 : Step(166): len = 495742, overlap = 139.844
+PHY-3002 : Step(167): len = 496601, overlap = 138.781
+PHY-3002 : Step(168): len = 497398, overlap = 139.594
+PHY-3002 : Step(169): len = 496985, overlap = 136.844
+PHY-3002 : Step(170): len = 497015, overlap = 136.844
+PHY-3002 : Step(171): len = 497913, overlap = 136.031
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00107645
+PHY-3002 : Step(172): len = 501059, overlap = 132.219
+PHY-3002 : Step(173): len = 505554, overlap = 130.531
+PHY-3002 : Step(174): len = 506753, overlap = 128.938
+PHY-3002 : Step(175): len = 508040, overlap = 129.062
+PHY-3002 : Step(176): len = 510724, overlap = 129.344
+PHY-3002 : Step(177): len = 512954, overlap = 130.875
+PHY-3002 : Step(178): len = 513167, overlap = 129.844
+PHY-3002 : Step(179): len = 513290, overlap = 132.812
+PHY-3002 : Step(180): len = 513623, overlap = 134.312
+PHY-3002 : Step(181): len = 513922, overlap = 130.281
+PHY-3002 : Step(182): len = 513958, overlap = 133.656
+PHY-3002 : Step(183): len = 514392, overlap = 130.188
+PHY-3002 : Step(184): len = 514953, overlap = 132.875
+PHY-3002 : Step(185): len = 515045, overlap = 132.875
+PHY-3002 : Step(186): len = 514773, overlap = 129
+PHY-3002 : Step(187): len = 514948, overlap = 128.5
+PHY-3002 : Step(188): len = 515478, overlap = 128.781
+PHY-3002 : Step(189): len = 515692, overlap = 129.156
+PHY-3002 : Step(190): len = 515646, overlap = 130.625
+PHY-3002 : Step(191): len = 515736, overlap = 130.656
+PHY-3002 : Step(192): len = 516181, overlap = 129.5
+PHY-3002 : Step(193): len = 516181, overlap = 129.5
+PHY-3002 : Step(194): len = 516004, overlap = 129.219
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.013602s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (344.6%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 684120, over cnt = 1527(4%), over = 7128, worst = 49
+PHY-1001 : End global iterations; 0.678265s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (135.9%)
+
+PHY-1001 : Congestion index: top1 = 80.99, top5 = 61.28, top10 = 52.14, top15 = 46.20.
+PHY-3001 : End congestion estimation; 0.916332s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (126.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.846857s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000127761
+PHY-3002 : Step(195): len = 630264, overlap = 88
+PHY-3002 : Step(196): len = 633459, overlap = 78.9062
+PHY-3002 : Step(197): len = 627546, overlap = 75
+PHY-3002 : Step(198): len = 624532, overlap = 70.875
+PHY-3002 : Step(199): len = 623860, overlap = 65.8438
+PHY-3002 : Step(200): len = 624532, overlap = 59.1875
+PHY-3002 : Step(201): len = 623493, overlap = 56.3125
+PHY-3002 : Step(202): len = 622604, overlap = 57.6875
+PHY-3002 : Step(203): len = 619913, overlap = 56.3438
+PHY-3002 : Step(204): len = 619171, overlap = 55
+PHY-3002 : Step(205): len = 615614, overlap = 52.125
+PHY-3002 : Step(206): len = 614226, overlap = 48.0312
+PHY-3002 : Step(207): len = 612115, overlap = 46.1875
+PHY-3002 : Step(208): len = 610816, overlap = 41.4062
+PHY-3002 : Step(209): len = 610073, overlap = 38.3125
+PHY-3002 : Step(210): len = 609158, overlap = 38.5938
+PHY-3002 : Step(211): len = 609920, overlap = 37.8438
+PHY-3002 : Step(212): len = 608922, overlap = 42.1562
+PHY-3002 : Step(213): len = 608529, overlap = 43.0938
+PHY-3002 : Step(214): len = 607928, overlap = 42.1875
+PHY-3002 : Step(215): len = 607055, overlap = 41.5625
+PHY-3002 : Step(216): len = 605774, overlap = 43.3125
+PHY-3002 : Step(217): len = 605029, overlap = 42.25
+PHY-3002 : Step(218): len = 603254, overlap = 42.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000255522
+PHY-3002 : Step(219): len = 604713, overlap = 40.8438
+PHY-3002 : Step(220): len = 607226, overlap = 41.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 115/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 686752, over cnt = 2669(7%), over = 11447, worst = 49
+PHY-1001 : End global iterations; 1.730091s wall, 2.375000s user + 0.078125s system = 2.453125s CPU (141.8%)
+
+PHY-1001 : Congestion index: top1 = 82.82, top5 = 65.43, top10 = 56.72, top15 = 51.61.
+PHY-3001 : End congestion estimation; 2.033400s wall, 2.671875s user + 0.078125s system = 2.750000s CPU (135.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.888893s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.61979e-05
+PHY-3002 : Step(221): len = 604888, overlap = 282.188
+PHY-3002 : Step(222): len = 608624, overlap = 232.375
+PHY-3002 : Step(223): len = 607138, overlap = 219.031
+PHY-3002 : Step(224): len = 604227, overlap = 209
+PHY-3002 : Step(225): len = 604882, overlap = 195.125
+PHY-3002 : Step(226): len = 602902, overlap = 188.031
+PHY-3002 : Step(227): len = 599512, overlap = 166.312
+PHY-3002 : Step(228): len = 598422, overlap = 154.719
+PHY-3002 : Step(229): len = 596358, overlap = 144.938
+PHY-3002 : Step(230): len = 594073, overlap = 142.406
+PHY-3002 : Step(231): len = 593884, overlap = 144.5
+PHY-3002 : Step(232): len = 591236, overlap = 143
+PHY-3002 : Step(233): len = 588497, overlap = 134.25
+PHY-3002 : Step(234): len = 585195, overlap = 133.75
+PHY-3002 : Step(235): len = 583427, overlap = 132.125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000172396
+PHY-3002 : Step(236): len = 583799, overlap = 128.156
+PHY-3002 : Step(237): len = 585710, overlap = 125.375
+PHY-3002 : Step(238): len = 589012, overlap = 123.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000344791
+PHY-3002 : Step(239): len = 593365, overlap = 119.688
+PHY-3002 : Step(240): len = 598718, overlap = 116.281
+PHY-3002 : Step(241): len = 604373, overlap = 110.688
+PHY-3002 : Step(242): len = 606008, overlap = 109.219
+PHY-3002 : Step(243): len = 608139, overlap = 101.531
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84563, tnet num: 20515, tinst num: 18119, tnode num: 115304, tedge num: 134838.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.438901s wall, 1.375000s user + 0.062500s system = 1.437500s CPU (99.9%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 564 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 427.75 peak overflow 4.50
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1177/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 699464, over cnt = 2977(8%), over = 11001, worst = 32
+PHY-1001 : End global iterations; 1.120756s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (153.4%)
+
+PHY-1001 : Congestion index: top1 = 74.81, top5 = 58.30, top10 = 51.78, top15 = 48.00.
+PHY-1001 : End incremental global routing; 1.443801s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (141.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.907579s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.9%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17986 has valid locations, 311 needs to be replaced
+PHY-3001 : design contains 18382 instances, 7759 luts, 9400 seqs, 1077 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6213 pins
+PHY-3001 : Found 1261 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 630318
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16954/20956.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712584, over cnt = 2992(8%), over = 11008, worst = 32
+PHY-1001 : End global iterations; 0.219153s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (128.3%)
+
+PHY-1001 : Congestion index: top1 = 74.85, top5 = 58.63, top10 = 52.06, top15 = 48.34.
+PHY-3001 : End congestion estimation; 0.470078s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (113.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85600, tnet num: 20778, tinst num: 18382, tnode num: 116862, tedge num: 136386.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.452424s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.0%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 613 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20778 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.398634s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(244): len = 629157, overlap = 0.5625
+PHY-3002 : Step(245): len = 628692, overlap = 0.5625
+PHY-3002 : Step(246): len = 628435, overlap = 0.625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17065/20956.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709952, over cnt = 3011(8%), over = 11073, worst = 32
+PHY-1001 : End global iterations; 0.182622s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (154.0%)
+
+PHY-1001 : Congestion index: top1 = 75.34, top5 = 58.99, top10 = 52.31, top15 = 48.48.
+PHY-3001 : End congestion estimation; 0.435709s wall, 0.515625s user + 0.015625s system = 0.531250s CPU (121.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20778 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.956992s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000453737
+PHY-3002 : Step(247): len = 628254, overlap = 104.5
+PHY-3002 : Step(248): len = 628442, overlap = 104.062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000907474
+PHY-3002 : Step(249): len = 628611, overlap = 103.906
+PHY-3002 : Step(250): len = 629330, overlap = 103.969
+PHY-3001 : Final: Len = 629330, Over = 103.969
+PHY-3001 : End incremental placement; 4.931725s wall, 5.296875s user + 0.234375s system = 5.531250s CPU (112.2%)
+
+OPT-1001 : Total overflow 433.25 peak overflow 4.50
+OPT-1001 : End high-fanout net optimization; 7.851385s wall, 8.875000s user + 0.250000s system = 9.125000s CPU (116.2%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 710, peak = 733.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17010/20956.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 713528, over cnt = 2975(8%), over = 10110, worst = 32
+PHY-1002 : len = 764056, over cnt = 2162(6%), over = 5490, worst = 32
+PHY-1002 : len = 817800, over cnt = 739(2%), over = 1479, worst = 13
+PHY-1002 : len = 834248, over cnt = 260(0%), over = 488, worst = 11
+PHY-1002 : len = 841280, over cnt = 28(0%), over = 64, worst = 8
+PHY-1001 : End global iterations; 1.895511s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (135.2%)
+
+PHY-1001 : Congestion index: top1 = 58.49, top5 = 51.15, top10 = 47.34, top15 = 44.90.
+OPT-1001 : End congestion update; 2.154843s wall, 2.812500s user + 0.015625s system = 2.828125s CPU (131.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20778 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 1.091632s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (100.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 101 cells processed and 16300 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 39 cells processed and 3600 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 14 cells processed and 900 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 250 slack improved
+OPT-1001 : End bottleneck based optimization; 3.664563s wall, 4.312500s user + 0.015625s system = 4.328125s CPU (118.1%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 691, peak = 733.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17077/20957.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842760, over cnt = 98(0%), over = 160, worst = 8
+PHY-1002 : len = 842520, over cnt = 66(0%), over = 82, worst = 7
+PHY-1002 : len = 842864, over cnt = 10(0%), over = 12, worst = 3
+PHY-1002 : len = 843056, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 843104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.747277s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 58.00, top5 = 50.95, top10 = 47.26, top15 = 44.88.
+OPT-1001 : End congestion update; 1.017581s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (104.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20779 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.793367s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.4%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 22 cells processed and 6500 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.935382s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (102.5%)
+
+OPT-1001 : Current memory(MB): used = 706, reserve = 701, peak = 733.
+OPT-1001 : End physical optimization; 15.206814s wall, 16.953125s user + 0.328125s system = 17.281250s CPU (113.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7759 LUT to BLE ...
+SYN-4008 : Packed 7759 LUT and 3142 SEQ to BLE.
+SYN-4003 : Packing 6259 remaining SEQ's ...
+SYN-4005 : Packed 3938 SEQ with LUT/SLICE
+SYN-4006 : 986 single LUT's are left
+SYN-4006 : 2321 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10080/13869 primitive instances ...
+PHY-3001 : End packing; 1.646849s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6815 instances
+RUN-1001 : 3333 mslices, 3334 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17946 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10084 nets have 2 pins
+RUN-1001 : 6497 nets have [3 - 5] pins
+RUN-1001 : 739 nets have [6 - 10] pins
+RUN-1001 : 301 nets have [11 - 20] pins
+RUN-1001 : 292 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6813 instances, 6667 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3598 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 643592, Over = 257.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7797/17946.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 796480, over cnt = 1995(5%), over = 3312, worst = 9
+PHY-1002 : len = 804512, over cnt = 1374(3%), over = 2016, worst = 9
+PHY-1002 : len = 815680, over cnt = 726(2%), over = 1045, worst = 7
+PHY-1002 : len = 823368, over cnt = 428(1%), over = 621, worst = 6
+PHY-1002 : len = 834280, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.837447s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (133.5%)
+
+PHY-1001 : Congestion index: top1 = 58.53, top5 = 51.20, top10 = 47.59, top15 = 45.08.
+PHY-3001 : End congestion estimation; 2.225297s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (128.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71708, tnet num: 17768, tinst num: 6813, tnode num: 94298, tedge num: 119172.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.594348s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.0%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 612 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17768 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.441434s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.95944e-05
+PHY-3002 : Step(251): len = 632506, overlap = 259.25
+PHY-3002 : Step(252): len = 626186, overlap = 251.5
+PHY-3002 : Step(253): len = 621930, overlap = 247.5
+PHY-3002 : Step(254): len = 619120, overlap = 255.75
+PHY-3002 : Step(255): len = 616621, overlap = 262.75
+PHY-3002 : Step(256): len = 615508, overlap = 269.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.91888e-05
+PHY-3002 : Step(257): len = 616191, overlap = 265.5
+PHY-3002 : Step(258): len = 621145, overlap = 248.25
+PHY-3002 : Step(259): len = 625438, overlap = 243.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000198378
+PHY-3002 : Step(260): len = 629850, overlap = 239.5
+PHY-3002 : Step(261): len = 635666, overlap = 237.75
+PHY-3002 : Step(262): len = 636877, overlap = 234
+PHY-3002 : Step(263): len = 638621, overlap = 219.5
+PHY-3002 : Step(264): len = 640021, overlap = 216.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.353154s wall, 0.312500s user + 0.625000s system = 0.937500s CPU (265.5%)
+
+PHY-3001 : Trial Legalized: Len = 723951
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 1068/17946.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 834320, over cnt = 2664(7%), over = 4485, worst = 8
+PHY-1002 : len = 851616, over cnt = 1492(4%), over = 2166, worst = 7
+PHY-1002 : len = 869960, over cnt = 507(1%), over = 736, worst = 7
+PHY-1002 : len = 876648, over cnt = 206(0%), over = 295, worst = 7
+PHY-1002 : len = 882496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.291736s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (148.6%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.98, top10 = 46.36, top15 = 44.38.
+PHY-3001 : End congestion estimation; 2.743594s wall, 3.828125s user + 0.015625s system = 3.843750s CPU (140.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17768 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.838997s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000163451
+PHY-3002 : Step(265): len = 697301, overlap = 38.5
+PHY-3002 : Step(266): len = 680858, overlap = 65.25
+PHY-3002 : Step(267): len = 667437, overlap = 92
+PHY-3002 : Step(268): len = 657507, overlap = 124.5
+PHY-3002 : Step(269): len = 652339, overlap = 149
+PHY-3002 : Step(270): len = 649456, overlap = 168.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000326903
+PHY-3002 : Step(271): len = 653530, overlap = 164.75
+PHY-3002 : Step(272): len = 658247, overlap = 162.25
+PHY-3002 : Step(273): len = 659398, overlap = 163.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000653805
+PHY-3002 : Step(274): len = 662106, overlap = 162.75
+PHY-3002 : Step(275): len = 669634, overlap = 158
+PHY-3002 : Step(276): len = 673469, overlap = 151.25
+PHY-3002 : Step(277): len = 673816, overlap = 151
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033590s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (93.0%)
+
+PHY-3001 : Legalized: Len = 704386, Over = 0
+PHY-3001 : Spreading special nets. 457 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.103027s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (106.2%)
+
+PHY-3001 : 673 instances has been re-located, deltaX = 240, deltaY = 390, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 715848, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71708, tnet num: 17768, tinst num: 6816, tnode num: 94298, tedge num: 119172.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.864971s wall, 1.843750s user + 0.031250s system = 1.875000s CPU (100.5%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 649 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3532/17946.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 836384, over cnt = 2447(6%), over = 4016, worst = 7
+PHY-1002 : len = 849344, over cnt = 1520(4%), over = 2254, worst = 6
+PHY-1002 : len = 869824, over cnt = 465(1%), over = 659, worst = 5
+PHY-1002 : len = 878056, over cnt = 86(0%), over = 104, worst = 4
+PHY-1002 : len = 880144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.934148s wall, 2.828125s user + 0.046875s system = 2.875000s CPU (148.6%)
+
+PHY-1001 : Congestion index: top1 = 51.72, top5 = 47.36, top10 = 44.92, top15 = 43.24.
+PHY-1001 : End incremental global routing; 2.307589s wall, 3.218750s user + 0.046875s system = 3.265625s CPU (141.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17768 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.852621s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.0%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6724 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3669 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 721743
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16308/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 887872, over cnt = 99(0%), over = 125, worst = 8
+PHY-1002 : len = 887960, over cnt = 59(0%), over = 60, worst = 2
+PHY-1002 : len = 888432, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 888712, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 888744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.781638s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 51.96, top5 = 47.50, top10 = 45.07, top15 = 43.43.
+PHY-3001 : End congestion estimation; 1.091938s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (104.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71972, tnet num: 17804, tinst num: 6839, tnode num: 94636, tedge num: 119547.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.831515s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.7%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 656 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.700360s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(278): len = 720018, overlap = 0
+PHY-3002 : Step(279): len = 720018, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16297/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 885608, over cnt = 92(0%), over = 129, worst = 6
+PHY-1002 : len = 885832, over cnt = 76(0%), over = 93, worst = 4
+PHY-1002 : len = 886648, over cnt = 11(0%), over = 12, worst = 2
+PHY-1002 : len = 886808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.604733s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (108.5%)
+
+PHY-1001 : Congestion index: top1 = 52.09, top5 = 47.53, top10 = 45.11, top15 = 43.41.
+PHY-3001 : End congestion estimation; 0.921981s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (105.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.862946s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000329524
+PHY-3002 : Step(280): len = 719571, overlap = 2.25
+PHY-3002 : Step(281): len = 719564, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005373s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 719410, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064457s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.0%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 1, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 719530, Over = 0
+PHY-3001 : End incremental placement; 6.063642s wall, 6.296875s user + 0.109375s system = 6.406250s CPU (105.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 9.697199s wall, 10.906250s user + 0.171875s system = 11.078125s CPU (114.2%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 732, peak = 735.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16287/17982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 886584, over cnt = 64(0%), over = 86, worst = 4
+PHY-1002 : len = 886696, over cnt = 32(0%), over = 34, worst = 2
+PHY-1002 : len = 886912, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 887136, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.601589s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (106.5%)
+
+PHY-1001 : Congestion index: top1 = 51.90, top5 = 47.53, top10 = 45.09, top15 = 43.41.
+OPT-1001 : End congestion update; 0.924950s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (104.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.703201s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.0%)
+
+OPT-0007 : Start: WNS -129 TNS -129 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6751 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3669 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 724990, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.060626s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.1%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 7, deltaY = 28, maxDist = 4.
+PHY-3001 : Final: Len = 725404, Over = 0
+PHY-3001 : End incremental legalization; 0.378461s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (123.9%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 52 cells processed and 16053 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6751 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3669 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 727144, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059603s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.6%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 7, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 727350, Over = 0
+PHY-3001 : End incremental legalization; 0.378433s wall, 0.390625s user + 0.046875s system = 0.437500s CPU (115.6%)
+
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 24 cells processed and 5259 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6751 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6839 instances, 6690 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3669 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 727660, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059191s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.6%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 10, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 727876, Over = 0
+PHY-3001 : End incremental legalization; 0.375964s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (99.7%)
+
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 12 cells processed and 1100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6757 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6845 instances, 6696 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3670 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 728764, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059281s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.4%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 728772, Over = 0
+PHY-3001 : End incremental legalization; 0.390999s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.9%)
+
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 5 cells processed and 800 slack improved
+OPT-1001 : End bottleneck based optimization; 3.678841s wall, 3.953125s user + 0.078125s system = 4.031250s CPU (109.6%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 732, peak = 735.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15969/17988.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896272, over cnt = 150(0%), over = 194, worst = 4
+PHY-1002 : len = 896280, over cnt = 99(0%), over = 109, worst = 3
+PHY-1002 : len = 897152, over cnt = 36(0%), over = 37, worst = 2
+PHY-1002 : len = 897584, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 897752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.834042s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (110.5%)
+
+PHY-1001 : Congestion index: top1 = 52.76, top5 = 48.01, top10 = 45.46, top15 = 43.72.
+OPT-1001 : End congestion update; 1.151106s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (108.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17810 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.710034s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.0%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6757 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6845 instances, 6696 slices, 223 macros(1077 instances: 704 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3670 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 729424, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058416s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.0%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 729782, Over = 0
+PHY-3001 : End incremental legalization; 0.381822s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.2%)
+
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 15 cells processed and 2257 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.386019s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (108.1%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 732, peak = 735.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17810 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.708853s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16280/17988.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 898520, over cnt = 45(0%), over = 53, worst = 3
+PHY-1002 : len = 898456, over cnt = 34(0%), over = 37, worst = 3
+PHY-1002 : len = 898728, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 898728, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 898848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.775160s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.8%)
+
+PHY-1001 : Congestion index: top1 = 52.72, top5 = 47.93, top10 = 45.40, top15 = 43.69.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17810 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.710201s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 171 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 52.310345
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 171ps with logic level 1
+OPT-1001 : End physical optimization; 20.391133s wall, 22.015625s user + 0.296875s system = 22.312500s CPU (109.4%)
+
+RUN-1003 : finish command "place" in 64.306709s wall, 90.390625s user + 5.593750s system = 95.984375s CPU (149.3%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 655 MB, peak memory is 735 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.701200s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (173.6%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 656 MB, peak memory is 735 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6847 instances
+RUN-1001 : 3350 mslices, 3346 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17988 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10097 nets have 2 pins
+RUN-1001 : 6498 nets have [3 - 5] pins
+RUN-1001 : 751 nets have [6 - 10] pins
+RUN-1001 : 309 nets have [11 - 20] pins
+RUN-1001 : 304 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72035, tnet num: 17810, tinst num: 6845, tnode num: 94719, tedge num: 119654.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.576875s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.1%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 629 MB, peak memory is 735 MB
+PHY-1001 : 3350 mslices, 3346 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17810 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[31] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_1d[21] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 828384, over cnt = 2726(7%), over = 4575, worst = 7
+PHY-1002 : len = 846296, over cnt = 1634(4%), over = 2390, worst = 6
+PHY-1002 : len = 868808, over cnt = 504(1%), over = 672, worst = 5
+PHY-1002 : len = 880104, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 880232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.113489s wall, 4.203125s user + 0.000000s system = 4.203125s CPU (135.0%)
+
+PHY-1001 : Congestion index: top1 = 52.74, top5 = 47.91, top10 = 45.16, top15 = 43.28.
+PHY-1001 : End global routing; 3.436233s wall, 4.515625s user + 0.000000s system = 4.515625s CPU (131.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 707, reserve = 710, peak = 735.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 983, reserve = 983, peak = 983.
+PHY-1001 : End build detailed router design. 4.020319s wall, 3.984375s user + 0.046875s system = 4.031250s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 264096, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.228865s wall, 5.218750s user + 0.000000s system = 5.218750s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 264152, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.426999s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.5%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1019, peak = 1018.
+PHY-1001 : End phase 1; 5.668176s wall, 5.656250s user + 0.000000s system = 5.656250s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.23174e+06, over cnt = 1920(0%), over = 1926, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1037, peak = 1035.
+PHY-1001 : End initial routed; 23.280748s wall, 53.109375s user + 0.375000s system = 53.484375s CPU (229.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 36/16908(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.678 | -1.384 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.234940s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1048, reserve = 1051, peak = 1048.
+PHY-1001 : End phase 2; 26.515749s wall, 56.343750s user + 0.375000s system = 56.718750s CPU (213.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 14 pins with SWNS -0.661ns STNS -1.329ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.153511s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.8%)
+
+PHY-1022 : len = 2.23177e+06, over cnt = 1924(0%), over = 1930, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.412235s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.20588e+06, over cnt = 740(0%), over = 742, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.245640s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (175.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.2029e+06, over cnt = 150(0%), over = 150, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.770845s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (148.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.20435e+06, over cnt = 12(0%), over = 12, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.286794s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (119.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.20431e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.210359s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (111.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.2044e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.163639s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (105.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 36/16908(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -1.329 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.202052s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 535 feed throughs used by 420 nets
+PHY-1001 : End commit to database; 2.202237s wall, 2.171875s user + 0.031250s system = 2.203125s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1150, reserve = 1156, peak = 1150.
+PHY-1001 : End phase 3; 8.888252s wall, 10.234375s user + 0.046875s system = 10.281250s CPU (115.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -0.661ns STNS -1.329ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.168562s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.0%)
+
+PHY-1022 : len = 2.2044e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.406664s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.661ns, -1.329ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 36/16908(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.661 | -1.329 | 3
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.199200s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 535 feed throughs used by 420 nets
+PHY-1001 : End commit to database; 2.271811s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1165, peak = 1159.
+PHY-1001 : End phase 4; 5.903087s wall, 5.890625s user + 0.000000s system = 5.890625s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.2044e+06
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1166, peak = 1160.
+PHY-1001 : End export database. 0.060012s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.1%)
+
+PHY-1001 : End detail routing; 51.442199s wall, 82.562500s user + 0.468750s system = 83.031250s CPU (161.4%)
+
+RUN-1003 : finish command "route" in 57.507503s wall, 89.703125s user + 0.468750s system = 90.171875s CPU (156.8%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1093 MB, peak memory is 1160 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10205 out of 19600 52.07%
+#reg 9598 out of 19600 48.97%
+#le 12490
+ #lut only 2892 out of 12490 23.15%
+ #reg only 2285 out of 12490 18.29%
+ #lut® 7313 out of 12490 58.55%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1772
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1444
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1336
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 934
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK lslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 138
+#6 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 72
+#7 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 71
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK mslice exdev_ctl_a/reg2_syn_167.f1 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_mipi_sot_min/reg1_syn_248.f1 3
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P170 LVCMOS33 N/A N/A NONE
+ paper_in INPUT P82 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P148 LVCMOS33 8 N/A NONE
+ frame_indicator OUTPUT P83 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P16 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P71 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P66 LVCMOS25 8 N/A NONE
+ sys_initial_done OUTPUT P32 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12490 |9176 |1029 |9630 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |530 |455 |23 |430 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |103 |89 |4 |89 |4 |0 |
+| U_crc16_24b |crc16_24b |43 |43 |0 |22 |0 |0 |
+| U_ecc_gen |ecc_gen |9 |9 |0 |6 |0 |0 |
+| exdev_ctl_a |exdev_ctl |756 |352 |96 |573 |0 |0 |
+| u_ADconfig |AD_config |185 |122 |25 |139 |0 |0 |
+| u_gen_sp |gen_sp |257 |153 |71 |120 |0 |0 |
+| exdev_ctl_b |exdev_ctl |737 |434 |96 |558 |0 |0 |
+| u_ADconfig |AD_config |172 |123 |25 |128 |0 |0 |
+| u_gen_sp |gen_sp |254 |163 |71 |119 |0 |0 |
+| sampling_fe_a |sampling_fe |2984 |2452 |306 |2097 |25 |0 |
+| u0_soft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u_ad_sampling |ad_sampling |193 |137 |17 |164 |0 |0 |
+| u0_soft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u_sort |sort |2758 |2301 |289 |1900 |25 |0 |
+| rddpram_ctl |rddpram_ctl |4 |4 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |6 |3 |0 |6 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2357 |1993 |253 |1557 |22 |0 |
+| channelPart |channel_part_8478 |129 |116 |3 |125 |0 |0 |
+| fifo_adc |fifo_adc |63 |54 |9 |48 |0 |0 |
+| ram_switch |ram_switch |1869 |1586 |197 |1169 |0 |0 |
+| adc_addr_gen |adc_addr_gen |231 |204 |27 |127 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |12 |9 |3 |8 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |26 |23 |3 |17 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |20 |17 |3 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |29 |26 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |25 |22 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |23 |20 |3 |10 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| insert |insert |973 |717 |170 |662 |0 |0 |
+| ram_switch_state |ram_switch_state |665 |665 |0 |380 |0 |0 |
+| read_ram_i |read_ram |270 |216 |44 |190 |0 |0 |
+| read_ram_addr |read_ram_addr |214 |174 |40 |149 |0 |0 |
+| read_ram_data |read_ram_data |54 |40 |4 |39 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |2 |2 |0 |1 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |306 |227 |36 |264 |3 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3221 |2494 |343 |2069 |25 |1 |
+| u0_soft_n |cdc_sync |8 |4 |0 |8 |0 |0 |
+| u_ad_sampling |ad_sampling |191 |105 |17 |162 |0 |0 |
+| u0_soft_n |cdc_sync |2 |0 |0 |2 |0 |0 |
+| u_sort |sort_rev |2992 |2381 |326 |1869 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2576 |2092 |284 |1513 |22 |1 |
+| channelPart |channel_part_8478 |128 |125 |3 |123 |0 |0 |
+| fifo_adc |fifo_adc |62 |53 |9 |45 |0 |1 |
+| ram_switch |ram_switch |2021 |1654 |197 |1110 |0 |0 |
+| adc_addr_gen |adc_addr_gen |197 |170 |27 |93 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |10 |7 |3 |4 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |16 |13 |3 |5 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |19 |16 |3 |8 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |24 |21 |3 |12 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |7 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |16 |13 |3 |7 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |14 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |9 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |21 |18 |3 |10 |0 |0 |
+| insert |insert |973 |633 |170 |690 |0 |0 |
+| ram_switch_state |ram_switch_state |851 |851 |0 |327 |0 |0 |
+| read_ram_i |read_ram_rev |337 |240 |75 |207 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |281 |202 |67 |165 |0 |0 |
+| read_ram_data |read_ram_data_rev |56 |38 |8 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 10035
+ #2 2 4226
+ #3 3 1714
+ #4 4 555
+ #5 5-10 788
+ #6 11-50 564
+ #7 51-100 9
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.056319s wall, 3.500000s user + 0.000000s system = 3.500000s CPU (170.2%)
+
+RUN-1004 : used memory is 1085 MB, reserved memory is 1095 MB, peak memory is 1160 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 72035, tnet num: 17810, tinst num: 6845, tnode num: 94719, tedge num: 119654.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.588837s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.3%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1099 MB, peak memory is 1160 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17810 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.430322s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.5%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1101 MB, peak memory is 1160 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6845
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17988, pip num: 167501
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 535
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3250 valid insts, and 468131 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.981936s wall, 62.750000s user + 0.156250s system = 62.906250s CPU (630.2%)
+
+RUN-1004 : used memory is 1248 MB, reserved memory is 1250 MB, peak memory is 1364 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240318_163236.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240319_092037.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240319_092037.log
new file mode 100644
index 0000000..b36629a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240319_092037.log
@@ -0,0 +1,2026 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Mar 19 09:20:37 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.235554s wall, 2.140625s user + 0.093750s system = 2.234375s CPU (99.9%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 316 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18051 instances
+RUN-0007 : 7660 luts, 9168 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20628 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13132 nets have 2 pins
+RUN-1001 : 6457 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 183 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1992
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18049 instances, 7660 luts, 9168 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6039 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84379, tnet num: 20450, tinst num: 18049, tnode num: 114931, tedge num: 134608.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.174276s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (101.1%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 515 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.973715s wall, 1.937500s user + 0.046875s system = 1.984375s CPU (100.5%)
+
+PHY-3001 : Found 1251 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09498e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18049.
+PHY-3001 : Level 1 #clusters 2055.
+PHY-3001 : End clustering; 0.126406s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (111.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35996e+06, overlap = 457.031
+PHY-3002 : Step(2): len = 1.25588e+06, overlap = 505.562
+PHY-3002 : Step(3): len = 857110, overlap = 602.219
+PHY-3002 : Step(4): len = 780238, overlap = 642.469
+PHY-3002 : Step(5): len = 613041, overlap = 763.594
+PHY-3002 : Step(6): len = 548002, overlap = 814.281
+PHY-3002 : Step(7): len = 470424, overlap = 893.719
+PHY-3002 : Step(8): len = 435220, overlap = 916.375
+PHY-3002 : Step(9): len = 385914, overlap = 970.125
+PHY-3002 : Step(10): len = 360121, overlap = 1024.56
+PHY-3002 : Step(11): len = 328894, overlap = 1094.25
+PHY-3002 : Step(12): len = 303340, overlap = 1162.72
+PHY-3002 : Step(13): len = 270470, overlap = 1241.19
+PHY-3002 : Step(14): len = 241536, overlap = 1290.41
+PHY-3002 : Step(15): len = 217781, overlap = 1318.25
+PHY-3002 : Step(16): len = 194309, overlap = 1354.88
+PHY-3002 : Step(17): len = 181622, overlap = 1362.34
+PHY-3002 : Step(18): len = 159590, overlap = 1387.75
+PHY-3002 : Step(19): len = 151735, overlap = 1417
+PHY-3002 : Step(20): len = 138248, overlap = 1438.91
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.06686e-07
+PHY-3002 : Step(21): len = 141280, overlap = 1411.16
+PHY-3002 : Step(22): len = 175842, overlap = 1296.78
+PHY-3002 : Step(23): len = 182657, overlap = 1244.25
+PHY-3002 : Step(24): len = 184083, overlap = 1181.41
+PHY-3002 : Step(25): len = 181348, overlap = 1192.25
+PHY-3002 : Step(26): len = 180167, overlap = 1168.06
+PHY-3002 : Step(27): len = 175852, overlap = 1165.47
+PHY-3002 : Step(28): len = 173395, overlap = 1143.75
+PHY-3002 : Step(29): len = 171448, overlap = 1108.69
+PHY-3002 : Step(30): len = 169801, overlap = 1086.81
+PHY-3002 : Step(31): len = 168495, overlap = 1106.03
+PHY-3002 : Step(32): len = 166361, overlap = 1124.47
+PHY-3002 : Step(33): len = 165227, overlap = 1116.06
+PHY-3002 : Step(34): len = 164485, overlap = 1128.69
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.81337e-06
+PHY-3002 : Step(35): len = 166476, overlap = 1121.69
+PHY-3002 : Step(36): len = 177393, overlap = 1078.38
+PHY-3002 : Step(37): len = 182267, overlap = 1008.91
+PHY-3002 : Step(38): len = 187467, overlap = 972.625
+PHY-3002 : Step(39): len = 189044, overlap = 955.875
+PHY-3002 : Step(40): len = 191400, overlap = 940.125
+PHY-3002 : Step(41): len = 191144, overlap = 935.938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.62674e-06
+PHY-3002 : Step(42): len = 196526, overlap = 911.938
+PHY-3002 : Step(43): len = 216078, overlap = 888.094
+PHY-3002 : Step(44): len = 222695, overlap = 875.188
+PHY-3002 : Step(45): len = 229347, overlap = 881.188
+PHY-3002 : Step(46): len = 231344, overlap = 876.062
+PHY-3002 : Step(47): len = 230867, overlap = 890.906
+PHY-3002 : Step(48): len = 229226, overlap = 897.094
+PHY-3002 : Step(49): len = 227934, overlap = 878.406
+PHY-3002 : Step(50): len = 226428, overlap = 857.844
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.25349e-06
+PHY-3002 : Step(51): len = 237215, overlap = 837.062
+PHY-3002 : Step(52): len = 253777, overlap = 750.094
+PHY-3002 : Step(53): len = 265375, overlap = 691.438
+PHY-3002 : Step(54): len = 274587, overlap = 642.656
+PHY-3002 : Step(55): len = 280480, overlap = 605.719
+PHY-3002 : Step(56): len = 281628, overlap = 589.031
+PHY-3002 : Step(57): len = 280737, overlap = 581.156
+PHY-3002 : Step(58): len = 278986, overlap = 564.312
+PHY-3002 : Step(59): len = 278345, overlap = 532.094
+PHY-3002 : Step(60): len = 278935, overlap = 536.125
+PHY-3002 : Step(61): len = 279773, overlap = 552.344
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.4507e-05
+PHY-3002 : Step(62): len = 295902, overlap = 525.688
+PHY-3002 : Step(63): len = 311872, overlap = 484.875
+PHY-3002 : Step(64): len = 318341, overlap = 471.875
+PHY-3002 : Step(65): len = 322386, overlap = 456.625
+PHY-3002 : Step(66): len = 319171, overlap = 451.375
+PHY-3002 : Step(67): len = 319091, overlap = 439.812
+PHY-3002 : Step(68): len = 316805, overlap = 434.344
+PHY-3002 : Step(69): len = 317760, overlap = 430.844
+PHY-3002 : Step(70): len = 319278, overlap = 439.812
+PHY-3002 : Step(71): len = 319603, overlap = 425.344
+PHY-3002 : Step(72): len = 317843, overlap = 419.188
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.9014e-05
+PHY-3002 : Step(73): len = 335160, overlap = 421.25
+PHY-3002 : Step(74): len = 348986, overlap = 382.219
+PHY-3002 : Step(75): len = 351329, overlap = 345.688
+PHY-3002 : Step(76): len = 352933, overlap = 329.625
+PHY-3002 : Step(77): len = 354075, overlap = 310.812
+PHY-3002 : Step(78): len = 359173, overlap = 290.781
+PHY-3002 : Step(79): len = 359095, overlap = 287.875
+PHY-3002 : Step(80): len = 360003, overlap = 284.031
+PHY-3002 : Step(81): len = 359752, overlap = 284.281
+PHY-3002 : Step(82): len = 360098, overlap = 283.969
+PHY-3002 : Step(83): len = 357781, overlap = 273.875
+PHY-3002 : Step(84): len = 357458, overlap = 285.562
+PHY-3002 : Step(85): len = 356858, overlap = 288.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.80279e-05
+PHY-3002 : Step(86): len = 374708, overlap = 273.812
+PHY-3002 : Step(87): len = 387504, overlap = 257.906
+PHY-3002 : Step(88): len = 387982, overlap = 255.125
+PHY-3002 : Step(89): len = 389247, overlap = 249.562
+PHY-3002 : Step(90): len = 390580, overlap = 247.312
+PHY-3002 : Step(91): len = 392165, overlap = 240.5
+PHY-3002 : Step(92): len = 390271, overlap = 235.594
+PHY-3002 : Step(93): len = 391461, overlap = 222.969
+PHY-3002 : Step(94): len = 392285, overlap = 223.75
+PHY-3002 : Step(95): len = 393404, overlap = 218.625
+PHY-3002 : Step(96): len = 391586, overlap = 219.969
+PHY-3002 : Step(97): len = 392260, overlap = 232.188
+PHY-3002 : Step(98): len = 393284, overlap = 234.875
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000116056
+PHY-3002 : Step(99): len = 410400, overlap = 227.25
+PHY-3002 : Step(100): len = 420960, overlap = 218.031
+PHY-3002 : Step(101): len = 418250, overlap = 207.625
+PHY-3002 : Step(102): len = 419613, overlap = 214.188
+PHY-3002 : Step(103): len = 423813, overlap = 210.125
+PHY-3002 : Step(104): len = 427760, overlap = 213.938
+PHY-3002 : Step(105): len = 424673, overlap = 212.156
+PHY-3002 : Step(106): len = 424554, overlap = 212.375
+PHY-3002 : Step(107): len = 426753, overlap = 217.094
+PHY-3002 : Step(108): len = 428249, overlap = 200.438
+PHY-3002 : Step(109): len = 425796, overlap = 205.438
+PHY-3002 : Step(110): len = 425250, overlap = 215.719
+PHY-3002 : Step(111): len = 426807, overlap = 212.469
+PHY-3002 : Step(112): len = 427962, overlap = 196.75
+PHY-3002 : Step(113): len = 425705, overlap = 204.781
+PHY-3002 : Step(114): len = 425319, overlap = 212.281
+PHY-3002 : Step(115): len = 426594, overlap = 219.375
+PHY-3002 : Step(116): len = 428178, overlap = 217.406
+PHY-3002 : Step(117): len = 426173, overlap = 222
+PHY-3002 : Step(118): len = 426144, overlap = 227.969
+PHY-3002 : Step(119): len = 427624, overlap = 231.156
+PHY-3002 : Step(120): len = 428974, overlap = 231.406
+PHY-3002 : Step(121): len = 427272, overlap = 221.625
+PHY-3002 : Step(122): len = 427296, overlap = 215.094
+PHY-3002 : Step(123): len = 428024, overlap = 222.031
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000232112
+PHY-3002 : Step(124): len = 440626, overlap = 219.938
+PHY-3002 : Step(125): len = 449289, overlap = 214.375
+PHY-3002 : Step(126): len = 448365, overlap = 204.406
+PHY-3002 : Step(127): len = 448310, overlap = 205.688
+PHY-3002 : Step(128): len = 450147, overlap = 212.438
+PHY-3002 : Step(129): len = 452577, overlap = 202.688
+PHY-3002 : Step(130): len = 452422, overlap = 202.344
+PHY-3002 : Step(131): len = 453749, overlap = 193
+PHY-3002 : Step(132): len = 455444, overlap = 192.75
+PHY-3002 : Step(133): len = 456332, overlap = 193.562
+PHY-3002 : Step(134): len = 454660, overlap = 191.969
+PHY-3002 : Step(135): len = 454579, overlap = 189.938
+PHY-3002 : Step(136): len = 455371, overlap = 197.438
+PHY-3002 : Step(137): len = 456093, overlap = 199.219
+PHY-3002 : Step(138): len = 455129, overlap = 193.5
+PHY-3002 : Step(139): len = 455418, overlap = 194.344
+PHY-3002 : Step(140): len = 456603, overlap = 194.062
+PHY-3002 : Step(141): len = 457018, overlap = 193.188
+PHY-3002 : Step(142): len = 455537, overlap = 196.219
+PHY-3002 : Step(143): len = 455395, overlap = 195.688
+PHY-3002 : Step(144): len = 456861, overlap = 191.75
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00045374
+PHY-3002 : Step(145): len = 462893, overlap = 185.25
+PHY-3002 : Step(146): len = 471861, overlap = 175.094
+PHY-3002 : Step(147): len = 475464, overlap = 172.156
+PHY-3002 : Step(148): len = 478548, overlap = 170.094
+PHY-3002 : Step(149): len = 481508, overlap = 166.406
+PHY-3002 : Step(150): len = 483060, overlap = 164.625
+PHY-3002 : Step(151): len = 481361, overlap = 170.812
+PHY-3002 : Step(152): len = 481055, overlap = 169.562
+PHY-3002 : Step(153): len = 482592, overlap = 173.312
+PHY-3002 : Step(154): len = 483954, overlap = 172.844
+PHY-3002 : Step(155): len = 483393, overlap = 168.656
+PHY-3002 : Step(156): len = 483652, overlap = 167.781
+PHY-3002 : Step(157): len = 484838, overlap = 164.781
+PHY-3002 : Step(158): len = 485540, overlap = 164.062
+PHY-3002 : Step(159): len = 485068, overlap = 168.031
+PHY-3002 : Step(160): len = 485760, overlap = 162.375
+PHY-3002 : Step(161): len = 486791, overlap = 158.75
+PHY-3002 : Step(162): len = 487224, overlap = 157.062
+PHY-3002 : Step(163): len = 486215, overlap = 160.562
+PHY-3002 : Step(164): len = 485910, overlap = 159.375
+PHY-3002 : Step(165): len = 486294, overlap = 160
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0008463
+PHY-3002 : Step(166): len = 491122, overlap = 153.812
+PHY-3002 : Step(167): len = 498926, overlap = 148.5
+PHY-3002 : Step(168): len = 500214, overlap = 147.438
+PHY-3002 : Step(169): len = 500939, overlap = 146.938
+PHY-3002 : Step(170): len = 502081, overlap = 143.719
+PHY-3002 : Step(171): len = 502464, overlap = 143.062
+PHY-3002 : Step(172): len = 501661, overlap = 144.906
+PHY-3002 : Step(173): len = 501345, overlap = 144.469
+PHY-3002 : Step(174): len = 502283, overlap = 144.219
+PHY-3002 : Step(175): len = 503034, overlap = 146.719
+PHY-3002 : Step(176): len = 502870, overlap = 146.531
+PHY-3002 : Step(177): len = 503020, overlap = 143.75
+PHY-3002 : Step(178): len = 504059, overlap = 143.781
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00138705
+PHY-3002 : Step(179): len = 505848, overlap = 145
+PHY-3002 : Step(180): len = 509120, overlap = 144.969
+PHY-3002 : Step(181): len = 511235, overlap = 142.812
+PHY-3002 : Step(182): len = 512855, overlap = 141.531
+PHY-3002 : Step(183): len = 515171, overlap = 139.875
+PHY-3002 : Step(184): len = 517248, overlap = 140.438
+PHY-3002 : Step(185): len = 518137, overlap = 136.219
+PHY-3002 : Step(186): len = 518380, overlap = 136.094
+PHY-3002 : Step(187): len = 518479, overlap = 135.844
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012535s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (124.6%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20628.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700096, over cnt = 1670(4%), over = 7537, worst = 61
+PHY-1001 : End global iterations; 0.702647s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (142.3%)
+
+PHY-1001 : Congestion index: top1 = 84.63, top5 = 64.31, top10 = 54.04, top15 = 47.95.
+PHY-3001 : End congestion estimation; 0.942283s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (131.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.864662s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000146658
+PHY-3002 : Step(188): len = 636302, overlap = 94.9688
+PHY-3002 : Step(189): len = 637097, overlap = 98.3438
+PHY-3002 : Step(190): len = 630577, overlap = 89.2188
+PHY-3002 : Step(191): len = 626896, overlap = 87.75
+PHY-3002 : Step(192): len = 628342, overlap = 77.9062
+PHY-3002 : Step(193): len = 629045, overlap = 72.1562
+PHY-3002 : Step(194): len = 626824, overlap = 69.0625
+PHY-3002 : Step(195): len = 624161, overlap = 64.4062
+PHY-3002 : Step(196): len = 621836, overlap = 60.0312
+PHY-3002 : Step(197): len = 618901, overlap = 58.125
+PHY-3002 : Step(198): len = 616825, overlap = 49.8438
+PHY-3002 : Step(199): len = 615788, overlap = 40.375
+PHY-3002 : Step(200): len = 614568, overlap = 35.875
+PHY-3002 : Step(201): len = 613595, overlap = 34.0625
+PHY-3002 : Step(202): len = 613070, overlap = 32
+PHY-3002 : Step(203): len = 613729, overlap = 28.3125
+PHY-3002 : Step(204): len = 613872, overlap = 27.8438
+PHY-3002 : Step(205): len = 614579, overlap = 26.1875
+PHY-3002 : Step(206): len = 614760, overlap = 26.75
+PHY-3002 : Step(207): len = 614446, overlap = 25
+PHY-3002 : Step(208): len = 614010, overlap = 24.2188
+PHY-3002 : Step(209): len = 613860, overlap = 27.5625
+PHY-3002 : Step(210): len = 613563, overlap = 30.2812
+PHY-3002 : Step(211): len = 612867, overlap = 35
+PHY-3002 : Step(212): len = 611499, overlap = 37.7812
+PHY-3002 : Step(213): len = 610596, overlap = 41.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000293316
+PHY-3002 : Step(214): len = 615827, overlap = 38.375
+PHY-3002 : Step(215): len = 621743, overlap = 39.1562
+PHY-3002 : Step(216): len = 623421, overlap = 37.0625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000586631
+PHY-3002 : Step(217): len = 628407, overlap = 36.9375
+PHY-3002 : Step(218): len = 644262, overlap = 42.25
+PHY-3002 : Step(219): len = 663701, overlap = 46.3438
+PHY-3002 : Step(220): len = 665453, overlap = 47.4688
+PHY-3002 : Step(221): len = 664229, overlap = 44.9688
+PHY-3002 : Step(222): len = 662890, overlap = 43.7188
+PHY-3002 : Step(223): len = 661016, overlap = 44.9375
+PHY-3002 : Step(224): len = 659421, overlap = 50.7188
+PHY-3002 : Step(225): len = 658514, overlap = 56.6875
+PHY-3002 : Step(226): len = 657436, overlap = 59.0625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.0011151
+PHY-3002 : Step(227): len = 662446, overlap = 56.6875
+PHY-3002 : Step(228): len = 672783, overlap = 55.3438
+PHY-3002 : Step(229): len = 679338, overlap = 56.6875
+PHY-3002 : Step(230): len = 683137, overlap = 58.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00195339
+PHY-3002 : Step(231): len = 688536, overlap = 57.9375
+PHY-3002 : Step(232): len = 701227, overlap = 59.875
+PHY-3002 : Step(233): len = 709458, overlap = 59.8125
+PHY-3002 : Step(234): len = 712723, overlap = 60.4062
+PHY-3002 : Step(235): len = 714060, overlap = 60.5
+PHY-3002 : Step(236): len = 716150, overlap = 60.8125
+PHY-3002 : Step(237): len = 716470, overlap = 67.3125
+PHY-3002 : Step(238): len = 716509, overlap = 67.25
+PHY-3002 : Step(239): len = 716612, overlap = 65.1875
+PHY-3002 : Step(240): len = 716331, overlap = 65.1562
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00316059
+PHY-3002 : Step(241): len = 718048, overlap = 64.4062
+PHY-3002 : Step(242): len = 724794, overlap = 63.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 75/20628.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808240, over cnt = 2878(8%), over = 14220, worst = 40
+PHY-1001 : End global iterations; 1.593528s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (126.5%)
+
+PHY-1001 : Congestion index: top1 = 95.84, top5 = 75.73, top10 = 66.32, top15 = 60.55.
+PHY-3001 : End congestion estimation; 1.874658s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (122.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.085681s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000120544
+PHY-3002 : Step(243): len = 710042, overlap = 260.438
+PHY-3002 : Step(244): len = 698909, overlap = 196.469
+PHY-3002 : Step(245): len = 684822, overlap = 178.062
+PHY-3002 : Step(246): len = 673670, overlap = 159.281
+PHY-3002 : Step(247): len = 661319, overlap = 138.125
+PHY-3002 : Step(248): len = 652738, overlap = 129.281
+PHY-3002 : Step(249): len = 646802, overlap = 124.406
+PHY-3002 : Step(250): len = 638513, overlap = 121.594
+PHY-3002 : Step(251): len = 633409, overlap = 114.062
+PHY-3002 : Step(252): len = 627787, overlap = 114.688
+PHY-3002 : Step(253): len = 622599, overlap = 122.531
+PHY-3002 : Step(254): len = 618487, overlap = 119.062
+PHY-3002 : Step(255): len = 615117, overlap = 118.875
+PHY-3002 : Step(256): len = 610263, overlap = 117.062
+PHY-3002 : Step(257): len = 606956, overlap = 119.281
+PHY-3002 : Step(258): len = 603886, overlap = 124
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000241089
+PHY-3002 : Step(259): len = 604318, overlap = 122
+PHY-3002 : Step(260): len = 606221, overlap = 118.812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000403005
+PHY-3002 : Step(261): len = 608726, overlap = 111.5
+PHY-3002 : Step(262): len = 613786, overlap = 104.5
+PHY-3002 : Step(263): len = 619112, overlap = 99.8438
+PHY-3002 : Step(264): len = 622863, overlap = 97.4688
+PHY-3002 : Step(265): len = 624001, overlap = 95.75
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84379, tnet num: 20450, tinst num: 18049, tnode num: 114931, tedge num: 134608.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.458088s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (99.7%)
+
+RUN-1004 : used memory is 576 MB, reserved memory is 565 MB, peak memory is 711 MB
+OPT-1001 : Total overflow 428.75 peak overflow 3.25
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 493/20628.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 714512, over cnt = 2968(8%), over = 10976, worst = 27
+PHY-1001 : End global iterations; 1.410366s wall, 1.968750s user + 0.078125s system = 2.046875s CPU (145.1%)
+
+PHY-1001 : Congestion index: top1 = 71.38, top5 = 58.55, top10 = 52.00, top15 = 48.03.
+PHY-1001 : End incremental global routing; 1.748319s wall, 2.312500s user + 0.078125s system = 2.390625s CPU (136.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.895217s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.5%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17917 has valid locations, 313 needs to be replaced
+PHY-3001 : design contains 18315 instances, 7748 luts, 9346 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6160 pins
+PHY-3001 : Found 1262 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 646254
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16727/20894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 728760, over cnt = 3011(8%), over = 11102, worst = 27
+PHY-1001 : End global iterations; 0.225144s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (131.9%)
+
+PHY-1001 : Congestion index: top1 = 71.94, top5 = 59.16, top10 = 52.55, top15 = 48.67.
+PHY-3001 : End congestion estimation; 0.473386s wall, 0.531250s user + 0.015625s system = 0.546875s CPU (115.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85448, tnet num: 20716, tinst num: 18315, tnode num: 116561, tedge num: 136214.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.473720s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (99.7%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 616 MB, peak memory is 717 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.413233s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(266): len = 645166, overlap = 2.28125
+PHY-3002 : Step(267): len = 644894, overlap = 2.15625
+PHY-3002 : Step(268): len = 644588, overlap = 2.09375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16837/20894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 727344, over cnt = 2998(8%), over = 11115, worst = 27
+PHY-1001 : End global iterations; 0.174998s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (125.0%)
+
+PHY-1001 : Congestion index: top1 = 71.64, top5 = 59.15, top10 = 52.58, top15 = 48.66.
+PHY-3001 : End congestion estimation; 0.425684s wall, 0.437500s user + 0.031250s system = 0.468750s CPU (110.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.938848s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000321145
+PHY-3002 : Step(269): len = 644405, overlap = 98.2812
+PHY-3002 : Step(270): len = 644481, overlap = 97.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00064229
+PHY-3002 : Step(271): len = 644602, overlap = 97.9375
+PHY-3002 : Step(272): len = 645066, overlap = 97.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00123825
+PHY-3002 : Step(273): len = 645199, overlap = 97.2188
+PHY-3002 : Step(274): len = 645658, overlap = 97.2812
+PHY-3001 : Final: Len = 645658, Over = 97.2812
+PHY-3001 : End incremental placement; 4.953222s wall, 5.187500s user + 0.281250s system = 5.468750s CPU (110.4%)
+
+OPT-1001 : Total overflow 435.59 peak overflow 3.25
+OPT-1001 : End high-fanout net optimization; 8.117560s wall, 8.906250s user + 0.375000s system = 9.281250s CPU (114.3%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 712, peak = 736.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16747/20894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730552, over cnt = 2944(8%), over = 10054, worst = 27
+PHY-1002 : len = 782312, over cnt = 2119(6%), over = 5345, worst = 18
+PHY-1002 : len = 814016, over cnt = 1264(3%), over = 3087, worst = 17
+PHY-1002 : len = 837624, over cnt = 553(1%), over = 1373, worst = 16
+PHY-1002 : len = 860024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.609631s wall, 2.453125s user + 0.015625s system = 2.468750s CPU (153.4%)
+
+PHY-1001 : Congestion index: top1 = 58.51, top5 = 51.16, top10 = 47.32, top15 = 44.85.
+OPT-1001 : End congestion update; 1.873414s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (146.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.788873s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.0%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 108 cells processed and 17550 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 55 cells processed and 5484 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 884 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 300 slack improved
+OPT-1001 : End bottleneck based optimization; 3.088753s wall, 3.921875s user + 0.015625s system = 3.937500s CPU (127.5%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 692, peak = 736.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16835/20895.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860648, over cnt = 68(0%), over = 93, worst = 4
+PHY-1002 : len = 860288, over cnt = 39(0%), over = 49, worst = 3
+PHY-1002 : len = 860520, over cnt = 19(0%), over = 20, worst = 2
+PHY-1002 : len = 860872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.523451s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (101.5%)
+
+PHY-1001 : Congestion index: top1 = 58.21, top5 = 51.10, top10 = 47.22, top15 = 44.74.
+OPT-1001 : End congestion update; 0.780886s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (102.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20717 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.782853s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.8%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 3850 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.681229s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (101.3%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 698, peak = 736.
+OPT-1001 : End physical optimization; 14.643786s wall, 16.328125s user + 0.453125s system = 16.781250s CPU (114.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7748 LUT to BLE ...
+SYN-4008 : Packed 7748 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6200 remaining SEQ's ...
+SYN-4005 : Packed 4042 SEQ with LUT/SLICE
+SYN-4006 : 862 single LUT's are left
+SYN-4006 : 2158 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9906/13693 primitive instances ...
+PHY-3001 : End packing; 1.585564s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6667 instances
+RUN-1001 : 3259 mslices, 3260 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17882 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10019 nets have 2 pins
+RUN-1001 : 6495 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 313 nets have [11 - 20] pins
+RUN-1001 : 288 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6665 instances, 6519 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3551 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 658117, Over = 228.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7560/17882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 810616, over cnt = 1962(5%), over = 3211, worst = 9
+PHY-1002 : len = 816472, over cnt = 1262(3%), over = 1921, worst = 9
+PHY-1002 : len = 829840, over cnt = 553(1%), over = 844, worst = 7
+PHY-1002 : len = 840568, over cnt = 194(0%), over = 272, worst = 6
+PHY-1002 : len = 844992, over cnt = 15(0%), over = 30, worst = 6
+PHY-1001 : End global iterations; 1.520249s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (135.7%)
+
+PHY-1001 : Congestion index: top1 = 58.58, top5 = 50.97, top10 = 46.93, top15 = 44.31.
+PHY-3001 : End congestion estimation; 1.903616s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (128.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71516, tnet num: 17704, tinst num: 6665, tnode num: 93936, tedge num: 118938.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.577471s wall, 1.546875s user + 0.031250s system = 1.578125s CPU (100.0%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 619 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.458321s wall, 2.437500s user + 0.031250s system = 2.468750s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.16856e-05
+PHY-3002 : Step(275): len = 648604, overlap = 235.25
+PHY-3002 : Step(276): len = 642801, overlap = 241.5
+PHY-3002 : Step(277): len = 638653, overlap = 232.75
+PHY-3002 : Step(278): len = 635388, overlap = 238.75
+PHY-3002 : Step(279): len = 633613, overlap = 251
+PHY-3002 : Step(280): len = 630830, overlap = 248.5
+PHY-3002 : Step(281): len = 628728, overlap = 247.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103371
+PHY-3002 : Step(282): len = 629760, overlap = 245.25
+PHY-3002 : Step(283): len = 633829, overlap = 230
+PHY-3002 : Step(284): len = 636618, overlap = 215.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000206742
+PHY-3002 : Step(285): len = 642221, overlap = 203
+PHY-3002 : Step(286): len = 647331, overlap = 198.25
+PHY-3002 : Step(287): len = 647935, overlap = 195.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.368088s wall, 0.375000s user + 0.484375s system = 0.859375s CPU (233.5%)
+
+PHY-3001 : Trial Legalized: Len = 735435
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 915/17882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844880, over cnt = 2647(7%), over = 4444, worst = 7
+PHY-1002 : len = 862680, over cnt = 1582(4%), over = 2285, worst = 6
+PHY-1002 : len = 877440, over cnt = 824(2%), over = 1194, worst = 6
+PHY-1002 : len = 886208, over cnt = 430(1%), over = 628, worst = 5
+PHY-1002 : len = 899080, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.471516s wall, 3.609375s user + 0.046875s system = 3.656250s CPU (147.9%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.45, top10 = 46.68, top15 = 44.78.
+PHY-3001 : End congestion estimation; 2.916701s wall, 4.062500s user + 0.046875s system = 4.109375s CPU (140.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.837083s wall, 0.765625s user + 0.062500s system = 0.828125s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00016604
+PHY-3002 : Step(288): len = 707180, overlap = 31.75
+PHY-3002 : Step(289): len = 690955, overlap = 59.25
+PHY-3002 : Step(290): len = 676956, overlap = 87.75
+PHY-3002 : Step(291): len = 667231, overlap = 111.25
+PHY-3002 : Step(292): len = 661968, overlap = 130.5
+PHY-3002 : Step(293): len = 658198, overlap = 147
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00033208
+PHY-3002 : Step(294): len = 661838, overlap = 142.5
+PHY-3002 : Step(295): len = 666123, overlap = 140.75
+PHY-3002 : Step(296): len = 665854, overlap = 146
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000649487
+PHY-3002 : Step(297): len = 670741, overlap = 143
+PHY-3002 : Step(298): len = 681504, overlap = 129.5
+PHY-3002 : Step(299): len = 681648, overlap = 131
+PHY-3002 : Step(300): len = 680965, overlap = 133.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.034870s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.6%)
+
+PHY-3001 : Legalized: Len = 711743, Over = 0
+PHY-3001 : Spreading special nets. 426 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.096023s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (97.6%)
+
+PHY-3001 : 616 instances has been re-located, deltaX = 206, deltaY = 342, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 721650, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71516, tnet num: 17704, tinst num: 6668, tnode num: 93936, tedge num: 118938.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.818800s wall, 1.796875s user + 0.031250s system = 1.828125s CPU (100.5%)
+
+RUN-1004 : used memory is 606 MB, reserved memory is 599 MB, peak memory is 736 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3611/17882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842928, over cnt = 2578(7%), over = 4133, worst = 7
+PHY-1002 : len = 858656, over cnt = 1367(3%), over = 1904, worst = 6
+PHY-1002 : len = 872672, over cnt = 583(1%), over = 774, worst = 4
+PHY-1002 : len = 879000, over cnt = 308(0%), over = 373, worst = 4
+PHY-1002 : len = 885760, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.116742s wall, 3.062500s user + 0.031250s system = 3.093750s CPU (146.2%)
+
+PHY-1001 : Congestion index: top1 = 52.35, top5 = 47.19, top10 = 44.40, top15 = 42.61.
+PHY-1001 : End incremental global routing; 2.494378s wall, 3.453125s user + 0.031250s system = 3.484375s CPU (139.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.870115s wall, 0.828125s user + 0.031250s system = 0.859375s CPU (98.8%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6575 has valid locations, 28 needs to be replaced
+PHY-3001 : design contains 6691 instances, 6542 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 727156
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16317/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892320, over cnt = 117(0%), over = 143, worst = 6
+PHY-1002 : len = 892520, over cnt = 46(0%), over = 53, worst = 5
+PHY-1002 : len = 892752, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 893032, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 893304, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.774783s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (112.9%)
+
+PHY-1001 : Congestion index: top1 = 52.41, top5 = 47.43, top10 = 44.59, top15 = 42.82.
+PHY-3001 : End congestion estimation; 1.075265s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (109.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71755, tnet num: 17722, tinst num: 6691, tnode num: 94223, tedge num: 119218.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.800343s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (99.8%)
+
+RUN-1004 : used memory is 656 MB, reserved memory is 661 MB, peak memory is 736 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.940531s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(301): len = 726493, overlap = 0
+PHY-3002 : Step(302): len = 725541, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16302/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891168, over cnt = 81(0%), over = 112, worst = 8
+PHY-1002 : len = 891400, over cnt = 42(0%), over = 48, worst = 2
+PHY-1002 : len = 891976, over cnt = 8(0%), over = 9, worst = 2
+PHY-1002 : len = 892152, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.568501s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (109.9%)
+
+PHY-1001 : Congestion index: top1 = 52.48, top5 = 47.32, top10 = 44.58, top15 = 42.86.
+PHY-3001 : End congestion estimation; 0.874096s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (107.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.837513s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000967567
+PHY-3002 : Step(303): len = 725333, overlap = 2
+PHY-3002 : Step(304): len = 725250, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005286s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (295.6%)
+
+PHY-3001 : Legalized: Len = 725372, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059081s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.8%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 1, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 725386, Over = 0
+PHY-3001 : End incremental placement; 6.196695s wall, 6.500000s user + 0.062500s system = 6.562500s CPU (105.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.032349s wall, 11.265625s user + 0.125000s system = 11.390625s CPU (113.5%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 732, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16279/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891992, over cnt = 80(0%), over = 115, worst = 6
+PHY-1002 : len = 892312, over cnt = 38(0%), over = 44, worst = 3
+PHY-1002 : len = 892640, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 892816, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.585076s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (104.2%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.24, top10 = 44.52, top15 = 42.77.
+OPT-1001 : End congestion update; 0.885692s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (104.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.733391s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6603 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6691 instances, 6542 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 734063, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.064446s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.0%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 22, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 734451, Over = 0
+PHY-3001 : End incremental legalization; 0.397646s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.2%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 56 cells processed and 17158 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6603 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6691 instances, 6542 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 734905, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.062219s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 5, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 735395, Over = 0
+PHY-3001 : End incremental legalization; 0.403405s wall, 0.515625s user + 0.031250s system = 0.546875s CPU (135.6%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 1450 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6605 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6693 instances, 6544 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3632 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 735707, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059336s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.3%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 735673, Over = 0
+PHY-3001 : End incremental legalization; 0.373348s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.4%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 300 slack improved
+OPT-1001 : End bottleneck based optimization; 3.193245s wall, 3.328125s user + 0.031250s system = 3.359375s CPU (105.2%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16008/17901.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902104, over cnt = 120(0%), over = 154, worst = 8
+PHY-1002 : len = 902096, over cnt = 75(0%), over = 90, worst = 3
+PHY-1002 : len = 902848, over cnt = 18(0%), over = 19, worst = 2
+PHY-1002 : len = 903064, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 903336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.808071s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.5%)
+
+PHY-1001 : Congestion index: top1 = 52.35, top5 = 47.36, top10 = 44.57, top15 = 42.79.
+OPT-1001 : End congestion update; 1.111094s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.699601s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.5%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6605 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6693 instances, 6544 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3632 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 735927, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.059645s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.8%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 5, deltaY = 14, maxDist = 3.
+PHY-3001 : Final: Len = 736157, Over = 0
+PHY-3001 : End incremental legalization; 0.373613s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (100.4%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 18 cells processed and 2098 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.326739s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 731, peak = 739.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.702483s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16234/17901.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903592, over cnt = 51(0%), over = 57, worst = 3
+PHY-1002 : len = 903544, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 903776, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 903824, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 903952, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.757558s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (109.3%)
+
+PHY-1001 : Congestion index: top1 = 52.31, top5 = 47.36, top10 = 44.56, top15 = 42.79.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.697311s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 51.793103
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 221ps with logic level 1
+OPT-1001 : End physical optimization; 20.104052s wall, 21.468750s user + 0.234375s system = 21.703125s CPU (108.0%)
+
+RUN-1003 : finish command "place" in 64.740387s wall, 96.265625s user + 6.703125s system = 102.968750s CPU (159.0%)
+
+RUN-1004 : used memory is 605 MB, reserved memory is 610 MB, peak memory is 739 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.659845s wall, 2.890625s user + 0.015625s system = 2.906250s CPU (175.1%)
+
+RUN-1004 : used memory is 606 MB, reserved memory is 611 MB, peak memory is 739 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6695 instances
+RUN-1001 : 3276 mslices, 3268 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17901 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10005 nets have 2 pins
+RUN-1001 : 6496 nets have [3 - 5] pins
+RUN-1001 : 750 nets have [6 - 10] pins
+RUN-1001 : 322 nets have [11 - 20] pins
+RUN-1001 : 300 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71777, tnet num: 17723, tinst num: 6693, tnode num: 94252, tedge num: 119250.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.572038s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.4%)
+
+RUN-1004 : used memory is 596 MB, reserved memory is 591 MB, peak memory is 739 MB
+PHY-1001 : 3276 mslices, 3268 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 835888, over cnt = 2708(7%), over = 4502, worst = 7
+PHY-1002 : len = 858024, over cnt = 1412(4%), over = 1916, worst = 7
+PHY-1002 : len = 876336, over cnt = 405(1%), over = 523, worst = 7
+PHY-1002 : len = 884408, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 884968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.012717s wall, 4.046875s user + 0.046875s system = 4.093750s CPU (135.9%)
+
+PHY-1001 : Congestion index: top1 = 51.06, top5 = 46.57, top10 = 43.93, top15 = 42.30.
+PHY-1001 : End global routing; 3.352327s wall, 4.390625s user + 0.046875s system = 4.437500s CPU (132.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 706, reserve = 710, peak = 739.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 979, reserve = 982, peak = 979.
+PHY-1001 : End build detailed router design. 3.987859s wall, 3.921875s user + 0.062500s system = 3.984375s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 268464, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.041123s wall, 5.015625s user + 0.015625s system = 5.031250s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 268520, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.418337s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.8%)
+
+PHY-1001 : Current memory(MB): used = 1016, reserve = 1019, peak = 1016.
+PHY-1001 : End phase 1; 5.471500s wall, 5.453125s user + 0.015625s system = 5.468750s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.26522e+06, over cnt = 1798(0%), over = 1800, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1035, peak = 1032.
+PHY-1001 : End initial routed; 25.275455s wall, 55.765625s user + 0.187500s system = 55.953125s CPU (221.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 12/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.761 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.199946s wall, 3.171875s user + 0.015625s system = 3.187500s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1048, reserve = 1051, peak = 1048.
+PHY-1001 : End phase 2; 28.475461s wall, 58.937500s user + 0.203125s system = 59.140625s CPU (207.7%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.134927s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.2%)
+
+PHY-1022 : len = 2.26524e+06, over cnt = 1799(0%), over = 1801, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.392434s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2335e+06, over cnt = 521(0%), over = 522, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.482830s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (166.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.23235e+06, over cnt = 92(0%), over = 92, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.570340s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (161.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.23281e+06, over cnt = 21(0%), over = 21, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.275336s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (119.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.23309e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.198381s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.216619s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (93.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.309873s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.462487s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.23317e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.169672s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (110.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.166289s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.4%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.209103s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.235717s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (106.1%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.316963s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (103.5%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.23311e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.175065s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.23313e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.160398s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (116.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.217928s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 358 nets
+PHY-1001 : End commit to database; 2.184296s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1147, reserve = 1153, peak = 1147.
+PHY-1001 : End phase 3; 11.150545s wall, 12.562500s user + 0.015625s system = 12.578125s CPU (112.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.132955s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.8%)
+
+PHY-1022 : len = 2.23313e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.369100s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.173038s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 358 nets
+PHY-1001 : End commit to database; 2.271076s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1155, reserve = 1162, peak = 1155.
+PHY-1001 : End phase 4; 5.839193s wall, 5.843750s user + 0.000000s system = 5.843750s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.23313e+06
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1164, peak = 1157.
+PHY-1001 : End export database. 0.058838s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.2%)
+
+PHY-1001 : End detail routing; 55.374978s wall, 87.187500s user + 0.296875s system = 87.484375s CPU (158.0%)
+
+RUN-1003 : finish command "route" in 61.372858s wall, 94.218750s user + 0.343750s system = 94.562500s CPU (154.1%)
+
+RUN-1004 : used memory is 1081 MB, reserved memory is 1084 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10178 out of 19600 51.93%
+#reg 9527 out of 19600 48.61%
+#le 12301
+ #lut only 2774 out of 12301 22.55%
+ #reg only 2123 out of 12301 17.26%
+ #lut® 7404 out of 12301 60.19%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1763
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1426
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1313
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 926
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 138
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg5_syn_21.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_204.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P4 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P14 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P16 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P15 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P156 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12301 |9151 |1027 |9559 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |524 |455 |23 |422 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |87 |4 |90 |4 |0 |
+| U_ecc_gen |ecc_gen |13 |13 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |47 |47 |0 |19 |0 |0 |
+| exdev_ctl_a |exdev_ctl |747 |410 |96 |568 |0 |0 |
+| u_ADconfig |AD_config |189 |127 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |248 |146 |71 |114 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |352 |96 |570 |0 |0 |
+| u_ADconfig |AD_config |172 |111 |25 |129 |0 |0 |
+| u_gen_sp |gen_sp |261 |149 |71 |125 |0 |0 |
+| sampling_fe_a |sampling_fe |3016 |2461 |306 |2101 |25 |0 |
+| u0_soft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |134 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_sort |sort |2789 |2306 |289 |1905 |25 |0 |
+| rddpram_ctl |rddpram_ctl |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2338 |1955 |253 |1540 |22 |0 |
+| channelPart |channel_part_8478 |144 |132 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |56 |47 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1847 |1547 |197 |1150 |0 |0 |
+| adc_addr_gen |adc_addr_gen |228 |201 |27 |136 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |13 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| insert |insert |945 |673 |170 |631 |0 |0 |
+| ram_switch_state |ram_switch_state |674 |673 |0 |383 |0 |0 |
+| read_ram_i |read_ram |268 |212 |44 |189 |0 |0 |
+| read_ram_addr |read_ram_addr |220 |180 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |46 |30 |4 |35 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |318 |228 |36 |278 |3 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3119 |2457 |349 |2099 |25 |1 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |131 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |2900 |2305 |332 |1911 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2463 |1977 |290 |1558 |22 |1 |
+| channelPart |channel_part_8478 |147 |138 |3 |142 |0 |0 |
+| fifo_adc |fifo_adc |63 |54 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1869 |1508 |197 |1134 |0 |0 |
+| adc_addr_gen |adc_addr_gen |206 |178 |27 |112 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |6 |0 |0 |
+| insert |insert |973 |641 |170 |666 |0 |0 |
+| ram_switch_state |ram_switch_state |690 |689 |0 |356 |0 |0 |
+| read_ram_i |read_ram_rev |359 |255 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |293 |209 |73 |166 |0 |0 |
+| read_ram_data |read_ram_data_rev |66 |46 |8 |46 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9943
+ #2 2 4231
+ #3 3 1704
+ #4 4 558
+ #5 5-10 785
+ #6 11-50 574
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.063614s wall, 3.531250s user + 0.015625s system = 3.546875s CPU (171.9%)
+
+RUN-1004 : used memory is 1083 MB, reserved memory is 1086 MB, peak memory is 1157 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71777, tnet num: 17723, tinst num: 6693, tnode num: 94252, tedge num: 119250.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.558263s wall, 1.546875s user + 0.015625s system = 1.562500s CPU (100.3%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1090 MB, peak memory is 1157 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.445833s wall, 1.437500s user + 0.000000s system = 1.437500s CPU (99.4%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1095 MB, peak memory is 1157 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6693
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17901, pip num: 167200
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 496
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 466724 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 10.566935s wall, 60.890625s user + 0.109375s system = 61.000000s CPU (577.3%)
+
+RUN-1004 : used memory is 1247 MB, reserved memory is 1249 MB, peak memory is 1363 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240319_092037.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240319_144011.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240319_144011.log
new file mode 100644
index 0000000..c23ea1e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240319_144011.log
@@ -0,0 +1,2026 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Tue Mar 19 14:40:11 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(925)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(934)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(958)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(960)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(966)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(969)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1140)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1229)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1530)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1541)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1559)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1744)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(2140)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in 2.192886s wall, 2.140625s user + 0.062500s system = 2.203125s CPU (100.5%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place effort high"
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : detailed_place | on | on |
+RUN-1001 : effort | high | medium | *
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : legalization | ori | ori |
+RUN-1001 : new_spreading | on | on |
+RUN-1001 : opt_timing | high | medium | *
+RUN-1001 : post_clock_route_opt | off | off |
+RUN-1001 : pr_strategy | 1 | 1 |
+RUN-1001 : relaxation | 1.00 | 1.00 |
+RUN-1001 : retiming | off | off |
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s) with high effort.
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2274 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2115 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18051 instances
+RUN-0007 : 7660 luts, 9168 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20628 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13132 nets have 2 pins
+RUN-1001 : 6457 nets have [3 - 5] pins
+RUN-1001 : 619 nets have [6 - 10] pins
+RUN-1001 : 183 nets have [11 - 20] pins
+RUN-1001 : 166 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 : CE | SSR | ASR | DFF Count
+RUN-1001 : ----------------------------------
+RUN-1001 : No | No | No | 797
+RUN-1001 : No | No | Yes | 1992
+RUN-1001 : No | Yes | No | 3570
+RUN-1001 : Yes | No | No | 64
+RUN-1001 : Yes | No | Yes | 72
+RUN-1001 : Yes | Yes | No | 2673
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 : #CLK | #CE | #SSR/ASR
+RUN-0007 : ---------------------------
+RUN-0007 : 12 | 76 | 57
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18049 instances, 7660 luts, 9168 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6039 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84379, tnet num: 20450, tinst num: 18049, tnode num: 114931, tedge num: 134608.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.180352s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (99.3%)
+
+RUN-1004 : used memory is 539 MB, reserved memory is 516 MB, peak memory is 539 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.960061s wall, 1.906250s user + 0.046875s system = 1.953125s CPU (99.6%)
+
+PHY-3001 : Found 1251 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09498e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18049.
+PHY-3001 : Level 1 #clusters 2055.
+PHY-3001 : End clustering; 0.131392s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (154.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35996e+06, overlap = 457.031
+PHY-3002 : Step(2): len = 1.25588e+06, overlap = 505.562
+PHY-3002 : Step(3): len = 857110, overlap = 602.219
+PHY-3002 : Step(4): len = 780238, overlap = 642.469
+PHY-3002 : Step(5): len = 613041, overlap = 763.594
+PHY-3002 : Step(6): len = 548002, overlap = 814.281
+PHY-3002 : Step(7): len = 470424, overlap = 893.719
+PHY-3002 : Step(8): len = 435220, overlap = 916.375
+PHY-3002 : Step(9): len = 385914, overlap = 970.125
+PHY-3002 : Step(10): len = 360121, overlap = 1024.56
+PHY-3002 : Step(11): len = 328894, overlap = 1094.25
+PHY-3002 : Step(12): len = 303340, overlap = 1162.72
+PHY-3002 : Step(13): len = 270470, overlap = 1241.19
+PHY-3002 : Step(14): len = 241536, overlap = 1290.41
+PHY-3002 : Step(15): len = 217781, overlap = 1318.25
+PHY-3002 : Step(16): len = 194309, overlap = 1354.88
+PHY-3002 : Step(17): len = 181622, overlap = 1362.34
+PHY-3002 : Step(18): len = 159590, overlap = 1387.75
+PHY-3002 : Step(19): len = 151735, overlap = 1417
+PHY-3002 : Step(20): len = 138248, overlap = 1438.91
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.06686e-07
+PHY-3002 : Step(21): len = 141280, overlap = 1411.16
+PHY-3002 : Step(22): len = 175842, overlap = 1296.78
+PHY-3002 : Step(23): len = 182657, overlap = 1244.25
+PHY-3002 : Step(24): len = 184083, overlap = 1181.41
+PHY-3002 : Step(25): len = 181348, overlap = 1192.25
+PHY-3002 : Step(26): len = 180167, overlap = 1168.06
+PHY-3002 : Step(27): len = 175852, overlap = 1165.47
+PHY-3002 : Step(28): len = 173395, overlap = 1143.75
+PHY-3002 : Step(29): len = 171448, overlap = 1108.69
+PHY-3002 : Step(30): len = 169801, overlap = 1086.81
+PHY-3002 : Step(31): len = 168495, overlap = 1106.03
+PHY-3002 : Step(32): len = 166361, overlap = 1124.47
+PHY-3002 : Step(33): len = 165227, overlap = 1116.06
+PHY-3002 : Step(34): len = 164485, overlap = 1128.69
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.81337e-06
+PHY-3002 : Step(35): len = 166476, overlap = 1121.69
+PHY-3002 : Step(36): len = 177393, overlap = 1078.38
+PHY-3002 : Step(37): len = 182267, overlap = 1008.91
+PHY-3002 : Step(38): len = 187467, overlap = 972.625
+PHY-3002 : Step(39): len = 189044, overlap = 955.875
+PHY-3002 : Step(40): len = 191400, overlap = 940.125
+PHY-3002 : Step(41): len = 191144, overlap = 935.938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.62674e-06
+PHY-3002 : Step(42): len = 196526, overlap = 911.938
+PHY-3002 : Step(43): len = 216078, overlap = 888.094
+PHY-3002 : Step(44): len = 222695, overlap = 875.188
+PHY-3002 : Step(45): len = 229347, overlap = 881.188
+PHY-3002 : Step(46): len = 231344, overlap = 876.062
+PHY-3002 : Step(47): len = 230867, overlap = 890.906
+PHY-3002 : Step(48): len = 229226, overlap = 897.094
+PHY-3002 : Step(49): len = 227934, overlap = 878.406
+PHY-3002 : Step(50): len = 226428, overlap = 857.844
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.25349e-06
+PHY-3002 : Step(51): len = 237215, overlap = 837.062
+PHY-3002 : Step(52): len = 253777, overlap = 750.094
+PHY-3002 : Step(53): len = 265375, overlap = 691.438
+PHY-3002 : Step(54): len = 274587, overlap = 642.656
+PHY-3002 : Step(55): len = 280480, overlap = 605.719
+PHY-3002 : Step(56): len = 281628, overlap = 589.031
+PHY-3002 : Step(57): len = 280737, overlap = 581.156
+PHY-3002 : Step(58): len = 278986, overlap = 564.312
+PHY-3002 : Step(59): len = 278345, overlap = 532.094
+PHY-3002 : Step(60): len = 278935, overlap = 536.125
+PHY-3002 : Step(61): len = 279773, overlap = 552.344
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.4507e-05
+PHY-3002 : Step(62): len = 295902, overlap = 525.688
+PHY-3002 : Step(63): len = 311872, overlap = 484.875
+PHY-3002 : Step(64): len = 318341, overlap = 471.875
+PHY-3002 : Step(65): len = 322386, overlap = 456.625
+PHY-3002 : Step(66): len = 319171, overlap = 451.375
+PHY-3002 : Step(67): len = 319091, overlap = 439.812
+PHY-3002 : Step(68): len = 316805, overlap = 434.344
+PHY-3002 : Step(69): len = 317760, overlap = 430.844
+PHY-3002 : Step(70): len = 319278, overlap = 439.812
+PHY-3002 : Step(71): len = 319603, overlap = 425.344
+PHY-3002 : Step(72): len = 317843, overlap = 419.188
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.9014e-05
+PHY-3002 : Step(73): len = 335160, overlap = 421.25
+PHY-3002 : Step(74): len = 348986, overlap = 382.219
+PHY-3002 : Step(75): len = 351329, overlap = 345.688
+PHY-3002 : Step(76): len = 352933, overlap = 329.625
+PHY-3002 : Step(77): len = 354075, overlap = 310.812
+PHY-3002 : Step(78): len = 359173, overlap = 290.781
+PHY-3002 : Step(79): len = 359095, overlap = 287.875
+PHY-3002 : Step(80): len = 360003, overlap = 284.031
+PHY-3002 : Step(81): len = 359752, overlap = 284.281
+PHY-3002 : Step(82): len = 360098, overlap = 283.969
+PHY-3002 : Step(83): len = 357781, overlap = 273.875
+PHY-3002 : Step(84): len = 357458, overlap = 285.562
+PHY-3002 : Step(85): len = 356858, overlap = 288.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.80279e-05
+PHY-3002 : Step(86): len = 374708, overlap = 273.812
+PHY-3002 : Step(87): len = 387504, overlap = 257.906
+PHY-3002 : Step(88): len = 387982, overlap = 255.125
+PHY-3002 : Step(89): len = 389247, overlap = 249.562
+PHY-3002 : Step(90): len = 390580, overlap = 247.312
+PHY-3002 : Step(91): len = 392165, overlap = 240.5
+PHY-3002 : Step(92): len = 390271, overlap = 235.594
+PHY-3002 : Step(93): len = 391461, overlap = 222.969
+PHY-3002 : Step(94): len = 392285, overlap = 223.75
+PHY-3002 : Step(95): len = 393404, overlap = 218.625
+PHY-3002 : Step(96): len = 391586, overlap = 219.969
+PHY-3002 : Step(97): len = 392260, overlap = 232.188
+PHY-3002 : Step(98): len = 393284, overlap = 234.875
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000116056
+PHY-3002 : Step(99): len = 410400, overlap = 227.25
+PHY-3002 : Step(100): len = 420960, overlap = 218.031
+PHY-3002 : Step(101): len = 418250, overlap = 207.625
+PHY-3002 : Step(102): len = 419613, overlap = 214.188
+PHY-3002 : Step(103): len = 423813, overlap = 210.125
+PHY-3002 : Step(104): len = 427760, overlap = 213.938
+PHY-3002 : Step(105): len = 424673, overlap = 212.156
+PHY-3002 : Step(106): len = 424554, overlap = 212.375
+PHY-3002 : Step(107): len = 426753, overlap = 217.094
+PHY-3002 : Step(108): len = 428249, overlap = 200.438
+PHY-3002 : Step(109): len = 425796, overlap = 205.438
+PHY-3002 : Step(110): len = 425250, overlap = 215.719
+PHY-3002 : Step(111): len = 426807, overlap = 212.469
+PHY-3002 : Step(112): len = 427962, overlap = 196.75
+PHY-3002 : Step(113): len = 425705, overlap = 204.781
+PHY-3002 : Step(114): len = 425319, overlap = 212.281
+PHY-3002 : Step(115): len = 426594, overlap = 219.375
+PHY-3002 : Step(116): len = 428178, overlap = 217.406
+PHY-3002 : Step(117): len = 426173, overlap = 222
+PHY-3002 : Step(118): len = 426144, overlap = 227.969
+PHY-3002 : Step(119): len = 427624, overlap = 231.156
+PHY-3002 : Step(120): len = 428974, overlap = 231.406
+PHY-3002 : Step(121): len = 427272, overlap = 221.625
+PHY-3002 : Step(122): len = 427296, overlap = 215.094
+PHY-3002 : Step(123): len = 428024, overlap = 222.031
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000232112
+PHY-3002 : Step(124): len = 440626, overlap = 219.938
+PHY-3002 : Step(125): len = 449289, overlap = 214.375
+PHY-3002 : Step(126): len = 448365, overlap = 204.406
+PHY-3002 : Step(127): len = 448310, overlap = 205.688
+PHY-3002 : Step(128): len = 450147, overlap = 212.438
+PHY-3002 : Step(129): len = 452577, overlap = 202.688
+PHY-3002 : Step(130): len = 452422, overlap = 202.344
+PHY-3002 : Step(131): len = 453749, overlap = 193
+PHY-3002 : Step(132): len = 455444, overlap = 192.75
+PHY-3002 : Step(133): len = 456332, overlap = 193.562
+PHY-3002 : Step(134): len = 454660, overlap = 191.969
+PHY-3002 : Step(135): len = 454579, overlap = 189.938
+PHY-3002 : Step(136): len = 455371, overlap = 197.438
+PHY-3002 : Step(137): len = 456093, overlap = 199.219
+PHY-3002 : Step(138): len = 455129, overlap = 193.5
+PHY-3002 : Step(139): len = 455418, overlap = 194.344
+PHY-3002 : Step(140): len = 456603, overlap = 194.062
+PHY-3002 : Step(141): len = 457018, overlap = 193.188
+PHY-3002 : Step(142): len = 455537, overlap = 196.219
+PHY-3002 : Step(143): len = 455395, overlap = 195.688
+PHY-3002 : Step(144): len = 456861, overlap = 191.75
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00045374
+PHY-3002 : Step(145): len = 462893, overlap = 185.25
+PHY-3002 : Step(146): len = 471861, overlap = 175.094
+PHY-3002 : Step(147): len = 475464, overlap = 172.156
+PHY-3002 : Step(148): len = 478548, overlap = 170.094
+PHY-3002 : Step(149): len = 481508, overlap = 166.406
+PHY-3002 : Step(150): len = 483060, overlap = 164.625
+PHY-3002 : Step(151): len = 481361, overlap = 170.812
+PHY-3002 : Step(152): len = 481055, overlap = 169.562
+PHY-3002 : Step(153): len = 482592, overlap = 173.312
+PHY-3002 : Step(154): len = 483954, overlap = 172.844
+PHY-3002 : Step(155): len = 483393, overlap = 168.656
+PHY-3002 : Step(156): len = 483652, overlap = 167.781
+PHY-3002 : Step(157): len = 484838, overlap = 164.781
+PHY-3002 : Step(158): len = 485540, overlap = 164.062
+PHY-3002 : Step(159): len = 485068, overlap = 168.031
+PHY-3002 : Step(160): len = 485760, overlap = 162.375
+PHY-3002 : Step(161): len = 486791, overlap = 158.75
+PHY-3002 : Step(162): len = 487224, overlap = 157.062
+PHY-3002 : Step(163): len = 486215, overlap = 160.562
+PHY-3002 : Step(164): len = 485910, overlap = 159.375
+PHY-3002 : Step(165): len = 486294, overlap = 160
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0008463
+PHY-3002 : Step(166): len = 491122, overlap = 153.812
+PHY-3002 : Step(167): len = 498926, overlap = 148.5
+PHY-3002 : Step(168): len = 500214, overlap = 147.438
+PHY-3002 : Step(169): len = 500939, overlap = 146.938
+PHY-3002 : Step(170): len = 502081, overlap = 143.719
+PHY-3002 : Step(171): len = 502464, overlap = 143.062
+PHY-3002 : Step(172): len = 501661, overlap = 144.906
+PHY-3002 : Step(173): len = 501345, overlap = 144.469
+PHY-3002 : Step(174): len = 502283, overlap = 144.219
+PHY-3002 : Step(175): len = 503034, overlap = 146.719
+PHY-3002 : Step(176): len = 502870, overlap = 146.531
+PHY-3002 : Step(177): len = 503020, overlap = 143.75
+PHY-3002 : Step(178): len = 504059, overlap = 143.781
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00138705
+PHY-3002 : Step(179): len = 505848, overlap = 145
+PHY-3002 : Step(180): len = 509120, overlap = 144.969
+PHY-3002 : Step(181): len = 511235, overlap = 142.812
+PHY-3002 : Step(182): len = 512855, overlap = 141.531
+PHY-3002 : Step(183): len = 515171, overlap = 139.875
+PHY-3002 : Step(184): len = 517248, overlap = 140.438
+PHY-3002 : Step(185): len = 518137, overlap = 136.219
+PHY-3002 : Step(186): len = 518380, overlap = 136.094
+PHY-3002 : Step(187): len = 518479, overlap = 135.844
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.012745s wall, 0.000000s user + 0.062500s system = 0.062500s CPU (490.4%)
+
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20628.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700096, over cnt = 1670(4%), over = 7537, worst = 61
+PHY-1001 : End global iterations; 0.697697s wall, 0.921875s user + 0.062500s system = 0.984375s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 84.63, top5 = 64.31, top10 = 54.04, top15 = 47.95.
+PHY-3001 : End congestion estimation; 0.936127s wall, 1.156250s user + 0.062500s system = 1.218750s CPU (130.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.851952s wall, 0.812500s user + 0.046875s system = 0.859375s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000146658
+PHY-3002 : Step(188): len = 636302, overlap = 94.9688
+PHY-3002 : Step(189): len = 637097, overlap = 98.3438
+PHY-3002 : Step(190): len = 630577, overlap = 89.2188
+PHY-3002 : Step(191): len = 626896, overlap = 87.75
+PHY-3002 : Step(192): len = 628342, overlap = 77.9062
+PHY-3002 : Step(193): len = 629045, overlap = 72.1562
+PHY-3002 : Step(194): len = 626824, overlap = 69.0625
+PHY-3002 : Step(195): len = 624161, overlap = 64.4062
+PHY-3002 : Step(196): len = 621836, overlap = 60.0312
+PHY-3002 : Step(197): len = 618901, overlap = 58.125
+PHY-3002 : Step(198): len = 616825, overlap = 49.8438
+PHY-3002 : Step(199): len = 615788, overlap = 40.375
+PHY-3002 : Step(200): len = 614568, overlap = 35.875
+PHY-3002 : Step(201): len = 613595, overlap = 34.0625
+PHY-3002 : Step(202): len = 613070, overlap = 32
+PHY-3002 : Step(203): len = 613729, overlap = 28.3125
+PHY-3002 : Step(204): len = 613872, overlap = 27.8438
+PHY-3002 : Step(205): len = 614579, overlap = 26.1875
+PHY-3002 : Step(206): len = 614760, overlap = 26.75
+PHY-3002 : Step(207): len = 614446, overlap = 25
+PHY-3002 : Step(208): len = 614010, overlap = 24.2188
+PHY-3002 : Step(209): len = 613860, overlap = 27.5625
+PHY-3002 : Step(210): len = 613563, overlap = 30.2812
+PHY-3002 : Step(211): len = 612867, overlap = 35
+PHY-3002 : Step(212): len = 611499, overlap = 37.7812
+PHY-3002 : Step(213): len = 610596, overlap = 41.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000293316
+PHY-3002 : Step(214): len = 615827, overlap = 38.375
+PHY-3002 : Step(215): len = 621743, overlap = 39.1562
+PHY-3002 : Step(216): len = 623421, overlap = 37.0625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000586631
+PHY-3002 : Step(217): len = 628407, overlap = 36.9375
+PHY-3002 : Step(218): len = 644262, overlap = 42.25
+PHY-3002 : Step(219): len = 663701, overlap = 46.3438
+PHY-3002 : Step(220): len = 665453, overlap = 47.4688
+PHY-3002 : Step(221): len = 664229, overlap = 44.9688
+PHY-3002 : Step(222): len = 662890, overlap = 43.7188
+PHY-3002 : Step(223): len = 661016, overlap = 44.9375
+PHY-3002 : Step(224): len = 659421, overlap = 50.7188
+PHY-3002 : Step(225): len = 658514, overlap = 56.6875
+PHY-3002 : Step(226): len = 657436, overlap = 59.0625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.0011151
+PHY-3002 : Step(227): len = 662446, overlap = 56.6875
+PHY-3002 : Step(228): len = 672783, overlap = 55.3438
+PHY-3002 : Step(229): len = 679338, overlap = 56.6875
+PHY-3002 : Step(230): len = 683137, overlap = 58.5
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00195339
+PHY-3002 : Step(231): len = 688536, overlap = 57.9375
+PHY-3002 : Step(232): len = 701227, overlap = 59.875
+PHY-3002 : Step(233): len = 709458, overlap = 59.8125
+PHY-3002 : Step(234): len = 712723, overlap = 60.4062
+PHY-3002 : Step(235): len = 714060, overlap = 60.5
+PHY-3002 : Step(236): len = 716150, overlap = 60.8125
+PHY-3002 : Step(237): len = 716470, overlap = 67.3125
+PHY-3002 : Step(238): len = 716509, overlap = 67.25
+PHY-3002 : Step(239): len = 716612, overlap = 65.1875
+PHY-3002 : Step(240): len = 716331, overlap = 65.1562
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00316059
+PHY-3002 : Step(241): len = 718048, overlap = 64.4062
+PHY-3002 : Step(242): len = 724794, overlap = 63.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 75/20628.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808240, over cnt = 2878(8%), over = 14220, worst = 40
+PHY-1001 : End global iterations; 1.593349s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (126.5%)
+
+PHY-1001 : Congestion index: top1 = 95.84, top5 = 75.73, top10 = 66.32, top15 = 60.55.
+PHY-3001 : End congestion estimation; 1.871877s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (122.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.883319s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000120544
+PHY-3002 : Step(243): len = 710042, overlap = 260.438
+PHY-3002 : Step(244): len = 698909, overlap = 196.469
+PHY-3002 : Step(245): len = 684822, overlap = 178.062
+PHY-3002 : Step(246): len = 673670, overlap = 159.281
+PHY-3002 : Step(247): len = 661319, overlap = 138.125
+PHY-3002 : Step(248): len = 652738, overlap = 129.281
+PHY-3002 : Step(249): len = 646802, overlap = 124.406
+PHY-3002 : Step(250): len = 638513, overlap = 121.594
+PHY-3002 : Step(251): len = 633409, overlap = 114.062
+PHY-3002 : Step(252): len = 627787, overlap = 114.688
+PHY-3002 : Step(253): len = 622599, overlap = 122.531
+PHY-3002 : Step(254): len = 618487, overlap = 119.062
+PHY-3002 : Step(255): len = 615117, overlap = 118.875
+PHY-3002 : Step(256): len = 610263, overlap = 117.062
+PHY-3002 : Step(257): len = 606956, overlap = 119.281
+PHY-3002 : Step(258): len = 603886, overlap = 124
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000241089
+PHY-3002 : Step(259): len = 604318, overlap = 122
+PHY-3002 : Step(260): len = 606221, overlap = 118.812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000403005
+PHY-3002 : Step(261): len = 608726, overlap = 111.5
+PHY-3002 : Step(262): len = 613786, overlap = 104.5
+PHY-3002 : Step(263): len = 619112, overlap = 99.8438
+PHY-3002 : Step(264): len = 622863, overlap = 97.4688
+PHY-3002 : Step(265): len = 624001, overlap = 95.75
+PHY-3001 : Detailed place not supported.
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84379, tnet num: 20450, tinst num: 18049, tnode num: 114931, tedge num: 134608.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.436703s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (100.1%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 566 MB, peak memory is 717 MB
+OPT-1001 : Total overflow 428.75 peak overflow 3.25
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 493/20628.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 714512, over cnt = 2968(8%), over = 10976, worst = 27
+PHY-1001 : End global iterations; 1.444395s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 71.38, top5 = 58.55, top10 = 52.00, top15 = 48.03.
+PHY-1001 : End incremental global routing; 1.780262s wall, 2.328125s user + 0.015625s system = 2.343750s CPU (131.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20450 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.913183s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.2%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17917 has valid locations, 313 needs to be replaced
+PHY-3001 : design contains 18315 instances, 7748 luts, 9346 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 6160 pins
+PHY-3001 : Found 1262 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 646254
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16727/20894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 728760, over cnt = 3011(8%), over = 11102, worst = 27
+PHY-1001 : End global iterations; 0.225811s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (159.1%)
+
+PHY-1001 : Congestion index: top1 = 71.94, top5 = 59.16, top10 = 52.55, top15 = 48.67.
+PHY-3001 : End congestion estimation; 0.473039s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (125.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85448, tnet num: 20716, tinst num: 18315, tnode num: 116561, tedge num: 136214.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.449386s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.3%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 638 MB, peak memory is 723 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.393817s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(266): len = 645166, overlap = 2.28125
+PHY-3002 : Step(267): len = 644894, overlap = 2.15625
+PHY-3002 : Step(268): len = 644588, overlap = 2.09375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16837/20894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 727344, over cnt = 2998(8%), over = 11115, worst = 27
+PHY-1001 : End global iterations; 0.171709s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (154.7%)
+
+PHY-1001 : Congestion index: top1 = 71.64, top5 = 59.15, top10 = 52.58, top15 = 48.66.
+PHY-3001 : End congestion estimation; 0.422846s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (121.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 1.017926s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000321145
+PHY-3002 : Step(269): len = 644405, overlap = 98.2812
+PHY-3002 : Step(270): len = 644481, overlap = 97.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00064229
+PHY-3002 : Step(271): len = 644602, overlap = 97.9375
+PHY-3002 : Step(272): len = 645066, overlap = 97.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00123825
+PHY-3002 : Step(273): len = 645199, overlap = 97.2188
+PHY-3002 : Step(274): len = 645658, overlap = 97.2812
+PHY-3001 : Final: Len = 645658, Over = 97.2812
+PHY-3001 : End incremental placement; 5.024666s wall, 5.812500s user + 0.109375s system = 5.921875s CPU (117.9%)
+
+OPT-1001 : Total overflow 435.59 peak overflow 3.25
+OPT-1001 : End high-fanout net optimization; 8.243346s wall, 9.656250s user + 0.140625s system = 9.796875s CPU (118.8%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 712, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16747/20894.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730552, over cnt = 2944(8%), over = 10054, worst = 27
+PHY-1002 : len = 782312, over cnt = 2119(6%), over = 5345, worst = 18
+PHY-1002 : len = 814016, over cnt = 1264(3%), over = 3087, worst = 17
+PHY-1002 : len = 837624, over cnt = 553(1%), over = 1373, worst = 16
+PHY-1002 : len = 860024, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 1.573951s wall, 2.359375s user + 0.031250s system = 2.390625s CPU (151.9%)
+
+PHY-1001 : Congestion index: top1 = 58.51, top5 = 51.16, top10 = 47.32, top15 = 44.85.
+OPT-1001 : End congestion update; 1.828500s wall, 2.609375s user + 0.031250s system = 2.640625s CPU (144.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20716 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.826681s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.2%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 108 cells processed and 17550 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 55 cells processed and 5484 slack improved
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 884 slack improved
+OPT-0007 : Iter 4: improved WNS 221 TNS 0 NUM_FEPS 0 with 1 cells processed and 300 slack improved
+OPT-1001 : End bottleneck based optimization; 3.116335s wall, 3.906250s user + 0.031250s system = 3.937500s CPU (126.4%)
+
+OPT-1001 : Current memory(MB): used = 703, reserve = 695, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16835/20895.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860648, over cnt = 68(0%), over = 93, worst = 4
+PHY-1002 : len = 860288, over cnt = 39(0%), over = 49, worst = 3
+PHY-1002 : len = 860520, over cnt = 19(0%), over = 20, worst = 2
+PHY-1002 : len = 860872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.532448s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (99.8%)
+
+PHY-1001 : Congestion index: top1 = 58.21, top5 = 51.10, top10 = 47.22, top15 = 44.74.
+OPT-1001 : End congestion update; 0.792549s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20717 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.789804s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.9%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 20 cells processed and 3850 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 1.701609s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 700, peak = 743.
+OPT-1001 : End physical optimization; 14.800579s wall, 16.953125s user + 0.234375s system = 17.187500s CPU (116.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7748 LUT to BLE ...
+SYN-4008 : Packed 7748 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6200 remaining SEQ's ...
+SYN-4005 : Packed 4042 SEQ with LUT/SLICE
+SYN-4006 : 862 single LUT's are left
+SYN-4006 : 2158 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9906/13693 primitive instances ...
+PHY-3001 : End packing; 1.611004s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (98.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6667 instances
+RUN-1001 : 3259 mslices, 3260 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17882 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10019 nets have 2 pins
+RUN-1001 : 6495 nets have [3 - 5] pins
+RUN-1001 : 735 nets have [6 - 10] pins
+RUN-1001 : 313 nets have [11 - 20] pins
+RUN-1001 : 288 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6665 instances, 6519 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3551 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 658117, Over = 228.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7560/17882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 810616, over cnt = 1962(5%), over = 3211, worst = 9
+PHY-1002 : len = 816472, over cnt = 1262(3%), over = 1921, worst = 9
+PHY-1002 : len = 829840, over cnt = 553(1%), over = 844, worst = 7
+PHY-1002 : len = 840568, over cnt = 194(0%), over = 272, worst = 6
+PHY-1002 : len = 844992, over cnt = 15(0%), over = 30, worst = 6
+PHY-1001 : End global iterations; 1.552877s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (138.9%)
+
+PHY-1001 : Congestion index: top1 = 58.58, top5 = 50.97, top10 = 46.93, top15 = 44.31.
+PHY-3001 : End congestion estimation; 1.945389s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (131.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71516, tnet num: 17704, tinst num: 6665, tnode num: 93936, tedge num: 118938.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.597025s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.8%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 614 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.451076s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.16856e-05
+PHY-3002 : Step(275): len = 648604, overlap = 235.25
+PHY-3002 : Step(276): len = 642801, overlap = 241.5
+PHY-3002 : Step(277): len = 638653, overlap = 232.75
+PHY-3002 : Step(278): len = 635388, overlap = 238.75
+PHY-3002 : Step(279): len = 633613, overlap = 251
+PHY-3002 : Step(280): len = 630830, overlap = 248.5
+PHY-3002 : Step(281): len = 628728, overlap = 247.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103371
+PHY-3002 : Step(282): len = 629760, overlap = 245.25
+PHY-3002 : Step(283): len = 633829, overlap = 230
+PHY-3002 : Step(284): len = 636618, overlap = 215.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000206742
+PHY-3002 : Step(285): len = 642221, overlap = 203
+PHY-3002 : Step(286): len = 647331, overlap = 198.25
+PHY-3002 : Step(287): len = 647935, overlap = 195.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.394762s wall, 0.437500s user + 0.625000s system = 1.062500s CPU (269.1%)
+
+PHY-3001 : Trial Legalized: Len = 735435
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 915/17882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844880, over cnt = 2647(7%), over = 4444, worst = 7
+PHY-1002 : len = 862680, over cnt = 1582(4%), over = 2285, worst = 6
+PHY-1002 : len = 877440, over cnt = 824(2%), over = 1194, worst = 6
+PHY-1002 : len = 886208, over cnt = 430(1%), over = 628, worst = 5
+PHY-1002 : len = 899080, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.548145s wall, 3.562500s user + 0.046875s system = 3.609375s CPU (141.6%)
+
+PHY-1001 : Congestion index: top1 = 55.26, top5 = 49.45, top10 = 46.68, top15 = 44.78.
+PHY-3001 : End congestion estimation; 3.021595s wall, 4.046875s user + 0.046875s system = 4.093750s CPU (135.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.849750s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00016604
+PHY-3002 : Step(288): len = 707180, overlap = 31.75
+PHY-3002 : Step(289): len = 690955, overlap = 59.25
+PHY-3002 : Step(290): len = 676956, overlap = 87.75
+PHY-3002 : Step(291): len = 667231, overlap = 111.25
+PHY-3002 : Step(292): len = 661968, overlap = 130.5
+PHY-3002 : Step(293): len = 658198, overlap = 147
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00033208
+PHY-3002 : Step(294): len = 661838, overlap = 142.5
+PHY-3002 : Step(295): len = 666123, overlap = 140.75
+PHY-3002 : Step(296): len = 665854, overlap = 146
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000649487
+PHY-3002 : Step(297): len = 670741, overlap = 143
+PHY-3002 : Step(298): len = 681504, overlap = 129.5
+PHY-3002 : Step(299): len = 681648, overlap = 131
+PHY-3002 : Step(300): len = 680965, overlap = 133.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.033931s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (138.1%)
+
+PHY-3001 : Legalized: Len = 711743, Over = 0
+PHY-3001 : Spreading special nets. 426 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.097303s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (112.4%)
+
+PHY-3001 : 616 instances has been re-located, deltaX = 206, deltaY = 342, maxDist = 3.
+PHY-3001 : Detailed place not supported.
+PHY-3001 : Final: Len = 721650, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71516, tnet num: 17704, tinst num: 6668, tnode num: 93936, tedge num: 118938.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.830790s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (100.7%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 650 MB, peak memory is 743 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3611/17882.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842928, over cnt = 2578(7%), over = 4133, worst = 7
+PHY-1002 : len = 858656, over cnt = 1367(3%), over = 1904, worst = 6
+PHY-1002 : len = 872672, over cnt = 583(1%), over = 774, worst = 4
+PHY-1002 : len = 879000, over cnt = 308(0%), over = 373, worst = 4
+PHY-1002 : len = 885760, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 2.144131s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (138.5%)
+
+PHY-1001 : Congestion index: top1 = 52.35, top5 = 47.19, top10 = 44.40, top15 = 42.61.
+PHY-1001 : End incremental global routing; 2.520722s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (132.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.874714s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.0%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6575 has valid locations, 28 needs to be replaced
+PHY-3001 : design contains 6691 instances, 6542 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 727156
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16317/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892320, over cnt = 117(0%), over = 143, worst = 6
+PHY-1002 : len = 892520, over cnt = 46(0%), over = 53, worst = 5
+PHY-1002 : len = 892752, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 893032, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 893304, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.795033s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (112.0%)
+
+PHY-1001 : Congestion index: top1 = 52.41, top5 = 47.43, top10 = 44.59, top15 = 42.82.
+PHY-3001 : End congestion estimation; 1.104101s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (109.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71755, tnet num: 17722, tinst num: 6691, tnode num: 94223, tedge num: 119218.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.815453s wall, 1.781250s user + 0.031250s system = 1.812500s CPU (99.8%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 660 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 2.699349s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(301): len = 726493, overlap = 0
+PHY-3002 : Step(302): len = 725541, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16302/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891168, over cnt = 81(0%), over = 112, worst = 8
+PHY-1002 : len = 891400, over cnt = 42(0%), over = 48, worst = 2
+PHY-1002 : len = 891976, over cnt = 8(0%), over = 9, worst = 2
+PHY-1002 : len = 892152, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.588000s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (108.9%)
+
+PHY-1001 : Congestion index: top1 = 52.48, top5 = 47.32, top10 = 44.58, top15 = 42.86.
+PHY-3001 : End congestion estimation; 0.898309s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (104.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update; 0.840288s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000967567
+PHY-3002 : Step(303): len = 725333, overlap = 2
+PHY-3002 : Step(304): len = 725250, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization; 0.005406s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 725372, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057776s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.1%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 1, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 725386, Over = 0
+PHY-3001 : End incremental placement; 6.019061s wall, 6.296875s user + 0.171875s system = 6.468750s CPU (107.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization; 10.106880s wall, 11.281250s user + 0.187500s system = 11.468750s CPU (113.5%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 734, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16279/17900.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891992, over cnt = 80(0%), over = 115, worst = 6
+PHY-1002 : len = 892312, over cnt = 38(0%), over = 44, worst = 3
+PHY-1002 : len = 892640, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 892816, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.600808s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (111.8%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.24, top10 = 44.52, top15 = 42.77.
+OPT-1001 : End congestion update; 0.912642s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (106.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17722 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.700926s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.3%)
+
+OPT-0007 : Start: WNS -79 TNS -79 NUM_FEPS 1
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6603 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6691 instances, 6542 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 734063, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058674s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.5%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 22, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 734451, Over = 0
+PHY-3001 : End incremental legalization; 0.376728s wall, 0.546875s user + 0.046875s system = 0.593750s CPU (157.6%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 56 cells processed and 17158 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6603 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6691 instances, 6542 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3631 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 734905, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.057251s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.2%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 5, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 735395, Over = 0
+PHY-3001 : End incremental legalization; 0.374711s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.1%)
+
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 16 cells processed and 1450 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6605 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6693 instances, 6544 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3632 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 735707, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.063018s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.2%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 735673, Over = 0
+PHY-3001 : End incremental legalization; 0.380771s wall, 0.453125s user + 0.031250s system = 0.484375s CPU (127.2%)
+
+OPT-0007 : Iter 3: improved WNS 221 TNS 0 NUM_FEPS 0 with 2 cells processed and 300 slack improved
+OPT-1001 : End bottleneck based optimization; 3.145742s wall, 3.453125s user + 0.125000s system = 3.578125s CPU (113.7%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 735, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16008/17901.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902104, over cnt = 120(0%), over = 154, worst = 8
+PHY-1002 : len = 902096, over cnt = 75(0%), over = 90, worst = 3
+PHY-1002 : len = 902848, over cnt = 18(0%), over = 19, worst = 2
+PHY-1002 : len = 903064, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 903336, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.833407s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 52.35, top5 = 47.36, top10 = 44.57, top15 = 42.79.
+OPT-1001 : End congestion update; 1.160507s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (102.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.702147s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.1%)
+
+OPT-0007 : Start: WNS 221 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6605 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6693 instances, 6544 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1175 with 3632 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 735927, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading; 0.058685s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.5%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 5, deltaY = 14, maxDist = 3.
+PHY-3001 : Final: Len = 736157, Over = 0
+PHY-3001 : End incremental legalization; 0.375380s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (124.9%)
+
+OPT-0007 : Iter 1: improved WNS 221 TNS 0 NUM_FEPS 0 with 18 cells processed and 2098 slack improved
+OPT-0007 : Iter 2: improved WNS 221 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization; 2.378530s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (105.1%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 735, peak = 744.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.700327s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16234/17901.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903592, over cnt = 51(0%), over = 57, worst = 3
+PHY-1002 : len = 903544, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 903776, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 903824, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 903952, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 0.751154s wall, 0.781250s user + 0.031250s system = 0.812500s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 52.31, top5 = 47.36, top10 = 44.56, top15 = 42.79.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update; 0.703096s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.0%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 : WNS 221 TNS 0 NUM_FEPS 0
+RUN-1001 : No local congestion issue, and most congested 1% tile average routing util is 51.793103
+RUN-1001 : Top critical paths
+RUN-1001 : #1 path slack 221ps with logic level 1
+OPT-1001 : End physical optimization; 20.172065s wall, 21.796875s user + 0.359375s system = 22.156250s CPU (109.8%)
+
+RUN-1003 : finish command "place" in 65.288977s wall, 98.906250s user + 6.078125s system = 104.984375s CPU (160.8%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 638 MB, peak memory is 744 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in 1.667979s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (174.2%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 639 MB, peak memory is 744 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : -------------------------------------------------------
+RUN-1001 : effort | medium | medium |
+RUN-1001 : fix_hold | off | off |
+RUN-1001 : opt_timing | medium | medium |
+RUN-1001 : phy_sim_model | off | off |
+RUN-1001 : priority | timing | timing |
+RUN-1001 : swap_pin | on | on |
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6695 instances
+RUN-1001 : 3276 mslices, 3268 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17901 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10005 nets have 2 pins
+RUN-1001 : 6496 nets have [3 - 5] pins
+RUN-1001 : 750 nets have [6 - 10] pins
+RUN-1001 : 322 nets have [11 - 20] pins
+RUN-1001 : 300 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71777, tnet num: 17723, tinst num: 6693, tnode num: 94252, tedge num: 119250.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in 1.601925s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.5%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 657 MB, peak memory is 744 MB
+PHY-1001 : 3276 mslices, 3268 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 835888, over cnt = 2708(7%), over = 4502, worst = 7
+PHY-1002 : len = 858024, over cnt = 1412(4%), over = 1916, worst = 7
+PHY-1002 : len = 876336, over cnt = 405(1%), over = 523, worst = 7
+PHY-1002 : len = 884408, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 884968, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations; 3.072772s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (132.7%)
+
+PHY-1001 : Congestion index: top1 = 51.06, top5 = 46.57, top10 = 43.93, top15 = 42.30.
+PHY-1001 : End global routing; 3.395529s wall, 4.375000s user + 0.015625s system = 4.390625s CPU (129.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 713, peak = 744.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 989, reserve = 984, peak = 989.
+PHY-1001 : End build detailed router design. 3.969309s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 268464, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.159479s wall, 5.156250s user + 0.015625s system = 5.171875s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 268520, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.425279s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1020, peak = 1025.
+PHY-1001 : End phase 1; 5.598751s wall, 5.593750s user + 0.015625s system = 5.609375s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.26522e+06, over cnt = 1798(0%), over = 1800, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1034, peak = 1040.
+PHY-1001 : End initial routed; 26.128103s wall, 56.765625s user + 0.250000s system = 57.015625s CPU (218.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 12/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.761 | 2
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.238118s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1047, peak = 1052.
+PHY-1001 : End phase 2; 29.366282s wall, 59.984375s user + 0.265625s system = 60.250000s CPU (205.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.134277s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.1%)
+
+PHY-1022 : len = 2.26524e+06, over cnt = 1799(0%), over = 1801, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.392158s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2335e+06, over cnt = 521(0%), over = 522, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.565665s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (166.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.23235e+06, over cnt = 92(0%), over = 92, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.618588s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (159.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.23281e+06, over cnt = 21(0%), over = 21, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.302802s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (139.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.23309e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.198611s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.214170s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.313186s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.473583s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.3%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.23317e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.169087s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.161702s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.230053s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (115.5%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.237970s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.23316e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.324794s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.23311e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.173870s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.8%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.23313e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.157738s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.261096s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 358 nets
+PHY-1001 : End commit to database; 2.378022s wall, 2.109375s user + 0.265625s system = 2.375000s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1150, peak = 1152.
+PHY-1001 : End phase 3; 11.580483s wall, 12.875000s user + 0.265625s system = 13.140625s CPU (113.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.658ns STNS -0.658ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.131677s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.8%)
+
+PHY-1022 : len = 2.23313e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.368004s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.658ns, -0.658ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 : Type | WNS(ns) | TNS(ns) | FEP
+RUN-1001 : --------------------------------------
+RUN-1001 : Setup | -0.658 | -0.658 | 1
+RUN-1001 : Hold | 0.067 | 0.000 | 0
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.193661s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 496 feed throughs used by 358 nets
+PHY-1001 : End commit to database; 2.258636s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1159, peak = 1160.
+PHY-1001 : End phase 4; 5.846215s wall, 5.843750s user + 0.000000s system = 5.843750s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.23313e+06
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1161, peak = 1162.
+PHY-1001 : End export database. 0.059325s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.4%)
+
+PHY-1001 : End detail routing; 56.808751s wall, 88.703125s user + 0.562500s system = 89.265625s CPU (157.1%)
+
+RUN-1003 : finish command "route" in 62.840181s wall, 95.703125s user + 0.578125s system = 96.281250s CPU (153.2%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1090 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Utilization Statistics
+#lut 10178 out of 19600 51.93%
+#reg 9527 out of 19600 48.61%
+#le 12301
+ #lut only 2774 out of 12301 22.55%
+ #reg only 2123 out of 12301 17.26%
+ #lut® 7404 out of 12301 60.19%
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 19
+ #treg 0
+#pll 3 out of 4 75.00%
+#gclk 6 out of 16 37.50%
+
+Clock Resource Statistics
+Index ClockNet Type DriverType Driver Fanout
+#1 u_pll/clk0_buf GCLK pll u_pll/pll_inst.clkc0 1763
+#2 u_pll_lvds/clk0_buf GCLK pll u_pll_lvds/pll_inst.clkc0 1426
+#3 uu_pll_lvds/clk0_buf GCLK pll uu_pll_lvds/pll_inst.clkc0 1313
+#4 exdev_ctl_a/clk_adc GCLK pll u_pll/pll_inst.clkc4 926
+#5 exdev_ctl_a/u_ADconfig/clk_config GCLK mslice exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0 138
+#6 ua_lvds_rx/sclk GCLK pll u_pll_lvds/pll_inst.clkc1 70
+#7 ub_lvds_rx/sclk GCLK pll uu_pll_lvds/pll_inst.clkc1 69
+#8 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 GCLK pll u_pll/pll_inst.clkc1 24
+#9 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 GCLK pll u_pll/pll_inst.clkc2 4
+#10 exdev_ctl_a/u_ADconfig/gret9lit16_n GCLK lslice exdev_ctl_a/u_ADconfig/reg5_syn_21.f0 3
+#11 exdev_ctl_b/u_ADconfig/gret9lit16_n GCLK lslice u_bus_top/u_local_bus_slve_cis/reg47_syn_204.f1 2
+#12 a_lvds_clk_p_dup_1 GCLK io a_lvds_clk_p_syn_2.di 1
+#13 b_lvds_clk_p_dup_1 GCLK io b_lvds_clk_p_syn_2.di 1
+#14 clock_source_dup_1 GCLK io clock_source_syn_2.di 1
+#15 u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d GCLK pll u_pll/pll_inst.clkc3 1
+
+
+Detailed IO Report
+
+ Name Direction Location IOStandard DriveStrength PullType PackReg
+ a_ad_sdi INPUT P51 LVCMOS33 N/A PULLUP NONE
+ a_lvds_clk_p INPUT P31 LVDS25 N/A NONE IDDRX1
+ a_lvds_clk_p(n) INPUT P30 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4] INPUT P42 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[4](n) INPUT P41 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3] INPUT P37 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[3](n) INPUT P36 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2] INPUT P28 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[2](n) INPUT P29 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1] INPUT P26 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[1](n) INPUT P27 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0] INPUT P22 LVDS25 N/A NONE IDDRX1
+ a_lvds_data_p[0](n) INPUT P23 LVDS25 N/A NONE IDDRX1
+ b_ad_sdi INPUT P56 LVCMOS33 N/A PULLUP NONE
+ b_lvds_clk_p INPUT P130 LVDS25 N/A NONE IDDRX1
+ b_lvds_clk_p(n) INPUT P129 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4] INPUT P103 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[4](n) INPUT P102 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3] INPUT P131 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[3](n) INPUT P132 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2] INPUT P126 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[2](n) INPUT P127 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1] INPUT P124 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[1](n) INPUT P123 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0] INPUT P121 LVDS25 N/A NONE IDDRX1
+ b_lvds_data_p[0](n) INPUT P122 LVDS25 N/A NONE IDDRX1
+ clock_source INPUT P176 LVCMOS33 N/A PULLUP NONE
+ global_reset_n INPUT P174 LVCMOS33 N/A PULLUP NONE
+ onoff_in INPUT P4 LVCMOS25 N/A N/A NONE
+ paper_in INPUT P14 LVCMOS25 N/A N/A NONE
+ rxd_dsp INPUT P144 LVCMOS33 N/A PULLUP IREG
+ O_clk_hs_p OUTPUT P98 LVDS25 NA NONE ODDRX2L
+ O_clk_hs_p(n) OUTPUT P99 LVDS25 NA NONE ODDRX2L
+ O_clk_lp_n OUTPUT P73 LVCMOS25 8 NONE NONE
+ O_clk_lp_p OUTPUT P74 LVCMOS25 8 NONE OREG
+ O_data_hs_p[3] OUTPUT P100 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[3](n) OUTPUT P101 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2] OUTPUT P97 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[2](n) OUTPUT P95 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1] OUTPUT P93 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[1](n) OUTPUT P94 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0] OUTPUT P90 LVDS25 NA NONE ODDRX2
+ O_data_hs_p[0](n) OUTPUT P89 LVDS25 NA NONE ODDRX2
+ O_data_lp_n[3] OUTPUT P81 LVCMOS25 8 NONE NONE
+ O_data_lp_n[2] OUTPUT P77 LVCMOS25 8 NONE NONE
+ O_data_lp_n[1] OUTPUT P75 LVCMOS25 8 NONE NONE
+ O_data_lp_n[0] OUTPUT P62 LVCMOS25 8 NONE NONE
+ O_data_lp_p[3] OUTPUT P79 LVCMOS25 8 NONE OREG
+ O_data_lp_p[2] OUTPUT P78 LVCMOS25 8 NONE OREG
+ O_data_lp_p[1] OUTPUT P76 LVCMOS25 8 NONE OREG
+ O_data_lp_p[0] OUTPUT P63 LVCMOS25 8 NONE OREG
+ a_ad_sck OUTPUT P52 LVCMOS33 8 NONE NONE
+ a_ad_sdo OUTPUT P50 LVCMOS33 8 NONE NONE
+ a_ad_sen OUTPUT P53 LVCMOS33 8 NONE NONE
+ a_sp_pad OUTPUT P49 LVCMOS33 8 NONE OREG
+ a_sp_sampling OUTPUT P39 LVCMOS25 8 N/A OREG
+ b_ad_sck OUTPUT P57 LVCMOS33 8 NONE NONE
+ b_ad_sdo OUTPUT P55 LVCMOS33 8 NONE NONE
+ b_ad_sen OUTPUT P58 LVCMOS33 8 NONE NONE
+ b_sp_pad OUTPUT P54 LVCMOS33 8 NONE OREG
+ debug[7] OUTPUT P161 LVCMOS33 8 NONE OREG
+ debug[6] OUTPUT P159 LVCMOS33 8 NONE NONE
+ debug[5] OUTPUT P158 LVCMOS33 8 NONE OREG
+ debug[4] OUTPUT P157 LVCMOS33 8 NONE OREG
+ debug[3] OUTPUT P155 LVCMOS33 8 NONE NONE
+ debug[2] OUTPUT P153 LVCMOS33 8 NONE NONE
+ debug[1] OUTPUT P61 LVCMOS33 8 NONE OREG
+ debug[0] OUTPUT P60 LVCMOS33 8 NONE NONE
+ fan_pwm OUTPUT P16 LVCMOS25 8 N/A NONE
+ frame_indicator OUTPUT P15 LVCMOS25 8 N/A OREG
+ onoff_out OUTPUT P35 LVCMOS25 8 N/A NONE
+ paper_out OUTPUT P32 LVCMOS25 8 N/A NONE
+ scan_out OUTPUT P156 LVCMOS33 8 N/A NONE
+ sys_initial_done OUTPUT P104 LVCMOS25 8 N/A NONE
+ txd_dsp OUTPUT P145 LVCMOS33 8 NONE OREG
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance |Module |le |lut |ripple |seq |bram |dsp |
++---------------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |12301 |9151 |1027 |9559 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |524 |455 |23 |422 |4 |1 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |102 |87 |4 |90 |4 |0 |
+| U_ecc_gen |ecc_gen |13 |13 |0 |8 |0 |0 |
+| U_crc16_24b |crc16_24b |47 |47 |0 |19 |0 |0 |
+| exdev_ctl_a |exdev_ctl |747 |410 |96 |568 |0 |0 |
+| u_ADconfig |AD_config |189 |127 |25 |144 |0 |0 |
+| u_gen_sp |gen_sp |248 |146 |71 |114 |0 |0 |
+| exdev_ctl_b |exdev_ctl |749 |352 |96 |570 |0 |0 |
+| u_ADconfig |AD_config |172 |111 |25 |129 |0 |0 |
+| u_gen_sp |gen_sp |261 |149 |71 |125 |0 |0 |
+| sampling_fe_a |sampling_fe |3016 |2461 |306 |2101 |25 |0 |
+| u0_soft_n |cdc_sync |8 |8 |0 |8 |0 |0 |
+| u_ad_sampling |ad_sampling |190 |134 |17 |159 |0 |0 |
+| u0_soft_n |cdc_sync |4 |3 |0 |4 |0 |0 |
+| u_sort |sort |2789 |2306 |289 |1905 |25 |0 |
+| rddpram_ctl |rddpram_ctl |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |3 |2 |0 |3 |0 |0 |
+| u0_rdsoft_n |cdc_sync |4 |2 |0 |4 |0 |0 |
+| u0_wrsoft_n |cdc_sync |4 |1 |0 |4 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2338 |1955 |253 |1540 |22 |0 |
+| channelPart |channel_part_8478 |144 |132 |3 |136 |0 |0 |
+| fifo_adc |fifo_adc |56 |47 |9 |42 |0 |0 |
+| ram_switch |ram_switch |1847 |1547 |197 |1150 |0 |0 |
+| adc_addr_gen |adc_addr_gen |228 |201 |27 |136 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |16 |13 |3 |12 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |25 |22 |3 |14 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |21 |18 |3 |13 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |28 |25 |3 |16 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |12 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |22 |19 |3 |12 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |24 |21 |3 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |22 |19 |3 |10 |0 |0 |
+| insert |insert |945 |673 |170 |631 |0 |0 |
+| ram_switch_state |ram_switch_state |674 |673 |0 |383 |0 |0 |
+| read_ram_i |read_ram |268 |212 |44 |189 |0 |0 |
+| read_ram_addr |read_ram_addr |220 |180 |40 |152 |0 |0 |
+| read_ram_data |read_ram_data |46 |30 |4 |35 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |318 |228 |36 |278 |3 |0 |
+| u0_soft_n |cdc_sync |6 |4 |0 |6 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |3119 |2457 |349 |2099 |25 |1 |
+| u0_soft_n |cdc_sync |4 |4 |0 |4 |0 |0 |
+| u_ad_sampling |ad_sampling |189 |131 |17 |158 |0 |0 |
+| u0_soft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_sort |sort_rev |2900 |2305 |332 |1911 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |1 |0 |2 |0 |0 |
+| u0_wrsoft_n |cdc_sync |2 |2 |0 |2 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2463 |1977 |290 |1558 |22 |1 |
+| channelPart |channel_part_8478 |147 |138 |3 |142 |0 |0 |
+| fifo_adc |fifo_adc |63 |54 |9 |45 |0 |1 |
+| ram_switch |ram_switch |1869 |1508 |197 |1134 |0 |0 |
+| adc_addr_gen |adc_addr_gen |206 |178 |27 |112 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |13 |9 |3 |9 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |20 |17 |3 |12 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |23 |20 |3 |12 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |23 |20 |3 |14 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |20 |17 |3 |10 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |19 |16 |3 |14 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |23 |20 |3 |13 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |20 |17 |3 |8 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |20 |17 |3 |6 |0 |0 |
+| insert |insert |973 |641 |170 |666 |0 |0 |
+| ram_switch_state |ram_switch_state |690 |689 |0 |356 |0 |0 |
+| read_ram_i |read_ram_rev |359 |255 |81 |212 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |293 |209 |73 |166 |0 |0 |
+| read_ram_data |read_ram_data_rev |66 |46 |8 |46 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |- |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+ Index Fanout Nets
+ #1 1 9943
+ #2 2 4231
+ #3 3 1704
+ #4 4 558
+ #5 5-10 785
+ #6 11-50 574
+ #7 51-100 10
+ #8 >500 1
+ Average 2.72
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in 2.060534s wall, 3.500000s user + 0.031250s system = 3.531250s CPU (171.4%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1090 MB, peak memory is 1162 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 71777, tnet num: 17723, tinst num: 6693, tnode num: 94252, tedge num: 119250.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in 1.569378s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.6%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1094 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17723 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s):
+ exdev_ctl_a/u_ADconfig/clk_config_syn_4
+ exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+ exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in 1.423969s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (99.9%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1097 MB, peak memory is 1162 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 :
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream.
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6693
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17901, pip num: 167200
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 496
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3242 valid insts, and 466724 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in 9.230139s wall, 59.546875s user + 0.234375s system = 59.781250s CPU (647.7%)
+
+RUN-1004 : used memory is 1249 MB, reserved memory is 1245 MB, peak memory is 1364 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240319_144011.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_150012.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_150012.log
new file mode 100644
index 0000000..fe9b0b2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_150012.log
@@ -0,0 +1,1906 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:00:12 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=86,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=85,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.100044s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (100.8%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 172 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54153/19277 useful/useless nets, 20876/1800 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38319 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42681/8974 useful/useless nets, 11122/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40354/363 useful/useless nets, 37551/556 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3952 distributor mux.
+SYN-1001 : Optimize 11 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6265 instances.
+SYN-1015 : Optimize round 1, 29954 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25967/1558 useful/useless nets, 23256/7601 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 25 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9457 better
+SYN-1032 : 25717/80 useful/useless nets, 23038/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25624/93 useful/useless nets, 22956/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25346/20 useful/useless nets, 22694/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.095116s wall, 16.562500s user + 1.531250s system = 18.093750s CPU (100.0%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 304 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14018
+ #and 2478
+ #nand 0
+ #or 1077
+ #nor 0
+ #xor 207
+ #xnor 0
+ #buf 0
+ #not 468
+ #bufif1 5
+ #MX21 619
+ #FADD 0
+ #DFF 9158
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 215
+#MACRO_MULT 4
+#MACRO_MUX 4814
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4854 |9164 |789 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.055234s wall, 1.703125s user + 0.031250s system = 1.734375s CPU (164.4%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 314 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 2.3889 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 2.3889 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | medium | medium |
+RUN-1001 : opt_timing | auto | auto |
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25380/24 useful/useless nets, 22743/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25698/670 useful/useless nets, 23077/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29067/338 useful/useless nets, 26447/38 useful/useless insts
+SYN-1016 : Merged 352 instances.
+SYN-2501 : Optimize round 1, 1672 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9744 mux instances.
+SYN-1016 : Merged 12131 instances.
+SYN-1032 : 36702/296 useful/useless nets, 33976/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122318, tnet num: 36704, tinst num: 33976, tnode num: 156682, tedge num: 180185.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.284438s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.8%)
+
+RUN-1004 : used memory is 523 MB, reserved memory is 498 MB, peak memory is 523 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36704 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7872 (3.87), #lev = 9 (3.01)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 8606 (3.94), #lev = 8 (2.93)
+SYN-3001 : Logic optimization runtime opt = 1.26 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18933 instances into 8634 LUTs, name keeping = 51%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 11210
+ #lut4 5833
+ #lut5 2821
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2556
+
+Utilization Statistics
+#lut 11210 out of 19600 57.19%
+#reg 9238 out of 19600 47.13%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |8654 |2556 |9272 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |355 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |55 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |335 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |115 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |153 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |316 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |104 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |145 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2837 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |42 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2763 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2414 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |53 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1974 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |142 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1568 |0 |216 |0 |0 |
+| read_ram_i |read_ram |199 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |173 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |25 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2834 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |43 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2759 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2410 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |53 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1961 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |144 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |15 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |16 |11 |11 |0 |0 |
+| insert |insert |265 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1552 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |210 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |182 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |28 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9238 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1268 adder to BLE ...
+SYN-4008 : Packed 1268 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 38.118125s wall, 37.734375s user + 0.234375s system = 37.968750s CPU (99.6%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 388 MB, peak memory is 703 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.613024s wall, 2.781250s user + 0.062500s system = 2.843750s CPU (176.3%)
+
+RUN-1004 : used memory is 413 MB, reserved memory is 396 MB, peak memory is 703 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_150012.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_152039.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_152039.log
new file mode 100644
index 0000000..12f811c
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_152039.log
@@ -0,0 +1,1906 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:20:40 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=86,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=85,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.274304s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (100.5%)
+
+RUN-1004 : used memory is 196 MB, reserved memory is 174 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54151/19277 useful/useless nets, 20876/1800 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38319 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42679/8974 useful/useless nets, 11122/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40352/363 useful/useless nets, 37549/556 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3952 distributor mux.
+SYN-1001 : Optimize 11 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6265 instances.
+SYN-1015 : Optimize round 1, 29952 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25965/1558 useful/useless nets, 23254/7601 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 25 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9457 better
+SYN-1032 : 25715/80 useful/useless nets, 23036/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25622/93 useful/useless nets, 22954/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25344/20 useful/useless nets, 22692/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 22.423496s wall, 19.843750s user + 2.328125s system = 22.171875s CPU (98.9%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 304 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14016
+ #and 2478
+ #nand 0
+ #or 1077
+ #nor 0
+ #xor 207
+ #xnor 0
+ #buf 0
+ #not 468
+ #bufif1 5
+ #MX21 619
+ #FADD 0
+ #DFF 9156
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 215
+#MACRO_MULT 4
+#MACRO_MUX 4814
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4854 |9162 |789 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.147026s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (163.5%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 299 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 2.3889 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 2.3889 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | medium | medium |
+RUN-1001 : opt_timing | auto | auto |
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25378/24 useful/useless nets, 22741/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25696/670 useful/useless nets, 23075/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29059/338 useful/useless nets, 26439/38 useful/useless insts
+SYN-1016 : Merged 352 instances.
+SYN-2501 : Optimize round 1, 1668 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9744 mux instances.
+SYN-1016 : Merged 12131 instances.
+SYN-1032 : 36694/296 useful/useless nets, 33968/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122294, tnet num: 36696, tinst num: 33968, tnode num: 156654, tedge num: 180155.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.303575s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (99.5%)
+
+RUN-1004 : used memory is 522 MB, reserved memory is 498 MB, peak memory is 522 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36696 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7858 (3.87), #lev = 9 (3.01)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 8650 (3.94), #lev = 8 (2.93)
+SYN-3001 : Logic optimization runtime opt = 1.29 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18927 instances into 8678 LUTs, name keeping = 52%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 11254
+ #lut4 5868
+ #lut5 2830
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2556
+
+Utilization Statistics
+#lut 11254 out of 19600 57.42%
+#reg 9236 out of 19600 47.12%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |8698 |2556 |9270 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |350 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |53 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |11 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |330 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |114 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |149 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |315 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |103 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |145 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2871 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |42 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2797 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |2449 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |54 |24 |41 |0 |0 |
+| ram_switch |ram_switch |2019 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |142 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1613 |0 |216 |0 |0 |
+| read_ram_i |read_ram |189 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |160 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |28 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |126 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2825 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |43 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2750 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |2407 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |54 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1954 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |143 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |18 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |14 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |16 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1547 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |213 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |184 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9236 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1268 adder to BLE ...
+SYN-4008 : Packed 1268 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 55.542788s wall, 55.281250s user + 0.187500s system = 55.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 402 MB, reserved memory is 386 MB, peak memory is 702 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.664652s wall, 2.859375s user + 0.031250s system = 2.890625s CPU (173.6%)
+
+RUN-1004 : used memory is 414 MB, reserved memory is 398 MB, peak memory is 702 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_152039.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_153002.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_153002.log
new file mode 100644
index 0000000..62cb5f8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_153002.log
@@ -0,0 +1,1906 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:30:02 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.033165s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (99.8%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 174 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54147/19277 useful/useless nets, 20876/1800 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38319 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29939 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.512773s wall, 16.437500s user + 2.171875s system = 18.609375s CPU (95.4%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 303 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14015
+ #and 2480
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 207
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 618
+ #FADD 0
+ #DFF 9152
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4813
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4857 |9158 |799 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.101395s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (156.1%)
+
+RUN-1004 : used memory is 328 MB, reserved memory is 298 MB, peak memory is 401 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | medium | medium |
+RUN-1001 : opt_timing | auto | auto |
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.260016s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (100.4%)
+
+RUN-1004 : used memory is 522 MB, reserved memory is 497 MB, peak memory is 522 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36686 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7686 (3.74), #lev = 9 (3.22)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7614 (3.68), #lev = 8 (3.57)
+SYN-3001 : Logic optimization runtime opt = 1.20 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18922 instances into 7642 LUTs, name keeping = 57%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10217
+ #lut4 6529
+ #lut5 1133
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10217 out of 19600 52.13%
+#reg 9232 out of 19600 47.10%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7662 |2555 |9266 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |360 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |52 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |55 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |326 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |116 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |139 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |314 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |105 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |138 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2318 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |43 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2243 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1913 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |52 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1476 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1082 |0 |216 |0 |0 |
+| read_ram_i |read_ram |199 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |169 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |108 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2332 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |44 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2256 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1928 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |52 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1473 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1079 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |215 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |185 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |30 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9232 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 39.862917s wall, 39.515625s user + 0.328125s system = 39.843750s CPU (100.0%)
+
+RUN-1004 : used memory is 398 MB, reserved memory is 384 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.526196s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (175.1%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 387 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_153002.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154034.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154034.log
new file mode 100644
index 0000000..d624a4e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154034.log
@@ -0,0 +1,1906 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:40:34 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.087074s wall, 1.031250s user + 0.062500s system = 1.093750s CPU (100.6%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 170 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54147/19277 useful/useless nets, 20876/1800 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38319 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42673/8976 useful/useless nets, 11122/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40346/363 useful/useless nets, 37543/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29939 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25972/1547 useful/useless nets, 23261/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25723/80 useful/useless nets, 23044/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25630/93 useful/useless nets, 22962/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25352/20 useful/useless nets, 22700/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.638931s wall, 16.484375s user + 2.156250s system = 18.640625s CPU (100.0%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 304 MB, peak memory is 351 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14015
+ #and 2480
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 207
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 618
+ #FADD 0
+ #DFF 9152
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 225
+#MACRO_MULT 4
+#MACRO_MUX 4813
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4857 |9158 |799 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |269 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |10 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.054751s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (164.4%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 299 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | medium | medium |
+RUN-1001 : opt_timing | auto | auto |
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25386/24 useful/useless nets, 22749/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25704/670 useful/useless nets, 23083/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29140/338 useful/useless nets, 26520/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36684/296 useful/useless nets, 33958/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122210, tnet num: 36686, tinst num: 33958, tnode num: 156562, tedge num: 180011.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.295798s wall, 1.234375s user + 0.062500s system = 1.296875s CPU (100.1%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36686 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7686 (3.73), #lev = 9 (3.22)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7626 (3.68), #lev = 8 (3.57)
+SYN-3001 : Logic optimization runtime opt = 1.22 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18922 instances into 7654 LUTs, name keeping = 57%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10229
+ #lut4 6545
+ #lut5 1129
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10229 out of 19600 52.19%
+#reg 9232 out of 19600 47.10%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 21
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7674 |2555 |9266 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |360 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |51 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |11 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |55 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |324 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |114 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |139 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |317 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |108 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |138 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2316 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |43 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2241 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1913 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |52 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1476 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1082 |0 |216 |0 |0 |
+| read_ram_i |read_ram |199 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |169 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |108 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2333 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |44 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2257 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1928 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |52 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1473 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1079 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |215 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |185 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |30 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9232 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 39.176703s wall, 38.515625s user + 0.343750s system = 38.859375s CPU (99.2%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 382 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.547845s wall, 2.625000s user + 0.062500s system = 2.687500s CPU (173.6%)
+
+RUN-1004 : used memory is 432 MB, reserved memory is 416 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_154034.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154806.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154806.log
new file mode 100644
index 0000000..8c16332
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154806.log
@@ -0,0 +1,419 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:48:07 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-5007 WARNING: actual bit length 3 differs from formal bit length 5 for port 'debug' in ../../../../hg_mp/fe/sampling_fe.v(141)
+HDL-8007 ERROR: net 'debug[2]' is constantly driven from multiple places in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-8007 ERROR: found another driver here in ../../../../hg_mp/fe/sampling_fe.v(121)
+HDL-1007 : module 'sampling_fe' remains a black box due to errors in its contents in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-5007 WARNING: actual bit length 6 differs from formal bit length 3 for port 'debug' in ../../../../hg_mp/fe/sampling_fe_rev.v(115)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_154806.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154841.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154841.log
new file mode 100644
index 0000000..8d16662
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_154841.log
@@ -0,0 +1,1907 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 15:48:41 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-5007 WARNING: actual bit length 6 differs from formal bit length 3 for port 'debug' in ../../../../hg_mp/fe/sampling_fe_rev.v(115)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.048132s wall, 1.000000s user + 0.046875s system = 1.046875s CPU (99.9%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 171 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54150/19267 useful/useless nets, 20879/1788 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38319 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42676/8979 useful/useless nets, 11125/4746 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(325) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(325) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40349/363 useful/useless nets, 37546/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29942 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25975/1547 useful/useless nets, 23264/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9430 better
+SYN-1032 : 25726/80 useful/useless nets, 23047/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25633/93 useful/useless nets, 22965/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25355/20 useful/useless nets, 22703/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 18.489148s wall, 16.296875s user + 2.171875s system = 18.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 304 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14015
+ #and 2480
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 207
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 618
+ #FADD 0
+ #DFF 9152
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 228
+#MACRO_MULT 4
+#MACRO_MUX 4813
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4857 |9158 |802 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |272 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |13 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.087829s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (163.7%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 300 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | medium | medium |
+RUN-1001 : opt_timing | auto | auto |
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25389/24 useful/useless nets, 22752/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25707/670 useful/useless nets, 23086/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29152/338 useful/useless nets, 26532/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1783 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36696/296 useful/useless nets, 33970/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122230, tnet num: 36698, tinst num: 33970, tnode num: 156567, tedge num: 180027.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.272227s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (99.5%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 498 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36698 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7686 (3.74), #lev = 9 (3.21)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7631 (3.72), #lev = 8 (3.27)
+SYN-3001 : Logic optimization runtime opt = 1.21 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18934 instances into 7659 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10234
+ #lut4 6471
+ #lut5 1208
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10234 out of 19600 52.21%
+#reg 9232 out of 19600 47.10%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 16
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7679 |2555 |9261 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |354 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |56 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |53 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |323 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |114 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |142 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |306 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |102 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |137 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2344 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |46 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2266 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1917 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |53 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1481 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1087 |0 |216 |0 |0 |
+| read_ram_i |read_ram |197 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |169 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |27 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |128 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2366 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |44 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2290 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1938 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |54 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1483 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1089 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |213 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |184 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |29 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9232 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 38.523734s wall, 38.265625s user + 0.234375s system = 38.500000s CPU (99.9%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 377 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.541623s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (175.3%)
+
+RUN-1004 : used memory is 434 MB, reserved memory is 417 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_154841.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_163032.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_163032.log
new file mode 100644
index 0000000..1da9f80
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_163032.log
@@ -0,0 +1,1907 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 16:30:32 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-5007 WARNING: actual bit length 6 differs from formal bit length 3 for port 'debug' in ../../../../hg_mp/fe/sampling_fe_rev.v(115)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.161480s wall, 1.125000s user + 0.046875s system = 1.171875s CPU (100.9%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 171 MB, peak memory is 235 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54146/19271 useful/useless nets, 20875/1792 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38319 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42674/8977 useful/useless nets, 11123/4744 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(325) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(325) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40347/363 useful/useless nets, 37544/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29940 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25973/1547 useful/useless nets, 23262/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9428 better
+SYN-1032 : 25724/80 useful/useless nets, 23045/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25631/93 useful/useless nets, 22963/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25353/20 useful/useless nets, 22701/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 19.826503s wall, 17.906250s user + 1.859375s system = 19.765625s CPU (99.7%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 303 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14015
+ #and 2480
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 207
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 618
+ #FADD 0
+ #DFF 9152
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 226
+#MACRO_MULT 4
+#MACRO_MUX 4813
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4857 |9158 |800 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |270 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |11 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.171232s wall, 1.812500s user + 0.015625s system = 1.828125s CPU (156.1%)
+
+RUN-1004 : used memory is 327 MB, reserved memory is 301 MB, peak memory is 401 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | medium | medium |
+RUN-1001 : opt_timing | auto | auto |
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25387/24 useful/useless nets, 22750/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25705/670 useful/useless nets, 23084/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29144/338 useful/useless nets, 26524/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1777 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36688/296 useful/useless nets, 33962/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122214, tnet num: 36690, tinst num: 33962, tnode num: 156557, tedge num: 180011.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in 1.401667s wall, 1.359375s user + 0.046875s system = 1.406250s CPU (100.3%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36690 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 2 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7696 (3.73), #lev = 9 (3.21)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7613 (3.68), #lev = 8 (3.57)
+SYN-3001 : Logic optimization runtime opt = 1.35 sec, map = 0.00 sec
+SYN-3001 : Mapper mapped 18926 instances into 7641 LUTs, name keeping = 57%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+LUT Statistics
+#Total_luts 10216
+ #lut4 6530
+ #lut5 1131
+ #lut6 0
+ #lut5_mx41 0
+ #lut4_alu1b 2555
+
+Utilization Statistics
+#lut 10216 out of 19600 52.12%
+#reg 9232 out of 19600 47.10%
+#le 0
+#dsp 3 out of 29 10.34%
+#bram 54 out of 64 84.38%
+ #bram9k 50
+ #fifo9k 4
+#bram32k 4 out of 16 25.00%
+#dram 16
+#pad 75 out of 130 57.69%
+ #ireg 13
+ #oreg 18
+ #treg 0
+#pll 3 out of 4 75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance |Module |lut |ripple |seq |bram |dsp |
++-------------------------------------------------------------------------------------------------+
+|top |huagao_mipi_top |7661 |2555 |9263 |58 |3 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |353 |81 |441 |4 |1 |
+| U_crc16_24b |crc16_24b |52 |0 |16 |0 |0 |
+| U_ecc_gen |ecc_gen |10 |0 |6 |0 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |55 |14 |90 |4 |0 |
+| exdev_ctl_a |exdev_ctl |324 |234 |559 |0 |0 |
+| u_ADconfig |AD_config |115 |49 |138 |0 |0 |
+| u_gen_sp |gen_sp |138 |185 |104 |0 |0 |
+| exdev_ctl_b |exdev_ctl |319 |234 |546 |0 |0 |
+| u_ADconfig |AD_config |107 |49 |125 |0 |0 |
+| u_gen_sp |gen_sp |141 |185 |104 |0 |0 |
+| sampling_fe_a |sampling_fe |2314 |738 |1919 |25 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |44 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort |2238 |691 |1737 |25 |0 |
+| rddpram_ctl |rddpram_ctl |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer |data_prebuffer |1910 |615 |1391 |22 |0 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |52 |24 |41 |0 |0 |
+| ram_switch |ram_switch |1475 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1081 |0 |216 |0 |0 |
+| read_ram_i |read_ram |197 |158 |164 |0 |0 |
+| read_ram_addr |read_ram_addr |167 |145 |127 |0 |0 |
+| read_ram_data |read_ram_data |29 |13 |32 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u_transfer_300_to_200 |transfer_300_to_200 |108 |76 |276 |3 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |0 |3 |0 |
+| sampling_fe_b |sampling_fe_rev |2332 |751 |1936 |25 |1 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_ad_sampling |ad_sampling |44 |47 |147 |0 |0 |
+| u0_soft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_sort |sort_rev |2256 |704 |1754 |25 |1 |
+| rddpram_ctl |rddpram_ctl_rev |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_rdsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u0_wrsoft_n |cdc_sync |1 |0 |5 |0 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1928 |628 |1408 |22 |1 |
+| channelPart |channel_part_8478 |150 |11 |144 |0 |0 |
+| fifo_adc |fifo_adc |52 |24 |41 |0 |1 |
+| ram_switch |ram_switch |1473 |422 |1023 |0 |0 |
+| adc_addr_gen |adc_addr_gen |130 |99 |115 |0 |0 |
+| [0]$ch_addr_gen |ch_addr_gen |1 |11 |11 |0 |0 |
+| [1]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [2]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [3]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [4]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [5]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [6]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [7]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| [8]$ch_addr_gen |ch_addr_gen |13 |11 |11 |0 |0 |
+| insert |insert |264 |323 |692 |0 |0 |
+| ram_switch_state |ram_switch_state |1079 |0 |216 |0 |0 |
+| read_ram_i |read_ram_rev |215 |171 |181 |0 |0 |
+| read_ram_addr |read_ram_addr_rev |185 |145 |139 |0 |0 |
+| read_ram_data |read_ram_data_rev |30 |26 |42 |0 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |1 |0 |0 |1 |0 |
+|...... |...... |- |- |- |- |- |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9232 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in 46.351991s wall, 46.000000s user + 0.312500s system = 46.312500s CPU (99.9%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 381 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in 1.633741s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (175.0%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 385 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240314_163032.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_164107.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_164107.log
new file mode 100644
index 0000000..9fc97f9
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240314_164107.log
@@ -0,0 +1,1907 @@
+============================================================
+ Tang Dynasty, V5.6.71036
+ Copyright (c) 2012-2023 Anlogic Inc.
+ Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+ Built at = 20:34:38 Mar 21 2023
+ Run by = holdtecs
+ Run Date = Thu Mar 14 16:41:07 2024
+
+ Run on = DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(740)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(766)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(772)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(775)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(946)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1035)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1365)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project. All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : OPTION | IO | SETTING
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 : cso_b/cclk/mosi/miso/dout | P140/P168/P166/P165/S5 | gpio
+ARC-1001 : done | P10 | gpio
+ARC-1001 : program_b | P134 | dedicate
+ARC-1001 : tdi/tms/tck/tdo | P46/P44/P47/P43 | dedicate
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : default_reg_initial | auto | auto |
+RUN-1001 : infer_add | on | on |
+RUN-1001 : infer_fsm | off | off |
+RUN-1001 : infer_mult | on | on |
+RUN-1001 : infer_ram | on | on |
+RUN-1001 : infer_reg | on | on |
+RUN-1001 : infer_reg_init_value | on | on |
+RUN-1001 : infer_rom | on | on |
+RUN-1001 : infer_shifter | on | on |
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(607)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(745)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(970)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(117)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-5007 WARNING: actual bit length 6 differs from formal bit length 3 for port 'debug' in ../../../../hg_mp/fe/sampling_fe_rev.v(115)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1347)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1426)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1509)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1547)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1943)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1309)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in 1.223501s wall, 1.203125s user + 0.031250s system = 1.234375s CPU (100.9%)
+
+RUN-1004 : used memory is 196 MB, reserved memory is 174 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment O_clk_hs_p LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_n LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_clk_lp_p LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[0] LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[1] LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[2] LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_hs_p[3] LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[0] LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[1] LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[2] LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_n[3] LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[0] LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[1] LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[2] LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment O_data_lp_p[3] LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment a_ad_sck LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdi LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment a_ad_sdo LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_ad_sen LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_clk_p LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[0] LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[1] LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[2] LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[3] LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment a_lvds_data_p[4] LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sck LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdi LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment b_ad_sdo LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_ad_sen LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_clk_p LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[0] LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[1] LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[2] LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[3] LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_lvds_data_p[4] LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment b_sp_pad LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment clock_source LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment debug[0] LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[1] LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[2] LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[3] LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[4] LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[5] LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[6] LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment debug[7] LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment global_reset_n LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment rxd_dsp LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment txd_dsp LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound bound2 -mode fixed -width 25 -height 25 -origin 0 0 "
+RUN-1002 : start command "create_bound bound3 -mode fixed -width 18 -height 30 -origin 23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound2 -cells U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound bound3 -cells u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : compress_add | ripple | ripple |
+RUN-1001 : elf_sload | off | off |
+RUN-1001 : fix_undriven | 0 | 0 |
+RUN-1001 : flatten | off | off |
+RUN-1001 : gate_sharing | on | on |
+RUN-1001 : hdl_warning_level | normal | normal |
+RUN-1001 : impl_internal_tribuf | on | on |
+RUN-1001 : impl_set_reset | on | on |
+RUN-1001 : infer_gsr | off | off |
+RUN-1001 : keep_hierarchy | auto | auto |
+RUN-1001 : max_fanout | 9999 | 9999 |
+RUN-1001 : max_oh2bin_len | 10 | 10 |
+RUN-1001 : merge_equal | on | on |
+RUN-1001 : merge_equiv | on | on |
+RUN-1001 : merge_mux | off | off |
+RUN-1001 : min_control_set | 8 | 8 |
+RUN-1001 : min_ripple_len | auto | auto |
+RUN-1001 : oh2bin_ratio | 0.08 | 0.08 |
+RUN-1001 : opt_adder_fanout | on | on |
+RUN-1001 : opt_arith | on | on |
+RUN-1001 : opt_big_gate | off | off |
+RUN-1001 : opt_const | on | on |
+RUN-1001 : opt_const_mult | on | on |
+RUN-1001 : opt_lessthan | on | on |
+RUN-1001 : opt_mux | off | off |
+RUN-1001 : opt_ram | high | high |
+RUN-1001 : rtl_sim_model | off | off |
+RUN-1001 : seq_syn | on | on |
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : instance | keep_hierarchy | down_module | file(line)
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 : u_pixel_cdc | true | pixel_cdc | ../../../../hg_mp/drx_t...
+RUN-1001 : ua_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : ub_lvds_rx | false | lvds_rx | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_eot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_mipi_sot_min | true | cdc_sync(DEPTH=3,WIDTH=13) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_p | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : u_O_clk_lp_n | true | cdc_sync(DEPTH=20) | ../../../../hg_mp/drx_t...
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54146/19271 useful/useless nets, 20875/1792 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38319 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42674/8977 useful/useless nets, 11123/4744 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(325) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(325) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40347/363 useful/useless nets, 37544/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 : U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 : U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 : U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 : u_bus_top/reg6_syn_19
+SYN-1002 : u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 : u_senor/reg0_syn_10
+SYN-1002 : reg16_syn_2
+SYN-1002 : exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 : u_senor/reg1_syn_10
+SYN-1002 : reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29940 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25973/1547 useful/useless nets, 23262/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 : reg18_syn_2
+SYN-1002 : reg22_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 : U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 : U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 : sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 : sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 : u_bus_top/reg8_syn_19
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 : u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9428 better
+SYN-1032 : 25724/80 useful/useless nets, 23045/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25631/93 useful/useless nets, 22963/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25353/20 useful/useless nets, 22701/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in 20.350604s wall, 17.796875s user + 2.500000s system = 20.296875s CPU (99.7%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 303 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO 61
+ #input 21
+ #output 40
+ #inout 0
+
+Gate Statistics
+#Basic gates 14015
+ #and 2480
+ #nand 0
+ #or 1078
+ #nor 0
+ #xor 207
+ #xnor 0
+ #buf 0
+ #not 469
+ #bufif1 5
+ #MX21 618
+ #FADD 0
+ #DFF 9152
+ #LATCH 6
+#MACRO_ADD 497
+#MACRO_EQ 226
+#MACRO_MULT 4
+#MACRO_MUX 4813
+#MACRO_OTHERS 73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance |Module |gates |seq |macros |
++----------------------------------------------------------------------------+
+|top |huagao_mipi_top |4857 |9158 |800 |
+| U_rgb_to_csi_pakage |rgb_to_csi_pakage |218 |351 |15 |
+| U_crc16_24b |crc16_24b |67 |16 |0 |
+| U_ecc_gen |ecc_gen |37 |6 |0 |
+| U_fifo_w32_d8192 |fifo_w32_d8192 |0 |0 |1 |
+| exdev_ctl_a |exdev_ctl |161 |559 |45 |
+| u_ADconfig |AD_config |84 |138 |22 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| exdev_ctl_b |exdev_ctl |158 |546 |41 |
+| u_ADconfig |AD_config |81 |125 |18 |
+| u_gen_sp |gen_sp |76 |104 |19 |
+| sampling_fe_a |sampling_fe |1847 |1919 |270 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |40 |147 |11 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort |1803 |1737 |258 |
+| rddpram_ctl |rddpram_ctl |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer |data_prebuffer |1548 |1391 |118 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram |121 |164 |32 |
+| read_ram_addr |read_ram_addr |69 |127 |22 |
+| read_ram_data |read_ram_data |50 |32 |10 |
+| mux_i |mux_i |0 |0 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_sort_ram_a_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_a_9 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_0 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_1 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_10 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_2 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_3 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_4 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_5 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_6 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_7 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_8 |SORT_RAM_9k |0 |0 |1 |
+| u0_sort_ram_b_9 |SORT_RAM_9k |0 |0 |1 |
+| u_transfer_300_to_200 |transfer_300_to_200 |215 |276 |139 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_SORT_RAM_200DPI |SORT_RAM_200DPI |0 |0 |1 |
+| sampling_fe_b |sampling_fe_rev |1807 |1936 |268 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_ad_sampling |ad_sampling |39 |147 |9 |
+| u0_soft_n |cdc_sync |2 |5 |0 |
+| u_sort |sort_rev |1765 |1754 |258 |
+| rddpram_ctl |rddpram_ctl_rev |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_rdsoft_n |cdc_sync |2 |5 |0 |
+| u0_wrsoft_n |cdc_sync |2 |5 |0 |
+| u_data_prebuffer_rev |data_prebuffer_rev |1511 |1408 |119 |
+| channelPart |channel_part_8478 |865 |144 |8 |
+| fifo_adc |fifo_adc |112 |41 |4 |
+| ram_switch |ram_switch |60 |1023 |52 |
+| adc_addr_gen |adc_addr_gen |25 |115 |9 |
+| [0]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [1]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [2]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [3]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [4]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [5]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [6]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [7]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| [8]$ch_addr_gen |ch_addr_gen |2 |11 |1 |
+| insert |insert |5 |692 |37 |
+| mapping |mapping |0 |0 |0 |
+| ram_switch_state |ram_switch_state |27 |216 |4 |
+| mux_addr |mux_e |0 |0 |0 |
+| mux_data |mux_e |0 |0 |0 |
+| mux_valid |mux_e |0 |0 |0 |
+| read_ram_i |read_ram_rev |90 |181 |33 |
+| read_ram_addr |read_ram_addr_rev |56 |139 |23 |
+|...... |...... |- |- |- |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in 1.167072s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (159.3%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 300 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "derive_pll_clocks"
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[0]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 4.5000 [get_pins {u_pll/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[0] -source -master_clock clock_source -multiply_by 4.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[1]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 9.0000 [get_pins {u_pll/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[1] -source -master_clock clock_source -multiply_by 9.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[2]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 [get_pins {u_pll/pll_inst.clkc[2]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[2] -source -master_clock clock_source -multiply_by 18.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[3]} -source [get_ports {clock_source}] -master_clock {clock_source} -multiply_by 18.0000 -phase 90 [get_pins {u_pll/pll_inst.clkc[3]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[3] -source -master_clock clock_source -multiply_by 18.0000 -phase 90 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll/pll_inst.clkc[4]} -source [get_ports {clock_source}] -master_clock {clock_source} -divide_by 4.0000 [get_pins {u_pll/pll_inst.clkc[4]}]
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name u_pll/pll_inst.clkc[4] -source -master_clock clock_source -divide_by 4.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[0]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -divide_by 1.0000 [get_pins {u_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[0] -source -master_clock a_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {u_pll_lvds/pll_inst.clkc[1]} -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -multiply_by 3.5000 [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name u_pll_lvds/pll_inst.clkc[1] -source -master_clock a_lvds_clk_p -multiply_by 3.5000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[0]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -divide_by 1.0000 [get_pins {uu_pll_lvds/pll_inst.clkc[0]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[0] -source -master_clock b_lvds_clk_p -divide_by 1.0000 "
+USR-1002 : Gen clock cmd: create_generated_clock -name {uu_pll_lvds/pll_inst.clkc[1]} -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -multiply_by 3.5000 [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name uu_pll_lvds/pll_inst.clkc[1] -source -master_clock b_lvds_clk_p -multiply_by 3.5000 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name S_clk -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[0] was renamed, new name is S_clk.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name S_clk_x2 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[1] was renamed, new name is S_clk_x2.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "rename_clock -name S_clk_x4 -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[2] was renamed, new name is S_clk_x4.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "rename_clock -name S_clk_x4_90d -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[3] was renamed, new name is S_clk_x4_90d.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "rename_clock -name clk_adc -source -master_clock clock_source "
+RUN-1105 : Rename Clock: clock u_pll/pll_inst.clkc[4] was renamed, new name is clk_adc.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name a_pclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[0] was renamed, new name is a_pclk.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name a_sclk -source -master_clock a_lvds_clk_p "
+RUN-1105 : Rename Clock: clock u_pll_lvds/pll_inst.clkc[1] was renamed, new name is a_sclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "rename_clock -name b_pclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[0] was renamed, new name is b_pclk.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "rename_clock -name b_sclk -source -master_clock b_lvds_clk_p "
+RUN-1105 : Rename Clock: clock uu_pll_lvds/pll_inst.clkc[1] was renamed, new name is b_sclk.
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : message | standard | standard |
+RUN-1001 : mixed_pack_place_flow | on | on |
+RUN-1001 : qor_monitor | off | off |
+RUN-1001 : syn_ip_flow | off | off |
+RUN-1001 : thread | auto | auto |
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : Parameters | Settings | Default Values | Note
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 : cascade_dsp | off | off |
+RUN-1001 : cascade_eram | off | off |
+RUN-1001 : gate_sim_model | off | off |
+RUN-1001 : map_sim_model | off | off |
+RUN-1001 : map_strategy | 1 | 1 |
+RUN-1001 : opt_area | medium | medium |
+RUN-1001 : opt_timing | auto | auto |
+RUN-1001 : pack_effort | medium | medium |
+RUN-1001 : pack_lslice_ripple | on | on |
+RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5 |
+RUN-1001 : pack_seq_in_io | auto | auto |
+RUN-1001 : ph1_mux_ratio | 1.0 | 1.0 |
+RUN-1001 : report | standard | standard |
+RUN-1001 : retiming | off | off |
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25387/24 useful/useless nets, 22750/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"